Signal processing circuit and signal processing method

Abstract

We provide a signal processing circuit. [Solution] The signal processing circuit comprises an AC signal generation unit, a binarization unit, and a time filter unit. The AC signal generation unit outputs a comparison AC signal having a predetermined amplitude and a predetermined frequency determined by a first threshold and a second threshold. The binarization unit outputs an AC signal corresponding to the comparison AC signal when the analog input signal is within the range from the second threshold to the first threshold, outputs a first-level DC signal when the analog input signal is greater than the first threshold, and outputs a second-level DC signal when the analog input signal is less than the second threshold. The binarized signal is input to the time filter unit. The time filter unit is configured to detect a first state in which the period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which the period during which the binarized signal is at the second level is longer than a predetermined time.

Description

[Technical Field]

[0001] The technologies disclosed herein relate to signal processing circuits and signal processing methods. [Background technology]

[0002] Patent Document 1 discloses a signal processing circuit for extracting specific signals, such as cellular action potential signals, from an analog input signal. Specifically, the signal processing circuit compares the analog input signal with a threshold. If the voltage amplitude exceeds, for example, the threshold, it is considered a positive detection, and the target specific signal is detected. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Special Publication No. 2024-023111 [Overview of the project] [Problems that the invention aims to solve]

[0004] In signal processing circuits, it is sometimes necessary to detect when an analog input signal is greater than a first threshold, or when it is less than a second threshold. In this case, it is necessary to handle two signals—one indicating the first threshold and another indicating the second threshold—which can increase the size of the signal processing circuit. This is problematic because it increases costs. [Means for solving the problem]

[0005] One embodiment of a signal processing circuit disclosed herein comprises an AC signal generation unit, a binarization unit, and a time filter unit. The AC signal generation unit outputs a comparison AC signal having a predetermined frequency and a predetermined amplitude determined by a first threshold and a second threshold smaller than the first threshold. The binarization unit receives the comparison AC signal and an analog input signal as inputs. The binarization unit outputs a binarized signal. When the analog input signal is within the range from the second threshold to the first threshold, the binarization unit outputs a binarized signal which is an AC signal corresponding to the comparison AC signal; when the analog input signal is greater than the first threshold, it outputs a binarized signal which is a first-level DC signal; and when the analog input signal is less than the second threshold, it outputs a binarized signal which is a second-level DC signal. The time filter unit receives the binarized signal as input. The time filter unit is configured to detect a first state in which the period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which the period during which the binarized signal is at the second level is longer than a predetermined time.

[0006] In the above configuration, the comparison AC signal has a predetermined amplitude determined by the first threshold and the second threshold. The binarization unit outputs an AC signal when the analog input signal is within the range from the second threshold to the first threshold. The binarization unit also outputs a first-level DC signal when the analog input signal is greater than the first threshold. Furthermore, the binarization unit outputs a second-level DC signal when the analog input signal is less than the second threshold. As a result, it is possible to detect whether the analog input signal is greater than the first threshold and whether it is less than the second threshold using only one comparison AC signal. In other words, two pieces of information, the first threshold and the second threshold, can be represented using a single comparison AC signal. This reduces the size of the signal processing circuit because only one comparison signal needs to be handled. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram of signal processing circuit 1. [Figure 2]This figure shows examples of waveforms for various signals. [Figure 3] This is a timing chart to explain the operation of the time filter unit 13. [Figure 4] This is a circuit diagram of Example 2. [Figure 5] This is a timing chart to explain the operation of the time filter unit 213. [Figure 6] This figure shows the signal processing circuit 301 of Example 3. [Figure 7] This figure shows the signal processing circuit 401 of Example 4. [Modes for carrying out the invention] [Examples]

[0008] (Configuration of signal processing circuit 1) Figure 1 shows a circuit diagram of the signal processing circuit 1 according to this embodiment. Figure 2 shows examples of waveforms of various signals processed by the signal processing circuit 1. The signal processing circuit 1 includes an AC signal generation unit 11, a binarization unit 12, and a time filter unit 13.

[0009] The AC signal generation unit 11 is the part that outputs the comparison AC signal AS. As shown in the example in Figure 2, the comparison AC signal AS has a constant predetermined frequency f REF This is an AC signal comprising the following characteristics. In this embodiment, the comparison AC signal AS is a triangular wave. The comparison AC signal AS may also be a square wave or a sine wave. The comparison AC signal AS has a predetermined amplitude PA. The predetermined amplitude PA is determined by a first threshold VT1 and a second threshold VT2 which is smaller than the first threshold.

[0010] The binarization unit 12 is a comparator having a first input terminal T1 and a second input terminal T2. The second input terminal T2 receives a comparison AC signal AS. The first input terminal T1 receives an analog input signal IS. The analog input signal IS will be described later. The binarization unit 12 compares the magnitude relationship between the analog input signal IS and the comparison AC signal AS and outputs a binarized signal CO.

[0011] The binarized signal CO is input to the time filter unit 13. The time filter unit 13 is an asynchronous time filter. The time filter unit 13 includes a first filter circuit 30 and a second filter circuit 40.

[0012] The first filter circuit 30 is a circuit that outputs a positive side detection signal DP, which will be described later. The first filter circuit 30 mainly comprises an input inverter 31, a charge / discharge unit 32, a capacitance unit 35, and an output inverter 36. The charge / discharge unit 32 comprises a resistor unit 33 and a switching unit 34. In this embodiment, the switching unit 34 is an NMOS transistor. The resistor unit 33 and the switching unit 34 are connected in series between the power supply voltage unit VDD and the reference voltage unit GND via a connection node N1. A binarization signal CO is input to the input inverter 31. The inverted binarization signal CO_B output from the input inverter 31 is input to the gate terminal of the switching unit 34. One end of the capacitance unit 35 is connected to the connection node N1. The other end of the capacitance unit 35 is connected to the reference voltage unit GND. The output voltage V1 of the capacitance unit 35 is input to the output inverter 36. The output inverter 36 is a two-stage inverter connected in series. The input terminal of the output inverter 36 is connected to the connection node N1. A positive side detection signal DP is output from the output terminal of the output inverter 36.

[0013] The second filter circuit 40 is a circuit that outputs a negative-side detection signal DM to be described later. The second filter circuit 40 mainly includes a charge / discharge section 42, a capacitance section 45, and an output inverter 46. The charge / discharge section 42 includes a resistance section 43 and a switching section 44. In this embodiment, the switching section 44 is an NMOS transistor. The resistance section 43 and the switching section 44 are serially connected between a power supply voltage portion VDD and a reference voltage portion GND via a connection node N2. A binarized signal CO is input to the gate terminal of the switching section 44. The output voltage V2 of the capacitance section 45 is input to the output inverter 46. Since the configurations of the resistance section 43, the switching section 44, the capacitance section 45, and the output inverter 46 of the second filter circuit 40 are the same as those of the resistance section 33, the switching section 34, the capacitance section 35, and the output inverter 36 of the first filter circuit 30 described above, the description thereof is omitted.

[0014] (Contents of various signals) The analog input signal IS will be described. FIG. 2 shows an example of the analog input signal IS. The analog input signal IS is a signal that includes a specific signal that the user attempts to detect. The specific signal is a pulse signal having a pulse width of a predetermined pulse time width Td or more. The specific signal may be various signals. The predetermined pulse time width Td can be appropriately determined in advance according to the type of the specific signal. For example, the specific signal may be an action potential signal of a cell. The action potential signal is a pulse-shaped potential generated by a nerve cell when the magnitude of the input to the nerve cell exceeds a threshold value. The analog input signal IS including the action potential signal can be obtained by bringing a detection electrode (not shown) into contact with the cell. The action potential signal is buried in the noise of the analog input signal IS. That is, the action potential signal is a signal with a low signal-to-noise ratio. Therefore, as will be described later, by using the signal processing circuit 1 of this specification, the action potential signal can be detected from the analog input signal IS including noise. Thereby, it becomes possible to use the signal processing circuit 1 of this specification in drug discovery, elucidation of disease mechanisms, brain implant devices for brain-machine interfaces, and the like.

[0015] In the technology of this specification, in order to detect a specific signal having a pulse waveform, it is necessary to detect a first state and a second state. The first state is a state in which the period during which the analog input signal IS is greater than the first threshold value VT1 continues for a predetermined time TT or more. The second state is a state in which the period during which the analog input signal IS is less than the second threshold value VT2 continues for a predetermined time TT or more.

[0016] The specific signal has a pulse width of a predetermined pulse time width Td or more. Therefore, by setting the predetermined time TT to be shorter than the predetermined pulse time width Td, it becomes possible to detect the specific signal. Also, the predetermined frequency f of the comparison AC signal AS REF is preferably higher than the reciprocal (1 / TT) of the predetermined time TT in order to reliably detect the specific signal. In this embodiment, based on the general waveform of the action potential signal, the predetermined frequency f REF is set to 12.5 kHz.

[0017] The first threshold value VT1 and the second threshold value VT2 can be determined by a predetermined amplitude PA of the comparison AC signal AS and the median value of the amplitude. There are various ways to determine the predetermined amplitude PA and the median value of the amplitude. For example, the predetermined amplitude PA and the median value of the amplitude may be determined so that the probability of misdetecting the first state and the second state is below a predetermined target value. A misdetection is detecting the first state and the second state when the specific signal is not included in the analog input signal IS (that is, when there is only noise). In other words, the predetermined amplitude PA and the median value of the amplitude may be set so that most of the noise components included in the analog input signal IS are included within the predetermined amplitude PA. The target value can be appropriately determined according to the detection sensitivity. For example, when using 3σ for the probability of misdetection, the target value is 0.3%. In this embodiment, the predetermined amplitude PA is set to 30 (mV) and the median value of the amplitude is set to 0 (V).

[0018] (Operation of the binarization unit 12) The operation of the binarization unit 12 will be specifically explained using the example in Figure 2. During the periods t0-t1, t2-t3, t4-t5, and t6 onward, the analog input signal IS is within the range from the second threshold VT2 to the first threshold VT1 (i.e., within the range of the predetermined amplitude PA). Since the absolute value of the analog input signal IS does not exceed the predetermined amplitude PA, the binarized signal CO inverts during one period of the comparison AC signal AS. Therefore, the AC signal of the binarized signal CO becomes the AC signal corresponding to the comparison AC signal AS. The AC signal of the binarized signal CO has an amplitude CA determined by a first level L1 and a second level L2 which is smaller than the first level L1. The frequency of the AC signal of the binarized signal CO is the predetermined frequency f of the comparison AC signal AS. REF This is almost equivalent to [the above].

[0019] During the periods t1-t2 and t5-t6, the analog input signal IS remains greater than the first threshold VT1. Therefore, the binarized signal CO becomes a DC signal (high level) at the first level L1 (see arrows Y1 and Y2).

[0020] During the period from time t3 to t4, the analog input signal IS remains below the second threshold VT2. Therefore, the binarized signal CO becomes a DC signal at the second level L2 (low level) (see arrow Y3).

[0021] Based on the above, the binarization unit 12 compares the analog input signal IS with the comparison AC signal AS to extract the time period in which the absolute value of the analog input signal IS continuously exceeds a predetermined amplitude PA of the comparison AC signal AS, and outputs a DC signal during that time period.

[0022] (Operation of the time filter unit 13) The contents of the first filter circuit 30 of the time filter unit 13 will be explained using Figure 1. The charge / discharge unit 32 is configured to charge and discharge the capacitor unit 35 based on the inverted binarized signal CO_B. That is, the capacitor unit 35 is discharged when the switching unit 34 is on, and the capacitor unit 35 is charged when the switching unit 34 is off. The time constant TC for charging by the charge / discharge unit 32 and the capacitor unit 35 is set to be equivalent to the predetermined time TT mentioned above. Specifically, the resistance value of the resistor unit 33 and the capacitance value of the capacitor unit 35 are set so that the time constant TC matches the predetermined time TT. The resistor unit 33 and the capacitor unit 35 may be variable elements. The resistance value of the resistor unit 33 and the capacitance value of the capacitor unit 35 may be adjusted as appropriate so that the time constant TC matches the predetermined time TT.

[0023] Furthermore, the contents of the second filter circuit 40 are the same as those of the first filter circuit 30. That is, the charge / discharge unit 42 is configured to charge and discharge the capacitance unit 45 based on the binarized signal CO. The time constant TC for charging by the charge / discharge unit 42 and the capacitance unit 45 is set to be equivalent to the predetermined time TT mentioned above.

[0024] The basic operation of the first filter circuit 30 will be explained using the timing chart in Figure 3. During the periods from time t11 to t12 and from time t12 to t13, the time for which the binarization signal CO is maintained at a high level is shorter than the time constant TC (see region A1). Therefore, the capacitance section 35 discharges before the output voltage V1 of the capacitance section 35 rises to the threshold voltage Vth1 of the output inverter 36. Thus, the positive detection signal DP is maintained at a low level (see region A2).

[0025] On the other hand, during the period from time t13 to t15, the time for which the binarization signal CO is maintained at a high level is longer than the time constant TC. Therefore, when the time for which the binarization signal CO is maintained at a high level exceeds the time constant TC (time t14), the output voltage V1 rises above the threshold voltage Vth1 of the output inverter 36, causing the positive side detection signal DP to invert to a high level (see arrow Y11). Subsequently, when the binarization signal CO returns to a low level (time t15), the capacitance section 35 discharges, and the positive side detection signal DP returns to a low level (see arrow Y12).

[0026] As described above, the first filter circuit 30 can determine that a specific signal (action potential signal) has been detected when the time during which the binarized signal CO is maintained at a high level exceeds a predetermined time constant TC (i.e., a predetermined time TT). Then, the positive detection signal DP can be inverted.

[0027] Next, the basic operation of the second filter circuit 40 will be explained. During the periods t15-t16 and t16-t17, the time for which the binarization signal CO is maintained at a low level is shorter than the time constant TC (see region A3). Therefore, the negative detection signal DM is maintained at a low level (see region A4). On the other hand, during the period t17-t19, the time for which the binarization signal CO is maintained at a low level is longer than the time constant TC. Therefore, when the time for which the binarization signal CO is maintained at a low level exceeds the time constant TC (time t18), the output voltage V2 rises above the threshold voltage Vth2 of the output inverter 46, causing the negative detection signal DM to invert to a high level (see arrow Y21). Subsequently, when the binarization signal CO becomes high level (time t19), the capacitance section 45 discharges, and the negative detection signal DM returns to a low level (see arrow Y22).

[0028] As described above, the second filter circuit 40 can determine that a specific signal (action potential signal) has been detected when the time during which the binarized signal CO is maintained at a low level exceeds a predetermined time constant TC (i.e., a predetermined time TT). Then, the negative detection signal DM can be inverted.

[0029] Using Figure 2, a specific example of the operation of the time filter unit 13 will be explained. During the periods of time t0-t1, t2-t3, t4-t5, and from time t6 onward, the binarized signal CO reaches a predetermined frequency f REF This is an AC signal. As mentioned above, the predetermined frequency f REF The frequency is higher than the reciprocal of the predetermined time TT (1 / TT). Therefore, the time during which the binarized signal CO is maintained at a low level or a high level will not exceed the predetermined time TT (i.e., the time constant TC). Thus, the positive detection signal DP and the negative detection signal DM are maintained at a low level.

[0030] At time t1, the binarized signal CO becomes high level, and if this high level state continues for longer than the time constant TC, the positive side detection signal DP inverts to a high level (see arrow Y31). This allows the specific signal to be detected. Then, at time t2, when the binarized signal CO changes to an AC signal, the positive side detection signal DP returns to a low level (see arrow Y32).

[0031] At time t3, the binarized signal CO becomes low level, and if this low level state continues for longer than the time constant TC, the negative detection signal DM inverts to a high level (see arrow Y33). This allows the specific signal to be detected. Then, at time t4, when the binarized signal CO changes to an AC signal, the negative detection signal DM returns to a low level (see arrow Y34).

[0032] During the period from time t5 to t6, the binarized signal CO reaches a high level. However, since the high level state does not persist for longer than the time constant TC, the positive detection signal DP does not invert to a high level (see region A11). Therefore, the specific signal is not detected.

[0033] (effect) Consider a case in a signal processing circuit where it is necessary to detect whether the analog input signal IS is greater than the first threshold VT1 and less than the second threshold VT2. If two signals, one indicating the first threshold VT1 and one indicating the second threshold VT2, are used, the size of the signal processing circuit may increase, for example, by requiring two binarization units. This is problematic because it increases costs. Therefore, in the technology of this embodiment, a comparison AC signal AS with a predetermined amplitude PA determined by the first threshold VT1 and the second threshold VT2 is used. A single binarization unit 12 is used to compare the comparison AC signal AS with the analog input signal IS. As a result, it is possible to detect whether the analog input signal IS is greater than the first threshold VT1 and less than the second threshold VT2 using only one comparison AC signal AS. In other words, two pieces of information, the first threshold VT1 and the second threshold VT2, can be represented using a single comparison AC signal AS. This allows for a reduction in the size of the signal processing circuit 1, for example, by requiring only one binarization unit 12, since only one comparison signal needs to be handled. This makes it possible to reduce costs.

[0034] In some cases, a signal processing circuit for detecting a specific signal from an analog input signal needs to be expanded to multiple channels and require real-time processing. For example, this may be the case when the signal processing circuit is used for learning control in a brain organoid. In this case, parallelization (scaling up) of the hardware becomes necessary, which significantly increases costs. However, by using the technology of this embodiment, the size of the signal processing circuit 1 can be reduced as described above. Even when hardware parallelization is performed, it is possible to suppress the increase in costs. Furthermore, because the signal processing can be simplified, it becomes possible to extract action potential signals in real time across multiple detection channels.

[0035] In this embodiment, the time filter unit 13 uses a time constant TC to detect a specific signal (action potential signal). Since there is no need to use a clock, an asynchronous time filter can be realized. As a result, the phase error can be reduced compared to a synchronous time filter that uses a clock, and thus the detection accuracy of the specific signal can be improved. [Examples]

[0036] Example 2 (Figure 4) differs from Example 1 (Figure 1) in that it uses a synchronous time filter unit 213. Parts common to both Example 2 and Example 1 are denoted by the same reference numerals, and their explanation is omitted.

[0037] (Configuration of the time filter unit 213) The time filter unit 213 includes a first filter circuit 230, a second filter circuit 240, and a clock generation unit 250. The clock generation unit 250 outputs a clock signal CK. The clock period Tck of the clock signal CK is set to be equivalent to a predetermined time TT.

[0038] The first filter circuit 230 will now be described. The first filter circuit 230 includes D flip-flops 231 and 232. D flip-flop 231 has an asynchronous reset function (negative logic). The input terminal D and reset terminal RB of D flip-flop 231 are input to the binarization signal CO. The output signal DP1 output from the output terminal Q of D flip-flop 231 is input to the input terminal D of the next stage D flip-flop 232. The output terminal Q of D flip-flop 232 outputs the positive side detection signal DP. In addition, the clock signal CK is input to the clock terminals of D flip-flops 231 and 232.

[0039] The D flip-flop 231, which has an asynchronous reset function, resets its output signal DP1 to a low level asynchronously when the binarization signal CO input to the reset terminal RB becomes low level. On the other hand, when the binarization signal CO is high level, it outputs a high-level output signal DP1 in synchronization with the rising edge of the clock signal CK. The next stage D flip-flop 232 takes the output signal DP1 in synchronization with the rising edge of the clock signal CK.

[0040] The second filter circuit 240 will now be described. The second filter circuit 240 comprises D flip-flops 241 and 242 and an input inverter 243. D flip-flop 241 has an asynchronous reset function (negative logic). The input inverter 243 receives the binarization signal CO. The inverted binarization signal CO_B output from the input inverter 243 is input to the input terminal D and reset terminal RB of D flip-flop 241. The output signal DM1 output from the output terminal Q of D flip-flop 241 is input to the input terminal D of the next stage D flip-flop 242. The output terminal Q of D flip-flop 242 outputs the negative side detection signal DM. The clock signal CK is also input to the clock terminals of D flip-flops 241 and 242.

[0041] In the second filter circuit 240, the inverted binarized signal CO_B is input to the first-stage D flip-flop 241. Therefore, its operation is the opposite of that of the first filter circuit 230 described above. That is, when the binarized signal CO is at a low level, it outputs a high-level output signal DM1 in synchronization with the rising edge of the clock signal CK. The next-stage D flip-flop 242 takes in the output signal DM1 in synchronization with the rising edge of the clock signal CK.

[0042] (Operation of the time filter unit 213) The basic operation of the first filter circuit 230 will be explained using the timing chart in Figure 5. At time t32, the output signal DP1 is reset to a low level in response to the binarization signal CO becoming low (arrow Y41). Next, at time t33, the value of the binarization signal CO is acquired in synchronization with the rising edge of the clock signal CK, and the output signal DP1 becomes high level. At the same time, the next stage D flip-flop 232 acquires the low-level output signal DP1, and the positive side detection signal DP becomes low level (arrow Y42).

[0043] On the other hand, during the period from time t33 to t34, the binarization signal CO remains at a high level for the duration of the clock period Tck (see region A21). Therefore, the output signal DP1 also remains at a high level. Synchronized with the rising edge of the clock signal CK at time t34, the next stage D flip-flop 232 captures the high-level output signal DP1. Thus, the positive side detection signal DP becomes high level (arrow Y43).

[0044] In other words, the positive detection signal DP becomes high in synchronization with the rising edge of the clock signal CK only when the binarization signal CO remains high for the duration of the clock period Tck (i.e., a predetermined time TT).

[0045] Next, the basic operation of the second filter circuit 240 will be explained. In the second filter circuit 240, the inverted binarized signal CO_B is input to the first stage D flip-flop 241. Therefore, its operation is the opposite of that of the first filter circuit 230 described above. Specifically, during the period from time t36 to t37, the binarized signal CO is continuously maintained at a low level for the duration of the clock period Tck (see region A22). Therefore, the output signal DM1 is also maintained at a high level, and in synchronization with the rising edge of the clock signal CK at time t37, the next stage D flip-flop 242 takes in the high-level output signal DM1. Thus, the negative detection signal DM becomes high level (arrow Y44).

[0046] In other words, the negative detection signal DM becomes high in synchronization with the rising edge of the clock signal CK only when the binarization signal CO remains low for the duration of the clock period Tck (i.e., a predetermined time TT).

[0047] (effect) In the technology of Example 2, a specific signal can be detected by using the clock period Tck as a predetermined time TT. The clock period Tck is easier to adjust than the time constant TC. Therefore, it is possible to increase the degree of freedom in adjusting the predetermined time TT. [Examples]

[0048] Figure 6 shows the signal processing circuit 301 of Example 3. In the signal processing circuit 301 of Example 3, the manner in which the analog input signal IS and the comparison AC signal AS are input to the binarization unit 12 differs from that of Examples 1 and 2. Parts common to Example 3 and Examples 1 and 2 are denoted by the same reference numerals, and their explanation is omitted.

[0049] The signal processing circuit 301 includes, in addition to the AC signal generation unit 11, the binarization unit 12, and the time filter unit 13, a preamplifier 311, a bandpass filter 312, and an adder circuit 313. The analog input signal IS is input to the adder circuit 313 via the preamplifier 311 and the bandpass filter 312. The preamplifier 311 performs signal amplification in a low-noise state. The bandpass filter 312 removes unwanted high-frequency noise.

[0050] In the addition circuit 313, a superimposed analog input signal IS_S is generated by adding the comparison AC signal AS to the analog input signal IS. The superimposed analog input signal IS_S is input to the first input terminal T1 of the binarization unit 12, and the reference voltage signal Vgnd is input to the second input terminal T2. As shown in Example 3, even in the embodiment using the superimposed analog input signal IS_S, the analog input signal IS and the comparison AC signal AS can be compared in the same manner as in Examples 1 and 2. [Examples]

[0051] Figure 7 shows the signal processing circuit 401 of Example 4. Parts common to Example 4 and Examples 1-3 are given the same reference numerals, and their explanation is omitted. The signal processing circuit 401 further includes a preamplifier 311, a high-pass filter 412, and a main amplifier 413, in addition to the binarization unit 12 and the time filter unit 13. The signal processing circuit 401 does not include an AC signal generation unit 11. The analog input signal IS inherently contains high-frequency noise components. That is, the circuit not shown prior to the preamplifier 311 functions as an AC signal generation unit. The analog input signal IS is input to the first input terminal T1 of the binarization unit 12 via the preamplifier 311, the high-pass filter 412, and the main amplifier 413.

[0052] The cutoff frequency of the high-pass filter 412 is the predetermined frequency f mentioned above. REF It is set to the above. This results in a predetermined frequency f REF The analog input signal IS, which has the above high-frequency noise components superimposed on it, is input to the second input terminal T2 via the main amplifier 413. This allows for the detection of a specific signal in the same manner as the signal processing circuit 301 in Embodiment 3.

[0053] In the embodiment of Example 4, the high-frequency noise component originally contained in the analog input signal IS can be used as the comparison AC signal AS. Since the AC signal generation unit 11 for generating the comparison AC signal AS can be eliminated, the size of the circuit can be further reduced.

[0054] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness.

[0055] (modified version) The specific signal is not limited to action potential signals, but can be any type of signal. For example, it can be various biological signals (e.g., heart rate, electroencephalogram). It can also be detection signals from various sensors (e.g., rotation sensors, gyroscopes).

[0056] The binarization unit 12 is not limited to a comparator and may take various forms. For example, it may be a microcontroller that performs binarization by software.

[0057] The following are embodiments of this technology. [Aspect 1] A signal processing circuit comprising an AC signal generation unit, a binarization unit, and a time filter unit, The AC signal generation unit outputs a comparative AC signal having a predetermined frequency and a predetermined amplitude determined by a first threshold and a second threshold smaller than the first threshold. The binarization unit receives the comparison AC signal and the analog input signal. The binarization unit outputs a binarized signal. The binarization unit is, When the analog input signal is within the range from the second threshold to the first threshold, the binarized signal, which is an AC signal corresponding to the comparison AC signal, is output. When the analog input signal is greater than the first threshold, the binarized signal, which is a first-level DC signal, is output. When the analog input signal is smaller than the second threshold, the binarized signal, which is a second-level DC signal, is output. The binarized signal is input to the time filter unit. The time filter unit is configured to detect a first state in which the period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which the period during which the binarized signal is at the second level is longer than the predetermined time. Signal processing circuit. [Aspect 2] The analog input signal includes a specific signal having pulses with a predetermined pulse time width or longer. The signal processing circuit according to embodiment 1, wherein the predetermined time is smaller than the predetermined pulse time width. [Aspect 3] The signal processing circuit according to embodiment 2, wherein the predetermined frequency of the comparison AC signal is a frequency higher than the reciprocal of the predetermined time. [Aspect 4] The signal processing circuit according to embodiment 2 or 3, wherein the predetermined amplitude value of the comparison AC signal is a value such that the probability of the time filter unit detecting the first state and the second state when the analog input signal does not include the specific signal is less than or equal to a predetermined target value. [Aspect 5] The aforementioned time filter unit comprises a charge / discharge unit, a capacity unit, and an inverter. The charging / discharging unit is configured to charge or discharge the capacity unit based on the binarization signal, The output voltage of the capacitive unit is input to the inverter. The time constant for charging and discharging by the charging / discharging unit and the capacity unit is equivalent to the predetermined time. A signal processing circuit according to any one of embodiments 1-4, wherein the output of the inverter is inverted in response to the capacitance being charged or discharged beyond the aforementioned time constant, thereby enabling the detection of the first state or the second state. [Aspect 6] The charging and discharging section comprises a resistor section and a switching section connected in series between the power supply voltage section and the reference voltage section. The input terminal of the switching unit receives the binarized signal. One end of the capacitance unit is connected to the connection node between the resistor unit and the switching unit. The other end of the capacitance unit is connected to the reference voltage unit. The signal processing circuit according to embodiment 5, wherein the input terminal of the inverter is connected to the connection node. [Aspect 7] The aforementioned time filter unit comprises a clock generation unit and a logic unit. The clock generation unit outputs a clock signal having a clock period equivalent to the predetermined time. The logic unit receives the clock signal and the binarization signal as inputs. The aforementioned logic unit is If the period during which the binarized signal is at the first level is longer than the clock period, the first state is detected by inverting the output of the logic unit. A signal processing circuit according to any one of embodiments 1-4, wherein the second state is detected by inverting the output of the logic unit when the period during which the binarized signal is at the second level is longer than the clock period. [Aspect 8] The logic unit comprises an asynchronous reset type first D flip-flop and a second D flip-flop. The clock signal is input to the first D flip-flop and the second D flip-flop, The binarized signal is input to the input terminal and reset terminal of the first D flip-flop. The output of the first D flip-flop is input to the input terminal of the second D flip-flop. If the period during which the binarized signal is at the first level or the second level is longer than the clock period, The state in which the output of the first D flip-flop is inverted is maintained for the duration of the clock period. The signal processing circuit according to embodiment 7, wherein the output of the second D flip-flop inverts in sync with the edge of the clock signal, thereby detecting the first state or the second state. [Aspect 9] The binarization unit includes a comparator having a first input terminal and a second input terminal. The analog input signal is input to the first input terminal and the comparison AC signal is input to the second input terminal, or a signal obtained by adding the comparison AC signal to the analog input signal is input to the first input terminal and a reference voltage signal is input to the second input terminal. The signal processing circuit according to any one of aspects 1-8. [Aspect 10] A signal processing method including an AC signal generation step, a binarization step, and a time filter step, The AC signal generation step is a step of generating a comparison AC signal having a predetermined frequency and a predetermined amplitude determined by a first threshold value and a second threshold value smaller than the first threshold value. The binarization step is a step of generating a binarized signal based on the comparison AC signal and the analog input signal. The binarization step is When the analog input signal is within the range from the second threshold value to the first threshold value, the binarized signal, which is an AC signal corresponding to the comparison AC signal, is generated. When the analog input signal is greater than the first threshold value, the binarized signal, which is a DC signal of the first level, is generated. When the analog input signal is smaller than the second threshold value, the binarized signal, which is a DC signal of the second level, is generated. The time filter step detects a first state in which a period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which a period during which the binarized signal is at the second level is longer than the predetermined time. Signal processing method.

Description of Reference Numerals

[0058] 1: Signal processing circuit 11: AC signal generation unit 12: Binarization unit 13: Time filter unit f REF : Predetermined frequency AS: Comparison AC signal VT1: First threshold value VT2: Second threshold value PA: Predetermined amplitude IS: Analog input signal CO: Binarized signal TT: Predetermined time

Claims

1. A signal processing circuit comprising an AC signal generation unit, a binarization unit, and a time filter unit, The AC signal generation unit outputs a comparative AC signal having a predetermined frequency and a predetermined amplitude determined by a first threshold and a second threshold smaller than the first threshold. The binarization unit receives the comparison AC signal and the analog input signal. The binarization unit outputs a binarized signal. The binarization unit is, When the analog input signal is within the range from the second threshold to the first threshold, the binarized signal, which is an AC signal corresponding to the comparison AC signal, is output. When the analog input signal is greater than the first threshold, the binarized signal, which is a first-level DC signal, is output. When the analog input signal is smaller than the second threshold, the binarized signal, which is a second-level DC signal, is output. The binarized signal is input to the time filter unit. The time filter unit is configured to detect a first state in which the period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which the period during which the binarized signal is at the second level is longer than the predetermined time. Signal processing circuit.

2. The analog input signal includes a specific signal having pulses with a predetermined pulse time width or longer. The signal processing circuit according to claim 1, wherein the predetermined time is smaller than the predetermined pulse time width.

3. The signal processing circuit according to claim 2, wherein the predetermined frequency of the comparison AC signal is a frequency higher than the reciprocal of the predetermined time.

4. The signal processing circuit according to claim 3, wherein the predetermined amplitude value of the comparison AC signal is a value such that the probability of the time filter unit detecting the first state and the second state when the analog input signal does not contain the specific signal is less than or equal to a predetermined target value.

5. The aforementioned time filter unit comprises a charge / discharge unit, a capacity unit, and an inverter. The charging / discharging unit is configured to charge or discharge the capacity unit based on the binarization signal, The output voltage of the capacitive unit is input to the inverter. The time constant for charging and discharging by the charging / discharging unit and the capacity unit is equivalent to the predetermined time. The signal processing circuit according to any one of claims 1 to 4, wherein the output of the inverter is inverted in response to the capacity unit being charged or discharged beyond the aforementioned time constant, thereby enabling the detection of the first state or the second state.

6. The charging and discharging section comprises a resistor section and a switching section connected in series between the power supply voltage section and the reference voltage section. The input terminal of the switching unit receives the binarized signal. One end of the capacitance unit is connected to the connection node between the resistor unit and the switching unit. The other end of the capacitance unit is connected to the reference voltage unit. The signal processing circuit according to claim 5, wherein the input terminal of the inverter is connected to the connection node.

7. The aforementioned time filter unit comprises a clock generation unit and a logic unit. The clock generation unit outputs a clock signal having a clock period equivalent to the predetermined time. The logic unit receives the clock signal and the binarization signal as inputs. The aforementioned logic unit is If the period during which the binarized signal is at the first level is longer than the clock period, the first state is detected by inverting the output of the logic unit. The signal processing circuit according to any one of claims 1 to 4, wherein the second state is detected by inverting the output of the logic unit when the period during which the binarized signal is at the second level is longer than the clock period.

8. The logic unit comprises an asynchronous reset type first D flip-flop and a second D flip-flop. The clock signal is input to the first D flip-flop and the second D flip-flop. The binarized signal is input to the input terminal and reset terminal of the first D flip-flop. The output of the first D flip-flop is input to the input terminal of the second D flip-flop. If the period during which the binarized signal is at the first level or the second level is longer than the clock period, The state in which the output of the first D flip-flop is inverted is maintained for the duration of the clock period. The signal processing circuit according to claim 7, wherein the output of the second D flip-flop inverts in sync with the edge of the clock signal, thereby detecting the first state or the second state.

9. The binarization unit includes a comparator having a first input terminal and a second input terminal. The analog input signal is input to the first input terminal and the comparison AC signal is input to the second input terminal, or the signal obtained by adding the comparison AC signal to the analog input signal is input to the first input terminal and a reference voltage signal is input to the second input terminal. A signal processing circuit according to any one of claims 1 to 4.

10. A signal processing method comprising an AC signal generation step, a binarization step, and a time filtering step, The AC signal generation step is a step of generating a comparative AC signal having a predetermined frequency and having a predetermined amplitude determined by a first threshold and a second threshold smaller than the first threshold, The binarization step is a step of generating a binarized signal based on the comparison AC signal and the analog input signal. The aforementioned binarization step is: When the analog input signal is within the range from the second threshold to the first threshold, the binarized signal, which is an AC signal corresponding to the comparison AC signal, is generated. When the analog input signal is greater than the first threshold, the binarized signal, which is a first-level DC signal, is generated. When the analog input signal is smaller than the second threshold, the binarized signal, which is a second-level DC signal, is generated. The time filtering step detects a first state in which the period during which the binarized signal is at the first level is longer than a predetermined time, and a second state in which the period during which the binarized signal is at the second level is longer than the predetermined time. Signal processing method.

Images