Semiconductor equipment

Abstract

To improve the reliability of semiconductor devices containing oxide semiconductors. [Solution] The semiconductor device includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, an oxide semiconductor layer on the gate insulating layer, a first insulating layer on the oxide semiconductor layer, and a first pattern layer made of an insulator on the first insulating layer, wherein the oxide semiconductor layer has a channel portion and a conductive portion, and in a plan view, the first pattern layer overlaps the channel portion.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a display device.

Background Art

[0002] In recent years, as materials for semiconductor devices, oxide semiconductors have attracted attention in place of amorphous silicon, polysilicon, and single-crystalline silicon. In particular, as semiconductor devices including oxide semiconductors, the development of thin-film transistors using an oxide semiconductor as a channel has been underway (for example, Patent Documents 1 to 6). A thin-film transistor using an oxide semiconductor as a channel can be formed with a simple structure and a low-temperature process, similar to a semiconductor device using amorphous silicon as a channel. A thin-film transistor using an oxide semiconductor as a channel is known to have a higher field-effect mobility than a thin-film transistor using amorphous silicon as a channel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventionally, thin-film transistors using oxide semiconductors have been studied in various device structures, including top-gate and bottom-gate structures, but they have several challenges in terms of reliability. For example, with conventional device structures, it is difficult to achieve both the breakdown voltage characteristics of the gate insulating layer (specifically, resistance to high voltages applied between the gate and source, or between the gate and drain) and the suppression of damage to the oxide semiconductor layer. Therefore, there is still room for improvement in the reliability of conventional thin-film transistors using oxide semiconductors.

[0005] One of the objectives of this invention is to improve the reliability of semiconductor devices containing oxide semiconductors. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, an oxide semiconductor layer on the gate insulating layer, a first insulating layer on the oxide semiconductor layer, and a first pattern layer made of an insulator on the first insulating layer, wherein the oxide semiconductor layer has a channel portion and a conductive portion, and in a plan view, the first pattern layer overlaps the channel portion. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 2] This is a schematic plan view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 3] This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6]It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 14] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 15] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a sequence diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 22]It is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 23] It is a sequence diagram showing a method of manufacturing a semiconductor device in one embodiment of the present invention. [Figure 24] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device in one embodiment of the present invention. [Figure 25] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device in one embodiment of the present invention. [Figure 26] It is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 27] It is a schematic plan view showing the overall configuration of a display device in one embodiment of the present invention. [Figure 28] It is a block diagram showing the circuit configuration of a display device in one embodiment of the present invention. [Figure 29] It is a circuit diagram showing the configuration of a pixel circuit of a display device in one embodiment of the present invention. [Figure 30] It is a cross-sectional view showing the configuration of a pixel of a display device in one embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. The drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect in order to make the explanation clearer. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previously presented figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but for example, the substrate and oxide semiconductor layer may be arranged in the opposite way to what is shown in the figures. In the following description, for example, the expression "oxide semiconductor layer on the substrate" merely describes the upward and downward relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer.

[0010] The term "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, although the embodiments described later will use an organic EL display device including an organic EL layer as an example, the structure in these embodiments can be applied to other display devices including electro-optical layers, such as liquid crystal display devices including a liquid crystal layer.

[0011] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] In this specification, “identical” includes not only perfectly identical but also substantially identical. “Substantially identical” means that the differences are not perfectly identical but are within a range of minor differences that can be considered identical, for example, within an error range of ±5% (preferably ±3%).

[0013] <First Embodiment> A semiconductor device according to one embodiment of the present invention will be described using a thin-film transistor as an example. The semiconductor device of the embodiment shown below may be a thin-film transistor used in a display device (for example, an organic EL display device or a liquid crystal display device), or it may be a thin-film transistor used in an integrated circuit (IC) such as a microprocessing unit (MPU), or in a memory circuit.

[0014] [Configuration of semiconductor device] The configuration of the semiconductor device 10 in one embodiment of the present invention will be described. Figure 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 in one embodiment of the present invention. Figure 2 is a schematic plan view showing the configuration of the semiconductor device 10 in one embodiment of the present invention. Specifically, Figure 1 corresponds to a cross-sectional view cut along the dashed line shown A-A' in Figure 2.

[0015] First, the cross-sectional structure of the semiconductor device 10 will be described using Figure 1. As shown in Figure 1, the semiconductor device 10 is provided above the substrate 100. The semiconductor device 10 includes a gate electrode 105, a gate insulating layer 110, an oxide semiconductor layer 130, an insulating layer 140, a pattern layer 151 made of metal oxide, a pattern layer 161 made of insulating material, and a terminal electrode 171.

[0016] The gate electrode 105 is provided on the substrate 100. The gate electrode 105 functions as the gate of the semiconductor device 10 (thin-film transistor). Specifically, the gate electrode 105 has the role of applying a gate voltage to the channel portion 131 of the oxide semiconductor layer 130, which will be described later. An insulating layer (not shown) may be provided on the substrate 100. That is, the gate electrode 105 can be placed directly or indirectly on the substrate 100. In other words, the gate electrode 105 is provided on an insulating surface.

[0017] The gate insulating layer 110 is provided on the substrate 100 and the gate electrode 105. The gate insulating layer 110 functions as a barrier film that shields against impurities diffusing from the substrate 100 toward the oxide semiconductor layer 130, and also functions as a base for the oxide semiconductor layer 130 positioned above it.

[0018] Although not shown in the diagram, in this embodiment, the gate insulating layer 110 has a two-layer structure to match the functions described above. Specifically, a silicon nitride layer is used as the insulating layer on the lower side (closer to the substrate 100), and a silicon oxide layer is used as the insulating layer on the upper side (closer to the oxide semiconductor layer 130). In this embodiment, the thickness of the lower insulating layer is 200 nm, and the thickness of the upper insulating layer is 100 nm, so the thickness of the gate insulating layer 110 is 300 nm. That is, in this embodiment, the thickness of the gate insulating layer 110 can be 200 nm or more (preferably 300 nm or more, and even more preferably 400 nm or more).

[0019] The oxide semiconductor layer 130 is provided on the gate insulating layer 110. The oxide semiconductor layer 130 has a channel portion 131 and a conductive portion 132 that are continuous in a first direction. The channel portion 131 functions as a channel region of the semiconductor device 10. The conductive portion 132 functions as a source region or drain region of the semiconductor device 10. The conductive portion 132 is a region with lower resistance than the channel portion 131 and has the role of transmitting carriers flowing through the channel portion 131 to the terminal electrode 171.

[0020] The insulating layer 140 is provided on top of the oxide semiconductor layer 130. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 is a dielectric layer that electrically insulates the layer on which the terminal electrode 171 (described later) is formed from the layer on which the oxide semiconductor layer 130 is formed. The thickness of the insulating layer 140 is 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 50 nm to 100 nm). The thickness of the insulating layer 140 is thinner than the thickness of the gate insulating layer 110. The advantages of having a thin insulating layer 140 will be described later.

[0021] The pattern layer 151, composed of a metal oxide, is provided on top of the insulating layer 140. The pattern layer 151 is obtained by processing the metal oxide layer into island shapes by patterning. The pattern layer 151 functions as a barrier layer that suppresses hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130. As will be described in detail later, the pattern layer 151 is a patterned layer of the metal oxide layer 150 (see Figure 6) that was used in the manufacturing process of the semiconductor device 10 when performing a heat treatment to supply oxygen to the oxide semiconductor layer 130.

[0022] The pattern layer 151 is positioned above the oxide semiconductor layer 130 via the insulating layer 140. In other words, the insulating layer 140 is in contact with both the oxide semiconductor layer 130 and the pattern layer 151. The pattern layer 151 overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as shown in Figure 1 using the dashed line, in a cross-sectional view, the position of the edge 151a of the pattern layer 151 and the position of the edge 131a of the channel portion 131 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 151a of the pattern layer 151 and the position of the boundary between the channel portion 131 and the conductive portion 132 coincide in the vertical direction. The reason why the position of the edge 151a of the pattern layer 151 and the position of the edge 131a of the channel portion 131 coincide will be explained later.

[0023] The pattern layer 161, composed of an insulating material, is provided on top of the pattern layer 151. The pattern layer 161 is obtained by processing an insulating layer such as silicon oxide into island shapes by patterning. The pattern layer 161 functions as a barrier layer that suppresses hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130. For example, if an insulating layer containing a large amount of oxygen or an insulating layer containing many defects is used as the insulating layer constituting the pattern layer 161, the oxygen and defects function as hydrogen traps.

[0024] In this embodiment, since the pattern layer 151 is formed using a resist mask 210 (see Figure 7) used when patterning the pattern layer 161, the pattern layer 151 and the pattern layer 161 have the same pattern shape. That is, the pattern layer 161, like the pattern layer 151, overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as shown in Figure 1 using a dashed line, in a cross-sectional view, the position of the edge 161a of the pattern layer 161 and the position of the edge 131a of the channel portion 131 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 161a of the pattern layer 161 and the position of the boundary between the channel portion 131 and the conductive portion 132 coincide in the vertical direction.

[0025] The terminal electrode 171 is placed on the insulating layer 140 and is electrically connected to the conductive part 132 via a contact hole 141 provided in the insulating layer 140. The terminal electrode 171 has the role of supplying carriers to the conductive part 132 and extracting carriers from the conductive part 132. In other words, the terminal electrode 171 functions as either a source electrode or a drain electrode of the semiconductor device 10 (thin-film transistor) depending on the role of the conductive part 132. Specifically, the terminal electrode 171 functions as a source electrode when the electrically connected conductive part 132 functions as a source region, and functions as a drain electrode when the electrically connected conductive part 132 functions as a drain region.

[0026] In this embodiment, the semiconductor device 10 is exemplified as a bottom-gate type transistor in which a gate electrode 105 is provided below an oxide semiconductor layer 130, but the configuration is not limited to this. For example, the semiconductor device 10 can also be made into a dual-gate type transistor by placing another gate electrode on top of the insulating layer 140 (on top of the pattern layer 151 in the example shown in Figure 1).

[0027] Next, the planar structure of the semiconductor device 10 will be described using Figure 2. As shown in Figure 2, the first direction (D1 direction) is the direction connecting the two terminal electrodes 171 to each other (the direction in which the channel portion 131 and the conductive portion 132 are continuous), and corresponds to the direction in which the carriers move. The length of the channel portion 131 in the first direction of the oxide semiconductor layer 130 is the channel length (L), and the length of the channel portion 131 in the second direction (D2 direction) is the channel width (W). The second direction is the direction that intersects the first direction. In this embodiment, the second direction is shown as being perpendicular to the first direction, but depending on the layout of the oxide semiconductor layer 130, the first direction and the second direction may not be perpendicular.

[0028] In this embodiment, in the first direction, the width of the gate electrode 105 is wider than the length of the channel portion 131 (channel length). The reason for this configuration is to effectively prevent external light from entering the channel portion 131. However, this is not the only example, and the width of the gate electrode 105 may be the same as the length of the channel portion 131.

[0029] As shown in Figure 2, in a plan view, the pattern layer 161, which is made of an insulating material, is arranged to overlap with the oxide semiconductor layer 130. Specifically, in a plan view, the pattern layer 161 is arranged to intersect with the channel portion 131 of the oxide semiconductor layer 130. Thus, it is desirable that the width of the pattern layer 161 in the second direction be wider than the width (W) of the oxide semiconductor layer 130 in the second direction. Such a configuration is effective in allowing the above-mentioned function of the pattern layer 161 (the function of suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130) to work effectively.

[0030] Furthermore, in a plan view, the outer edge of the portion of the pattern layer 161 that overlaps with the oxide semiconductor layer 130 coincides with the outer edge of the channel portion 131. In other words, the pattern layer 161 intersects with the channel portion 131 and does not overlap with the conductive portion 132. However, the expression "the pattern layer 161 intersects with the channel portion 131 and does not overlap with the conductive portion 132" includes cases where the pattern layer 161 overlaps with a portion of the conductive portion 132 within the margin of error. As will be described later, the conductive portion 132 is formed by adding impurities to the oxide semiconductor layer 130 by methods such as ion implantation. Therefore, due to the leakage of impurities below the pattern layer 161, there may be cases where a small portion of the conductive portion 132 slightly overlaps with the pattern layer 161. Note that the positional relationship between the pattern layer 161 and the oxide semiconductor layer 130 has been explained here. However, as mentioned above, since pattern layer 151 and pattern layer 161 have the same pattern shape, the positional relationship between pattern layer 151 and oxide semiconductor layer 130 is also the same.

[0031] Figure 2 illustrates a configuration in which the terminal electrodes 171 do not overlap with the gate electrode 105 in a plan view, but the configuration is not limited to this. For example, in a plan view, both or one of the two terminal electrodes 171 may overlap with the gate electrode 105.

[0032] [Materials of each layer in a semiconductor device] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a translucent rigid substrate such as a glass substrate, quartz substrate, or sapphire substrate can be used as the substrate 100. Alternatively, a non-translucent rigid substrate such as a silicon substrate can be used. Furthermore, a translucent flexible substrate such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate can be used as the substrate. Impurities may be introduced into the resin substrate to improve the heat resistance of the substrate 100. In addition, a substrate on which a silicon oxide film or silicon nitride film is deposited can also be used as the substrate 100.

[0033] As described above, since the gate electrode 105 has a larger area than the channel portion 131 of the oxide semiconductor layer 130, it is preferable to use a material that can block ambient light incident on the channel portion 131. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof can be used as the gate electrode 105. The gate electrode 105 may have a single-layer structure or a multilayer structure.

[0034] As the gate insulating layer 110, for example, silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) can be used. Here, silicon oxide nitride (SiOxNy) and aluminum oxide nitride (AlOxNy) are silicon and aluminum compounds, respectively, that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). Similarly, silicon oxide nitride (SiNxOy) and aluminum oxide nitride (AlNxOy) are silicon and aluminum compounds, respectively, that contain oxygen in a smaller proportion (x>y) than nitrogen. In this embodiment, the gate insulating layer 110 has a two-layer structure, with a silicon nitride layer used as the lower insulating layer and a silicon oxide layer used as the upper insulating layer.

[0035] The oxide semiconductor layer 130 may have an amorphous structure or a polycrystalline structure.

[0036] The insulating layer 140 contains an insulating oxide. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), etc. can be used as the insulating layer 140. In this embodiment, a silicon oxide layer with a thickness of 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 50 nm to 100 nm) is used as the insulating layer 140.

[0037] The pattern layer 151 is composed of a metal oxide. In this embodiment, an aluminum oxide (e.g., aluminum oxide) is used as the metal oxide constituting the pattern layer 151. Since aluminum oxide has high barrier properties against gases, the pattern layer 151 has the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. The thickness of the pattern layer 151 can be, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm.

[0038] The pattern layer 161 is composed of an insulator. In this embodiment, the insulator constituting the pattern layer 161 can be, for example, an insulator mainly composed of silicon, such as silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride (SiNx), or silicon oxide nitride (SiNxOy). As described above, by using an insulator containing a large amount of oxygen or an insulator containing a large amount of defects as the insulator, the pattern layer 161 can be given the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. The thickness of the pattern layer 161 can be, for example, 100 nm to 300 nm, 150 nm to 250 nm, or 175 nm to 200 nm.

[0039] The terminal electrode 171 is conductive. For example, the material of the terminal electrode 171 can be copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof. The terminal electrode 171 may have a single-layer structure or a multilayer structure.

[0040] [Manufacturing method for semiconductor devices] Next, a method for manufacturing the semiconductor device 10 in one embodiment of the present invention will be described. Figure 3 is a sequence diagram showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention. Figures 4 to 12 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention.

[0041] As shown in Figures 3 and 4, a gate electrode 105 is formed on the substrate 100, and a gate insulating layer 110 is formed on the gate electrode 105 (step S1001 in Figure 4). For example, a laminated structure of a silicon nitride layer and a silicon oxide layer is formed as the gate insulating layer 110. The gate insulating layer 110 is formed by the CVD (Chemical Vapor Deposition) method. In this specification, the act of forming a film on a substrate by methods such as sputtering or CVD may be expressed as "forming a thin film," but this is used in the same sense as the expression "depositing a thin film."

[0042] If a silicon nitride layer is provided as part of the gate insulating layer 110 on the side closer to the substrate 100, impurities diffusing from the substrate 100 towards the oxide semiconductor layer 130 can be blocked. If a silicon oxide layer is provided as part of the gate insulating layer 110 on the side in contact with the oxide semiconductor layer 130 that is formed later, the characteristics of the interface between the gate insulating layer 110 and the oxide semiconductor layer 130 are improved.

[0043] The silicon oxide layer can have its oxygen content increased by setting a relatively low deposition temperature. As will be described later, increasing the amount of oxygen contained in the gate insulating layer 110 can reduce the amount of hydrogen that diffuses into the oxide semiconductor layer 130. The deposition temperature for the gate insulating layer 110 should be set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0044] Next, as shown in Figures 3 and 5, a patterned oxide semiconductor layer 130 is formed on the gate insulating layer 110 (step S1002 in Figure 3). In this embodiment, the process of forming the oxide semiconductor layer 130 is referred to as "OS pattern formation". In other words, the oxide semiconductor layer 130 is formed by applying a patterning process to the oxide semiconductor layer deposited on the gate insulating layer 110. In the description of this embodiment, when "oxide semiconductor layer" is written without a reference numeral, it refers to the oxide semiconductor layer in its deposited state (i.e., in its unprocessed state).

[0045] The oxide semiconductor layer may be etched using either wet etching or dry etching. In wet etching, for example, an acidic etchant (oxalic acid or hydrofluoric acid) can be used.

[0046] In this embodiment, the oxide semiconductor layer is formed by sputtering. The thickness of the oxide semiconductor layer to be formed is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm.

[0047] When a thin film is formed on a substrate by sputtering, ions generated in the plasma and atoms recoiling from the sputtering target collide with the object being formed on (specifically, the structure formed on the substrate 100), causing the temperature of the substrate to rise during the thin film formation process.

[0048] To control the substrate temperature (i.e., film deposition temperature) when forming the oxide semiconductor layer, for example, the thin film may be formed while cooling the substrate. For example, the substrate can be cooled from the side opposite to the surface to be formed so that the film deposition temperature is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film deposition temperature of the oxide semiconductor layer in this embodiment is preferably 50°C or less. In this embodiment, the oxide semiconductor layer is formed at a film deposition temperature of 50°C or less, and the OS annealing described later is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, it is preferable that the difference between the temperature when forming the oxide semiconductor layer and the temperature when performing OS annealing on the oxide semiconductor layer 130 is 350°C or more.

[0049] Next, after forming the oxide semiconductor layer 130 by patterning, the oxide semiconductor layer 130 is subjected to a heat treatment (OS annealing) (step S1003 in Figure 3). In OS annealing, the oxide semiconductor layer 130 is heat-treated in an air atmosphere at a temperature of 250°C to 500°C (preferably 300°C to 500°C, and more preferably 350°C to 450°C). The heating atmosphere is not limited to an air atmosphere, but an oxidizing atmosphere (an atmosphere containing oxygen) is preferred. The heat treatment time is 15 minutes to 120 minutes, or 30 minutes to 60 minutes, after reaching the predetermined temperature.

[0050] In this embodiment, a substrate on which an oxide semiconductor layer 130 is formed is placed in a heating furnace having a heating medium (e.g., a support plate) maintained at a pre-set temperature (250°C to 500°C). The support plate, acting as the heating medium, serves to support the substrate and to heat the substrate and the coating (including the oxide semiconductor layer 130) formed on it. When the substrate on which the oxide semiconductor layer 130 is formed is placed on the support plate, the oxide semiconductor layer 130 is rapidly heated. When the substrate is placed in the heating furnace, it is desirable to keep the temperature drop of the support plate within 15%, 10%, or 5% of the set temperature. In other words, it is preferable to control the temperature of the support plate so that the oxide semiconductor layer 130 reaches the set temperature in the shortest possible time.

[0051] Next, as shown in Figures 3 and 6, an insulating layer 140 and a metal oxide layer 150 are formed (step S1004 in Figure 3). For example, a silicon oxide layer is formed as the insulating layer 140. The insulating layer 140 is formed by the CVD method. In this embodiment, the film formation temperature of the insulating layer 140 is 350°C. The thickness of the insulating layer 140 is, for example, 50 nm to 200 nm, 50 nm to 150 nm, or 50 nm to 100 nm. In this embodiment, the thickness of the insulating layer 140 is 100 nm.

[0052] The metal oxide layer 150 is formed by sputtering. By using sputtering to deposit the metal oxide layer 150, oxygen is injected into the insulating layer 140 during the formation of the metal oxide layer 150. Therefore, the insulating layer 140 contains a large amount of oxygen after the metal oxide layer 150 has been formed. The thickness of the metal oxide layer 150 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 150. As mentioned above, aluminum oxide has high barrier properties against gases, so it can suppress the upward diffusion of oxygen injected into the insulating layer 140 during the heat treatment described later.

[0053] When the metal oxide layer 150 is formed by sputtering, the process gas used in sputtering remains in the metal oxide layer 150. For example, if Ar is used as the process gas for sputtering, Ar may remain in the metal oxide layer 150. The remaining Ar is SIMS (Secondary It can be detected by ion mass spectrometry (ION) analysis, etc. That is, if Ar is used as the process gas for sputtering, Ar will be detected in SIMS analysis of the pattern layer 151 obtained by patterning the metal oxide layer 150.

[0054] Next, with the metal oxide layer 150 formed on the insulating layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 130 (step S1005 in Figure 3). During the process between the formation of the oxide semiconductor layer 130 and the formation of the insulating layer 140 on the oxide semiconductor layer 130, oxygen vacancies may occur on the upper and side surfaces of the oxide semiconductor layer 130. Oxidation annealing supplies oxygen released from the gate insulating layer 110 and the insulating layer 140 to the oxide semiconductor layer 130, repairing the oxygen vacancies. Oxidation annealing should be performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, and more preferably 350°C to 450°C).

[0055] During the oxide annealing process, oxygen released from the gate insulating layer 110 and the insulating layer 140 is supplied to the oxide semiconductor layer 130. If a silicon nitride layer is used for part of the gate insulating layer 110, hydrogen may be released from the gate insulating layer 110 during the oxide annealing process. However, most of the released hydrogen is captured by the oxygen contained in the silicon oxide layer located above it before it reaches the oxide semiconductor layer 130.

[0056] As described above, oxygen can be supplied to the oxide semiconductor layer 130 by oxide annealing. During oxide annealing, the upward diffusion of oxygen injected into the insulating layer 140 is blocked by the metal oxide layer 150, thus suppressing its release into the atmosphere. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during oxide annealing.

[0057] Next, as shown in Figures 3 and 7, an insulating layer 160 is formed on the metal oxide layer 150, and a resist mask 210 is further formed on the insulating layer 160 (step S1006 in Figure 3). In this embodiment, a silicon oxynitride (SiOxNy) layer is used as the insulating layer 160. Since the insulating layer 160 is a silicon oxynitride layer, the amount of oxygen it contains can be increased by setting the film deposition temperature to a relatively low level. By increasing the amount of oxygen contained in the insulating layer 160, hydrogen diffusion from above into the oxide semiconductor layer 130 can be effectively suppressed. The film deposition temperature for the insulating layer 160 should be set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0058] The resist mask 210 is positioned to overlap with the oxide semiconductor layer 130. As will be described later, the portion of the oxide semiconductor layer 130 that overlaps with the resist mask 210 corresponds to the portion where the channel portion 131 is formed. As shown in Figure 2, the resist mask 210 is positioned to intersect with the oxide semiconductor layer 130 in the second direction.

[0059] Next, as shown in Figures 3 and 8, the metal oxide layer 150 and the insulating layer 160 are etched using the resist mask 210 as a mask to form a pattern layer 151 composed of metal oxide and a pattern layer 161 composed of insulating material (step S1007 in Figure 3). The etching of the metal oxide layer 150 and the insulating layer 160 may be wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0060] When etching the insulating layer 160, it is preferable that the selectivity ratio between the metal oxide layer 150 and the insulating layer 160 is high. If the selectivity ratio is high, the metal oxide layer 150 can be used as an etching stopper in etching the insulating layer 160. In this case, after etching the insulating layer 160, the etchant or etching gas can be changed to etch the metal oxide layer 150. Furthermore, when etching the metal oxide layer 150, it is also preferable that the selectivity ratio between the insulating layer 140 and the metal oxide layer 150 is high.

[0061] Next, as shown in Figures 3 and 9, the resist mask 210 is removed (step S1008 in Figure 3). By removing the resist mask 210, a pattern layer 151 made of metal oxide and a pattern layer 161 made of insulating material remain on the insulating layer 140.

[0062] Next, as shown in Figures 3 and 10, ion implantation is performed from above the pattern layer 161, which is made of an insulating material, to add impurities to the oxide semiconductor layer 130 (step S1009 in Figure 3). Phosphorus, boron, argon, etc., can be used as impurities. The purpose of adding impurities is to create oxygen vacancies in a portion of the oxide semiconductor layer 130 to improve conductivity; therefore, it is preferable to use elements with a large atomic radius as impurities. This embodiment shows an example of adding impurities by ion implantation, but ion doping may also be used. In this embodiment, boron is added using ion implantation. The ion implantation conditions in this embodiment are an acceleration voltage of 30 keV and a dose of 1 × 10⁻⁶. 15 / cm 2 However, this is not the only example.

[0063] As shown in Figure 10, when impurities are ion-implanted into the oxide semiconductor layer 130, conductive portions 132 are formed in the oxide semiconductor layer 130. At this time, the regions where impurities are not implanted and the original state is maintained function as channel portions 131. That is, in a cross-sectional view, the positions of the edges of the pattern layers 151 and 161 and the positions of the edges of the channel portions 131 coincide in the vertical direction.

[0064] Impurities are added to the conductive portion 132 via the insulating layer 140. As described above, the conductive portion 132 functions as either the source region or the drain region of the semiconductor device 10.

[0065] In this embodiment, since the insulating layer 140 does not need to be used as a gate insulating layer, its thickness can be set to 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 50 nm to 100 nm). Also, since the metal oxide layer 150 is removed in areas other than directly beneath the pattern layer 161, the insulating layer 140 is exposed. In other words, impurities can be added to the oxide semiconductor layer 130 without going through the metal oxide layer, which has high barrier properties against gases. Thus, in this embodiment, the thickness of the insulating layer 140 can be reduced, and since it is not necessary to pass through the dense metal oxide layer, the dose of impurities can be increased even with a relatively low acceleration voltage. In other words, a sufficient amount of impurities can be added to the oxide semiconductor layer 130 without placing an excessive burden on the manufacturing equipment used for impurity addition, so the resistance value of the conductive part 132 can be sufficiently reduced.

[0066] Furthermore, in this embodiment, the pattern layer 161 can be used as a mask, eliminating the need to use the resist mask 210 as a mask for impurity addition. If a large amount of impurities are injected into the resist mask 210, it may become difficult to remove, but this problem does not occur in this embodiment. However, this is not the only example, and impurities may be added while the resist mask 210 remains on the pattern layer 161.

[0067] Next, as shown in Figures 3 and 11, a contact hole 141 is formed in the insulating layer 140 (step S1010 in Figure 3). The contact hole 141 exposes a portion of the conductive portion 132. In this embodiment, since the metal oxide layer 150 located directly above the conductive portion 132 has been removed, there is an advantage in that the formation of the contact hole 141 is easy.

[0068] Finally, as shown in Figures 3 and 12, terminal electrodes 171 are formed on the conductive portion 132 exposed by the contact hole 141 (step S1011 in Figure 3). The semiconductor device 10 shown in Figure 1 is completed by the process described above.

[0069] In this embodiment, the semiconductor device 10 can use an insulating layer with a thickness of 200 nm or more (preferably 300 nm or more) as the gate insulating layer 110, thereby ensuring sufficient breakdown voltage characteristics of the gate insulating layer. Furthermore, when forming the conductive portion 132 in the oxide semiconductor layer 130, the resistance is reduced by adding impurities via the insulating layer 140, thereby suppressing damage to the oxide semiconductor layer 130 (especially damage to the channel portion 131). At this time, since the thickness of the insulating layer 140 is 200 nm or less (preferably 150 nm or less), the resistance value of the conductive portion 132 can be sufficiently reduced by adding a sufficient amount of impurities while suppressing the load on the equipment used for impurity addition. As described above, according to this embodiment, the reliability of the semiconductor device 10 including an oxide semiconductor can be improved.

[0070] In this specification, "field-effect mobility" refers to the field-effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field-effect mobility in the region where the potential difference between the source and drain (Vd) is greater than the value obtained by subtracting the threshold voltage of the semiconductor device 10 (Vth) from the voltage supplied to the gate (Vg) (Vg-Vth).

[0071] (Modification 1 of the first embodiment) In the semiconductor device 10 described above, an example was shown in which the metal oxide layer 150 is etched to form a pattern layer 151 composed of metal oxide, but it is also possible to leave the metal oxide layer 150 without etching.

[0072] Figure 13 is a schematic cross-sectional view showing the configuration of a semiconductor device 10a in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 10a has a metal oxide layer 150 remaining on top of the insulating layer 140 without being patterned. That is, the metal oxide layer 150 is superimposed not only on the channel portion 131 of the oxide semiconductor layer 130 but also on the conductive portion 132.

[0073] In the semiconductor device 10a of this modified example, the metal oxide layer 150 functions as a barrier layer that suppresses hydrogen diffusion from above into the oxide semiconductor layer 130, similar to the pattern layer 151 shown in Figure 1.

[0074] (Modification 2 of the first embodiment) In the semiconductor device 10 described above, an example was shown in which the metal oxide layer 150 is etched to form a pattern layer 151 composed of metal oxide. However, it is also possible to etch and remove the metal oxide layer 150 without patterning it.

[0075] Figure 14 is a schematic cross-sectional view showing the configuration of a semiconductor device 10b in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 10b undergoes oxidation annealing as shown in step S1005 of Figure 3, after which the metal oxide layer 150 formed on the insulating layer 140 is etched and completely removed. In other words, in this modified example, there is no metal oxide layer 150 or pattern layer 151 composed of metal oxide on the insulating layer 140.

[0076] According to this modified example, in the process of adding impurities to the oxide semiconductor layer 130 shown in S1008 of Figure 3, a sufficiently large dose of impurities can be added even if the acceleration voltage is set to a low value. Furthermore, according to this modified example, the formation of contact holes 141 in the insulating layer 140 shown in S1010 of Figure 3 is facilitated.

[0077] In this modified example, dry etching is preferred when etching the insulating layer 160 to form a pattern layer 161 composed of an insulating material. In this embodiment, the underlying insulating layer 140 is a silicon oxide layer, and the insulating layer 160 is a silicon oxide layer containing nitrogen. Therefore, the etching endpoint of the insulating layer 160 can be confirmed by monitoring the amount of nitrogen in the reaction gas. Using this technique, it is possible to prevent over-etching of the underlying insulating layer 140 after forming the pattern layer 161 composed of an insulating material.

[0078] <Second Embodiment> In this embodiment, a semiconductor device 20 with a different layer structure from the semiconductor device 10 of the first embodiment will be described. In the description of this embodiment, elements identical to those in the first embodiment may be shown in the drawings using the same reference numerals and their descriptions may be omitted.

[0079] [Configuration of semiconductor device] Figure 15 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 in one embodiment of the present invention. The differences from the semiconductor device 10 shown in Figure 1 are that an insulating layer 180 is provided on top of a pattern layer 161 composed of an insulating layer 140 and an insulating material, and terminal electrodes 191 are provided on top of the insulating layer 180.

[0080] In this embodiment, insulating layers 140 and 180 are used to insulate the oxide semiconductor layer 130 from the terminal electrode 191. The insulating layer 180 can be any insulating layer selected from, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or silicon oxide nitride (SiOxNy). The insulating layer 180 may also be composed of a resin material such as acrylic or polyimide. Furthermore, the insulating layer 180 may be a single-layer structure including a layer made of the above-mentioned material, or it may be a laminated structure.

[0081] The terminal electrode 191 is electrically connected to the conductive portion 132 of the oxide semiconductor layer 130 via a contact hole 181 formed in a laminated structure composed of an insulating layer 140 and an insulating layer 180. In this embodiment, the layer on which the terminal electrode 191 is formed and the layer on which the oxide semiconductor layer 130 is formed are separated by a distance equal to the sum of the thicknesses of the insulating layers 140 and 180. Therefore, there is an advantage in that the insulating properties between the layer on which the terminal electrode 191 is formed and the layer on which the oxide semiconductor layer 130 is formed are high.

[0082] Other effects of the semiconductor device 20 of this embodiment are the same as those of the semiconductor device 10 of the first embodiment.

[0083] [Manufacturing method for semiconductor devices] Next, a method for manufacturing the semiconductor device 20 in one embodiment of the present invention will be described. Figure 16 is a sequence diagram showing the method for manufacturing the semiconductor device 20 in one embodiment of the present invention. Figures 17 to 19 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 20 in one embodiment of the present invention.

[0084] The manufacturing method for the semiconductor device 20 in this embodiment is the same as the manufacturing method described in the first embodiment up to the process from step S1001 to step S1009 shown in Figure 3 of the first embodiment. The manufacturing method in this embodiment differs from the manufacturing method in the first embodiment in that it includes steps S1110 to step S1112 shown in Figure 16 instead of steps S1010 and S1011 shown in Figure 3.

[0085] Similar to the first embodiment, after adding impurities to the oxide semiconductor layer 130 in steps S1001 to S1009 of Figure 3, an insulating layer 180 is formed on the pattern layer 161 composed of the insulating layer 140 and an insulating material, as shown in Figures 16 and 17 (step S1110 in Figure 16). As described above, the material constituting the insulating layer 180 can be any material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxide nitride (SiOxNy), or resin.

[0086] In this embodiment, the insulating layer 180 is formed using the CVD method to create a laminated structure composed of a silicon oxide layer and a silicon nitride layer. The thickness of the insulating layer 180 may be, for example, 30 nm to 500 nm. In this embodiment, the thickness of the lower silicon oxide layer is 100 nm, and the thickness of the upper silicon nitride layer is 300 nm. That is, the thickness of the insulating layer 180 in this embodiment is 400 nm. However, the thickness of the insulating layer 180 is not limited to this example and may be thicker or thinner.

[0087] The film formation temperature for the insulating layer 180 is preferably set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0088] The insulating layer 180 functions as a passivation layer (protective layer) to prevent gas and moisture from entering from the outside. Furthermore, as described above, it also plays a role in insulating and separating the terminal electrode 191 from the conductive portion 132 of the oxide semiconductor layer 130. In addition, in this embodiment, since a silicon nitride layer is used in part of the insulating layer 180, it is possible to promote the reduction of the resistance of the conductive portion 132.

[0089] When forming a silicon nitride layer by the CVD method, ammonia is used as the raw material gas, so the silicon nitride layer contains a large amount of hydrogen. Therefore, when forming the insulating layer 180 and after forming the insulating layer 180, hydrogen diffuses from the silicon nitride layer when the insulating layer 180 is heated. The diffused hydrogen reaches the conductive part 132 via the silicon oxide layer and insulating layer 140 below the insulating layer 180. At this time, the hydrogen is trapped in the oxygen vacancies inside the conductive part 132 formed by the ion implantation described above, forming a donor level. This promotes the reduction of the resistance of the conductive part 132. In this case, the pattern layer 151 composed of metal oxide (aluminum oxide) and the pattern layer 161 composed of insulator (silicon oxide nitride) function as barrier layers that suppress the movement of hydrogen diffusing from the insulating layer 170 toward the channel portion 131 of the oxide semiconductor layer 130.

[0090] Next, as shown in Figures 16 and 18, a contact hole 181 is formed in the laminated structure composed of insulating layer 140 and insulating layer 180 (step S1111 in Figure 16). The contact hole 181 exposes a portion of the conductive portion 132. In this embodiment, as in the first embodiment, the metal oxide layer 150 located directly above the conductive portion 132 is removed, which has the advantage of making it easier to form the contact hole 181.

[0091] Finally, as shown in Figures 16 and 19, terminal electrodes 191 are formed on the conductive portion 132 exposed by the contact hole 181 (step S1112 in Figure 16). The semiconductor device 20 shown in Figure 15 is completed by the process described above.

[0092] (Modification 1 of the second embodiment) In the semiconductor device 20 described above, an example was shown in which the metal oxide layer 150 is etched to form a pattern layer 151 composed of metal oxide, but it is also possible to leave the metal oxide layer 150 without etching.

[0093] Figure 20 is a schematic cross-sectional view showing the configuration of a semiconductor device 20a in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 20a has a metal oxide layer 150 remaining on top of the insulating layer 140 without being patterned. That is, the metal oxide layer 150 is superimposed not only on the channel portion 131 of the oxide semiconductor layer 130 but also on the conductive portion 132.

[0094] In the semiconductor device 20a of this modified example, the metal oxide layer 150 functions as a barrier layer that suppresses hydrogen diffusion from above into the oxide semiconductor layer 130, similar to the pattern layer 151 shown in Figure 15.

[0095] (Modification 2 of the second embodiment) In the semiconductor device 20 described above, an example was shown in which the metal oxide layer 150 is etched to form a pattern layer 151 composed of metal oxide. However, it is also possible to etch and remove the metal oxide layer 150 without patterning it.

[0096] Figure 21 is a schematic cross-sectional view showing the configuration of a semiconductor device 20b in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 20b undergoes an annealing process as shown in step S1005 of Figure 16, after which the metal oxide layer 150 formed on the insulating layer 140 is etched and completely removed. In other words, in this modified example, there is no metal oxide layer 150 or pattern layer 151 composed of metal oxide on the insulating layer 140.

[0097] According to this modified example, in the process of adding impurities to the oxide semiconductor layer 130 shown in S1008 of Figure 16, a sufficiently large dose of impurities can be added even if the acceleration voltage is set to a low value. Furthermore, according to this modified example, the formation of contact holes 181 in the laminated structure composed of the insulating layer 140 and insulating layer 180 shown in S1111 of Figure 16 is facilitated.

[0098] <Third Embodiment> In this embodiment, a semiconductor device 30 with a different oxide semiconductor layer 130 configuration from the semiconductor device 20 of the second embodiment will be described. In the description of this embodiment, elements identical to those in the second embodiment may be indicated in the drawings using the same reference numerals and their descriptions may be omitted.

[0099] [Configuration of semiconductor device] Figure 22 is a schematic cross-sectional view showing the configuration of a semiconductor device 30 in one embodiment of the present invention. One difference from the semiconductor device 20 shown in Figure 15 is that an LDD portion 134 is provided in the oxide semiconductor layer 130. "LDD" stands for "Light Doped LDD stands for "Drain". In other words, the LDD section 134 refers to a portion that has a lower resistance value than the channel section 131 and a higher resistance value than the conductive section 132. As shown in Figure 22, the LDD section 134 is positioned between the channel section 131 and the conductive section 132. In other words, the oxide semiconductor layer 130 of this embodiment has a structure in which the channel section 131, the LDD section 134, and the conductive section 132 are continuous in the first direction.

[0100] The pattern layer 151, composed of a metal oxide, is superimposed on the channel portion 131 and the conductive portion 132. In this embodiment, in a cross-sectional view, the position of the edge 151a of the pattern layer 151 and the position of the edge 134a on the conductive portion 132 side of the LDD portion 134 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 151a of the pattern layer 151 and the position of the boundary between the LDD portion 134 and the conductive portion 132 coincide in the vertical direction. Thus, in this embodiment, in the first direction, the width of the pattern layer 151 is wider than the width of the channel portion 131, which is effective in effectively enabling the function of the pattern layer 151 described above (the function of suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130). However, this configuration is not limited to this, and the pattern layer 151 does not have to be superimposed on the LDD portion 134.

[0101] Furthermore, the pattern layer 161, which is composed of an insulating material, is superimposed on the channel portion 131. In this embodiment, in a cross-sectional view, the position of the edge 161a of the pattern layer 161 and the position of the edge 134b of the LDD portion 134 on the channel portion 131 side coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 161a of the pattern layer 161 and the position of the boundary between the channel portion 131 and the LDD portion 134 coincide in the vertical direction.

[0102] Furthermore, in the example shown in Figure 22, the portion of the insulating layer 140 that overlaps with the conductive portion 132 is removed, and a pattern layer 142 made of insulating material is formed. That is, in the semiconductor device 30 of this embodiment, the insulating layer 180 is in contact with the side surface of the pattern layer 142 and the conductive portion 132.

[0103] Other effects of the semiconductor device 30 of this embodiment are the same as those of the semiconductor device 10 of the first embodiment.

[0104] [Manufacturing method for semiconductor devices] Next, a method for manufacturing the semiconductor device 30 in one embodiment of the present invention will be described. Figure 23 is a sequence diagram showing the method for manufacturing the semiconductor device 30 in one embodiment of the present invention. Figures 24 to 26 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 30 in one embodiment of the present invention.

[0105] The manufacturing method for the semiconductor device 30 in this embodiment is the same as the manufacturing method described in the second embodiment up to the process from step S1001 to step S1009 shown in Figure 16 of the second embodiment. The manufacturing method in this embodiment differs from the manufacturing method of the second embodiment in that steps S1201 to step S1203 shown in Figure 23 are added between steps S1009 and S1110 shown in Figure 16.

[0106] First, similar to the second embodiment, impurities are added to the oxide semiconductor layer 130 by steps S1001 to S1009 in Figure 16 to form the conductive portion 132. Next, as shown in Figures 23 and 24, a resist mask 220 is formed again on the pattern layer 161, which is made of an insulating material. At this time, as shown in Figure 24, the width of the resist mask 220 is made narrower than the width of the pattern layer 161 in the first direction. After that, the pattern layer 161 is etched using the resist mask 220 as a mask (step S1201 in Figure 23).

[0107] In step S1201, the pattern layer 161 exposed from the resist mask 220 is removed. In this embodiment, a silicon oxynitride layer is used as the pattern layer 161 and a silicon oxide layer is used as the insulating layer 140. Therefore, because the selectivity ratio for etching between the pattern layer 161 and the insulating layer 140 is small, the insulating layer 140 exposed from the pattern layer 151, which is made of metal oxide, is also removed while the pattern layer 161 is being etched.

[0108] The etching process of the pattern layer 161 is stopped when a portion of the upper surface of the pattern layer 151 located below it is exposed. In this embodiment, since the thickness of the pattern layer 161 is greater than the thickness of the insulating layer 140, the insulating layer 140 directly above the conductive portion 132 is removed, and the conductive portion 132 is exposed. However, as described above, the oxide semiconductor layer 130 in this embodiment has very high etching resistance, so the etching damage to the conductive portion 132 is negligible.

[0109] Next, as shown in Figures 23 and 25, the resist mask is removed (step S1202 in Figure 23). Then, ion implantation is performed from above the pattern layer 161 to add impurities to the oxide semiconductor layer 130 for the second time (step S1203 in Figure 23). The impurities to be added can be the same as those added in step S1009 of Figure 23 (phosphorus, boron, argon, etc.).

[0110] The ion implantation conditions may be the same as or different from those in step S1009 in Figure 23. In this embodiment, the acceleration voltage is 30 keV and the dose is 1 × 10⁻⁶ 13 / cm 2 As shown in Figure 25, in this embodiment, the LDD portion 134 is formed at the end of the channel portion 131 in the first direction (the portion that does not overlap with the pattern layer 161) by the second impurity addition. At this time, since impurities are added to the LDD portion 134 via the pattern layer 151 and the insulating layer 140, even if impurities are added under the same conditions as in step S1009, the amount of impurities added will be less than that of the conductive portion 132. In other words, the resistance value of the LDD portion 134 will be higher than the resistance value of the conductive portion 132.

[0111] After forming the LDD section 134 through the above process, the semiconductor device 30 shown in Figure 22 is completed by following steps S1110 to S1112 shown in Figure 23. Steps S1110 to S1112 have already been described in the second embodiment.

[0112] (Modification 1 of the third embodiment) In the semiconductor device 30 described above, a pattern layer 151 made of metal oxide is formed on top of the insulating layer 140. Therefore, when step S1201 (etching of the side of the pattern layer 161) in Figure 23 is performed, the insulating layer 140 located directly above the conductive portion 132 is removed. However, as described in Modifications 1 and 2 of the Second Embodiment, the final device structure differs if the metal oxide layer 150 is left or completely removed.

[0113] For example, in the case of Modification 1 of the second embodiment, the metal oxide layer 150 remains on the insulating layer 140 without being etched. In this case, even if step S1201 in Figure 23 is performed, the metal oxide layer 150 functions as an etching stopper, thus preventing the insulating layer 140 from being etched. In this case, in the device structure of Figure 22, the insulating layer 140 is provided in place of the pattern layer 142, and the metal oxide layer 150 is provided in place of the pattern layer 151.

[0114] Furthermore, in the modified example 2 of the second embodiment, there is no metal oxide layer 150 or pattern layer 151 on the insulating layer 140. In this case, when step S1201 in Figure 23 is performed, the portion of the insulating layer 140 that does not overlap with the resist mask 220 (i.e., the portion that does not overlap with the pattern layer 161) is completely removed. Therefore, when the etching process is completed, the edges of the channel portion 131 (the portion that does not overlap with the resist mask 220) are exposed. In this case, in the impurity addition process to the oxide semiconductor layer 130 shown in S1203 of Figure 23, even if the acceleration voltage is set low, a sufficiently large dose of impurities can be added to the LDD portion 134.

[0115] (Modification 2 of the third embodiment) The structure shown in Figure 22 illustrates an example in which the terminal electrode 191 and the conductive part 132 are electrically connected via a contact hole 181 provided in the insulating layer 180, but the method is not limited to this example. For example, it is also possible to directly connect the terminal electrode 191 and the conductive part 132 without providing an insulating layer 180. In this case, after adding impurities to the oxide semiconductor layer 130 in the process S1203 of Figure 23, a conductive layer is formed to cover the oxide semiconductor layer 130 and the pattern layer 161. Then, the conductive layer is patterned to form the terminal electrode 191 that contacts the conductive part 132.

[0116] <Fourth Embodiment> In the first embodiment, an example was shown in which the oxide semiconductor layer 130 is in contact with the gate insulating layer 110, but it is also possible to provide a metal oxide layer between the gate insulating layer 110 and the oxide semiconductor layer 130. In the description of this embodiment, elements identical to those in the first embodiment may be indicated in the drawings using the same reference numerals and their description may be omitted.

[0117] Figure 26 is a schematic cross-sectional view showing the configuration of a semiconductor device 40 in one embodiment of the present invention. The basic structure is the same as that of the semiconductor device 10 shown in Figure 1, but in this embodiment, the semiconductor device 40 has a metal oxide layer 120 placed between the gate insulating layer 110 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 120 is made of a metal oxide mainly composed of aluminum (specifically, an aluminum oxide (AlOx) layer). The metal oxide layer 120 can be formed, for example, by a sputtering method.

[0118] As shown in Figure 26, in this embodiment, the metal oxide layer 120 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, after performing step S1001 in Figure 3, the metal oxide layer 120 and the oxide semiconductor layer 130 are continuously deposited. Then, the processes of steps S1002 and S1003 in Figure 3 are performed to obtain the oxide semiconductor layer 130. Furthermore, by etching the oxide semiconductor layer 130 and the metal oxide layer 120, a metal oxide layer 120 having the same pattern shape as the oxide semiconductor layer 130 can be formed.

[0119] The thickness of the metal oxide layer 120 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 120 is 3 nm. In this embodiment, the aluminum oxide layer used as the metal oxide layer 120 has high barrier properties against gas even if its thickness is 1 nm to 10 nm. Therefore, the metal oxide layer 120 in this embodiment blocks hydrogen and oxygen released from the gate insulating layer 110 and suppresses hydrogen and oxygen released from below from reaching the oxide semiconductor layer 130.

[0120] Blocking hydrogen released from the gate insulating layer 110 by the metal oxide layer 120 is preferable for suppressing the reduction reaction of the oxide semiconductor layer 130.

[0121] Furthermore, after the oxide semiconductor layer 130 is formed, during various manufacturing processes (such as patterning), more oxygen vacancies are formed on the upper side of the oxide semiconductor layer 130 than on the lower side. In other words, the oxygen vacancies in the oxide semiconductor layer 130 are distributed non-uniformly in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen vacancies formed on the upper side of the oxide semiconductor layer 130, an excess of oxygen will be supplied to the lower side of the oxide semiconductor layer 130. As a result, the excess oxygen may form defect levels different from oxygen vacancies, which may lead to phenomena such as characteristic fluctuations in reliability tests or a decrease in field-effect mobility. Therefore, blocking the oxygen released from the gate insulating layer 110 with the metal oxide layer 120 is also preferable in suppressing the excessive supply of oxygen to the lower side of the oxide semiconductor layer 130.

[0122] Thus, in this embodiment, when performing the oxide annealing shown in step S1005 of Figure 3, it is possible to suppress the supply of oxygen to the lower surface of the oxide semiconductor layer 130, which has a small amount of oxygen vacancy, while supplying oxygen to the upper and side surfaces of the oxide semiconductor layer 130, which has a relatively large amount of oxygen vacancy. Therefore, during oxide annealing, oxygen can be efficiently supplied to the oxide semiconductor layer 130, and the reliability of the semiconductor device 40 can be improved.

[0123] In this embodiment, an example of application to the semiconductor device 10 shown in Figure 1 of the first embodiment has been described, but it is also possible to apply it to other semiconductor devices shown in the second or third embodiment.

[0124] <Fifth Embodiment> This embodiment describes a display device 500 using a semiconductor device 10 according to one embodiment of the present invention. In the embodiments described below, the semiconductor device 10 described in the first embodiment is used as an element constituting the circuit of a liquid crystal display device. However, the invention is not limited to this example, and the semiconductor device described in the second to fourth embodiments may be used as an element constituting the circuit of a liquid crystal display device. Alternatively, instead of being used as an element constituting the circuit of a liquid crystal display device, it may be used as an element constituting the circuit of another display device, such as an organic EL display device.

[0125] [Overview of display devices] Figure 27 is a schematic plan view showing the overall configuration of a display device 500 in one embodiment of the present invention. As shown in Figure 27, the display device 500 has an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. Multiple pixels 51 are arranged in a matrix in the liquid crystal area 52 surrounded by the sealing portion 310. That is, the display area is formed by multiple pixels 51 arranged side by side in the X and Y directions, respectively. The liquid crystal area 52 is the area that overlaps with the liquid crystal element 311, which will be described later, in a plan view. Regarding the pixels 51, the letters "R", "G", and "B" indicate that they correspond to pixels for red display, pixels for green display, and pixels for blue display, respectively.

[0126] The sealing region 54, where the sealing portion 310 is provided, is the area surrounding the liquid crystal region 52. The flexible printed circuit board 330 is provided in the terminal region 56. The terminal region 56 is the area of ​​the array substrate 300 that is exposed from the opposing substrate 320 and is provided outside the sealing region 54. The area outside the sealing region 54 means the area outside where the sealing portion 310 is provided and the area enclosed by the sealing portion 310. The IC chip 340 is provided on the flexible printed circuit board 330. The IC chip 340 supplies signals to drive each pixel circuit 301 (see Figure 28) arranged in each pixel 51.

[0127] [Circuit configuration of the display device] Figure 28 is a block diagram showing the circuit configuration of a display device 500 in one embodiment of the present invention. As shown in Figure 28, a plurality of pixel circuits 301 are arranged in a matrix corresponding to each pixel 51 shown in Figure 27. A source driver circuit 302 is provided at a position adjacent to the liquid crystal area 52 in the Y direction (column direction) with respect to the liquid crystal area 52 where the pixel circuits 301 are arranged. A gate driver circuit 303 is provided at a position adjacent to the liquid crystal area 52 in the X direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the seal area 54. However, the area in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the seal area 54, but can be anywhere outside the area in which the pixel circuits 301 are provided.

[0128] A data signal line 304 extends from the source driver circuit 302 in the Y direction and is connected to multiple pixel circuits 301 arranged in the Y direction. A scan signal line 305 extends from the gate driver circuit 303 in the X direction and is connected to multiple pixel circuits 301 arranged in the X direction.

[0129] A terminal section 306 is provided in the terminal area 56. The terminal section 306 and the source driver circuit 302 are connected by a connecting wire 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connecting wire 308. By connecting the flexible printed circuit board 330 to the terminal section 306, the display device 500 is connected to an external device via the flexible printed circuit board 330. Each pixel circuit 301 provided in the display device 500 is driven by a signal from an external device input via the flexible printed circuit board 330.

[0130] The semiconductor device 10 shown in the first embodiment is used as a switching element or current control element included in the pixel circuit 301, source driver circuit 302, and gate driver circuit 303.

[0131] [Pixel circuit of display device] Figure 29 is a circuit diagram showing the configuration of a pixel circuit 301 of a display device 500 in one embodiment of the present invention. As shown in Figure 29, the pixel circuit 301 includes elements such as a switching element 410, a holding capacitor 420, and a liquid crystal element 311.

[0132] The switching element 410 is composed of the semiconductor device 10 of the first embodiment. The switching element 410 has a gate electrode 411, a source electrode 412, and a drain electrode 413. The gate electrode 411 is connected to the scan signal line 305. However, the gate electrode 411 and the scan signal line 305 may be formed from a single conductive layer. The source electrode 412 is connected to the data signal line 304. However, the source electrode 412 and the data signal line 304 may be formed from a single conductive layer.

[0133] The drain electrode 413 is connected to the holding capacitor 420 and the liquid crystal element 311. Note that the roles of the source electrode 412 and the drain electrode 413 may be reversed depending on the relationship between the voltage supplied to the data signal line 304 and the voltage stored in the holding capacitor 420. That is, the source electrode 412 may function as the drain electrode, and the drain electrode 413 may function as the source electrode.

[0134] [Pixel structure of display device] Figure 30 is a cross-sectional view showing the pixel structure of a display device 500 in one embodiment of the present invention. The display device 500 uses the semiconductor device 10 described in the first embodiment as a switching element 410 included in the pixel circuit 301. In the following description, the configuration of the semiconductor device 10 is the same as that of the semiconductor device 10 shown in Figure 1, so a detailed explanation will be omitted.

[0135] An insulating layer 360 is provided on the terminal electrode 171 of the semiconductor device 10. For example, acrylic resin can be used as the insulating layer 360. A common electrode 370, which is provided in common to multiple pixels, is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. For example, a silicon nitride layer can be used as the insulating layer 380. Contact holes 381 are provided in the insulating layers 360 and 380. A pixel electrode 390, which is connected to the terminal electrode 171 via the contact hole 381, is provided on the insulating layer 380.

[0136] A transparent conductive layer is used for the common electrode 370 and the pixel electrode 390. In this embodiment, ITO (Indium Tin Oxide) is used as the material for the transparent conductive layer constituting the common electrode 370 and the pixel electrode 390, but other metal oxide layers may be used. The common electrode 370 is composed of a flat transparent conductive layer. Although not shown in Figure 30, the pixel electrode 390 is composed of a comb-shaped transparent conductive layer that combines a portion extending in a first direction and a portion extending in a second direction. The portion extending in the second direction is composed of multiple linear electrodes, each connected to an electrode corresponding to a trunk extending in the first direction.

[0137] A liquid crystal layer 311a is sealed between the active matrix substrate, which has pixel electrodes 390 formed on the substrate 100, and the opposing substrate 320. The liquid crystal layer 311a is arranged across multiple pixels 51. The region where the liquid crystal layer 311a is arranged corresponds to the liquid crystal region 52 shown in Figure 27.

[0138] As shown in Figure 30, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This transverse electric field causes the liquid crystal molecules contained in the liquid crystal layer 311a to act, thereby determining the gradation of light passing through the pixel 51.

[0139] The embodiments described above (including variations of each embodiment) can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on each embodiment, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0140] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0141] 10-40, 10a, 10b, 20a, 20b… Semiconductor device, 51… Pixel, 52… Liquid crystal area, 54… Seal area, 56… Terminal area, 100… Substrate, 105… Gate electrode, 108… Gate electrode, 110… Gate insulating layer, 120… Metal oxide layer, 130… Oxide semiconductor layer, 131… Channel area, 131a, 131b… Edge, 132… Conductive area, 134… LDD area, 134a… Edge, 140… Insulating layer, 141… Contact hole, 142… Pattern layer, 150… Metal oxide layer, 151… Pattern layer, 151a… Edge, 160… Insulating layer, 161… Pattern layer, 161a… Edge, 171… Terminal electrode, 180… Insulating layer, 181… Contact hole, 19 1…Terminal electrode, 210, 220…Resist mask, 300…Array substrate, 301…Pixel circuit, 302…Source driver circuit, 303…Gate driver circuit, 304…Data signal line, 305…Scan signal line, 306…Terminal section, 307, 308…Connection wiring, 310…Seal section, 311…Liquid crystal element, 311a…Liquid crystal layer, 320…Opposite substrate, 330…Flexible printed circuit board, 340…Chip, 360…Insulating layer, 370…Common electrode, 380…Insulating layer, 381…Contact hole, 390…Pixel electrode, 410…Switching element, 411…Gate electrode, 412…Source electrode, 413…Drain electrode, 420…Holding capacitance, 500…Display device

Claims

1. The gate electrode on the insulating surface, The gate insulating layer on the gate electrode, The oxide semiconductor layer on the gate insulating layer, The first insulating layer on the oxide semiconductor layer, A first pattern layer composed of an insulating material on the first insulating layer, Includes, The oxide semiconductor layer has a channel portion and a conductive portion, In a plan view, the first pattern layer is superimposed on the channel portion, in a semiconductor device.

2. The semiconductor device according to claim 1, wherein, in a plan view, the outer edge of the portion of the first pattern layer that overlaps with the oxide semiconductor layer coincides with the outer edge of the channel portion.

3. The channel portion and the conductive portion are arranged continuously in the first direction. The semiconductor device according to claim 1, wherein, in a plan view, the first pattern layer intersects with the oxide semiconductor layer in a second direction intersecting the first direction.

4. The semiconductor device according to claim 1, wherein the first pattern layer is composed of an insulator containing silicon.

5. The semiconductor device according to claim 1, wherein the thickness of the first insulating layer is 200 nm or less.

6. The semiconductor device according to claim 1, wherein the first insulating layer is in contact with the oxide semiconductor layer.

7. The semiconductor device according to claim 6, wherein the first insulating layer includes one selected from a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

8. The semiconductor device according to claim 1, further comprising terminal electrodes disposed on the first insulating layer and electrically connected to the conductive portion.

9. The semiconductor device according to claim 1, further comprising an aluminum-containing metal oxide layer between the first insulating layer and the first pattern layer.

10. The semiconductor device according to claim 1, further comprising a second pattern layer made of a metal oxide between the first insulating layer and the first pattern layer.

11. The semiconductor device according to claim 10, wherein the second pattern layer has the same pattern shape as the first pattern layer.

12. The second insulating layer on the first pattern layer, A terminal electrode is placed on the second insulating layer and electrically connected to the conductive part, The semiconductor device according to claim 1, 9, or 10, further comprising:

13. The semiconductor device according to claim 12, wherein the second insulating layer includes a silicon nitride layer.

14. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has an LDD portion between the channel portion and the conductive portion.

15. The semiconductor device according to claim 14, wherein the LDD portion has a lower resistance value than the channel portion and a higher resistance value than the conductive portion.

16. The semiconductor device according to claim 14, wherein the position of the edge of the first pattern layer and the position of the edge on the channel side of the LDD portion coincide in the vertical direction.

17. The semiconductor device according to claim 1, further comprising an aluminum-containing metal oxide layer in contact with the oxide semiconductor layer between the gate insulating layer and the oxide semiconductor layer.

18. The semiconductor device according to claim 17, wherein the metal oxide layer has the same pattern shape as the oxide semiconductor layer.

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