Semiconductor equipment

Abstract

To provide a semiconductor device with improved electrical characteristics and reliability. [Solution] The semiconductor device 100 includes a plurality of channel structures 130 spaced apart and arranged on a semiconductor pattern 105, a plurality of gate structures GS, a source / drain (S / D) pattern 150 disposed between the plurality of channel structures 130, an insulating layer separation layer 210 disposed on the lower surface of the semiconductor pattern 105, a plurality of insulating separation patterns 230 disposed on the lower surface of the insulating separation layer 210 and extending toward the plurality of gate structures GS, a plurality of contact blocks 280 disposed between the plurality of insulating separation patterns 230 on the lower surface of the insulating separation layer 210, one or more contact vias 286 penetrating the insulating separation layer 210 and extending adjacently within the S / D pattern 150, and a conductive barrier 282 extending on the surface of the contact vias 286, wherein the plurality of contact blocks 280 have sides that contact the side walls of the plurality of insulating separation patterns 230.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved electrical characteristics and reliability. [Background technology]

[0002] The demand for higher performance, faster speeds, and / or more functionality in semiconductor devices is increasing, and the integration density of semiconductor devices is also increasing. In response to the trend towards higher integration in semiconductor devices, semiconductor devices with a BackSide Power Delivery Network (BSPDN) structure, where power rails are placed on the back surface of the wafer, are being developed.

[0003] Furthermore, in order to overcome the limitations in operating characteristics due to the reduction in size of planar MOSFETs (metal oxide semiconductor FETs), efforts are underway to develop semiconductor devices with three-dimensional channel structures, and this remains a daily challenge. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The present invention has been made in view of the problems of the above-mentioned conventional semiconductor devices, and the object of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability. [Means for solving the problem]

[0005] To achieve the above objective, the semiconductor device according to the present invention comprises: a semiconductor pattern extending in a first direction; a plurality of channel structures arranged on the semiconductor pattern spaced apart from each other in the first direction, where each of the plurality of channel structures includes a plurality of channel patterns; a plurality of gate structures that surround the plurality of channel patterns, each crossing the plurality of channel structures in a second direction intersecting the first direction; a source / drain pattern disposed between the plurality of channel structures on the semiconductor pattern and connected to the sides of the plurality of channel patterns; an insulating isolation layer disposed on the lower surface of the semiconductor pattern; and a plurality of insulating elements disposed on the lower surface of the insulating isolation layer in regions corresponding to the plurality of gate structures, each extending toward the plurality of gate structures, and separating the semiconductor pattern into a plurality of patterns. The invention is characterized by comprising: an isolation pattern; a plurality of contact blocks arranged on the lower surface of the insulating isolation layer between adjacent insulating isolation patterns among the plurality of insulating isolation patterns; at least one contact via extending from at least one of the plurality of contact blocks through the insulating isolation layer to an adjacent source / drain pattern among the source / drain patterns; a conductive barrier disposed between the insulating isolation layer and the plurality of contact blocks and on the surface of the at least one contact via; wherein each of the plurality of contact blocks has a side surface that contacts the side wall of the plurality of insulating isolation patterns, and a wiring structure disposed on the lower surface of the plurality of contact blocks and the plurality of insulating isolation patterns and electrically connected to the at least one contact block.

[0006] A semiconductor device according to one embodiment of the present invention includes a semiconductor pattern extending in a first direction, element isolation layers disposed on both sides of the semiconductor pattern extending in the first direction, a plurality of channel structures arranged on the semiconductor pattern spaced apart from each other in the first direction, a plurality of gate structures that cross the plurality of channel structures in a second direction intersecting the first direction, a source / drain pattern disposed between the plurality of channel structures on the semiconductor pattern, an insulating isolation layer disposed on the lower surface of the semiconductor pattern, a plurality of insulating isolation patterns disposed on the lower surface of the insulating isolation layer in regions corresponding to the plurality of gate structures, each extending toward the plurality of gate structures, and separating the semiconductor pattern into a plurality of patterns, and the plurality of insulating isolation patterns disposed on the lower surface of the insulating isolation layer A semiconductor device can be provided, comprising: a plurality of contact blocks arranged between edge isolation patterns; at least one contact via extending from at least one of the plurality of contact blocks through the insulating isolation layer to an adjacent source / drain pattern in the source / drain pattern; a conductive barrier disposed between the insulating isolation layer and the plurality of contact blocks and extending to the surface of the at least one contact via, wherein each of the plurality of contact blocks has a side surface that contacts the sidewall of the plurality of insulating isolation patterns; and a wiring structure disposed on the lower surface of the plurality of contact blocks, the plurality of insulating isolation patterns, and the element isolation layer and electrically connected to the at least one contact block.

[0007] Furthermore, a semiconductor device according to one embodiment of the present invention includes a semiconductor pattern extending in a first direction, element isolation layers disposed on both sides of the semiconductor pattern extending in the first direction, a plurality of channel structures arranged on the semiconductor pattern spaced apart from each other in the first direction, a plurality of gate structures that cross the plurality of channel structures in a second direction intersecting the first direction, first and second source / drain patterns disposed between the plurality of channel structures on the semiconductor pattern, an interlayer insulating layer disposed on the element isolation layer and covering the plurality of gate structures and the first and second source / drain patterns, an insulating isolation layer disposed on the lower surface of the semiconductor pattern, a plurality of insulating isolation patterns disposed on the lower surface of the insulating isolation layer in regions corresponding to the plurality of gate structures and penetrating the insulating isolation layer and extending toward the plurality of gate structures, and the first source / drain pattern penetrating the interlayer insulating layer A semiconductor device can be provided, comprising: an upper contact connected to an in-pattern; a plurality of lower contact blocks arranged between the plurality of insulating isolation patterns on the lower surface of the insulating isolation layer; contact vias extending from a contact block adjacent to the second source / drain pattern among the plurality of contact blocks through the insulating isolation layer to the second source / drain pattern; a conductive barrier disposed between the insulating isolation layer and the plurality of contact blocks and extending to the surface of the contact vias; a first wiring structure disposed on the interlayer insulating layer and electrically connected to the upper contact, each of the plurality of contact blocks having a side surface that contacts the side walls of the plurality of insulating isolation patterns; and a second wiring structure disposed on the lower surface of the plurality of contact blocks, the plurality of insulating isolation patterns, and the element isolation layer and electrically connected to the adjacent contact blocks. [Effects of the Invention]

[0008] According to the semiconductor device of the present invention, by etching back the contact block along with the conductive barrier so that only a portion of the contact block remains, and then using the remaining region as a seed to regrow it, the conductive barrier can be minimized, contact resistance can be improved, and a high-quality contact block (minimized grain boundary) can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing the schematic configuration of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figure 1 is a cross-sectional view of the semiconductor device cut along the line I-I'. [Figure 3a] Figure 1 is a cross-sectional view of the semiconductor device cut along the line II1-II1'. [Figure 3b] Figure 1 is a cross-sectional view of the semiconductor device cut along the line II2-II2'. [Figure 4a] This is a magnified view of section "A1" of the semiconductor device shown in Figure 2. [Figure 4b] This is a magnified view of section "B" of the semiconductor device shown in Figure 3. [Figure 5] This is a side cross-sectional view showing a semiconductor device according to one embodiment of the present invention. [Figure 6] This is a side cross-sectional view showing a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a magnified view of section "A2" of the semiconductor device shown in Figure 5. [Figure 8a] This is a cross-sectional view showing the main steps involved in a partial process (insulation isolation pattern formation step) of a semiconductor device manufacturing method according to one embodiment of the present invention. [Figure 8b] This is a cross-sectional view showing the main steps involved in a partial process (insulation isolation pattern formation step) of a semiconductor device manufacturing method according to one embodiment of the present invention. [Figure 8c] This is a cross-sectional view showing the main steps involved in a partial process (insulation isolation pattern formation step) of a semiconductor device manufacturing method according to one embodiment of the present invention. [Figure 8d]It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (insulating isolation pattern formation process) according to an embodiment of the present invention. [Figure 8e] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (insulating isolation pattern formation process) according to an embodiment of the present invention. [Figure 8f] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (insulating isolation pattern formation process) according to an embodiment of the present invention. [Figure 9a] It is another side view corresponding to the semiconductor device of Fig. 8a. [Figure 9b] It is another side view corresponding to the semiconductor device of Fig. 8b. [Figure 9c] It is another side view corresponding to the semiconductor device of Fig. 8c. [Figure 9d] It is another side view corresponding to the semiconductor device of Fig. 8f. [Figure 10a] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (back contact formation process) according to an embodiment of the present invention. [Figure 10b] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (back contact formation process) according to an embodiment of the present invention. [Figure 10c] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (back contact formation process) according to an embodiment of the present invention. [Figure 10d] It is a cross-sectional view by main process for explaining a part of the manufacturing method of a semiconductor device (back contact formation process) according to an embodiment of the present invention. [Figure 11a] It is another side view corresponding to the semiconductor device of Fig. 10a. [Figure 11b] It is another side view corresponding to the semiconductor device of Fig. 10b. [Figure 11c] It is another side view corresponding to the semiconductor device of Fig. 10c. [Figure 11d] It is another side view corresponding to the semiconductor device of Fig. 10d. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for implementing the semiconductor device according to the present invention will be described with reference to the drawings.

[0011] Figure 1 is a plan view showing the schematic configuration of a semiconductor device according to one embodiment of the present invention, Figure 2 is a cross-sectional view of the semiconductor device in Figure 1 cut along the line I-I', and Figures 3a and 3b are cross-sectional views of the semiconductor device in Figure 1 cut along the lines II1-II1' and II2-II2', respectively. Referring to Figures 1, 2, 3a, 3b, and 4, the semiconductor device 100 according to this embodiment includes a semiconductor pattern 105 extending in a first direction (e.g., the X direction), a plurality of channel structures CH arranged spaced apart on the semiconductor pattern 105 in the first direction (e.g., the X direction), a plurality of gate structures GS that cross each of the plurality of channel structures CH in a second direction (e.g., the Y direction) intersecting the first direction (e.g., the X direction), and a source / drain pattern 150 disposed between the plurality of channel structures CH.

[0012] The semiconductor device 100 according to this embodiment includes, as a base structure, a gate structure GS and a semiconductor pattern 105 arranged along the lower surface of the first and second source / drain patterns (150A, 150B). In this embodiment, the semiconductor pattern 105 may be part of an "active pattern" that protrudes onto the substrate 101 and extends in a first direction (e.g., the X direction) before the substrate 101 is ground (see Figures 8a and 9a).

[0013] Referring to Figure 3a, the element isolation layer 110 is placed between the semiconductor patterns 105. The element isolation layer 110 is arranged on both sides of the semiconductor pattern 105 that extend in the first direction. The upper region of the semiconductor pattern 105 is exposed from the upper surface of the device isolation layer 110. As shown in Figures 2 and 3b, the channel structures GS are arranged on the semiconductor pattern 105 at regular intervals in a first direction (e.g., the X direction).

[0014] In this embodiment, the channel structure GS includes a plurality of channel patterns 130 stacked on the semiconductor pattern 105 at intervals in the vertical direction (e.g., the Z direction). Multiple channel patterns 130 are provided as channel structures for transistors and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In one embodiment, the multiple channel patterns 130 may be silicon semiconductors. In this embodiment, three channel patterns 130 are exemplified, but their number and shape can be varied.

[0015] As shown in Figures 1, 2, and 3b, the gate structure GS includes a gate electrode 145 that extends in a second direction (e.g., the Y direction) and surrounds a plurality of channel patterns 130, a gate insulating film 142 disposed between the gate electrode 145 and the plurality of channel patterns 130, gate spacers 141 disposed on both sides of the portion of the gate electrode 145 located on the uppermost channel pattern, and a gate capping layer 147 disposed on the gate electrode 145 between the gate spacers 141.

[0016] The gate electrode 145 contains a conductive material. For example, the gate electrode 145 may contain at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. In one embodiment, the gate electrode 145 may contain a semiconductor material such as doped polysilicon. At least one of the gate electrodes 145 may include a multilayer structure composed of different materials.

[0017] The gate insulating film 142 contains a dielectric material. For example, the gate insulating film 142 includes an oxide, a nitride, or a high-k (high dielectric constant) material. The high-k material refers to a dielectric material having a higher dielectric constant than a silicon oxide film (SiO2). Examples of the high-k material include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3), and can be any one of them. In one embodiment, the gate insulating film 142 may include two or more other dielectric films.

[0018] The gate spacer 141 includes an insulating material. For example, the gate spacer 141 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the gate spacer 141 may include a multilayer structure composed of different materials. The gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

[0019] Referring to FIG. 2, the semiconductor device 100 according to the present embodiment includes source / drain patterns 150 respectively connected to both side surfaces of a plurality of channel patterns 130, which are channel regions, on both sides of the gate structure GS. In this embodiment, the portions of the semiconductor pattern 105 located on both sides of the gate structure GS have recessed regions, and the source / drain pattern 150 is positioned in the recessed region of the semiconductor pattern 105.

[0020] Referring to Figures 2 and 3a, the source / drain pattern 150 adopted in this embodiment includes a first epitaxial layer 151 and a second epitaxial layer 152 disposed on the first epitaxial layer 151. In this embodiment, the first epitaxial layer 151 is in direct contact with the sides of the multiple channel patterns 130. In this embodiment, the first epitaxial layer 151 and the second epitaxial layer 152 contain different materials. For example, in the case of a P-type MOSFET, the first and second epitaxial layers (151, 152) contain SiGe with different Ge components (for example, the second epitaxial layer 152 contains an even higher Ge content), or the first and second epitaxial layers (151, 152) contain Si and SiGe, respectively. In one embodiment, the first epitaxial layer 151 and the second epitaxial layer 152 contain different types of impurities or the same impurities at different concentrations. In the case of an N-type MOSFET, the first and second epitaxial layers (151, 152) all contain Si, but the first epitaxial layer 151 and the second epitaxial layer 152 may contain different types of impurities or the same impurities at different concentrations.

[0021] The semiconductor device 100 according to this embodiment includes an upper contact structure 180 connected to a first wiring structure 190 on the front side and a lower contact structure 280 connected to a second wiring structure 290 on the back side. For example, the first wiring structure 190 is configured to include signal lines connected to the second source / drain pattern 150B of the semiconductor device 100 via the upper contact structure 180, and the second wiring structure 290 is configured to include power lines connected to the first source / drain pattern 150A of the semiconductor device 100 via the lower contact structure 280. In this embodiment, the upper contact structure 180 is connected to the second source / drain pattern 150B between adjacent gate structures GS, and the lower contact structure 280 is connected to the first source / drain pattern 180A between adjacent isolation patterns 230. The upper and lower contact structures used in this embodiment will be described in more detail below.

[0022] As shown in Figures 2 and 3b, the semiconductor device 100 according to this embodiment further includes a first interlayer insulating layer 161 disposed on the element isolation layer 110 so as to cover the source / drain pattern 150, i.e., the first and second source / drain patterns (150A, 150B), and a second interlayer insulating layer 162 on the first interlayer insulating layer 161 that covers the gate structure GS. For example, the interlayer insulating layers (161, 162) between the first and second layers may include SOH (Spin-on Hardmask), FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilaca Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. The first and second interlayer insulating layers (161, 162) can be formed using chemical vapor deposition, fluid CVD, or spin coating, respectively.

[0023] In this embodiment, the upper contact structure 180 penetrates the first interlayer insulating layer 161 and is connected to the second source / drain pattern 150B. The upper contact structure 180 extends from the upper surface of the second source / drain pattern 150B into its interior. Each upper contact structure 180 includes a contact plug and a conductive barrier surrounding the contact plug. For example, the contact plug may contain Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the conductive barrier may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof.

[0024] As shown in Figure 2, the insulating isolation layer 210 is placed on the underside of the semiconductor pattern 105. Multiple insulating isolation patterns 230 are arranged on the lower surface of the insulating isolation layer 210 in regions corresponding to multiple gate structures GS. Multiple insulating isolation patterns 230 have a structure that extends in the vertical direction (for example, the Z direction). Multiple insulating isolation patterns 230 define space for contact blocks 285 on the underside of the insulating isolation layer 210. Each of the multiple insulating isolation patterns 230 extends through the insulating isolation layer 210 toward each of the multiple gate structures GS. The extended portion in this way separates the semiconductor pattern 105 into multiple patterns. For example, at least one of the insulating separation layer 210 and the insulating separation pattern 230 may include silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride. In one embodiment, the insulating separation layer 210 and the insulating separation pattern 230 may contain the same insulating material.

[0025] Multiple contact blocks 285 are arranged in the spaces between multiple insulating separation patterns 230 on the lower surface of the insulating separation layer 210. Multiple contact blocks 285 are each located beneath a source / drain pattern 150 and are utilized as part of a potential lower contact structure for the source / drain pattern 150. As described above, in this embodiment, the contact block 285 is used as a lower contact structure 280 together with the contact vias 286 extending therefrom. The contact block 280 used in this embodiment can be distinguished and referred to as "active contact black 280A" which is involved in the operation of the transistor, and "dummy contact block 280B" which is not involved in the operation of the transistor.

[0026] The lower contact structure 280 employed in this embodiment includes at least one contact block 285A among the contact blocks 285 and a contact via 286 extending from at least one contact block 285A to the first source / drain pattern 150A. The contact via 286 extends from at least one contact block 285A through the insulating isolation layer 210 to an adjacent first source / drain pattern 150A in the source / drain pattern 150. The contact via 286 is connected to the second epitaxial layer 152 through the first epitaxial layer 151 to reduce contact resistance (see Figure 4a).

[0027] In this embodiment, in a cross-section of the semiconductor device 100 in the first direction (see Figure 2), each of the multiple insulating isolation patterns 230 has a shape in which the width Wb of the portion adjacent to the second wiring structure 290 is larger than the width Wa of the portion adjacent to the multiple gate structures GS. This is because the etching process for the insulating separation pattern 230 is carried out at a relatively low temperature (e.g., below 400°C) to avoid adversely affecting the metal components of the first wiring structure 190, thus inevitably resulting in a tapered structure. As a result, each of the contact blocks 285 defined by the multiple insulating isolation patterns 230 has a shape in which the width W2 of the portion adjacent to the second wiring structure 290 is smaller than the width W1 of the portion adjacent to the insulating isolation layer 210.

[0028] The semiconductor device 100 used in this embodiment further includes a conductive barrier 282 disposed between an insulating separation layer 210 and a plurality of contact blocks 285. In the lower contact structure 280, the conductive barrier 282 extends to the surface of at least one contact via 286. On the side of the contact block 285, there is a portion where the conductive barrier 282 is not extended. Each of the multiple contact blocks 285 has a side portion that contacts the side walls of the multiple insulating isolation patterns 230.

[0029] Figure 4a is a magnified view of section "A1" of the semiconductor device in Figure 2, and Figure 4b is a magnified view of section "B1" of the semiconductor device in Figure 3. Referring to Figures 4a and 4b in conjunction with Figures 2 and 3a, the conductive barrier 282 has a portion 282E that extends from the side walls of the multiple insulating isolation patterns 230 to a portion adjacent to the insulating isolation layer 210. With respect to the extended portion 282E of the conductive barrier 282, each of the multiple contact blocks 285 is divided into two parts (285a, 285b). Each of the multiple contact blocks 285 includes a first portion 285a that horizontally overlaps with the extended portion 282E and a second portion 285b that contacts the multiple insulating isolation patterns 230.

[0030] In this embodiment, the first portion 285a and the second portion 285b of the contact block 285 contain the same metallic material. However, the first portion 285a and the second portion 285b can also be formed by other deposition processes (see Figures 10b and 10d). The first part 285a is used as a seed layer in the deposition process for the second part 285b. Multiple contact blocks 285, particularly the second portion 285b, contain a metal with a nearly single-crystal structure that lacks grain boundaries. For example, the first part 285a is carried out by a non-selective deposition process, such as PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition), and the second part 285b is carried out by a selective deposition process, i.e., a CVD process.

[0031] In this embodiment, the extended portion 282E of the conductive barrier 282 determines the thickness of the first portion. The first part has an appropriate thickness for the seed layer. For example, the length d of the extended portion 282E is 1 nm or more, but is not limited to this. In this embodiment, the contact via 286 contains the same metallic material as the first portion 285a of the plurality of contact blocks 285. Each of the multiple contact blocks 285 contains the same metallic material as the contact via 286. In this embodiment, the contact vias and contact blocks contain molybdenum (Mo) or tungsten (W). For example, this embodiment is useful when forming a contact block 285 using molybdenum, as voids tend to occur during this process. For example, the conductive barrier 282 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof.

[0032] The lower contact structure 280 introduced in this embodiment can not only form a high-quality contact block 285A, but can also replace the relatively high-resistance conductive barrier 282 with the material of the contact block 285A. Therefore, the lower contact structure 280 can improve electrical characteristics such as contact resistance and reliability. In one embodiment, it may have a sufficient length to adequately remove the conductive barrier. For example, the length d of the extended portion 282E is 10 nm or less, but is not limited to this.

[0033] The semiconductor device 100 according to this embodiment has a double-sided wiring structure including a first wiring structure 190 and a second wiring structure 290. The first wiring structure 190 is provided on the upper surface of the semiconductor device 100, and the second wiring structure 290 is provided on the lower surface of the semiconductor device 100. The first wiring structure 190 includes a first wiring insulation layer 191 and a first wiring line M1 located within the first wiring insulation layer 191. The first wiring line M1 is connected to the upper contact structure 180 by a first via V1 that penetrates the second interlayer insulating layer 162. Similarly, the second wiring structure 290 includes a second wiring insulation layer 291 and a second wiring line M2 located within the second wiring insulation layer 291. In this embodiment, the second wiring line M2 is electrically insulated from the dummy contact block 280B by the second wiring insulation layer 291, while it is connected to the active contact block 280A of the lower contact structure 280 by a second via V2 that penetrates the second wiring insulation layer 291.

[0034] In this structure, power for the element operation is supplied to the first source / drain pattern 150A via the second wiring line M2 and the lower contact structure 280 connected thereto, thereby simplifying the first wiring line M1. For example, the first and second wiring insulating layers (191, 291) may contain low dielectric materials such as silicon oxide, silicon oxynitride, SiOC, and SiCOH. For example, the first and second wiring lines (M1, M2) and the first and second vias (V1, V2) contain copper or a copper-containing alloy.

[0035] Figures 5 and 6 are side cross-sectional views showing a schematic configuration of a semiconductor device according to one embodiment of the present invention. Referring to Figures 5 and 6, the semiconductor device 100A according to this embodiment can be understood to be similar to the semiconductor device 100 shown in Figures 1 to 4b, except that the lower contact structure 280' is configured to contain different metallic materials and that it further includes a metal-semiconductor compound film SC between the contact via 286 and the first source / drain pattern 150A. Furthermore, unless otherwise specified, the components of this embodiment can be understood by referring to the descriptions of components identical or similar to those of the semiconductor device 100 shown in Figures 1 to 4b.

[0036] Similar to the embodiments described above, each of the plurality of contact blocks 285 employed in this embodiment includes a first portion 285a that horizontally overlaps with the extended portion 282E of the conductive barrier 282, and a second portion 285b that contacts the plurality of insulating isolation patterns 230. However, in this embodiment, the first part 285a includes a first metallic substance, and the second part 285b includes a second metallic substance different from the first metallic substance.

[0037] Figure 7 is a magnified view of section "A2" of the semiconductor device shown in Figure 5. Referring to Figures 5 to 7, in this embodiment, the first portion 285a and the second portion 285b of the contact block 285 each contain different first and second metallic materials. For example, the first metallic substance may contain W, Mo, Co, or Ru, and the second metallic substance may contain W or Mo. Since the first and second metallic materials have the same or similar crystal structures, even if the first and second parts (285a and 285b) are made of different metals, the first part 285a can be used as a seed layer for the second part 285b. In this embodiment as well, the second portion 285b of the contact block 285 contains a metal with a nearly single-crystal structure that does not have grain boundaries. For example, the first part 285a is carried out by a non-selective deposition process, such as PVD or CVD, and the second part 285b is carried out by a selective deposition process, i.e., a CVD process.

[0038] In this embodiment, it is preferable from the viewpoint of improving resistance to reduce the extended portion 282E of the conductive barrier 282 to the extent that it provides a seed layer. For example, the length d of the extended portion 282E is between 1 nm and 10 nm, but is not limited to this. Thus, the lower contact structure 280 adopted in this embodiment can not only form a high-quality contact block 285A, but can also replace the relatively high-resistance conductive barrier 282 with the material of the contact block 285A. Therefore, the lower contact structure 280 can improve electrical characteristics such as contact resistance and reliability.

[0039] In this embodiment, a metal-semiconductor compound film SC is placed between the contact via 286 and the first source / drain pattern 150A. Referring to Figure 5, the metal-semiconductor compound film SC extends to the surface region of the semiconductor pattern 105 in contact with the contact via 285. Metal-semiconductor compound films (SC) contain metal-silicide. For example, a metal-semiconductor compound film SC may contain at least one metal from among Ti, Co, Ni, Pt, Zr, Mo, and Sc.

[0040] The features, operation, and effects of this embodiment can be understood in more detail by the following description of the semiconductor device manufacturing method. Figures 8a to 8f and 9a to 9d are cross-sectional views of key processes illustrating some of the processes in the manufacturing method of a semiconductor device according to one embodiment of the present invention, and are understood to be the processes for manufacturing the semiconductor device 100 shown in Figures 1 to 4. Here, Figures 8a to 8f are cross-sectional views corresponding to Figure 2, and Figures 9a to 9d are cross-sectional views corresponding to Figure 3, showing the processes in Figures 8a, 8b, 8c, and 8f, respectively.

[0041] Referring to Figures 8a and 9a, a gate all-around type transistor element is formed on the substrate 101, including a plurality of channel structures CH, a plurality of gate structures GS, and first and second source / drain patterns (150A, 150B). The semiconductor substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI semiconductor. For example, Group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, or an SOI (Silicon On Insulator) layer.

[0042] The multiple channel structures include multiple channel patterns 130 stacked vertically spaced apart from each other on a semiconductor pattern 105 that extends in a first direction (e.g., the X direction). Multiple gate structures GS are formed to surround multiple channel patterns 130, each traversing multiple channel structures CH in a second direction (for example, the Y direction). The first and second source / drain patterns (150A, 150B) are located in recess regions that extend from between the multiple channel structures CH to a portion of the semiconductor pattern 105 and are connected to both sides of the multiple channel patterns 130 in a first direction (e.g., the X direction), respectively.

[0043] Furthermore, a first interlayer insulating layer 161 is formed between multiple gate structures GS, covering the first and second source / drain patterns (150A, 150B), and an upper contact structure 180 is formed that penetrates the first interlayer insulating layer 161 and is connected to the first source / drain pattern 150A. Furthermore, a second interlayer insulating layer 162 is formed on the first interlayer insulating layer 161 so as to cover multiple gate structures GS, and a first wiring structure 190 is formed which is connected to the upper contact structure 180. Since the first wiring structure is formed in advance, subsequent processes must be carried out at relatively low temperatures (for example, below 400°C) in order to avoid adversely affecting the metal components of the first wiring structure 190. For example, along with the process of forming the first opening TH for the insulating isolation pattern (see Figure 8d), it is necessary to form a conductive barrier of sufficient thickness (see Figure 10b) to prevent pinhole defects.

[0044] Next, referring to Figures 8b and 9b, the substrate 101 is removed, leaving the semiconductor pattern 105 partially intact. This process is carried out sequentially in the steps of removing the substrate 101 and partially removing the semiconductor pattern 105. First, the removal of the substrate 101 is carried out by a polishing process and / or an etching process. This removal process is carried out until the element isolation layer 110 is exposed. Furthermore, by partially removing the semiconductor pattern 105 using a selective etching process, a semiconductor pattern 105 of a predetermined thickness is left behind. The remaining semiconductor pattern 105 extends in the first direction and has a recessed lower surface compared to the exposed lower surface of the device isolation layer 110, as shown in Figure 9b. The element isolation layer 110 defines the space FH where the semiconductor pattern 105 is removed.

[0045] Next, referring to Figures 8c and 9c, an insulating separation layer 210 is formed on the lower surface of the remaining semiconductor pattern 105, and an insulating base layer 220 is formed on the insulating separation layer 210. First, an insulating isolation layer 210 is formed on the semiconductor pattern 105 and the device isolation layer 110. As shown in Figure 9c, the insulating isolation layer 210 is formed along the recessed lower surface of the semiconductor pattern 105, the side wall exposed to the space FH, and the lower surface of the element isolation layer 110. The insulating separation layer 210 is formed relatively conformally using a deposition process such as CVD. For example, the insulating separation layer 210 may be silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0046] The insulating base layer 220 is formed to fill the space FH on the insulating isolation layer 210 where the semiconductor pattern 105 is partially removed. The insulating base layer 220 may include, for example, SOH, FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or a combination thereof. For example, the insulating base layer 220 can be formed using chemical vapor deposition, fluid CVD, or spin coating processes, respectively. In one embodiment, a planarization process can be further performed on the lower surface of the insulating base layer 220.

[0047] Next, referring to Figure 8d, the insulating base layer 220 and the insulating separation layer 210 are partially removed to form a plurality of first openings TH. Using a selective etching process, multiple first openings TH are formed in the insulating base layer 220 in the corresponding regions beneath each of the multiple gate structures GS. Multiple first openings TH extend through the insulating separation layer 210 to the gate structure GS. In this embodiment, the semiconductor pattern 105 is formed to be separated into multiple units by a plurality of first apertures TH.

[0048] The etching process for multiple first openings TH is performed at a relatively low temperature (e.g., below 400°C) to avoid adversely affecting the metal components of the first wiring structure 190, and therefore is unlikely to form an almost vertical structure. Therefore, the first opening TH inevitably has a tapered structure. As shown in Figure 8d, each of the multiple first openings TH has a shape in which the width Wb' of the portion adjacent to the lower surface of the insulating base layer 220 is greater than the width Wa of the portion adjacent to the multiple gate structures GS. Furthermore, due to differences in etching rates, the internal sidewalls of the semiconductor layer 105 and the internal sidewalls of the insulating base layer 220 have different profiles (e.g., inclination angles).

[0049] Next, referring to Figure 8e, an insulating isolation pattern 230 is formed in each of the multiple first openings TH. In this embodiment, a vapor deposition process is performed to form insulating separation patterns 230 in a plurality of first openings TH. The deposition process for the insulating material is carried out so that the first opening TH is filled. For example, the insulating isolation pattern 230 includes silicon nitride or silicon oxynitride. In the insulating material deposition process that forms multiple insulating separation patterns 230, the insulating separation patterns are formed to cover the lower surface of the insulating base layer 220, and further polishing is performed to expose the lower surface of the insulating base layer 220, as shown in Figure 8e, resulting in a surface that is substantially flat with the lower surface of the insulating separation patterns 230.

[0050] Next, referring to Figures 8f and 9d, the insulating base layer 220 is removed to create the second opening CS. The second aperture CS roughly corresponds to the space FH where the semiconductor pattern 105 is partially removed under the respective first and second source / drain patterns (150A, 150B). An insulating isolation layer 210 is formed on the inner surface of the second opening CS and on the lower surface of the element isolation layer 110. In this removal process, the insulating separation layer 210 is used as an etching stop layer. The width of each second opening CS in its first direction (e.g., the X direction) is defined by a plurality of insulating isolation patterns 230, and the width of each second opening CS in its second direction (e.g., the Y direction) is defined by the space FH in which the semiconductor pattern 105 on which the insulating isolation layer 210 is formed is partially removed (see Figure 9b).

[0051] Figures 10a to 10d and 11a to 11d are cross-sectional views showing key steps in a partial process (back contact formation process) for manufacturing a semiconductor device according to one embodiment of the present invention. Here, Figures 10a to 10d are cross-sectional views corresponding to Figure 2, and Figures 11a to 11d are cross-sectional views corresponding to Figure 3, each showing the process in Figures 10a to 10d. Referring to Figures 10a and 11a, a third opening CH' connected to the first source / drain pattern 150A is further formed in at least one of the second openings CS.

[0052] This selective removal process is applied to the second opening CS located below the first source / drain pattern 150A. A portion of the insulating separation layer 210 exposed at the second opening CS is removed, and the semiconductor pattern 105 is removed through the removed region, thereby forming a third opening CH' connected to the first source / drain pattern 150A. The second opening CS, on which the third opening CH' is formed, is provided in the space that forms the active contact block 285A connected to the first source / drain pattern 150A, and the third opening CH' is provided in the space that forms the contact via 286. Furthermore, the remaining second opening CS is provided in the region that forms the dummy contact block 285B below the second source / drain pattern 150B.

[0053] Next, referring to Figures 10b and 11b, the second opening CS and the third opening CH' are filled with the conductive barrier 282 and the first conductive material MP1 (or contact plug) to form the lower contact structure 280 and the dummy contact block 285B. Prior to the deposition of the first conductive material MP1, a conductive barrier 282 is conformally formed along the surface exposed by the second opening CS and the third opening CH'. Since the conductive barrier 282 is formed at a relatively low temperature (e.g., below 400°C) so as not to adversely affect the metal component of the first wiring structure 190, it needs to be formed with a sufficient thickness to prevent pinhole defects. Therefore, the relatively high-resistance conductive barrier 282 may inevitably fill the second opening CS and the third opening CH' to a certain level.

[0054] Next, the first conductive material MP1 is formed in the second opening CS such that the third opening CH' is filled on the conductive barrier 282. The deposition process for the first conductive material MP1 is carried out using a non-selective deposition process, such as CVD or PVD. Since the deposited first conductive material MP1 grows from almost the entire surface of the conductive barrier 282, it can be a polycrystalline metal. Therefore, the deposited first conductive material MP1 has a large electrical resistance compared to a single-crystal metal because it has a large distribution of grain boundaries. The first conductive material MP1 is filled into the third opening CH' to form a contact via 286 connected to the exposed region of the first source / drain pattern 150A.

[0055] Next, referring to Figures 10c and 11c, an etch-back process is performed on the deposited first conductive material MP1. This etching process is carried out under conditions that remove not only the first conductive material MP1 but also the conductive barrier 282 together. This etching process removes the first conductive material MP1 and conductive barrier 282 located at the second opening CS', but is carried out in such a way that a portion of the first conductive material MP1 remains. The remaining first conductive material 285a is used as a seed layer. Here, it is sufficient for the first conductive material 285a to remain with a thickness such that there are almost no pinholes, and for example, it may have a thickness of 1 nm or more, but is not limited to this. In this etch-back process, the conductive barrier 282 is removed along with the majority of the sidewalls of the insulating isolation pattern 230 that defines the second opening CS'. This significantly reduces the volume of the conductive barrier 280, which has relatively high resistance, thereby improving the electrical characteristics of the final lower contact structure 280.

[0056] Next, referring to Figures 10d and 11d, the second conductive material MP2 is deposited onto the remaining first conductive material portion 285a. In this embodiment, the second conductive material MP2 is the same material as the first conductive material MP1. For example, the first conductive material MP1 is molybdenum, and the second conductive material MP2 is also molybdenum. The present invention is not limited thereto, and the first and second conductive materials (MP1, MP2) may be other conductive materials having the same or similar crystal structure. The second conductive material MP2 is formed by selective deposition. The second conductive material MP2 was grown using a bottom-up method with the remaining first conductive material portion 285a as a seed layer, and as a result, it has a nearly single-crystal structure. For example, when growing the second conductive material MP2 in the ALD (Atomic Layer Deposition) process, MoCl5, which allows for selective deposition, is used as a precursor.

[0057] In one embodiment, the deposition of the first conductive material MP1 (see Figure 10b) and the deposition of the second conductive material MP2 (see Figure 10d) are both performed in the ALD process. However, different precursors may be used and the deposition may be performed by non-selective deposition (i.e., conformal filling) and selective deposition (i.e., bottom-up growth), respectively. For example, if both the first and second conductive materials (MP1 and MP2) are molybdenum (Mo), then MoO2Cl2 can be used as a precursor for the deposition of the first conductive material MP1, and MoCl5 can be used as a precursor for the deposition of the second conductive material MP2.

[0058] In this way, by etching back the contact block 285 together with the conductive barrier 282 so that only a portion 285a of the first conductive material MP1 that has been grown in the primary stage remains, the volume of the highly resistive conductive barrier is reduced in the final lower contact structure, and the second conductive material is regrowthed using the remaining region 285a as a seed, thereby providing a high-quality contact block 285 (minimizing grain boundaries).

[0059] Next, a polishing process is performed so that the second conductive material MP2 is removed and the lower surface of the insulating separation pattern 230 is exposed. As a result, the contact blocks 285 are separated from each other by the insulating separation pattern 230. This polishing process is carried out so that the semiconductor device 100 is reduced to a desired thickness. A second wiring structure 290 is formed on the insulating isolation pattern 230 and the contact block 285.

[0060] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0061] 100 Semiconductor Devices 105 Semiconductor Patterns 130 channel pattern 141 Gate Spacer 142 Gate insulating film 145 Guard gate 147 Gate capping layer 150 Source / Drain Patterns 150B Second Source / Drain Pattern 151, 152 (First and Second) Epitaxial Layers 161, 162 (First and Second) Interlayer Insulation Layers 180 Upper Contact Structure 190 1st wiring structure 210 Insulating separation layer 230 insulating isolation patterns 280 Lower Contact Structure 282 Conductive barrier 285 Contact Block 286 Contact vias 290 2nd wiring structure 291 Second wiring insulation layer GS Gate Structure M1, M2 (1st, 2nd) wiring lines V1, V2 (First, Second) Via

Claims

1. A semiconductor pattern extended in the first direction, A plurality of channel structures arranged on the semiconductor pattern, spaced apart from each other in a first direction, Here, each of the plurality of channel structures includes a plurality of channel patterns, Each of the aforementioned plurality of channel structures is crossed in a second direction intersecting the first direction, and a plurality of gate structures surround the plurality of channel patterns, On the semiconductor pattern, a source / drain pattern is disposed between the plurality of channel structures and connected to the side of the plurality of channel patterns, An insulating isolation layer is disposed on the lower surface of the semiconductor pattern, On the lower surface of the insulating isolation layer, a plurality of insulating isolation patterns are arranged in regions corresponding to the plurality of gate structures, each extending toward the plurality of gate structures, and separating the semiconductor pattern into a plurality of patterns. On the lower surface of the insulating separation layer, a plurality of contact blocks are arranged between adjacent insulating separation patterns among the plurality of insulating separation patterns, At least one contact via extends from at least one of the plurality of contact blocks through the insulating isolation layer to an adjacent source / drain pattern in the source / drain pattern, A conductive barrier is disposed between the insulating separation layer and the plurality of contact blocks and extends to the surface of at least one contact via, Here, each of the plurality of contact blocks has a side surface that contacts the side wall of the plurality of insulating isolation patterns, A semiconductor device comprising a plurality of contact blocks and a wiring structure disposed on the lower surface of the plurality of insulating isolation patterns and electrically connected to at least one of the contact blocks.

2. The semiconductor device according to claim 1, characterized in that, in a cross-section in the first direction, each of the plurality of insulating isolation patterns has a shape in which the width of the portion adjacent to the wiring structure is greater than the width of the portion adjacent to the plurality of gate structures.

3. The semiconductor device according to claim 1, characterized in that, in a cross-section in the first direction, each of the plurality of contact blocks has a shape in which the width of the portion adjacent to the wiring structure is smaller than the width of the portion adjacent to the insulating separation layer.

4. The semiconductor device according to claim 1, characterized in that the conductive barrier has a portion that extends from the side walls of the plurality of insulating separation patterns to a portion adjacent to the insulating separation layer.

5. The semiconductor device according to claim 4, characterized in that each of the plurality of contact blocks contains the same metallic substance as the contact via.

6. The semiconductor device according to claim 4, characterized in that each of the plurality of contact blocks contains a metal with a single crystal structure.

7. Each of the aforementioned contact blocks is The first portion of the conductive barrier overlaps the extended portion horizontally with the first portion, A second portion that contacts the plurality of insulating isolation patterns, The semiconductor device according to claim 4, characterized in that the first and second parts contain different metallic materials.

8. The semiconductor device according to claim 7, characterized in that the contact via contains the same metallic substance as the first portion of the plurality of contact blocks.

9. The semiconductor device according to claim 1, characterized in that the plurality of contact blocks and the at least one contact via include tungsten (W) or molybdenum (Mo).

10. The semiconductor device according to claim 1, characterized in that the conductive barrier includes Ta, TaN, Ti, or TiN.

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