Phase change material device using sidewall liners and method for forming the same

Abstract

By suppressing the effects of resistive drift, the phase-change memory cell of the present invention can improve performance, reliability, and efficiency in CIM applications. [Solution] The device structure may be provided by: forming a bottom electrode and a heater element in a dielectric material layer; depositing and patterning a continuous layer stack including a bottom liner layer, a phase change material layer including a phase change material, and an upper electrode material layer; and depositing and patterning a sidewall liner material to form at least one sidewall liner. The at least one sidewall liner is formed on at least one sidewall of the patterned portion of the continuous layer stack. The at least one sidewall liner includes a material having a conductivity higher than the conductivity of the amorphous phase of the phase change material.

Description

[Background technology]

[0001] Phase-change material (PCM) devices can be used in memory-based computing applications due to their scalability and non-volatility. However, PCM devices are known to be susceptible to resistive drift, particularly in high-resistance states (HRS), which can negatively impact computing accuracy. Improving the reliability of PCM devices in high-performance computing applications such as computation in memory (CIM) requires enhanced reliability in high-resistance states. [Overview of the Initiative] [Problems that the invention aims to solve]

[0002] Phase-change memory (PCM) devices can be used to store weights in computation-in-memory (CIM) applications. Achieving high efficiency and low power consumption in CIM depends on the accuracy of the weights. In other words, the resistance programmed into the PCM memory cell must be able to reproduce the target resistance with high reliability. Resistance in high-resistance states can be volatile. Furthermore, both low-resistance (LRS) and high-resistance (HRS) states exhibit resistance drift. Resistance drift varies with the number of program cycles and can lead to weight instability and increased error rates in CIM calculations. Additionally, associated PCM designs, where HRS resistance is dominated by mushroom-shaped amorphous regions, often suffer from inherent limitations such as large cell size, narrow memory windows, and high write power. These inherent limitations can impair the efficiency, scalability, and accuracy of PCMs in modern CIM applications. [Means for solving the problem]

[0003] The present invention provides a method for forming a device structure in several embodiments. The method includes: forming a bottom electrode and a heater element in a dielectric material layer; depositing and patterning a continuous layer stack including a bottom liner layer, a phase change material layer including a phase change material, and an upper electrode material layer; and forming at least one sidewall liner by depositing and patterning a sidewall liner material, wherein the at least one sidewall liner is formed on at least one sidewall of the patterned portion of the continuous layer stack, and the at least one sidewall liner comprises a material having a conductivity higher than that of the amorphous phase of the phase change material.

[0004] The present invention provides a device structure in several embodiments. The device structure includes: a bottom electrode and heater element formed in a dielectric material layer; a layer stack including a bottom liner layer, a phase change material portion including a phase change material, and an upper electrode; and at least one sidewall liner disposed on at least one sidewall of the layer stack and containing a material having a conductivity higher than that of the amorphous phase of the phase change material.

[0005] The present invention provides a device structure in several embodiments. The device structure includes a programming transistor disposed on a substrate; a bottom electrode and heater element formed in a dielectric material layer, the heater element being electrically connected to the electrical node of the programming transistor; and a phase change memory cell comprising a layer stack including a bottom liner, a phase change material portion including a phase change material, and an upper electrode, disposed on at least one sidewall of the layer stack and further comprising at least one sidewall liner, wherein the programming transistor is configured to program the phase change memory cell to at least three different resistive states by applying at least three different programming pulse patterns to the heater element. [Effects of the Invention]

[0006] According to the present invention, the resistive drift of a phase-change memory cell can be reduced to an extremely small level, and the weights in CIM applications represented by the resistance of the phase-change memory cell can be stabilized. Embodiments of the present invention can provide reduced power consumption, smaller cell size, and improved reliability for accurate calculations. By suppressing the effects of resistive drift, the phase-change memory cell of the present invention can improve performance, reliability, and efficiency in CIM applications. [Brief explanation of the drawing]

[0007] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. For clarity of explanation, the dimensions of various features may be arbitrarily enlarged or reduced. [Figure 1] This is a vertical cross-sectional view of an intermediate embodiment structure after forming a field-effect transistor, a metal interconnect structure, and a dielectric material layer according to one embodiment of the present invention. [Figure 2] This is a vertical cross-sectional view of an intermediate embodiment structure after forming a via cavity penetrating a dielectric material layer according to one embodiment of the present invention. [Figure 3] This is a vertical cross-sectional view of an intermediate embodiment structure after forming a metal via structure according to one embodiment of the present invention. [Figure 4] This is a vertical cross-sectional view of an intermediate embodiment structure after the bottom electrode and heater cavity have been formed according to one embodiment of the present invention. [Figure 5] This is a vertical cross-sectional view of an intermediate embodiment structure after lateral expansion of the heater cavity according to one embodiment of the present invention. [Figure 6] This is a vertical cross-sectional view of an intermediate embodiment structure after the heater element has been formed according to one embodiment of the present invention. [Figure 7] This is a vertical cross-sectional view of an intermediate embodiment structure after forming a continuous layer stack including a bottom liner layer, a phase change material layer including a phase change material, and an upper electrode material layer, according to one embodiment of the present invention. [Figure 8] This is a vertical cross-sectional view of an intermediate embodiment structure after the continuous layer stack has been patterned into an in-process layer stack including an in-process bottom liner, an in-process phase change material portion, and an in-process upper electrode, respectively, according to one embodiment of the present invention. [Figure 9] This is a vertical cross-sectional view of an intermediate embodiment structure after the sidewall liner layer has been formed according to one embodiment of the present invention. [Figure 10] This is a vertical cross-sectional view of an intermediate embodiment structure after an in-process sidewall liner has been formed according to one embodiment of the present invention. [Figure 11] This is a vertical cross-sectional view of an intermediate embodiment structure after an in-process layer stack has been patterned into a layer stack including a bottom liner, a phase change material portion, and an upper electrode, according to one embodiment of the present invention, and the in-process sidewall liner has been patterned into a sidewall liner. [Figure 12] This is a vertical cross-sectional view of the structure of the embodiment after the patterned etching mask layer has been removed, according to one embodiment of the present invention. [Figure 13A] Figures 10-12 show one of a series of top views of the region of the first configuration of the embodiment structure in the processing steps. [Figure 13B] Figures 10-12 show one of a series of top views of the region of the first configuration of the embodiment structure in the processing steps. [Figure 13C] Figures 10-12 show one of a series of top views of the region of the first configuration of the embodiment structure in the processing steps. [Figure 14A] Figures 10-12 show one of a series of top views of the region of the second configuration of the embodiment structure in the processing steps. [Figure 14B] Figures 10-12 show one of a series of top views of the region of the second configuration of the embodiment structure in the processing steps. [Figure 14C] Figures 10-12 show one of a series of top views of the region of the second configuration of the embodiment structure in the processing steps. [Figure 15A]Shows one of the continuous top views of the area of the third configuration of the embodiment structure in the processing steps of FIGS. 10 to 12. [Figure 15B] Shows one of the continuous top views of the area of the third configuration of the embodiment structure in the processing steps of FIGS. 10 to 12. [Figure 15C] Shows one of the continuous top views of the area of the third configuration of the embodiment structure in the processing steps of FIGS. 10 to 12. [Figure 16] Is a top view of the area of the fourth configuration of the embodiment structure after the processing step of FIG. 10. [Figure 17] Is a vertical cross-sectional view of the embodiment structure after forming a sealing dielectric material layer and an additional metal interconnect structure according to an embodiment of the present invention. [Figure 18A] Is one of the various configurations of the phase change material portion in various programmed resistance states according to an embodiment of the present invention. [Figure 18B] Is one of the various configurations of the phase change material portion in various programmed resistance states according to an embodiment of the present invention. [Figure 18C] Is one of the various configurations of the phase change material portion in various programmed resistance states according to an embodiment of the present invention. [Figure 18D] Is one of the various configurations of the phase change material portion in various programmed resistance states according to an embodiment of the present invention. [Figure 19] Is a vertical cross-sectional view of the first alternative configuration of the embodiment structure after forming a heater element according to an embodiment of the present invention. [Figure 20] Is a vertical cross-sectional view of the first alternative configuration of the embodiment structure after forming a sealing dielectric material layer and an additional metal interconnect structure according to an embodiment of the present invention. [Figure 21] Is a vertical cross-sectional view of the second alternative configuration of the embodiment structure after forming a heater element according to an embodiment of the present invention. [Figure 22] Is a vertical cross-sectional view of the second alternative configuration of the embodiment structure after forming a sealing dielectric material layer and an additional metal interconnect structure according to an embodiment of the present invention. [Figure 23] This flowchart shows general processing steps for manufacturing a device structure according to an embodiment of the present invention. [Modes for carrying out the invention]

[0008] The following disclosure provides many different embodiments or examples for realizing various features of the subject matter of the present invention. Specific examples of components and arrangements are described below to clarify the present invention. These are merely examples and not limiting. The drawings are not drawn to scale. Elements with the same reference numeral refer to the same element and are considered to have the same material composition and the same thickness range unless otherwise specified. All features of the original embodiment are considered to be present in the derived embodiment unless otherwise specified. Thus, features described in the drawings and / or herein with reference to relevant embodiments are relatable to the features of the embodiment. Embodiments in which the described elements are repeated multiple times are explicitly assumed unless otherwise specified. Embodiments in which non-essential elements are omitted are explicitly assumed, even if such embodiments are known in the art but are not explicitly disclosed.

[0009] Furthermore, as shown in the figures, spatially relative terms such as “down,” “below,” “bottom,” “up,” and “top” may be used herein to facilitate the description of the relationship between one element or feature and another. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may be positioned in other orientations (90-degree rotation or other directions), and the spatially relative descriptions used herein should be interpreted accordingly. Unless otherwise specified, elements bearing the same reference numeral are presumed to have the same material composition and thickness within the same thickness range.

[0010] Various embodiments of the present invention can provide a phase-change memory cell using at least one sidewall liner. Each sidewall liner is formed on the sidewall of the phase-change material portion and can control the resistance in the high-resistance state. Furthermore, the phase-change material portion can be programmed to form different volumes relative to the amorphous volume of the phase-change material portion. In such embodiments, the phase-change material portion can be programmed to have three or more different states with different resistance values, thereby providing a configuration suitable for CIM operation. Furthermore, a bottom liner may be provided below the phase-change material portion and on the heater element.

[0011] The overall resistance of a phase-change memory cell may also be determined by the surface area of ​​the bottom liner and sidewall liner combination separated from the crystalline volume of the phase-change memory cell, i.e., the surface area of ​​the bottom liner and sidewall liner combination in contact with the amorphous volume of the phase-change memory cell. Since the overall resistance of a phase-change memory cell can be determined by the resistance of the segments of the bottom liner and sidewall liner in contact with the amorphous volume of the phase-change memory cell, the resistance drift of the phase-change memory cell can be reduced to an extremely small level, and the weight in CIM applications indicated by the resistance of the phase-change memory cell can be stabilized.

[0012] The resistance range of the phase-change memory cell can be extended by increasing the resistivity of the sidewall liner material relative to the resistivity of the bottom liner material, which may be achieved by incorporating nitrogen atoms or carbon atoms into the metallic material of the sidewall liner. Embodiments of the present invention can provide reduced power consumption, smaller cell size, and improved reliability for accurate calculations. By suppressing the effects of resistive drift, the phase-change memory cell of the present invention can improve performance, reliability, and efficiency in CIM applications. Various embodiments of the present invention will be described below with reference to the accompanying drawings.

[0013] Referring to Figure 1, an intermediate embodiment structure according to the present invention is shown. The intermediate embodiment structure includes a substrate 8. The substrate 8 may be a semiconductor substrate such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least on its upper surface. The semiconductor material layer 9 may be the surface portion of a bulk semiconductor substrate, or it may be the top semiconductor layer of a semiconductor on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate containing a single-crystal silicon material.

[0014] A shallow trench isolation structure 720 containing a dielectric material such as silicon oxide may be formed on top of the semiconductor material layer 9. Within each region laterally enclosed by a portion of the shallow trench isolation structure 720, appropriate doped semiconductor wells such as p-type wells and n-type wells may be formed.

[0015] A semiconductor device 700 may be formed on the semiconductor material layer 9. The semiconductor device 700 may include a complementary metal-oxide-semiconductor (CMOS) transistor and optionally additional semiconductor devices (such as resistors, diodes, and capacitor structures). The semiconductor device 700 may include a programming transistor 701 formed in the memory array region 100 and a peripheral transistor 702 formed in the peripheral region 300. Each field-effect transistor (701, 702) may include a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. In one embodiment, the channel region may include a part of the semiconductor material layer 9 and may include a single-crystal semiconductor material. Each programming transistor 701 may be configured to provide a series of programming pulses to each subsequently formed phase-change memory cell. The peripheral transistor 702 may be formed as a component of a peripheral circuit that controls the operation of the programming transistor 701 and as an interface with an input / output (I / O) circuit (not shown).

[0016] In one embodiment, the substrate 8 includes a single-crystal silicon substrate, and the field-effect transistors (701, 702) may include each portion of the single-crystal silicon substrate as a semiconductor channel. In this specification, the term "semiconductor" refers to a 1.0x10⁻¹⁰ element. -6 S / cm~1.0x10 5 This refers to an element having conductivity in the range of S / cm. In this specification, "semiconductor material" means a material with conductivity of 1.0 x 10⁻¹⁰ in the absence of an electrical dopant. -6 S / cm~1.0x10 5 It has conductivity in the range of S / cm, and by appropriately doping with an electrical dopant, it can be increased to 1.0 S / cm ~ 1.0 x 10⁻¹⁰ 5 This refers to a material capable of producing doped materials with conductivity in the range of S / cm.

[0017] Various metal interconnection structures can be formed within the dielectric material layer formed on the substrate 8 and on the semiconductor device. In one exemplary example, the dielectric material layer may include, for example, a first dielectric material layer 601 (sometimes called a contact-level dielectric material layer 601) which surrounds a contact structure connected to a source and a drain, a first interconnection-level dielectric material layer 610, a second interconnection-level dielectric material layer 620, a third interconnection-level dielectric material layer 630, and a fourth interconnection-level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the first dielectric material layer 601 and in contact with each component of the semiconductor device 700, a first metal wiring structure 618 formed in the first interconnection-level dielectric material layer 610, a first metal via structure 622 formed below the second interconnection-level dielectric material layer 620, a second metal wiring structure 628 formed above the second interconnection-level dielectric material layer 620, a second metal via structure 632 formed below the third interconnection-level dielectric material layer 630, and a third metal wiring structure 638 formed above the third interconnection-level dielectric material layer 630. In this specification, an additional dielectric material layer referred to as a lower fourth interconnection-level dielectric material layer 641 may be formed on the third interconnection-level dielectric material layer 630.

[0018] Each dielectric material layer (601, 610, 620, 630, 641) may contain dielectric materials such as undoped silicate glass, doped silicate glass, organic silicate glass, amorphous fluorinated carbon, porous heterogenes thereof, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628, 632, 638) may contain at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or metal carbide) and a metal filler. Each metal liner may contain TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. In one embodiment, the first metal via structure 622 and the second metal wiring structure 628 may be formed as an integrated line and via structure by a dual damascene process. Generally, any consecutive set of metal wiring structures (628, 638) and at least one metal via structure (622, 632) beneath them may be formed as an integrated line and via structure.

[0019] Generally, a semiconductor device (such as a field-effect transistor (701, 702)) is formed on a substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638) and dielectric material layers (601, 610, 620, 630, 641) are formed on the semiconductor device. The metal interconnect structures (612, 618, 622, 628, 632, 638) may be formed within the dielectric material layers (601, 610, 620, 630, 641) or they may be electrically connected to the semiconductor device.

[0020] In summary, a programming transistor 701 may be formed on the substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638) formed within the interconnection-level dielectric material layers (601, 610, 620, 630, 641) may be formed on the programming transistor 701. The metal interconnect structures (612, 618, 622, 628, 632, 638) may be configured to be electrically connected to the heater elements of the phase-change memory cells that are subsequently formed.

[0021] According to one aspect of the present invention, the programming transistor 701 may be configured to program each of the phase-change memory cells to at least two different resistance states, preferably at least three different resistance states, and more preferably at least four different resistance states. Programming each phase-change memory cell to a different resistance state may be performed by selecting a pulse pattern from a set of pre-programmed pulse patterns that each programming transistor 701 can apply. The pulse patterns may differ from one another in terms of the duration of the pulse pattern and the peak voltage of the pulse pattern. In one embodiment, the total number of resistance states that may be programmed into the phase-change memory cells may be in the range of 2 to 64, for example, 3 to 16 and / or 4 to 8, but more resistance states may be programmed by changing the pulse patterns generated from each programming transistor 701 as needed.

[0022] Referring to Figure 2, the via cavities 41 may be formed through a dielectric material layer (e.g., the lower fourth wiring level dielectric material layer 641). Each via cavity 41 is formed on each of the underlying metal interconnect structures (e.g., a subset of the third metal interconnect structure 638), and the upper segments of the underlying metal interconnect structures may be physically exposed. The dielectric material layer on which the via cavities 41 are formed includes a heat-resistant dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the dielectric material layer may be in the range of 200 nm to 1,000 nm, but thinner or thicker thicknesses may also be used. The lateral dimension (e.g., diameter) of each via cavity 41 may be in the range of 30 nm to 300 nm, but thinner or thicker lateral dimensions may also be used. Peripheral via cavities 6411 may be formed through a dielectric material layer within the peripheral region 300.

[0023] Referring to Figure 3, a highly conductive metal filler, such as copper or tungsten, may be deposited in the via cavity 41 and the peripheral via cavity 6411. A metal liner material, such as a conductive metal nitride material, may optionally be deposited as a thin liner before the metal filler is deposited. Excess metal filler may be removed from above the horizontal plane including the upper surface of the dielectric material layer (e.g., the lower fourth interconnection level dielectric material layer 641) by performing a planarization process (which may include a recess etching process and / or a chemical mechanical polishing process). Any metal liner material filling each via cavity 41 and the remaining portions of metal filler each constitute an in-process bottom electrode 42', which is then modified to become the bottom electrode of each phase-change memory cell. In this specification, “in-process” component means a component that is subsequently modified structurally or compositionally. Any metal liner material filling the peripheral via cavity 6411 and the remaining portions of metal filler each constitute the lower peripheral via structure 6421.

[0024] Referring to Figure 4, a masking layer 57, such as a patterned photoresist layer, may be formed on the dielectric material layer (e.g., the lower fourth interconnection level dielectric material layer 641) to cover the peripheral region 300 without covering the memory array region 100. A recess etching process may be performed to selectively recess the in-process bottom electrode 42' with respect to the material of the dielectric material layer, i.e., without removing the material of the dielectric material layer. The recess etching process may include a wet etching process or a reactive ion etching process. The upper part of the in-process bottom electrode 42' may be removed by the recess etching process. The remaining portion of the in-process bottom electrode 42' constitutes the bottom electrode 42 of the subsequently formed phase change memory cell. A heater cavity 47 may be formed in the volume from which the upper part of the in-process bottom electrode 42' can be removed. The height of the bottom electrode 42 may be in the range of 100 nm to 800 nm, for example, 200 nm to 400 nm, but lower or higher heights may also be used. The depth of the heater cavity 47 may be in the range of 100 nm to 800 nm, for example, 200 nm to 400 nm, but lower or higher heights may also be used.

[0025] Referring to Figure 5, the isotropic recess etching process may be performed to isotropically recess the physically exposed surfaces of the dielectric material layer, including the sidewalls of the heater cavity 47 and the flat upper surface of the dielectric material layer. For example, in embodiments in which the dielectric material layer (e.g., the lower fourth interconnection level dielectric material layer 641) includes silicate glass, the isotropic recess etching process may include a wet etching process using dilute hydrofluoric acid. The duration of the isotropic recess etching process may be selected so that the recess distance of the dielectric material layer is in the range of 1 nm to 100 nm, for example, 5 nm to 50 nm, although smaller or larger recess distances may also be used. In this embodiment, the upper surface of the dielectric material layer may have a step between the memory array region 100 and the peripheral region 300. In embodiments in which the isotropic recess etching process is performed, the heater cavity 47 can be expanded laterally. Generally, the metallic material later deposited in the heater cavity 47 has a higher electrical resistivity than the metal filler of the bottom electrode 42. Lateral extension of the heater cavity 47 may be advantageously utilized to optimize the electrical resistance of the heater element later formed within the heater cavity 47. The masking layer 57 may then be removed, for example, by ashing.

[0026] Referring to Figure 6, a metal heater material having a higher conductivity than the metal filler of the bottom electrode 42 may be deposited in the heater cavity 47. The metal heater material may include and / or be essentially composed of at least one metal nitride material such as TiN, TaN, WN, and / or MoN. The metal heater material may be deposited by chemical vapor deposition or physical vapor deposition. In one embodiment, the metal heater material may include stoichiometric or near-stoichiometric metal nitride materials such as TiN, TaN, WN, and / or MoN. If the aspect ratio (i.e., height-to-width ratio) of the heater cavity 47 is greater than 1, the metal heater material may be deposited using conformal deposition methods such as chemical vapor deposition.

[0027] The planarization process may be performed to remove a portion of the metal heater material deposited on the upper surface of the dielectric material layer (such as the lower fourth interconnection level dielectric material layer 641) that embeds the bottom electrode 42. The planarization process may include a selective recess etching process that selectively etches the metal heater material against the dielectric material of the dielectric material layer. Each remaining portion of the metal heater material filling each of the heater cavities 47 constitutes a heater element 48. In one embodiment, the upper surface of the heater element 48 may be coplanar, or substantially coplanar, with a portion of the upper surface of the dielectric material layer (such as the lower fourth interconnection level dielectric material layer 641) located in the memory array region 100.

[0028] For each phase-change memory cell formed thereafter, bottom electrodes 42 and heater elements 48 may be formed within the dielectric material layer (such as the lower fourth interconnection level dielectric material layer 641). The heater elements 48 are electrically connected to each electrical node (i.e., output node) of the programming transistor 701. In one embodiment, a two-dimensional array of stacked bottom electrodes 42 and heater elements 48 may be formed in the memory array region 100.

[0029] Referring to Figure 7, a continuous layer stack (52L, 54L, 56L) including a bottom liner layer 52L, a phase change material layer 54L containing a phase change material, and an upper electrode material layer 56L may be sequentially deposited on the upper surface of the dielectric material layer (such as the lower fourth interconnection level dielectric material layer 641) that embeds the bottom electrode 42 and the heater element 48.

[0030] The bottom liner layer 52L contains a first metal nitride material. The first metal nitride material may be a stoichiometric or near-stoichiometric metal nitride material. For example, the bottom liner layer 52L may contain TaN, TiN, WN, and / or MoN. In one embodiment, the electrical conductivity of the metal material of the bottom liner layer 52L is 1.0 x 10⁻¹⁰. 3 S / cm~1.0x10 5The density may be in the range of S / cm. The thickness of the bottom liner layer 52L is selected so that the patterned portion of the bottom liner layer 52L provides electrical resistance during the operation of the subsequently formed phase memory cell. For example, the thickness of the bottom liner layer 52L may be in the range of 1 nm to 20 nm, for example, 2 nm to 4 nm, but thinner or thicker thicknesses may also be used. The bottom liner layer 52L may be deposited by chemical vapor deposition or physical vapor deposition.

[0031] The phase-change material layer 54L includes and / or is essentially composed of a phase-change material. In this specification, “phase-change material” means a material having at least two distinct phases that provide different resistivity. The phase-change material (PCM) may be used to store information as resistivity states of the material, which may be in different resistivity states corresponding to the different phases of the material. The distinct phases include an amorphous state having high resistivity and a crystalline state having low resistivity (i.e., lower resistivity than the amorphous state). A transition between the amorphous and crystalline states can be induced in a first part of the programming process by applying an electrical pulse to make the phase-change material amorphous, and then controlling the cooling rate. A second part of the programming process includes controlling the cooling rate of the phase-change material. In embodiments where rapid quenching occurs, the phase-change material may be cooled to an amorphous, high-resistivity state. In embodiments where slow cooling occurs, the phase-change material may be cooled to a crystalline, low-resistivity state.

[0032] Exemplary phase change materials include, but are not limited to, germanium antimony tellurium (GST) compounds such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium tellurium compounds, aluminum selenium tellurium compounds, indium selenium tellurium compounds, and aluminum indium selenium tellurium compounds. In one embodiment, the phase change material of the phase change material layer 54L may include doped GST compounds such as N-doped GST, Si-doped GST, C-doped GST, Ge-doped GST, Ru-doped GST, or Al-doped GST, or doped GeTe compounds such as N-doped GeTe, Si-doped GeTe, C-doped GeTe, or Ge-doped GeTe. The phase change material layer 54L may be deposited by physical vapor deposition. The thickness of the phase change material layer 54L may range from 30 nm to 200 nm, for example, from 50 nm to 90 nm, but thinner or thicker thicknesses may also be used. In one embodiment, the phase change material of the phase change material layer has a conductivity of the amorphous phase of the phase change material in the range of 1.0x10 -8 S / cm to 1.0x10 -3 S / cm, and the conductivity of the crystalline phase of the phase change material is in the range of 1.0x10 -1 S / cm to 1.0x10 3 S / cm and may be selected accordingly.

[0033] The upper electrode material layer 56L includes a metal material such as W, Ta, Ti, Mo, WN, TiN, WN, or MoN. The thickness of the upper electrode material layer 56L may range from 100 nm to 200 nm, but thinner or thicker thicknesses may also be used. The upper electrode material layer 56L may be deposited by chemical vapor deposition or physical vapor deposition.

[0034] Referring to Figure 8, a first patterning process may be performed to pattern the continuous layer stack (52L, 54L, 56L) into an in-process layer stack (52', 54', 56'). Specifically, a first patterned etching mask layer 77 is formed on the continuous layer stack (52L, 54L, 56L). For example, the first patterned etching mask layer 77 may be formed by coating a photoresist layer onto the continuous layer stack (52L, 54L, 56L), patterning the photoresist layer by lithography, and forming an array of individual patterned photoresist material portions. In one embodiment, the first patterned etching mask layer 77 may include a two-dimensional array of patterned photoresist material portions (e.g., a two-dimensional rectangular periodic array) arranged in the memory array region 100. In one embodiment, each patterned photoresist material portion may have a rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimensions of each patterned photoresist material portion may be selected so that at least two phase-change memory cells can be patterned in a subsequent processing step. Alternatively, the lateral dimensions of each patterned photoresist material portion may be selected so that a single phase-change memory cell can be patterned in a subsequent processing step.

[0035] A first anisotropic etching process may be performed to etch portions of the continuous layer stack (52L, 54L, 56L) that are not masked by the first patterned etching mask layer 77. The first anisotropic etching process has an etching chemical reaction that selectively etches the material of the continuous layer stack (52L, 54L, 56L) relative to the material of the dielectric material layer (such as the lower fourth interconnect-level dielectric material layer 641) that embeds the heater element 48. The continuous layer stack (52L, 54L, 56L) is patterned into in-process layer stacks (52', 54', 56') which each include an in-process bottom liner 52', an in-process phase-change material portion 54', and an in-process upper electrode 56'. In this specification, “in-process” component means a component that is structurally and / or compositionally modified in a subsequent processing step. Each in-process bottom liner 52' ​​is a patterned portion of the bottom liner layer 52L. Each in-process phase change material portion 54' is a patterned portion of the phase change material layer 54L. Each in-process upper electrode 56' is a patterned portion of the top electrode material layer 56L. For each in-process layer stack (52', 54', 56'), the sidewall of the in-process bottom liner 52' ​​may coincide perpendicularly with the sidewall of the in-process phase change material portion 54', and may also coincide perpendicularly with the sidewall of the in-process upper electrode 56'. In this specification, the first surface is "perpendicularly coincidental" with the second surface, the second surface is located above or below the first surface, and the first and second surfaces are located in the same vertical plane, which may be planar or curved in horizontal cross-section. The first patterned etching mask layer 77 may then be removed, for example, by ashing.

[0036] Referring to Figure 9, according to one aspect of the present invention, a sidewall liner layer 58L may be deposited on the physically exposed surfaces of the in-process layer stack (52', 54', 56') and on the physically exposed upper surface of the dielectric material layer (e.g., the lower fourth interconnection level dielectric material layer 641) that embeds the bottom electrode 42 and heater element 48. In one embodiment, the sidewall liner layer 58L may include a metal nitride material layer deposited by a conformal deposition process such as chemical vapor deposition. In one embodiment, the sidewall liner layer 58L may include a second metal nitride material which may include TiN, TaN, WN, and / or MoN, and / or be essentially composed of them. The thickness of the sidewall liner layer 58L may be in the range of 1 nm to 20 nm, for example, 2 nm to 4 nm, but thinner or thicker thicknesses may also be used.

[0037] According to one aspect of the present invention, the conductivity of the second metal nitride material can be reduced by incorporating carbon or nitrogen atoms into the metal nitride material layer by in-situ doping or ex-situ doping of carbon or nitrogen atoms, that is, by incorporating carbon or nitrogen atoms during or after the deposition of the sidewall liner layer 58L. For example, carbon or nitrogen atoms may be provided by a reactive carbon-containing gas (such as acetylene or ethylene) or a reactive nitrogen-containing gas (such as ammonia) during chemical vapor deposition in which the sidewall liner layer 58L is deposited. Alternatively, after the deposition process in which the sidewall liner layer 58L is deposited, the sidewall liner layer 58L may be exposed to a high-temperature atmosphere containing reactive carbon-containing species or reactive nitrogen-containing species. Alternatively, an ion implantation process or a plasma doping process may be performed after the deposition process in which the sidewall liner layer 58L is deposited.

[0038] Carbon atoms or nitrogen atoms are incorporated into the second metal nitride material of the sidewall liner layer 58L at an atomic concentration such that the conductivity of the doped metal nitride material of the sidewall liner layer 58L after the incorporation of carbon atoms or nitrogen atoms is less than 1 / 3 of the conductivity of the second metal nitride material before the incorporation of carbon atoms or nitrogen atoms. In an exemplary example, the conductivity of the sidewall liner layer 58L after the incorporation of carbon atoms or nitrogen atoms is 1.0 x 10⁻¹⁰. 1 S / cm~1.0x10 5 It can be within the range of S / cm.

[0039] Generally, the ratio of metal atoms to nitrogen atoms in a stoichiometric metal compound MN (where M is Ta, Ti, Mo, or W) is 1:1. In embodiments where nitrogen doping is used, when forming the sidewall liner layer 58L of the present invention by doping a stoichiometric metal compound with nitrogen atoms, the ratio of metal atoms to nitrogen atoms in the sidewall liner layer 58L may be in the range of 1:1.02 to 1:1.05. In embodiments where carbon doping is used, when forming the sidewall liner layer 58L of the present invention by doping a stoichiometric metal compound with carbon atoms, the ratio of metal atoms, nitrogen atoms, and carbon atoms in the sidewall liner layer 58L may be in the range of 1:1:0.02 to 1:1:0.05. Generally, the atomic concentration of excess nitrogen atoms in the nitrogen-doped metal nitride material may be in the range of 0.02 to 0.05 times the atomic concentration of metal atoms. Similarly, the atomic concentration of carbon atoms in a carbon-doped metal nitride material may be in the range of 0.02 to 0.05 times the atomic concentration of metal atoms.

[0040] In one embodiment, the conductivity of the second metal nitride material of the sidewall liner layer 58L after the doping process may be less than 1 / 3, preferably less than 1 / 10, of the conductivity of the first metal nitride material of the in-process bottom liner 52'. In other words, the in-process bottom liner 52' ​​includes a material having a conductivity at least 3 times, preferably at least 10 times, that of the sidewall liner material of the sidewall liner layer 58L.

[0041] Generally, the first metal nitride material of the bottom liner layer 52L (and the in-process bottom liner 52') and the second metal nitride material (doped metal nitride material) of the sidewall liner layer 58L are selected such that the resistance of the bottom liner patterned from the in-process bottom liner 52' ​​and the resistance of the sidewall liner patterned from the sidewall liner layer 58L govern the resistance of the phase-change memory cell states having high resistance values ​​(including high-resistance states and intermediate-resistance states having relatively high resistance values). In this embodiment, the resistance of the amorphous volume of the phase-change material portion does not determine the resistance of the high-resistance state of the phase-change memory cell. Therefore, the phase-change memory cell can operate without being affected by the resistance drift of the phase-change material.

[0042] Referring to Figure 10, an anisotropic etching process may be performed to remove the horizontally extending portion of the sidewall liner layer 58L. The anisotropic etching process may be selective for the material of the dielectric material layer on which the heater element 48 is formed (such as the lower fourth interconnection level dielectric material layer 641). Each of the remaining vertically extending portions of the sidewall liner layer 58L constitutes an in-process sidewall liner 58' that laterally surrounds each in-process layer stack (52', 54', 56'). Each in-process sidewall liner 58' contacts the sidewalls of the in-process bottom liner 52', the in-process phase change material portion 54', and the in-process upper electrode 56' of each in-process layer stack (52', 54', 56'). In one embodiment, the upper surface segments of each sidewall of the in-process upper electrode 56' may be physically exposed. Generally, the in-process sidewall liner 58' may be formed by conformally depositing a layer of sidewall liner material around each in-process layer stack (52', 54', 56') and then anisotropically etching it.

[0043] Referring to Figure 11, a second patterning process may be performed to pattern the in-process layer stack (52', 54', 56') and the in-process sidewall liner 58'. The second patterned etching mask layer 79 may be formed on the in-process layer stack (52', 54', 56') and the in-process sidewall liner 58' such that it covers a first region of the in-process layer stack (52', 54', 56') and the in-process sidewall liner 58', but does not cover a second region of the in-process layer stack (52', 54', 56') and the in-process sidewall liner 58'. For example, a photoresist layer (not shown) may be provided on the in-process layer stack (52', 54', 56') and the in-process sidewall liner 58', and lithography may be used to pattern a two-dimensional array (such as a rectangular array) of patterned photoresist material portions. In one embodiment, the second patterned etching mask layer 79 may cover at least two separate regions separated by uninterconnected gaps in each in-process layer stack (52', 54', 56') that are not covered by the second patterned etching mask layer 79.

[0044] To etch the unmasked portions of the in-process layer stacks (52', 54', 56') and the in-process sidewall liner 58', a second anisotropic etching process may be performed to etch the portions of the in-process layer stacks (52', 54', 56') and the in-process sidewall liner 58' that are not masked by the second patterned etching mask layer 79. The second anisotropic etching process has an etching chemical reaction that selectively etches the material of the in-process layer stacks (52', 54', 56') and the in-process sidewall liner 58' with respect to the material of the dielectric material layer (such as the lower fourth interconnection level dielectric material layer 641) that embeds the heater element 48.

[0045] In one embodiment, the second patterning process can pattern each consecutive combination of in-process layer stacks (52', 54', 56') and in-process sidewall liners 58' into a plurality of separate material portions that are not adjacent to each other. In one embodiment, each patterned portion of the in-process layer stacks (52', 54', 56') includes a bottom liner 52, a phase change material portion 54, and an upper electrode 56. Each patterned portion of the in-process sidewall liner 58' constitutes a sidewall liner 58 according to one embodiment of the present invention. The in-process layer stacks (52', 54', 56') can be patterned into a plurality of layer stacks (52, 54, 56). The in-process sidewall liner 58' may be patterned into a plurality of sidewall liners 58. For each layer stack (52, 54, 56), the lateral distance between the sidewall of the layer stack (52, 54, 56) and the proximal sidewall of the heater element 48 below it may be in the range of 30 nm to 200 nm, for example, 50 nm to 150 nm, but smaller or larger lateral distances may also be used.

[0046] Generally, at least one sidewall liner 58 may be formed by depositing and patterning a sidewall liner material on the sidewalls of each layer stack (52, 54, 56), which are patterned portions of the continuous layer stack (52L, 54L, 56L). The sidewall liner material of at least one sidewall liner 58 includes a material having a conductivity higher than that of the amorphous phase of the phase change material. The sidewall liner material may include a metal nitride material formed by incorporating carbon or nitrogen atoms, resulting in the metal nitride material having a lower conductivity than the stoichiometric metal nitride material. Thus, in embodiments where the amorphous phase portion of the phase change material and the sidewall liner 58 provide two parallel conductive paths, the sidewall liner 58 provides a lower-resistance path, primarily determining the total resistance of the two parallel conductive paths during operation of the phase change memory cell of the present invention. According to this embodiment, the resistive drift effect of the phase change material is suppressed during operation of the phase change memory cell, making it particularly useful for the operation of phase change memory cells in computation in memory (CIM) applications.

[0047] Referring to Figure 12, the second patterned etching mask layer 79 may be removed, for example, by ashing. Each consecutive combination of the bottom electrode 42, heater element 48, bottom liner 52, phase change material portion 54, top electrode 56, and at least one sidewall liner 58 constitutes a phase change memory cell 50. A two-dimensional array of phase change memory cells 50 may be provided.

[0048] Generally, the first patterning process described with reference to Figure 8 and the second patterning process described with reference to Figure 11 can use various combinations of patterns to provide arrays of phase-change memory cells 50 having different configurations. Figures 13A to 13C show sequential top views of the regions of the first configuration of the embodiment structure in the processing steps of Figures 10 to 12. Figures 14A to 14C show sequential top views of the regions of the second configuration of the embodiment structure in the processing steps of Figures 10 to 12. Figures 15A to 15C show sequential top views of the regions of the third configuration of the embodiment structure in the processing steps of Figures 10 to 12. Figure 16 shows a top view of the region of the fourth configuration of the embodiment structure after the processing step of Figure 10. The various configurations shown in Figures 13A to 13C are merely illustrative examples to illustrate specific configurations and do not limit the scope of the present invention.

[0049] Referring to Figure 13A, a region of the first configuration of the embodiment structure, including the in-process layer stacks (52', 54', 56') and the in-process sidewall liner 58', is shown in the processing step of Figure 10. Each in-process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0050] Referring to Figure 13B, a region of the first configuration of the embodiment structure is shown after the second patterned etching mask layer 79 has been formed and before the second anisotropic etching process is performed. The second patterned etching mask layer 79 may include a two-dimensional array (e.g., a 2 × N array) of patterned individual etching mask material portions (e.g., patterned photoresist material portions) covering 2N segments of the first sidewall of the in-process layer stack (52', 54', 56'). In the illustrated example, the integer N is 4. In general, the integer N may be any positive integer. As described above, the in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portions of the second patterned etching mask layer 79 extend laterally along the second horizontal direction hd2 and may be separated laterally from each other along the first horizontal direction hd1.

[0051] Referring to Figure 13C, a second anisotropic etching process may be performed as described with reference to Figure 11. The second anisotropic etching process removes the unmasked portions of the in-process layer stacks (52', 54', 56') that are not covered by the second patterned etching mask layer 79. Each patterned portion of the in-process layer stacks (52', 54', 56') includes a bottom liner 52, a phase change material portion 54, and a top electrode 56, respectively. Generally, the multiple patterned portions of each in-process layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. In the first configuration shown in Figure 13C, at least one patterned column may include two patterned columns of an in-process layer stack (52', 54', 56'), i.e., two layer stacks (52, 54, 56) that constitute a 2×N column layer stack (52, 54, 56). Generally, a P×Q array of in-process layer stacks (52', 54', 56') may be used, and a 2P×QN array of phase-change memory cells 50 may be formed using the first configuration shown in Figures 13A to 13C.

[0052] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase-change memory cell 50. In the first configuration, at least one sidewall liner 58 within each phase-change memory cell 50 may consist of a single sidewall liner 58 formed directly on the sidewall of the layer stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of the continuous layer stack (52L, 54L, 56L).

[0053] Referring to Figure 14A, a region of a second configuration of the embodiment structure in the processing step of Figure 10 is shown, which includes two in-process layer stacks (52', 54', 56') and two in-process sidewall liners 58'. Each in-process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0054] Referring to Figure 14B, a region of the second configuration of the embodiment structure is shown after the second patterned etching mask layer 79 has been formed and before the second anisotropic etching process is performed. The second patterned etching mask layer 79 may include a 1 × N array of patterned individual etching mask material portions (such as patterned photoresist material portions) covering 2N segments of the first sidewall of each in-process layer stack (52', 54', 56'). Each patterned individual etching mask material portion may include a photoresist material strip extending laterally along the second horizontal direction hd2 and having a uniform width along the first horizontal direction hd1. In the illustrated example, the integer N is 4. In general, the integer N may be any positive integer. As described above, each in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portions of the second patterned etching mask layer 79 extend laterally along the second horizontal direction hd2 and may be separated laterally from each other along the first horizontal direction hd1.

[0055] Referring to Figure 14C, a second anisotropic etching process may be performed as described with reference to Figure 11. The second anisotropic etching process removes the unmasked portions of the in-process layer stacks (52', 54', 56') that are not covered by the second patterned etching mask layer 79. Each patterned portion of the in-process layer stacks (52', 54', 56') includes a bottom liner 52, a phase change material portion 54, and a top electrode 56, respectively. Generally, the multiple patterned portions of each in-process layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. In the second configuration shown in Figure 14C, at least one row of patterned portions may include a row of patterned portions of an in-process layer stack (52', 54', 56'), i.e., a row of layer stacks (52, 54, 56) that constitute a 1×N array of layer stacks (52, 54, 56). Generally, a P×Q array of in-process layer stacks (52', 54', 56') may be used, and a P×QN array of phase-change memory cells 50 may be formed using the second configuration shown in Figures 14A to 14C.

[0056] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase-change memory cell 50. In a second configuration, the at least one sidewall liner 58 within each phase-change memory cell 50 may include two sidewall liners 58 formed directly on a pair of sidewalls of the layer stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of the continuous layer stack (52L, 54L, 56L). The pair of sidewalls may be parallel to each other, and the two sidewall liners 58 are separated laterally from each other along a horizontal direction such as a second horizontal direction hd2.

[0057] Referring to Figure 15A, a region of a third configuration of the embodiment structure, including the in-process layer stacks (52', 54', 56') and the in-process sidewall liner 58', is shown in the processing step of Figure 10. Each in-process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0058] Referring to Figure 15B, a region of the third configuration of the embodiment structure is shown after the second patterned etching mask layer 79 has been formed and before the second anisotropic etching process is performed. The second patterned etching mask layer 79 may include a pair of patterned individual etching mask material portions (such as patterned photoresist material portions) that cover all of the second sidewalls of the in-process layer stacks (52', 54', 56') and each first sidewall segment adjacent to each second sidewall of the in-process layer stacks (52', 54', 56'). Each first sidewall of the in-process layer stacks (52', 54', 56') includes a central segment not covered by the second patterned etching mask layer 79. As described above, each in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The two masking material portions of the second patterned etching mask layer 79 extend laterally along the second horizontal hd2 and may be separated laterally from each other along the first horizontal hd1 so that the central segments of each first sidewall of the in-process layer stack (52', 54', 56') are not covered by the second patterned etching mask layer 79.

[0059] Referring to Figure 15C, a second anisotropic etching process may be performed as described with reference to Figure 11. The second anisotropic etching process removes the unmasked portions of the in-process layer stacks (52', 54', 56') that are not covered by the second patterned etching mask layer 79. Each patterned portion of the in-process layer stacks (52', 54', 56') includes a bottom liner 52, a phase change material portion 54, and a top electrode 56, respectively. Generally, the multiple patterned portions of each in-process layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. In the third configuration shown in Figure 15C, at least one patterned column may include a column containing two patterned columns of in-process layer stacks (52', 54', 56'), i.e., a column of layer stacks (52, 54, 56) that constitute a 1×2 array of layer stacks (52, 54, 56). Generally, a P×Q array of in-process layer stacks (52', 54', 56') may be used, and a P×2Q array of phase-change memory cells 50 may be formed using the third configuration shown in Figures 15A to 15C.

[0060] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase-change memory cell 50. In a third configuration, at least one sidewall liner 58 within each phase-change memory cell 50 may consist of a single sidewall liner 58 directly formed on the three sidewalls of the layer stack (52, 54, 56) of the phase-change memory cell 50, which is a patterned portion of the continuous layer stack (52L, 54L, 56L).

[0061] Referring to Figure 16, a fourth configuration of the embodiment structure after the processing step of Figure 10 is shown. In the fourth configuration, the masking pattern of the first patterned etching mask layer 77 used in the processing step of Figure 8 is modified to be the same as the target pattern of the array of layer stacks (52, 54, 56) of the array of phase change memory cells 50. In this embodiment, the first anisotropic etching process described with reference to Figure 8 directly patterns the continuous layer stacks (52L, 54L, 56L) onto the array of layer stacks (52, 54, 56). Furthermore, when performing the processing steps described with reference to Figures 9 and 10, the sidewall liner layer 58L may be directly patterned onto the sidewall liner 58. Therefore, the processing steps described with reference to Figures 11 and 12 may be omitted when the fourth configuration of the embodiment structure is used.

[0062] Generally speaking, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase-change memory cell 50. In a fourth configuration, at least one sidewall liner 58 within each phase-change memory cell 50 may have an annular configuration. In other words, at least one sidewall liner 58 within each phase-change memory cell 50 may consist of a single sidewall liner 58 that is phase-in-phase with the torus, i.e., it may be continuously deformed without forming new holes or removing existing holes within the torus. The single sidewall liner 58 may be formed directly on each sidewall of each layer stack (52, 54, 56), which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0063] Referring to Figure 17, a sealing dielectric material layer 643 and additional metal interconnect structures (62, 6422, 648) may be formed on the phase change memory cell 50. The sealing dielectric material layer 643 includes at least one interlayer dielectric material such as silicon oxide, silicon nitride, and / or silicon carbidine nitride. The additional metal interconnect structures (62, 6422, 648) may include an upper contact via structure 62 that contacts the upper surfaces of each of the upper electrodes 56, an upper peripheral via structure 6422 formed on the lower peripheral via structure 6421, and a fourth metal wiring structure 648 formed on the upper contact via structure 62 and the upper peripheral via structure 6422. The upper surface of the fourth metal wiring structure 648 may be coplanar with the horizontal upper surface of the sealing dielectric material layer 643. The sealing dielectric material layer 643 constitutes an upper fourth interconnect level dielectric material layer. The combination of the lower fourth interconnection-level dielectric material layer 641 and the sealing dielectric material layer 643 constitutes the fourth interconnection-level dielectric material layer 640. Additional dielectric material layers (not shown) and additional metal interconnect structures may be formed as needed to provide electrical connections between the upper electrodes 56 of the phase-change memory cell 50 and the various semiconductor devices 700 located beneath the dielectric material layers (601, 610, 620, 630, 640).

[0064] Generally, the programming transistor 701 may be provided on the substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638, 42, 6421) embedded in interconnect-level dielectric material layers (601, 610, 620, 630, 641) may be formed on the programming transistor 701. The bottom electrode 42 and heater elements 48 may be formed in dielectric material layers such as the lower fourth interconnect-level dielectric material layer 641. Each heater element 48 is electrically connected to an electrical node such as the output node of each programming transistor 701. A continuous layer stack (52L, 54L, 56L) including a bottom liner layer 52L, a phase change material layer 54L containing a phase change material, and an upper electrode material layer 56L is deposited and patterned to form a layer stack (52, 54, 56) of the bottom liner 52, the phase change material portion 54, and the upper electrode 56. A sidewall liner layer 58L may be formed and patterned to form a sidewall liner 58. At least one sidewall liner 58 may be formed on at least one sidewall of each layer stack (52, 54, 56).

[0065] Each sidewall liner 58 contains a material having a conductivity higher than that of the amorphous phase of the phase change material in the phase change material portion 54. For each phase change memory cell 50, the sealing dielectric material layer 643 may be deposited directly on at least one sidewall of the layer stack (52, 54, 56) (the patterned portion of the continuous layer stack (52L, 54L, 56L)), directly on each outer sidewall of at least one sidewall liner 58, and directly on the top surface of the layer stack (52, 54, 56). Thus, for each phase change memory cell 50, the sealing dielectric material layer 643 is in contact with at least one sidewall of the layer stack, each outer sidewall of at least one sidewall liner 58, and the top surface of the layer stack (52, 54, 56).

[0066] For each phase-change memory cell 50 electrically connected to the programming transistor 701, the programming transistor 701 is configured to program the phase-change memory cell 50 to at least three different resistance states by applying at least three different programming pulse patterns to the heater element. Figures 18A to 18D show various configurations of the phase-change material portion 54 in various programmed resistance states according to one embodiment of the present invention.

[0067] Referring to Figure 18A, the phase-change memory cell 50 in a low-resistance state is shown. In this embodiment, at least 99% of the total volume of the phase-change material portion 54 is a polycrystalline phase. In one embodiment, the entire phase-change material portion 54 may be a crystalline phase-change material portion 54C containing a polycrystalline phase-change material. The conductivity of the crystalline phase-change material is higher than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends vertically between the heater element 48 and the upper electrode 56.

[0068] Referring to Figure 18B, the phase-change memory cell 50 in a first intermediate state is shown. In this embodiment, the phase-change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes the amorphous phase-change material portion 54A, and the second volume includes the crystalline phase-change material portion 54C. The first volume does not directly contact at least one sidewall liner 58. The conductivity of the amorphous phase-change material is lower than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally within the bottom liner 52 beneath the amorphous phase-change material portion 54A, and extends between the peripheral portion of the bottom liner 52 and the upper electrode 56, penetrating the crystalline phase-change material portion 54C at an angle with respect to the vertical.

[0069] Referring to Figure 18C, a phase-change memory cell 50 in a second intermediate state that provides a higher resistance than the first intermediate state is shown. In this embodiment, the phase-change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes the amorphous phase-change material portion 54A, and the second volume includes the crystalline phase-change material portion 54C. The first volume is in direct contact with at least one sidewall liner 58 but not with the upper electrode 56. The conductivity of the amorphous phase-change material is lower than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally beneath the amorphous phase-change material portion 54A within the bottom liner 52, extends vertically through the lower part of each sidewall liner 58, and extends between the central portion of each sidewall liner 58 and the upper electrode 56, through the crystalline phase-change material portion 54C at an angle to the vertical.

[0070] Referring to Figure 18D, a phase-change memory cell 50 in a high-resistance state is shown. In this embodiment, at least 99% of the total volume of the phase-change material portion 54 is in the amorphous phase.

[0071] Figures 18A to 18D show four resistance states of the phase-change memory cell 50, but the pulse pattern of the programming pulse from the programming transistor 701 may be pre-programmed to be selected from a plurality of programming pulse patterns stored in the programming circuit for the phase-change memory cell 50. The total number of pre-programmed pulse patterns may be in the range of 2 to 210, for example, 3 to 28 and / or 4 to 26. The total number of resistance states that may be programmed for each phase-change memory cell 50 may be the same as the total number of pre-programmed pulse patterns. In one embodiment, each programming transistor 701 may be configured to apply at least four different programming pulse patterns to each heater element 48. The programming pulses may each have different durations and / or voltage ramp-down rates to control the cooling rate of the molten region of the phase-change material portion 54. The duration of the programming pulses may be in the range of 10 nanoseconds to 500 nanoseconds, and longer programming pulses generally correspond to the formation of larger crystallized regions of the phase-change material portion 54.

[0072] Referring to Figure 19, a first alternative configuration of the embodiment structure after the formation of the heater element 48 is shown. In the first alternative configuration, the processing steps described with reference to Figure 5 can be omitted. In this embodiment, each heater element 48 may have the same lateral dimensions as the bottom electrode 42 below it. The side walls of each heater element 48 may coincide perpendicularly with the side walls of the bottom electrode 42 below it, that is, they may be located in the same vertical plane as the side walls of the bottom electrode 42 below them.

[0073] Referring to Figure 20, the processing steps described with reference to Figures 7-17 can be performed on the first alternative configuration of the embodiment structure to provide an array of phase-change memory cells 50.

[0074] Referring to Figure 21, a second alternative configuration of the embodiment structure is shown, derived from the embodiment structure shown in Figure 6 by removing a portion of the metal filler overlapping the dielectric material layer embedding the bottom electrode 42 using a chemical mechanical polishing process. In this embodiment, the entire upper surface of the dielectric material layer embedding the bottom electrode 42 may be formed in the horizontal plane. In other words, the upper surface of the dielectric material layer may be formed without steps. The upper surface of the heater element 48 may be formed in the same horizontal plane as the upper surface of the dielectric material layer embedding the heater element 48.

[0075] Referring to Figure 22, the processing steps described with reference to Figures 7-17 can be performed on a second alternative configuration of the embodiment structure to provide an array of phase-change memory cells 50.

[0076] Referring comprehensively to Figures 1 to 22, various embodiments of the present invention provide a device structure comprising: a bottom electrode 42 and a heater element 48 embedded in a dielectric material layer; a layer stack (52, 54, 56) including a bottom liner 52, a phase change material portion 54 including a phase change material, and an upper electrode 56; and at least one sidewall liner 58 disposed on at least one sidewall of the layer stack, comprising a material having a conductivity higher than that of the amorphous phase of the phase change material.

[0077] In one embodiment, the conductivity of the amorphous phase of the phase change material is 1.0 x 10⁻¹⁰ -8 S / cm~1.0x10 -3 The range is S / cm, and the conductivity of the sidewall liner 58 material is 1.0 x 10 1 S / cm~1.0x10 5 The range is S / cm. In one embodiment, the bottom liner layer 52L includes a material having a conductivity at least three times that of the sidewall liner material. In one embodiment, the device structure includes at least one sidewall of the layer stack, the outer sidewall of each at least one sidewall liner 58, and a sealing dielectric material layer 643 that contacts the top surface of the layer stack (52, 54, 56).

[0078] According to another aspect of the present invention, a device structure is provided comprising: a programming transistor 701 disposed on a substrate 8; a bottom electrode 42 and a heater element 48 embedded in a dielectric material layer, the heater element 48 being electrically connected to an electrical node of the programming transistor 701; and a phase change memory cell 50 comprising a layer stack including a bottom liner 52, a phase change material portion 54 including a phase change material, and an upper electrode 56, and further comprising at least one sidewall liner 58 disposed on at least one sidewall of the layer stack, wherein the programming transistor 701 is configured to program the phase change memory cell 50 to at least three different resistive states by applying at least three different programming pulse patterns to the heater element 48.

[0079] In one embodiment, the at least three different resistance states include: a high-resistance state in which at least 99% of the total volume of the phase-change material portion 54 is in an amorphous phase; a low-resistance state in which at least 99% of the total volume of the phase-change material portion 54 is in a polycrystalline phase; and a first intermediate state in which the phase-change material portion 54 comprises a first volume having an amorphous phase and a second volume having a crystalline phase, the first volume not in direct contact with at least one sidewall liner 58, and having a higher resistance than the low-resistance state. In one embodiment, the at least three different resistance states further include a second intermediate state in which an amorphous volume having an amorphous phase is in contact with the bottom liner 52 and at least one sidewall liner 58 but not with the upper electrode 56; and the programming transistor 701 is configured to apply at least four different programming pulse patterns to the heater element 48.

[0080] In one embodiment, the bottom liner 52 comprises a first metal nitride material; and at least one sidewall liner 58 comprises a second metal nitride material having an conductivity less than one-third of that of the first metal nitride material.

[0081] Referring to Figure 23, the flowchart shows the general processing steps for manufacturing a device structure.

[0082] Referring to step 2310 and Figures 1-6, the bottom electrode 42 and heater element 48 may be formed within the dielectric material layer (which may also be, but is not limited to, the lower fourth interconnection level dielectric material layer 641).

[0083] Referring to step 2320 and Figures 7-16, a continuous layer stack (52L, 54L, 56L) including a bottom liner layer 52L, a phase change material layer 54L containing a phase change material, and an upper electrode material layer 56L may be deposited and patterned.

[0084] Referring to step 2330 and Figures 9-16, at least one sidewall liner 58 may be formed by depositing and patterning sidewall liner 58 material. At least one sidewall liner 58 is formed on at least one sidewall of the patterned portion of the continuous layer stack (52L, 54L, 56L). At least one sidewall liner 58 comprises a material having a conductivity higher than that of the amorphous phase of the phase change material.

[0085] Within each phase-change memory cell, the bottom liner 52 and sidewall liners 58 are used to set the resistance level of the high-resistance state of the phase-change memory cell. The combination of the bottom liner 52 and sidewall liners 58 suppresses the effects of resistance drift in the phase-change material portion 54, reduces the power consumption of the phase-change memory cell, lowers the error rate during operation of the phase-change memory cell, and allows for a reduction in the cell size of the phase-change memory cell. Generally, the thickness of the bottom liner 52 and the thickness of the sidewall liners 58 can be optimized to broadly vary the resistance of the various resistance states of the phase-change memory cell, facilitating efficient multilevel cell (MLC) operation, i.e., cell operation in which the cell is programmed to three or more resistance states. Thus, a large programming window can be provided for using the phase-change memory cell 50 for MLC operation.

[0086] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Each embodiment described using the term “including” essentially discloses that, unless expressly otherwise disclosed herein, the term “including” may be replaced with the terms “essentially consisting of” or “consisting of” in some embodiments. Whenever two or more elements are listed as options in the same or different paragraphs, a Markush group containing the enumeration of two or more elements may also be implicitly disclosed. Whenever the auxiliary verb “can, may” is used in the present invention to describe the formation of an element or the performance of a processing step, embodiments in which such an element or processing step is not performed are also explicitly envisioned, insofar as the resulting apparatus or device yields an equivalent result. Thus, the auxiliary verb “can, may” applied to the formation of an element or the performance of a processing step should be interpreted as “may” or “may, or may” if the omission of such an element or processing step may result in the same or equivalent result (including slightly better and slightly worse results). Those skilled in the art will understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as those described herein. Those skilled in the art will also understand that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention. [Industrial applicability]

[0087] This invention provides a novel method for forming a device structure and a novel device structure. [Explanation of Symbols]

[0088] 8: Circuit board 9: Semiconductor material layer 41: Beer Cavity 42:Bottom electrode 42': In-process bottom electrode 47: Heater Cavity 48: Heater element 50: Phase-change memory cell 52: Bottom liner 52L: Bottom liner layer 52': In-process bottom liner 54: Phase change material portion 54A: Amorphous phase change material portion 54C: Crystal phase change material portion 54L: Phase change material layer 54': In-process phase change material portion 56:Top electrode 56L: Upper electrode material layer 56': In-process upper electrode 57: Masking layer 58: Sidewall liner 58L: Sidewall liner layer 58': In-process sidewall liner 62: Upper contact via structure 77: First patterned etching mask layer 79: Second patterned etching mask layer 100: Memory array area 300: Peripheral area 601: First dielectric material layer 610: First interconnection level dielectric material layer 612: Device Contact Via Structure 618: First Metal Wiring Structure 620: Second interconnection level dielectric material layer 622: First Metal Via Structure 628: Second Metal Wiring Structure 630: Third interconnection level dielectric material layer 632: Second Metal Via Structure 638: Third Metal Wiring Structure 640: Fourth interconnection level dielectric material layer 641: Lower fourth interconnection level dielectric material layer 643: Sealing dielectric material layer 648: Fourth Metal Wiring Structure 700: Semiconductor devices 701: Programmable Transistor 702: Peripheral Transistors 720: Shallow trench isolation structure 6411: Surrounding beer cavity 6421: Lower peripheral via structure 6422: Upper peripheral via structure hd1: First horizontal direction hd2: Second horizontal direction 2310, 2320, 2330: Step

Claims

1. Forming a bottom electrode and heater element within a dielectric material layer, Depositing and patterning a continuous layer stack including a bottom liner layer, a phase change material layer containing a phase change material, and an upper electrode material layer, Forming at least one sidewall liner by depositing and patterning a sidewall liner material, wherein the at least one sidewall liner is formed on at least one sidewall of the patterned portion of the continuous layer stack, and the at least one sidewall liner comprises a material having a conductivity higher than that of the amorphous phase of the phase change material. A method for forming a device structure, including [a specific component].

2. The at least one sidewall liner is Conformally depositing a metal nitride material layer, By incorporating carbon atoms or nitrogen atoms into the metal nitride material layer, the conductivity of the metal nitride material layer is reduced, The process involves incorporating the carbon atoms or nitrogen atoms into the metal nitride material layer and then patterning the metal nitride material layer. The method according to claim 1, formed by...

3. The carbon atoms or nitrogen atoms are incorporated into the metal nitride material layer at an atomic concentration such that the conductivity of the metal nitride material layer after the incorporation of the carbon atoms or nitrogen atoms is less than one-third of the conductivity of the metal nitride material layer before the incorporation of the carbon atoms or nitrogen atoms. The method according to claim 2.

4. The method according to claim 1, The combination of the patterned portion of the continuous layer stack and the at least one sidewall liner includes a phase-change memory cell. The method further includes forming a programming transistor on a substrate and forming a metal interconnect structure embedded in an interconnect-level dielectric material layer on the programming transistor. The heater element is electrically connected to the electrical node of the programming transistor. The programming transistor is configured to program the phase-change memory cell into at least three different resistance states. The method according to claim 1.

5. The first patterning process is performed to pattern the continuous layer stack, wherein the remaining portion of the continuous layer stack includes an in-process layer stack comprising an in-process bottom liner, an in-process phase change material portion, and an in-process upper electrode. The execution of a second patterning process, which patterns the in-process layer stack into a plurality of patterned parts, wherein the patterned part of the continuous layer stack includes one of the plurality of patterned parts. The method according to claim 1, further comprising:

6. The in-process layer stack includes a first side wall extending laterally along a first horizontal direction and a second side wall extending laterally along a second horizontal direction. The second patterning process removes unmasked portions of the in-process layer stack using masking material portions that extend laterally along the second horizontal direction and are laterally separated from each other along the first horizontal direction. The plurality of patterned portions include at least one row of patterned portions arranged along the first horizontal direction, The method according to claim 5.

7. The second patterning process further includes conformally depositing a layer of the sidewall liner material and anisotropically etching it to form an in-process sidewall liner around the in-process layer stack, wherein the second patterning process patterns the in-process sidewall liner into a plurality of portions including at least one sidewall liner. The method according to claim 5.

8. The at least one sidewall liner consists of a single sidewall liner formed directly on the sidewall of the patterned portion of the continuous layer stack. The method according to claim 7.

9. The at least one sidewall liner includes two sidewall liners formed on a pair of parallel sidewalls of the patterned portion of the continuous layer stack. The method according to claim 7.

10. The at least one sidewall liner consists of a single sidewall liner formed directly on the three sidewalls of the patterned portion of the continuous layer stack. The method according to claim 7.

11. The at least one sidewall liner has an annular configuration and is formed directly on each sidewall of the patterned portion of the continuous layer stack. The method according to claim 7.

12. The further includes depositing a sealing dielectric material layer directly on at least one sidewall of the patterned portion of the continuous layer stack, directly on the outer sidewall of each of the at least one sidewall liners, and directly on the upper surface of the patterned portion of the continuous layer stack. The method according to claim 1.

13. A bottom electrode and heater element formed within a dielectric material layer, A layer stack comprising a bottom liner layer, a phase change material portion including a phase change material, and an upper electrode, At least one sidewall liner is disposed on at least one sidewall of the layer stack and comprises a material having a conductivity higher than that of the amorphous phase of the phase change material, A device structure that includes this.

14. The conductivity of the amorphous phase of the phase change material is 1.0 x 10 －８ S / cm~1.0x10 －３ It is in the range of S / cm, The conductivity of the at least one sidewall liner material is 1.0 x 10 １ S / cm~1.0x10 ５ The range is S / cm. The device structure according to claim 13.

15. The bottom liner layer includes a material having an conductivity at least three times that of the conductivity of the at least one sidewall liner material. The device structure according to claim 13.

16. The layer further includes at least one side wall of the layer stack, the outer side wall of each of the at least one side wall liners, and a sealing dielectric material layer in contact with the upper surface of the layer stack. The device structure according to claim 13.

17. Programming transistors arranged on the circuit board, A bottom electrode and a heater element formed within a dielectric material layer, wherein the heater element is electrically connected to the programming transistor electrical node, and the bottom electrode and the heater element, A phase change memory cell comprising a layer stack including a bottom liner, a phase change material portion including a phase change material, and an upper electrode, further comprising at least one sidewall liner disposed on at least one sidewall of the layer stack, Includes, The programming transistor is configured to program the phase-change memory cell to at least three different resistance states by applying at least three different programming pulse patterns to the heater element. Device structure.

18. The aforementioned at least three different resistance states are, The high-resistance state in which at least 99% of the total volume of the phase-change material portion is in the amorphous phase, The low-resistance state in which at least 99% of the total volume of the phase-change material portion is a polycrystalline phase, A first intermediate state having a resistance higher than the low-resistance state, wherein the phase-change material portion includes a first volume having the amorphous phase and a second volume having the crystalline phase, and the first volume does not directly contact the at least one sidewall liner, The device structure according to claim 17, including the device structure according to claim 17.

19. The at least three different resistance states further include a second intermediate state having the amorphous phase and including an amorphous volume that is in contact with the bottom liner and the at least one sidewall liner but not with the upper electrode, The programming transistor is configured to apply at least four different programming pulse patterns to the heater element. The device structure according to claim 18.

20. The bottom liner comprises a first metal nitride material, The at least one sidewall liner comprises a second metal nitride material having an electrical conductivity less than one-third of the electrical conductivity of the first metal nitride material. The device structure according to claim 17.

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