Semiconductor equipment

Abstract

To provide a semiconductor device that can improve output. [Solution] The semiconductor device comprises a substrate, a first barrier layer provided on the substrate, a second barrier layer provided on the first barrier layer, and a channel layer provided on the second barrier layer, wherein the first barrier layer has a superlattice structure having a first nitride semiconductor layer containing Al and a second nitride semiconductor layer containing Ga, the second barrier layer has a third nitride semiconductor layer containing Al and Ga, the channel layer has a fourth nitride semiconductor layer containing Ga, and the surface of the second barrier layer facing the channel layer has nitrogen polarity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] As semiconductor devices using nitride semiconductors, numerous reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). As a HEMT using a nitride semiconductor, a HEMT in which a channel layer is provided on a barrier layer with a nitrogen polarity on the upper surface is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is an increasing demand for improving the output of semiconductor devices using nitride semiconductors.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving the output.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, a semiconductor device is provided comprising a substrate, a first barrier layer provided on the substrate, a second barrier layer provided on the first barrier layer, and a channel layer provided on the second barrier layer, wherein the first barrier layer has a superlattice structure having a first nitride semiconductor layer containing Al and a second nitride semiconductor layer containing Ga, the second barrier layer has a third nitride semiconductor layer containing Al and Ga, the channel layer has a fourth nitride semiconductor layer containing Ga, and the surface of the second barrier layer facing the channel layer has nitrogen polarity. [Effects of the Invention]

[0007] According to this disclosure, the output can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view showing the first barrier layer. [Figure 3] This is a cross-sectional view showing a semiconductor device related to a reference example. [Figure 4] This figure shows the lower end of the conduction band of a semiconductor device. [Figure 5] This is a diagram showing the concentration of electrons. [Figure 6] This is a cross-sectional view showing the sample used to measure the sheet resistance. [Figure 7] This figure shows the measurement results of the sheet resistance. [Figure 8] This figure shows the surface irregularities of the sample. [Figure 9] This figure shows a discrete package according to the second embodiment. [Figure 10] This is a wiring diagram showing a PFC circuit according to the third embodiment. [Figure 11] This is a wiring diagram showing the power supply unit according to the fourth embodiment. [Figure 12] This is a wiring diagram showing the amplifier according to the fifth embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted.

[0010] (First Embodiment) The first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0011] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment has a substrate 11 and a nitride semiconductor layer structure 10 provided above the substrate 11. The nitride semiconductor layer structure 10 has a buffer layer 12, a first barrier layer 13, a second barrier layer 14, a channel layer 15, and a cap layer 16. The buffer layer 12 is provided on the substrate 11. The first barrier layer 13 is provided on the buffer layer 12. The second barrier layer 14 is provided on the first barrier layer 13. The channel layer 15 is provided on the second barrier layer 14. The cap layer 16 is provided on the channel layer 15.

[0012] The substrate 11 is, for example, a SiC substrate, a GaN substrate, or a sapphire substrate. When the substrate 11 is a SiC substrate, the upper surface of the substrate 11 has a carbon (C) polarity. When the substrate 11 is a GaN substrate, the upper surface of the substrate 11 has a nitrogen (N) polarity. When the substrate 11 is a sapphire substrate, the upper surface of the substrate 11 has an off angle. The magnitude of the off angle is, for example, about 4°. The buffer layer 12 has an AlN layer, a GaN layer, an AlGaN layer, or any combination thereof. The Al composition in the AlGaN layer may be constant or may vary. For example, when the buffer layer 12 has a GaN layer and an AlGaN layer thereon, the Al composition in the AlGaN layer may increase as it moves away from the GaN layer. The thickness of the buffer layer 12 is, for example, about 1 μm.

[0013] FIG. 2 is a cross-sectional view showing the first barrier layer 13. The first barrier layer 13 includes a superlattice structure having a first nitride semiconductor layer 131 containing Al and a second nitride semiconductor layer 132 containing Ga. That is, as shown in FIG. 2, the first barrier layer 13 has one or more sets of the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132. When the first barrier layer 13 has two or more sets of the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132, the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132 are alternately arranged. The first nitride semiconductor layer 131 is, for example, an AlN layer having a thickness of 1 nm or more and 10 nm or less. The second nitride semiconductor layer 132 is, for example, a GaN layer having a thickness of 1 nm or more and 30 nm or less. The thickness of the second nitride semiconductor layer 132 may be equal to the thickness of the first nitride semiconductor layer 131, may be larger than the thickness of the first nitride semiconductor layer 131, or may be smaller than the thickness of the first nitride semiconductor layer 131.

[0014] The second barrier layer 14 has a third nitride semiconductor layer containing Al and Ga. The third nitride semiconductor layer is, for example, an Al x Ga 1-x N layer having a thickness of 5 nm or more and 40 nm or less. The value of x is, for example, 0.10 or more and 0.50 or less. The channel layer 15 has a fourth nitride semiconductor layer containing Ga. The fourth nitride semiconductor layer is, for example, a GaN layer having a thickness of 10 nm or more and 30 nm or less. The cap layer 16 has an AlN layer, a GaN layer, an AlGaN layer, or any combination thereof. The thickness of the cap layer 16 is, for example, 1 nm or more and 5 nm or less. A two-dimensional electron gas (2DEG) 19 exists in the vicinity of the lower surface of the channel layer 15.

[0015] The semiconductor device 1 has a source electrode 181, a drain electrode 182, and a gate electrode 183. The source electrode 181, the drain electrode 182, and the gate electrode 183 are provided on a nitride semiconductor multilayer structure 10. The gate electrode 183 is provided between the source electrode 181 and the drain electrode 182. The source electrode 181 and the drain electrode 182 are in contact with the nitride semiconductor multilayer structure 10. The gate electrode 183 may also be in contact with the nitride semiconductor multilayer structure 10, and there may be a gate insulating film between the gate electrode 183 and the nitride semiconductor multilayer structure 10.

[0016] Next, the band structure and electron concentration in semiconductor device 1 will be explained in comparison with a reference example. Here, the number of pairs of first nitride semiconductor layers 131 and second nitride semiconductor layers 132 is 3, the first nitride semiconductor layer 131 is an AlN layer with a thickness of 5 nm, the second nitride semiconductor layer 132 is a GaN layer with a thickness of 20 nm, and the buffer layer 12 is a GaN layer. Also, as shown in Figure 3, in the semiconductor device 1X according to the reference example, the first barrier layer 13 is not provided, and the buffer layer 12 is in contact with the second barrier layer 14. Figure 3 is a cross-sectional view showing the semiconductor device according to the reference example. Figure 4 is a diagram showing the lower end of the conduction band of the semiconductor device. Figure 5 is a diagram showing the electron concentration. In Figure 4, the horizontal axis shows the depth relative to the top surface of the channel layer 15, and the vertical axis shows the energy at the lower end of the conduction band. Fermi level E F The energy is 0 eV. In Figure 5, the horizontal axis represents the depth relative to the top surface of the channel layer 15, and the vertical axis represents the electron concentration.

[0017] As shown in Figure 4, in semiconductor device 1, the energy change of the channel layer 15 is steeper and the energy near the lower surface of the channel layer 15 is lower compared to semiconductor device 1X. Therefore, as shown in Figure 5, in semiconductor device 1, the confinement effect of 2DEG19 is higher and the maximum electron concentration is higher compared to semiconductor device 1X. For this reason, semiconductor device 1 can improve output power. It can also suppress short-channel effects.

[0018] The greater the number of pairs of the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132, the higher the concentration of 2DEG19. On the other hand, if the number of pairs of the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132 is six or more, the electric field changes, and the electron mobility in 2DEG19 may decrease. For this reason, it is preferable that the number of pairs of the first nitride semiconductor layer 131 and the second nitride semiconductor layer 132 be five or less.

[0019] The nitride semiconductor multilayer structure 10 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). The source electrode 181, drain electrode 182, and gate electrode 183 can be formed, for example, by vapor deposition and lift-off.

[0020] Next, the measurement results of the sheet resistance of a nitride semiconductor multilayer structure sample formed by the present inventor will be described. Figure 6 is a cross-sectional view showing the sample used for measuring the sheet resistance. Figure 7 is a diagram showing the measurement results of the sheet resistance. The numerical values ​​in Figure 7 represent the sheet resistance (Ω / sq.).

[0021] The sample 2 used for measuring the sheet resistance comprises a substrate 21 and a nitride semiconductor multilayer structure 20 provided above the substrate 21. The nitride semiconductor multilayer structure 20 includes a buffer layer 22, a first barrier layer 23, a second barrier layer 24, a channel layer 25, and a cap layer 26. The buffer layer 22 is provided on the substrate 21. The first barrier layer 23 is provided on the buffer layer 22. The second barrier layer 24 is provided on the first barrier layer 23. The channel layer 25 is provided on the second barrier layer 24. The cap layer 26 is provided on the channel layer 25.

[0022] The substrate 21 is a sapphire substrate with a 4° off-angle and a diameter of 7.62 cm (3 inches). The buffer layer 22 has an AlN layer with a thickness of 100 nm and a GaN layer with a thickness of 1 μm. The AlN layer is on the substrate 21, and the GaN layer is on top of the AlN layer. The first barrier layer 23 has alternatingly arranged AlN layers with a thickness of 10 nm and GaN layers with a thickness of 5 nm. The first barrier layer 23 has four sets of AlN and GaN layers. The second barrier layer 24 is an AlGaN layer with a thickness of 30 nm. The channel layer 25 is a GaN layer with a thickness of 20 nm. The cap layer 26 has an AlGaN layer with a thickness of 3 nm and a GaN layer with a thickness of 2 nm. The AlGaN layer is on top of the channel layer 25, and the GaN layer is on top of the AlGaN layer. 2DEG29 is located near the bottom surface of the channel layer 25.

[0023] As shown in Figure 7, the maximum sheet resistance was approximately 170 Ω / sq., and the average sheet resistance was 131.0 Ω / sq. Compared to the sheet resistance (approximately 300.0 Ω / sq.) when the first barrier layer 23 is not present, as in the reference example, a significantly lower sheet resistance was obtained.

[0024] Furthermore, good flatness was obtained on the surface of the cap layer 26 in sample 2. Figure 8 shows the surface irregularities of the sample. In Figure 8, the horizontal axis indicates the position in a plane parallel to the surface of the cap layer 26, and the vertical axis indicates the displacement from a reference plane parallel to the surface of the cap layer 26. As shown in Figure 8, the absolute value of the displacement is small, indicating good flatness.

[0025] (Second Embodiment) Next, a second embodiment will be described. The second embodiment relates to a discrete package of HEMT. Figure 9 is a diagram showing a discrete package according to the second embodiment.

[0026] In the second embodiment, as shown in Figure 9, the back surface of the semiconductor device 1210, which has the same structure as in the first embodiment, is fixed to the land (die pad) 1233 using a die attach agent 1234 such as solder. A wire 1235d, such as an Al wire, is connected to a drain pad 1226d to which a drain electrode 182 is connected, and the other end of the wire 1235d is connected to a drain lead 1232d which is integrated with the land 1233. A wire 1235s, such as an Al wire, is connected to a source pad 1226s connected to a source electrode 181, and the other end of the wire 1235s is connected to a source lead 1232s which is independent of the land 1233. A wire 1235g, such as an Al wire, is connected to a gate pad 1226g connected to a gate electrode 183, and the other end of the wire 1235g is connected to a gate lead 1232g which is independent of the land 1233. Then, the land 1233 and semiconductor device 1210, etc., are packaged with mold resin 1231, with a portion of the gate lead 1232g, a portion of the drain lead 1232d, and a portion of the source lead 1232s protruding.

[0027] Such discrete packages can be manufactured, for example, as follows: First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame by bonding using wires 1235g, 1235d, and 1235s. After that, sealing is performed using a molding resin 1231 by the transfer molding method. Subsequently, the lead frame is detached.

[0028] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Figure 10 is a wiring diagram showing the PFC circuit according to the third embodiment.

[0029] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. DC power is connected between both terminals of the capacitor 1255. In this embodiment, the switch element 1251 is a semiconductor device having the same structure as in the first embodiment.

[0030] In manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252 and the choke coil 1253 using solder or the like.

[0031] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device equipped with a HEMT, which is suitable for server power supplies. Figure 11 is a wiring diagram showing the power supply device according to the fourth embodiment.

[0032] The power supply unit is equipped with a high-voltage primary circuit 1261, a low-voltage secondary circuit 1262, and a transformer 1263 located between the primary circuit 1261 and the secondary circuit 1262.

[0033] The primary circuit 1261 is provided with a PFC circuit 1250 according to the third embodiment, and an inverter circuit, such as a full-bridge inverter circuit 1260, connected between the terminals of the capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality (in this case, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

[0034] The secondary circuit 1262 is provided with multiple (in this case, three) switching elements 1265a, 1265b, and 1265c.

[0035] In this embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary circuit 1261, and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260, are semiconductor devices having the same structure as in the first embodiment. On the other hand, the switch elements 1265a, 1265b, and 1265c of the secondary circuit 1262 are ordinary MIS-type FETs (field-effect transistors) made of silicon.

[0036] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to an amplifier equipped with a HEMT. Figure 12 is a wiring diagram showing the amplifier according to the fourth embodiment.

[0037] The amplifier includes a digital pre-distortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0038] The digital pre-distortion circuit 1271 compensates for the nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, which has been compensated for the nonlinear distortion, with the AC signal. The power amplifier 1273 has a semiconductor device with the same structure as in the first embodiment and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal in the mixer 1272b and sent to the digital pre-distortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used, for example, in transceivers for mobile phone base stations, radar equipment, and microwave generators.

[0039] A silicon substrate, AlN substrate, or diamond substrate may be used as the substrate. The substrate may be conductive, semi-insulating, or insulating.

[0040] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0041] The various aspects of this disclosure are summarized below as an appendix.

[0042] (Note 1) circuit board and A first barrier layer provided on the substrate, A second barrier layer is provided on the first barrier layer, A channel layer provided on the second barrier layer, It has, The first barrier layer comprises a superlattice structure having a first nitride semiconductor layer containing Al and a second nitride semiconductor layer containing Ga. The second barrier layer has a third nitride semiconductor layer containing Al and Ga, The channel layer has a fourth nitride semiconductor layer containing Ga, The semiconductor device has a nitrogen polarity on the surface of the second barrier layer facing the channel layer. (Note 2) The first nitride semiconductor layer is an AlN layer, The semiconductor device described in Appendix 1, wherein the second nitride semiconductor layer is a GaN layer. (Note 3) The third nitride semiconductor layer is an AlGaN layer. The semiconductor device according to Appendix 1 or 2, wherein the fourth nitride semiconductor layer is a GaN layer. (Note 4) A semiconductor device according to any one of the appendices 1 to 3, having a source electrode, a gate electrode, and a drain electrode provided on the channel layer. (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the substrate is a SiC substrate, a GaN substrate, or a sapphire substrate. (Note 6) A semiconductor device according to any one of the appendices 1 to 5, having a buffer layer provided between the substrate and the first barrier layer. (Note 7) A semiconductor device according to any one of the appendices 1 to 6, having a cap layer provided on the channel layer. (Note 8) An amplifier characterized by having a semiconductor device as described in any one of the appendices 1 to 7. (Note 9) A power supply device characterized by having a semiconductor device as described in any one of the appendices 1 to 7. [Explanation of symbols]

[0043] 1: Semiconductor device 10: Nitride semiconductor stacked structure 11: Circuit board 12: Buffer Layer 13: First barrier layer 14: Second barrier layer 15: Channel Layer 16: Cap layer 131: First nitride semiconductor layer 132: Second nitride semiconductor layer 181: Source electrode 182: Drain electrode 183: Gate Tube

Claims

1. circuit board and A first barrier layer provided on the substrate, A second barrier layer is provided on the first barrier layer, A channel layer provided on the second barrier layer, It has, The first barrier layer comprises a superlattice structure having a first nitride semiconductor layer containing Al and a second nitride semiconductor layer containing Ga. The second barrier layer has a third nitride semiconductor layer containing Al and Ga, The channel layer has a fourth nitride semiconductor layer containing Ga, The semiconductor device has a nitrogen polarity on the surface of the second barrier layer facing the channel layer.

2. The first nitride semiconductor layer is an AlN layer, The semiconductor device according to claim 1, wherein the second nitride semiconductor layer is a GaN layer.

3. The third nitride semiconductor layer is an AlGaN layer, The semiconductor device according to claim 1 or 2, wherein the fourth nitride semiconductor layer is a GaN layer.

4. The semiconductor device according to claim 1 or 2, having a source electrode, a gate electrode, and a drain electrode provided on the channel layer.

5. The semiconductor device according to claim 1 or 2, wherein the substrate is a SiC substrate, a GaN substrate, or a sapphire substrate.

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