Output amplifier circuit and display driver

Abstract

This invention provides an output amplifier circuit and display driver that can suppress display unevenness, achieve high-speed response, and reduce power consumption. [Configuration] This disclosure includes first to K (where K is an integer of 2 or more) sub-bias circuits, each corresponding to a group of amplifiers (first to K) that divide a plurality of amplifiers into groups of amplifiers (first to K) that amplify an input signal using an operating current based on a high power supply voltage to generate an output voltage. These sub-bias circuits generate a bias voltage based on a high power supply voltage and a reference current and supply it to each of the first to K amplifier groups. A bias control circuit transmits a bias control signal, which indicates the voltage value of the bias voltage at a signal level based on a low power supply voltage, to each of the first to K sub-bias circuits. Each sub-bias circuit includes a level conversion circuit that converts the signal level of the bias control signal it receives from a signal level based on a low power supply voltage to a signal level based on a high power supply voltage to obtain a high-voltage bias control signal, and generates a bias voltage having a voltage value based on the high-voltage bias control signal.

Description

Technical Field

[0001] The present disclosure relates to an output amplifier circuit and a display driver.

Background Art

[0002] A display driver for driving, for example, a liquid crystal display panel or an organic EL panel as a display panel includes a plurality of output amplifiers that amplify a gradation voltage corresponding to a luminance level represented by a video signal and supply it to a source line of the display panel.

[0003] In addition, with the recent trend of larger screen sizes and higher resolutions in display panels, there is a demand for the output amplifier to shorten the rise or fall time of the output voltage, so-called high slew rate. The output amplifier is composed of, for example, an operational amplifier, and it is possible to increase the slew rate and achieve high-speed response by increasing the operating current flowing through its differential stage. However, there is a problem that the power consumption increases accordingly.

[0004] Therefore, a display driver has been proposed that can adjust the magnitude of the operating current flowing through the differential stage of the output amplifier from the outside by a bias voltage so that it is large in the first half of one data period and small in the second half (see, for example, Patent Document 1). In this display driver, a plurality of output amplifiers are divided into a plurality of groups, and a sub-bias circuit that generates a bias voltage for each group is provided. Each sub-bias circuit receives a reference current with a constant current value and also receives a bias control signal from a control unit for controlling the voltage value of the bias voltage. Each sub-bias circuit generates a plurality of currents based on the reference current, and generates a desired combined current by combining the generated plurality of currents in a combination according to the bias control signal. Then, each sub-bias circuit generates a bias voltage having a current value corresponding to the generated combined current and supplies it to each output amplifier belonging to its group.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-95545

[0006] [overview] Each output amplifier of the display driver described in Patent Document 1 amplifies a high-voltage gradation voltage based on an analog power supply voltage higher than the logic power supply voltage. Therefore, in order to control the magnitude of the operating current of each output amplifier, the control unit transmits a bias control signal having the analog power supply voltage to each of the multiple sub-bias circuits. The wiring length of the wiring that transmits the bias control signal to each of the multiple sub-bias circuits differs depending on the location of each sub-bias circuit within the semiconductor IC chip. As a result, there is a time difference in the timing of receiving the bias control signal between sub-bias circuits located close to the control unit and those located far away. Consequently, there is a difference in the timing of slew rate switching of the output amplifiers for each of the above groups, which may lead to display inconsistencies.

[0007] Each output amplifier circuit according to this disclosure includes: a plurality of amplifiers that receive a predetermined high power supply voltage and an input signal and generate an output voltage by amplifying the input signal with an operating current generated based on the high power supply voltage; first to K sub-bias circuits, each corresponding to a predetermined number of amplifier groups, which are divided into groups of 1 to K (where K is an integer of 2 or more); first to K sub-bias circuits that generate a bias voltage for setting the magnitude of the operating current based on the high power supply voltage and supply the bias voltage to each amplifier belonging to the corresponding first to K amplifier groups; and a bias control circuit that generates a bias control signal indicating the voltage value of the bias voltage at a signal level based on a low power supply voltage lower than the high power supply voltage and transmits the bias control signal to each of the first to K sub-bias circuits via wiring. Each of the first to K sub-bias circuits includes a level conversion circuit that converts the signal level of the bias control signal it receives from a signal level based on the low power supply voltage to a signal level based on the high power supply voltage to obtain a high-voltage bias control signal, and generates the bias voltage having a voltage value based on the high-voltage bias control signal. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the schematic configuration of the display device 100, including the display driver related to this disclosure. [Figure 2] This is a layout diagram showing an example of the arrangement of functional blocks constituting the output amplifier section 133 according to this disclosure within a semiconductor IC chip CHP. [Figure 3] This is a block diagram showing the internal configuration of the output amplifier section 133 according to the first embodiment. [Figure 4] This is a circuit diagram showing the internal configuration of the APx amplifier. [Figure 5] This is a circuit diagram showing the internal configuration of the main bias circuit MB. [Figure 6] This figure shows an example of the internal configuration of the bias control circuit BCC and an example of the circuit configuration of the sub-bias circuit SB1_R. [Figure 7]This is a time chart showing the waveforms of the clock signal CLK, bias control signal PWRC, gradation voltage Vx, and output voltage Gx. [Figure 8] This figure shows an example of the circuit configuration of the sub-bias circuit SB1_R as a second embodiment. [Figure 9] This is a block diagram showing the internal configuration of the output amplifier section 133a according to the third embodiment. [Figure 10] This is a block diagram showing the internal configuration of the output amplifier section 133b according to the fourth embodiment. [Figure 11] This is a block diagram showing the internal configuration of the bias control circuit BCCa.

[0009] [Detailed explanation] [Example 1] The embodiments of this disclosure will be described in detail below with reference to the drawings.

[0010] Figure 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to an embodiment.

[0011] As shown in Figure 1, the display device 100 includes a drive control unit 11, a scanning driver 12, a data driver 13, and a display panel 20.

[0012] The display panel 20 consists of, for example, an organic EL panel or a liquid crystal display panel. The display panel 20 has scan lines S1 to Sm (where m is an integer of 2 or more) extending horizontally in the 2D screen and data lines D1 to Dn (where n is an integer of 2 or more) extending vertically in the 2D screen. Display cells are formed in the regions (areas enclosed by dashed lines) at each intersection of the scan lines and data lines.

[0013] Furthermore, scan lines S1 to Sm are connected to the scan driver 12, and data lines D1 to Dn are connected to the data driver 13.

[0014] The drive control unit 11 receives the video signal VD and detects the horizontal synchronization signal and the vertical synchronization signal from the video signal VD. The drive control unit 11 supplies the detected horizontal synchronization signal to the scan driver 12. Also, based on the video signal VD, the drive control unit 11 generates various control signals such as a clock signal CLK synchronized with the horizontal synchronization signal, a load signal indicating the data capture timing, etc., and a series of pixel data pieces representing the luminance level of each pixel, for example, in 8-bit luminance gradations. The drive control unit 11 generates an image data signal PD including the above-described various control signals and the column of pixel data pieces, and supplies this to the data driver 13.

[0015] The scan driver 12 sequentially applies scan pulses to each of the scan lines S1 to Sm of the display panel 20 at a timing synchronized with the horizontal synchronization signal supplied from the drive control unit 11.

[0016] The data driver 13 is formed on a semiconductor IC (integrated circuit) chip and includes a data capture unit 131, a gradation voltage generation unit 132, and an output amplifier unit 133.

[0017] The data capture unit 131 captures pixel data pieces included in the image data signal PD one scan line at a time, that is, every n pieces. The data capture unit 131 designates the n captured pixel data pieces as pixel data P1 to Pn, and supplies these pixel data P1 to Pn to the gradation voltage generation unit 132 at the timing of, for example, the rising edge of the clock signal CLK.

[0018] The gradation voltage generation unit 132 converts the pixel data P1 to Pn supplied from the data capture unit 131 into gradation voltages V1 to Vn having voltage values corresponding to the luminance levels indicated by each. The gradation voltage generation unit 132 supplies the gradation voltages V1 to Vn to the output amplifier unit 133.

[0019] The output amplifier unit 133 supplies n voltages obtained by individually amplifying the gradation voltages V1 to Vn as output voltages G1 to Gn to the data lines D1 to Dn of the display panel 20.

[0020] Here, the data driver 13 is formed, for example, within a semiconductor IC chip having a rectangular chip shape. Also, in the semiconductor IC chip, along one side of the rectangle, n output terminals for outputting output voltages G1 to Gn to the outside are juxtaposed in a row, and an output amplifier section 133 is formed in the vicinity of these n output terminals.

[0021] FIG. 2 is a layout diagram showing an example of the arrangement form within the semiconductor IC chip CHP of the functional blocks constituting the output amplifier section 133. It is assumed that the entire area of the semiconductor IC chip CHP is divided into a central region, a left region and a right region that are adjacent to each other on the left and right sides sandwiching the central region in the direction along the long side of its four sides.

[0022] As shown in FIG. 2, as functional blocks, the output amplifier section 133 includes a main bias circuit MB, a bias control circuit BCC, sub-bias circuits SB1_R to SB3_R, SB1_L to SB3_L, and amplifier circuits OBLK_L and OBLK_R. The main bias circuit MB and the bias control circuit BCC are arranged in the central region of the semiconductor IC chip CHP. In the left region of the semiconductor IC chip CHP, sub-bias circuits SB1_L to SB3_L and amplifier circuit OBLK_L responsible for generating G1 to G(x - 1) (where x is an integer represented by n / 2 or 1 + n / 2) among the output voltages G1 to Gn are arranged. In the right region of the semiconductor IC chip CHP, sub-bias circuits SB1_R to SB3_R and amplifier circuit OBLK_R responsible for generating Gx to Gn among the output voltages G1 to Gn are arranged.

[0023] Note that the bias control circuit BCC receives the low power supply voltage LV which is the power supply voltage for the logic circuit, and each of the amplifier circuits OBLK_L and OBLK_R receives the high power supply voltage HV which is a higher voltage than the low power supply voltage LV for the analog circuit. Each of the sub-bias circuits SB1_L to SB3_L and SB1_R to SB3_R receives both the low power supply voltage LV and the high power supply voltage HV.

[0024] Figure 3 is a block diagram showing a portion of the configuration of the output amplifier section 133, specifically the main bias circuit MB, sub-bias circuits SB1_R~SB3_R, bias control circuit BCC, and amplifier circuit OBLK_R extracted from the functional block group included in the semiconductor IC chip CHP.

[0025] The output amplifier section OBLK_R includes amplifiers APx~APn that individually receive the gradation voltages Vx~Vn from the gradation voltages V1~Vn generated by the gradation voltage generation section 132. Each of the amplifiers APx~APn individually amplifies the gradation voltages Vx~Vn it receives and outputs the n resulting voltages as output voltages Gx~Gn via the output terminals Tx~Tn of the semiconductor IC chip.

[0026] Each of the amplifiers APx to APn is composed of a differential amplifier, for example, a differential stage, a current mirror stage, and an output stage. The operating current flowing through the respective differential stage and current mirror stage of each amplifier APx to APn is set based on the bias voltage group supplied from the sub-bias circuits SB1_R to SB3_R.

[0027] In other words, each of the amplifiers APx to APn has its output slew rate set by the bias voltages supplied from the sub-bias circuits SB1_R to SB3_R.

[0028] The main bias circuit MB generates three reference currents IB_1 to IB_3, each having a predetermined constant current value. The main bias circuit MB supplies reference voltage IB_1 to sub-bias circuit SB1_R, reference voltage IB_2 to sub-bias circuit SB2_R, and reference voltage IB_3 to sub-bias circuit SB3_R.

[0029] The bias control circuit BCC generates a bias control signal group PWRC that specifies the voltage value of the bias voltage using, for example, a 3-bit bias control signal, each having a binary level (LV, VSS) based on the low supply voltage LV. The bias control circuit BCC transmits this bias control signal group PWRC to each of the sub-bias circuits SB1_R to SB3_R via the wiring group BL0.

[0030] Each of the sub-bias circuits SB1_R to SB3_R corresponds to one of three groups formed by dividing the amplifiers APx to APn into sub-biases. For example, sub-bias circuit SB1_R corresponds to the first group consisting of amplifiers AP1 to APr (where r is an integer less than n). Sub-bias circuit SB2_R corresponds to the second group consisting of amplifiers AP(r+1) to APg (where g is an integer greater than r and less than n). Sub-bias circuit SB3_R corresponds to the third group consisting of amplifiers AP(g+1) to APn.

[0031] Sub-bias circuit SB1_R receives the reference current IB_1 sent from the main bias circuit MB, and also receives the bias control signal group PWRC transmitted from the bias control circuit BCC via the wiring group BL0. Sub-bias circuit SB2_R receives the reference current IB_2 sent from the main bias circuit MB, and also receives the bias control signal group PWRC transmitted from the bias control circuit BCC via the wiring group BL0. Sub-bias circuit SB3_R receives the reference current IB_3 sent from the main bias circuit MB, and also receives the bias control signal group PWRC transmitted from the bias control circuit BCC via the wiring group BL0.

[0032] Furthermore, each of the sub-bias circuits SB1_R to SB3_R has the same circuit configuration, including the LV / HV conversion circuit COV which acts as a level conversion circuit.

[0033] The LV / HV conversion circuit COV included in the sub-bias circuit SB1_R converts each signal level (LV) of the bias control signal group PWRC into a high-voltage bias control signal group that has been level-shifted to a signal level (HV) based on a higher high-power supply voltage HV.

[0034] The sub-bias circuit SB1_R generates a group of bias voltages to set the magnitude of the operating current for each of the amplifiers APx to APr belonging to the first group, based on the high power supply voltage HV and the reference current IB_1. The sub-bias circuit SB1_R then supplies the generated group of bias voltages to each of the amplifiers APx to APr belonging to the first group.

[0035] The LV / HV conversion circuit COV included in the sub-bias circuit SB2_R converts each signal level (LV) of the bias control signal group PWRC into a high-voltage bias control signal group that is level-shifted to a signal level (HV) based on a higher high-power supply voltage HV.

[0036] The sub-bias circuit SB2_R generates a group of bias voltages to set the magnitude of the operating current for each of the amplifiers AP(r+1) to APg belonging to the second group, based on the high power supply voltage HV and the reference current IB_2. The sub-bias circuit SB2_R then supplies the generated group of bias voltages to each of the amplifiers AP(r+1) to APg belonging to the second group.

[0037] The LV / HV conversion circuit COV included in the sub-bias circuit SB3_R converts each signal level (LV) of the bias control signal group PWRC into a high-voltage bias control signal group that has been level-shifted to a signal level (HV) based on a higher high-power supply voltage HV.

[0038] The sub-bias circuit SB3_R generates a group of bias voltages to set the magnitude of the operating current for each of the amplifiers AP(g+1) to APn belonging to the third group, based on the high power supply voltage HV and the reference current IB_3. The sub-bias circuit SB3_R then supplies the generated group of bias voltages to each of the amplifiers AP(g+1) to APn belonging to the third group.

[0039] The following describes the detailed configuration of the main bias circuit MB, amplifiers APx to APn, sub-bias circuits SB1_R to SB3_R, and bias control circuit BCC shown in Figure 3.

[0040] Figure 4 is a circuit diagram showing the internal configuration of amplifier APx, which is extracted from amplifiers APx to APn.

[0041] The amplifier APx has a differential stage including P-channel transistors U2-U4 and N-channel transistors J2-J4, and an output stage including P-channel transistor U11 and N-channel transistor J11. Furthermore, the amplifier APx has cascode current mirror circuits 30 and 40, and stray current sources 50 and 60.

[0042] A high power supply voltage HV is applied to the source of the differential stage transistor U2, and a bias voltage VBH1 is supplied to its gate. Transistor U2 generates an operating current Iu1 having a current value corresponding to the bias voltage VBH1, and supplies this to the sources of transistors U3 and U4, respectively. Transistor U3 receives the gradation voltage Vx at its gate. Transistor U4 receives the output voltage Gx, which is the output of amplifier APx, at its gate. Transistors U3 and U4 generate differential output currents NCM1 and NCM2 by dividing the operating current Iu1 supplied from transistor U2 into two based on the voltage ratio of the gradation voltage Vx and the output voltage Gx. Transistors U3 and U4 supply currents NCM1 and NCM2 to nodes n3 and n4 of the cascode current mirror circuit 40 via their respective drains. That is, transistor U3 supplies current NCM2 corresponding to the voltage value of the gradation voltage Vx to node n4 of the cascode current mirror circuit 40. Transistor U4 supplies a current NCM1 corresponding to the voltage value of the output voltage Gx to node n3 of the cascode current mirror circuit 40.

[0043] The ground voltage AVSS is applied to the source of the differential stage transistor J2, and the bias voltage VBL1 is supplied to its gate. The drain of transistor J2 is connected to the sources of transistors J3 and J4, respectively. Transistor J2 generates an operating current Ij1 with a current value corresponding to the bias voltage VBL1, and draws this from the sources of transistors J3 and J4. Transistor J3 receives the gradation voltage Vx at its gate. Transistor J4 receives the output voltage Gx at its gate. Transistors J3 and J4 generate differential output currents PCM1 and PCM2 by dividing the operating current Ij1 into two based on the voltage ratio between the gradation voltage Vx and the output voltage Gx received at their respective gates. Transistor J3 draws the current PCM2 corresponding to the gradation voltage Vx from node n2 of the cascode current mirror circuit 30 and supplies this to the drain of transistor J2. Transistor J4 draws the current PCM1 corresponding to the output voltage Gx from node n1 of the cascode current mirror circuit 30 and supplies it to the drain of transistor J2.

[0044] Furthermore, in the differential stage described above, the operating current Iu1 is adjusted by the bias voltage VBH1, and the operating current Ij1 is further adjusted by the bias voltage VBL1. As a result, for example, the lower the voltage value of the bias voltage VBH1, the larger the current supplied to nodes n3 and n4 of the cascode current mirror circuit 40. Also, the higher the voltage value of the bias voltage VBL1, the larger the current drawn from nodes n1 and n2 of the cascode current mirror circuit 30.

[0045] The cascode current mirror circuit 30 includes P-channel transistors U5 to U8, and the cascode current mirror circuit 40 includes N-channel transistors J7 to J10. Furthermore, the stray current source 50 includes a P-channel transistor U9 and an N-channel transistor J5, and the stray current source 60 includes a P-channel transistor U10 and an N-channel transistor J6.

[0046] A high power supply voltage HV is applied to the sources of transistors U5 and U6 in the cascode current mirror circuit 30, and their gates are connected to each other. The drain of transistor U5 is connected to the source of transistor U7 via node n1. The drain of transistor U6 is connected to the source of transistor U8 via node n2. A bias voltage VBH2 is applied to the gates of both transistors U7 and U8. The drain of transistor U7 is connected to the gates of transistors U5 and U6, the source of transistor U9 of the stray current source 50, and the drain of transistor J5 via node n5.

[0047] The drain of transistor U8 is connected to the source of transistor U10 and the drain of transistor J6 of the stray current source 60 via node n6, which acts as a high-potential drive node. A bias voltage VBH3 is applied to the gates of transistors U9 and U10, and a bias voltage VBL3 is applied to the gates of transistors J5 and J6. The drain of transistor U9 and the source of transistor J5 are connected to the drain of transistor J7 of the cascode current mirror circuit 40 via node n7. The drain of transistor U10 and the source of transistor J6 are connected to the drain of transistor J8 of the cascode current mirror circuit 40 via node n8, which acts as a low-potential drive node.

[0048] A bias voltage VBL2 is applied to the gates of transistors J7 and J8. The source of transistor J7 is connected to the drain of transistor J9 via node n3. The source of transistor J8 is connected to the drain of transistor J10 via node n4. A ground voltage AVSS is applied to the sources of transistors J9 and J10, and the gates of transistors J9 and J10 are connected to the drain of transistor J7.

[0049] In the cascode current mirror circuits 30 and 40 and the stray current sources 50 and 60 described above, an operating current Iu2 having a current value corresponding to the difference between current PCM1 and current PCM2 supplied from the differential stage flows to node n6. Furthermore, in the cascode current mirror circuits 30 and 40 and the stray current sources 50 and 60, an operating current Ij2 having a current value corresponding to the difference between current NCM1 and current NCM2 supplied from the differential stage flows to node n8.

[0050] As a result, the cascode current mirror circuits 30 and 40 and the stray current sources 50 and 60 supply or draw from node n6 an operating current Iu2 corresponding to the difference between currents PCM1 and PCM2, thereby generating a high-potential drive voltage PG at node n6. This drive voltage PG is supplied to the gate of transistor U11 in the output stage. Furthermore, the cascode current mirror circuits 30 and 40 and the stray current sources 50 and 60 supply or draw from node n8 an operating current Ij2 corresponding to the difference between currents NCM1 and NCM2, thereby generating a low-potential output drive voltage NG at node n8. This output drive voltage NG is supplied to the gate of transistor J11 in the output stage.

[0051] A high power supply voltage HV is applied to the source of transistor U11 in the output stage. Transistor U11 generates a current corresponding to the output drive voltage PG received at its gate and supplies this current to the output node nZ, thereby increasing the voltage at output node nZ. The ground voltage AVSS is applied to the source of transistor J11. Transistor J11 draws a current from output node nZ corresponding to the output drive voltage NG received at its gate, thereby decreasing the voltage at output node nZ.

[0052] The operation of transistors U11 and J11 described above generates an output voltage Gx at the output node nZ, which is then output via the output terminal. This output voltage Gx is fed back to the gates of transistor U4 on the high-potential side and transistor J4 on the low-potential side of the differential stage.

[0053] Furthermore, to ensure stable output operation of amplifier APx, it is equipped with phase compensation capacitors C1 and C2. In Figure 4, as an example of connecting the phase compensation capacitors, phase compensation capacitor C1 is connected between output node nZ and node n2, and phase compensation capacitor C2 is connected between output node nZ and node n4.

[0054] In the amplifier APx configuration shown in Figure 4, the bias voltages VBL1 to VBL3 and VBH1 to VBH3 adjust the operating currents Iu2 and Ij2 flowing through nodes n6 and n8, which act as drive nodes driving the output stage transistors U11 and J11. This changes the magnitude of the current sent to and drawn from the output node nZ, thereby adjusting the driving capability of the amplifier APx. The rate of change of the output voltage Gx when the gradation voltage Vx of the amplifier APx changes significantly, i.e., the slew rate, mainly depends on the operating currents Ij1 and Iu1 flowing through the differential stage. In simple terms, the slew rate can be considered as the charging and discharging rate of the phase compensation capacitors C1 and C2 accompanying the change in output voltage Gx. Therefore, the larger the current values ​​of the operating currents Ij1 and Iu1, the higher the driving capability and slew rate of the amplifier APx.

[0055] Thus, as shown in Figure 4, each of the amplifiers APx to APn receives a high power supply voltage HV and a gradation voltage Vx as an input signal, and generates an output voltage Gx by amplifying the gradation voltage Vx using the operating current generated based on the high power supply voltage HV.

[0056] Figure 5 is a circuit diagram showing an example of the internal configuration of the main bias circuit MB shown in Figure 3.

[0057] As shown in Figure 5, the main bias circuit MB includes P-channel transistors 81-84 that constitute a current mirror circuit, and a current source CG.

[0058] Transistor 81 has its gate and drain connected to each other. The gates of transistors 82-84 are connected to the gate of transistor 81. One end of current source CG is connected to the drain of transistor 81. The other end of current source CG is connected to the ground voltage AVSS.

[0059] In this configuration, in the main bias circuit MB, a reference current Io having a predetermined constant current value generated by the current source CG flows to the drain of transistor 81. As a result, reference currents IB_1, IB_2, and IB_3, which are current mirrors of the reference current Io, are individually supplied from the drains of transistors 82 to 84 to each of the sub-bias circuits SB1_R to SB3_R.

[0060] Each of the sub-bias circuits SB1_R to SB3_R has the same internal circuit configuration as described above.

[0061] Therefore, below, we will extract SB1_R from the sub-bias circuits SB1_R to SB3_R and explain in detail the circuit configuration of the sub-bias circuit and the internal configuration of the bias control circuit BCC.

[0062] Figure 6 shows the internal configuration of the bias control circuit BCC and the circuit configuration of the sub-bias circuit SB1_R.

[0063] The bias control circuit BCC includes a setting register RG1 and a PWRC signal generation circuit PGC that operate under a low supply voltage LV for the logic circuit.

[0064] The setting register RG1 receives a setting signal SET, which includes bias voltage information specifying the voltage values ​​for bias voltages VBH1 to VBH3 and VBL1 to VBL3, as well as switching timing information specifying the timing for switching the bias voltage values. The setting register RG1 stores the bias voltage information and switching timing information included in the setting signal SET, and supplies this bias voltage information and switching timing information to the PWRC signal generation circuit PGC.

[0065] The PWRC signal generation circuit PGC generates a bias control signal group PWRC, which consists of 3-bit bias control signals, each having a signal level (LV, VSS) based on the low power supply voltage LV, based on the clock signal CLK, bias voltage information, and switching timing information.

[0066] Figure 7 is a time chart showing an example of the signal configuration of a single bit of bias control signal extracted from the bias control signal group PWRC.

[0067] In other words, as shown in Figure 7, the PWRC signal generation circuit PGC first generates a bias control signal with the low supply voltage LV indicated in the bias voltage information at time t0, for example, the rising edge of the clock signal CLK. Subsequently, at time t1, after the period Tdyn indicated in the switching timing information has elapsed from time t0, the PWRC signal generation circuit PGC switches the voltage value of the bias control signal from the low supply voltage LV to the ground voltage VSS. Here, the PWRC signal generation circuit PGC maintains the voltage value of the bias voltage control signal at the ground potential VSS for the remainder of the data period Tsta. Then, as shown in Figure 7, at time t2, the beginning of the next data period, the PWRC signal generation circuit PGC switches the voltage value of the bias voltage control signal from the ground voltage VSS to the low supply voltage LV. That is, for each data period, the PWRC signal generation circuit PGC generates a group of bias control signals PWRC with the low supply voltage LV that increases the slew rate of the amplifier during the first period (Tdyn). Then, in the subsequent period (Tsta), the PWRC signal generation circuit PGC generates a bias control signal PWRC of the ground voltage VSS, which reduces the slew rate of the amplifier.

[0068] As described above, the bias control circuit BCC, which includes the setting register RG1 and the PWRC signal generation circuit PGC, receives a low power supply voltage LV, which is lower than the high power supply voltage HV, as the power supply voltage for the logic circuit to operate itself. The bias control circuit BCC then generates a bias control signal group PWRC that specifies the voltage value of the bias voltage in 3 bits based on the signal level (LV, VSS) of the low power supply voltage LV, and transmits this to each of the sub-bias circuits SB1_R to SB3_R via the wiring group BL0.

[0069] As shown in Figure 6, the sub-bias circuit SB1_R includes an LV / HV conversion circuit COV and an adjustment circuit VCN which includes P-channel MOS transistors Q1-Q5 and switch circuits SW1-SW3. Furthermore, the sub-bias circuit SB1_R includes P-channel MOS transistors Q6-Q12 and N-channel MOS transistors R1-R10.

[0070] As described above, the LV / HV conversion circuit COV shifts the signal levels of each signal in the bias control signal group PWRC from signal levels based on the low power supply voltage LV (LV, VSS) to signal levels based on the high power supply voltage HV (HV, AVSS). The LV / HV conversion circuit COV acquires three bias control signals, each with a signal level based on the high power supply voltage HV (HV, AVSS), converted by this level shift, as high-voltage bias control signals b1 to b3, and supplies each of them to the adjustment circuit VCN.

[0071] Transistor R1 receives the reference current IB_1 supplied from the main bias circuit MB through its drain. The drain and gate of transistor R1 are connected to the gate of transistor R2, and the ground voltage AVSS is applied to the sources of both transistors R1 and R2. The drain of transistor R2 is connected to the adjustment circuit VCN via node L2.

[0072] In this configuration, transistor R2 generates a current I2 corresponding to the reference current IB_1 and flows it to node L2.

[0073] The gates of transistors Q1 and Q2 in the adjustment circuit VCN are connected to node L2. A high power supply voltage HV is applied to the sources of transistors Q1 and Q2. The drain of transistor Q2 is connected to the drain and gate of transistor R3 via node L3. The ground voltage AVSS is applied to the source of transistor R3. With this configuration, transistor Q2 generates a reference bias voltage VQ at node L3 by sending a current I3 corresponding to the current I2 described above to node L3. The sources of transistors Q3 to Q5 in the adjustment circuit VCN are each connected to node L3, and their respective drains are connected to node L3.

[0074] Switch circuit SW1 receives a high-voltage bias control signal b1 sent from the LV / HV conversion circuit COV. Switch circuit SW1 is set to either a state in which the high power supply voltage HV is supplied to the gate of transistor Q3 (referred to as the off state) or a state in which node L2 is connected to the gate of transistor Q3 (referred to as the on state) in response to the high-voltage bias control signal b1. Switch circuit SW2 receives a high-voltage bias control signal b2 sent from the LV / HV conversion circuit COV. Switch circuit SW2 is set to either a state in which the high power supply voltage HV is supplied to the gate of transistor Q4 (referred to as the off state) or a state in which node L2 is connected to the gate of transistor Q4 (referred to as the on state) in response to the high-voltage bias control signal b2. Switch circuit SW3 receives a high-voltage bias control signal b3 sent from the LV / HV conversion circuit COV. The switch circuit SW3 is set to either a state in which the high power supply voltage HV is supplied to the gate of transistor Q5 (referred to as the off state) or a state in which node L2 is connected to the gate of transistor Q5 (referred to as the on state), in response to the high voltage bias control signal b3.

[0075] Transistor Q3 turns on only when switch circuit SW1 is turned on, and sends a current Ic, which is a current mirror of the current I2 described above, to node L3. Transistor Q4 turns on only when switch circuit SW2 is turned on, and sends a current Ic, which is a current mirror of the current I2 described above, to node L3. Transistor Q5 turns on only when switch circuit SW3 is turned on, and sends a current Ic, which is a current mirror of the current I2 described above, to node L3.

[0076] With the above configuration, the adjustment circuit VCN sends a combined current, which is the adjustment current It, to node L3. This combined current is the current I3 corresponding to the reference current IB_1 and the current Ic sent from each of the transistors Q3 to Q5.

[0077] For example, if the adjustment circuit VCN receives high-voltage bias control signals b1 to b3, each with a signal level equal to the high power supply voltage HV, then transistors Q3 to Q5 will all be in the OFF state. As a result, the adjustment current It flowing to node L3 will be only the current I3 sent from transistor Q2. Also, for example, if the adjustment circuit VCN receives high-voltage bias control signals b1 to b3, each with a signal level equal to the ground voltage AVSS, then transistors Q3 to Q5 will all be in the ON state. As a result, the adjustment current It flowing to node L3 will be the current I3 sent from transistor Q2 plus the current Ic sent from each of transistors Q3 to Q5 (I3 + 3·Ic). Furthermore, for example, if the adjustment circuit VCN receives high-voltage bias control signal b1, where the signal level is the ground voltage AVSS, and high-voltage bias control signals b2 and b3, where the signal levels are both equal to the high power supply voltage HV, then only transistor Q3 among transistors Q3 to Q5 will be in the ON state. As a result, the adjustment current It flowing through node L3 is the sum of the current I3 supplied from transistor Q2 and the current Ic supplied from transistor Q3 (I3 + Ic).

[0078] Thus, the adjustment circuit VCN generates the adjustment current It by current-mirroring the reference currents (IB_1, I2) using a current mirror ratio based on the high-voltage bias control signal.

[0079] Then, the adjustment current It generated as described above is sent to node L3, and a voltage with a voltage value corresponding to the magnitude of the adjustment current It is generated on node L3 as the reference bias voltage VQ.

[0080] Here, as shown in Figure 6, the gates of transistors R4 to R7 are connected to the gate of transistor R3 and node L3, and the ground voltage AVSS is applied to the sources of transistors R4 to R7.

[0081] The drain of transistor R4 is connected to the gate and drain of transistor Q6 via node L4. The drain of transistor R5 is connected to the gate and drain of transistor Q7 via node L5. The drain of transistor R6 is connected to the gate and drain of transistor Q8 via node L6. A high power supply voltage HV is applied to the sources of each of transistors Q6 to Q8.

[0082] The drain of transistor R7 is connected to the drain of transistor Q9 and to the gates of transistors Q9 through Q12. A high power supply voltage HV is applied to the sources of transistors Q9 through Q12. The drain of transistor Q10 is connected to the gate and drain of transistor R8 via node L7. The drain of transistor Q11 is connected to the gate and drain of transistor R9 via node L8. The drain of transistor Q12 is connected to the gate and drain of transistor R9 via node L9. The ground voltage AVSS is applied to the sources of transistors R8 through R10.

[0083] In the circuit consisting of transistors R4 and Q6 described above, transistor R4 flows a current corresponding to the reference bias voltage VQ supplied to its gate to node L4. The voltage generated at node L4 is supplied to amplifiers APx to APn as bias voltage VBH1. In the circuit consisting of transistors R5 and Q7, transistor R5 flows a current corresponding to the reference bias voltage VQ supplied to its gate to node L5. The voltage generated at node L5 is supplied to amplifiers APx to APn as bias voltage VBH2. In the circuit consisting of transistors R6 and Q8, transistor R6 flows a current corresponding to the reference bias voltage VQ supplied to its gate to node L6. The voltage generated at node L6 is supplied to amplifiers APx to APn as bias voltage VBH3.

[0084] Transistor R7 supplies a current corresponding to the reference bias voltage VQ to its gate via transistor Q9. This current corresponding to the reference bias voltage VQ is then sent from the drains of transistors Q10 to Q12 to nodes L7 to L9, respectively. When transistor Q10 sends the current corresponding to the reference bias voltage VQ to node L7, the voltage generated at node L7 is supplied to amplifiers APx to APn as bias voltage VBL1. Similarly, when transistor Q11 sends the current corresponding to the reference bias voltage VQ to node L8, the voltage generated at node L8 is supplied to amplifiers APx to APn as bias voltage VBL2. Furthermore, when transistor Q12 sends the current corresponding to the reference bias voltage VQ to node L9, the voltage generated at node L9 is supplied to amplifiers APx to APn as bias voltage VBL3.

[0085] Thus, in the sub-bias circuit SB1_R, a current-voltage conversion circuit composed of transistors R3~R10 and Q6~Q12 performs a current-voltage conversion process on the reference current IB_1 to generate bias voltages VBH1~VBH3 and VBL1~VBL3.

[0086] Furthermore, the sub-bias circuit SB1_R switches the voltage values ​​of the bias voltages VBH1~VBH3 and VBL1~VBL3 in two stages for each data period, according to the bias control signal group PWRC shown in Figure 7.

[0087] In other words, as shown in Figure 7, the bias control signal group PWRC maintains the low power supply voltage LV state, which instructs the amplifier to achieve a high slew rate, during the first period Tdyn, and maintains the ground voltage VSS state, which instructs a low slew rate, during the subsequent period Tsta, for each data period.

[0088] In response to the PWRC bias control signal, the sub-bias circuit SB1_R generates bias voltages (VBH1~VBH3, VBL1~VBL3) with a first voltage value that increases the slew rate of amplifiers APx~APn during the period Tdyn shown in Figure 7. Then, during the period Tsta following Tdyn, the sub-bias circuit SB1_R generates bias voltages (VBH1~VBH3, VBL1~VBL3) with a second voltage value that decreases the slew rate of amplifiers APx~APn. The bias voltage (first voltage value) during period Tdyn is variably set by the combination of logic values ​​(LV / VSS) of the 3-bit bias control signal that generates the PWRC signal during period Tdyn, thereby adjusting the level of slew rate increase during period Tdyn.

[0089] According to the above operation, in each data period, the operating current flowing through each of the amplifiers APx to APn is larger in the initial period Tdyn compared to the subsequent period Tsta. As a result, at the beginning of a data period, for example, the slew rate of amplifier APx is increased, and as shown in Figure 7, even when a large gradation voltage Vx (Vm) is input, the rise or fall time of the output voltage Gx can be shortened. On the other hand, in the period Tsta following the initial period Tdyn, the voltage change of the output voltage Gx is sufficiently small, so there is no need to increase the slew rate, and the operating current flowing through amplifier APx is reduced, thereby lowering power consumption. In other words, the sub-bias circuit SB1_R enables high-speed response processing with low power consumption.

[0090] Furthermore, by adopting the configuration shown in Figure 6 for the sub-bias circuits SB2_R and SB3_R, it becomes possible to achieve low power consumption and high-speed response processing.

[0091] By the way, in the output amplifier section 133 of this disclosure, as shown in Figure 2, the distances from the bias control circuit BCC to each of the sub-bias circuits SB1_R, SB2_R, and SB3_R (SB1_L, SB2_L, SB3_L) are different within the semiconductor IC chip.

[0092] Therefore, the wiring length of the wiring group BL0 that transmits the bias control signal group PWRC generated by the bias control circuit BCC to each sub-bias circuit also differs, for example, between sub-bias circuits SB1_R and SB3_R. As a result, as shown in Figure 7, for example, the delay time from when the bias control circuit BCC sends out the bias control signal group PWRC until it reaches sub-bias circuit SB3_R is greater than the delay time until it reaches sub-bias circuit SB1_R. In this case, if the difference in delay time is large, for example, a difference will occur in the rise (fall) time of the output voltage output from amplifier APn, which receives the bias voltage group from sub-bias circuit SB3_R, and amplifier APr, which receives the bias voltage group from sub-bias circuit SB1_R. As a result, there was a risk of display inconsistencies.

[0093] Therefore, in the output amplifier section 133 of this disclosure, the bias control signal group PWRC is transmitted to each sub-bias circuit (SB1_R~SB3_R, SB1_L~SB3_L) in the form of a low signal level based on a low power supply voltage LV, which is lower than the high power supply voltage HV that operates the amplifiers AP1~APn. By transmitting with a low amplitude voltage signal based on the low power supply voltage LV in this way, the distortion and delay of the signal waveform during low-level / high-level switching can be reduced compared to high-amplitude voltage signal transmission based on the high power supply voltage HV. In this case, the output amplifier section 133 of this disclosure controls the slew rate of the amplifier operating at the high power supply voltage HV by converting each signal level of the bias control signal group PWRC to a high signal level based on the high power supply voltage HV within each sub-bias circuit.

[0094] Therefore, according to the output amplifier section 133 of this disclosure, it is possible to suppress the degradation of the signal waveform of the wiring group BL0 used for transmission compared to when the bias control signal group is transmitted to each sub-bias circuit in the form of a high signal level based on the high power supply voltage HV. In addition, it is possible to reduce the size of elements such as the output transistor that is responsible for the output of the bias control signal group PWRC within the bias control circuit BCC, which is composed of low-voltage transistors with high current drive capability.

[0095] Thus, the binary bias control signal group PWRC based on the low power supply voltage LV has a smaller signal amplitude than the binary signal based on the high power supply voltage HV, and therefore the rise time or fall time is shorter. In other words, the output amplifier section 133 of this disclosure can reduce the transmission delay time of the bias control signal group PWRC.

[0096] As a result, it becomes possible to reduce the time difference between the delay time from when the bias control circuit BCC sends out the bias control signal group PWRC until it reaches the sub-bias circuit SB3_R, and the delay time until it reaches the sub-bias circuit SB1_R.

[0097] Therefore, the difference between the rise (fall) time of the output voltage of the amplifier group receiving the bias voltage from sub-bias circuit SB3_R and the rise (fall) time of the output voltage of the amplifier group receiving the bias voltage from sub-bias circuit SB1_R becomes smaller. This makes it possible to suppress display irregularities caused by this time difference.

[0098] As described in detail above, the output amplifier section 133 of this disclosure makes it possible to suppress display unevenness, achieve high-speed response, and reduce power consumption.

[0099] In the above embodiment, six sub-bias circuits SB1_R~SB3_R and SB1_L~SB3_L are used as sub-bias circuits in the output amplifier section 133, but the number of sub-bias circuits is not limited to six. Furthermore, the circuit configuration of the sub-bias circuits is not limited to that shown in Figure 6, nor is the circuit configuration of each amplifier limited to that shown in Figure 4.

[0100] In short, the output amplifier section 133 can include any of the following: multiple amplifiers, sub-bias circuits numbered 1 to K (where K is an integer of 2 or more), and a bias control circuit.

[0101] In other words, each of the multiple amplifiers (e.g., APx to APn) receives a predetermined high power supply voltage (HV) and an input signal (e.g., Vx), and generates an output voltage (e.g., Gx) by amplifying the input signal with an operating current generated based on the high power supply voltage. The first to K sub-bias circuits (e.g., SB1_R to SB3_R) are provided corresponding to each of the first to K amplifier groups, which are obtained by dividing the multiple amplifiers into predetermined numbers. Each of the first to K sub-bias circuits generates a bias voltage (e.g., VBH1 to VBH3, VBL1 to VBL3) to set the magnitude of the amplifier's operating current based on the high power supply voltage and a reference current, and supplies it to each amplifier belonging to the corresponding first to K amplifier group. The bias control circuit (BCC) receives a low power supply voltage (LV) lower than the high power supply voltage (HV) and generates a bias control signal (PWRC) that indicates the voltage value of the bias voltage at a signal level based on the low power supply voltage. The bias control circuit then transmits the generated bias control signal to each of the first to K sub-bias circuits via wiring (BL0). Each of the first to K sub-bias circuits includes a level conversion circuit (COV) that converts the signal level of the bias control signal (PWRC) it receives from a low supply voltage (LV) to a high supply voltage (HV) to obtain a high-voltage bias control signal (e.g., b1 to b3). Each of the first to K sub-bias circuits generates a bias voltage having a voltage value based on this high-voltage bias control signal.

[0102] [Example 2] Figure 8 is a circuit diagram showing the other circuit configurations of sub-bias circuit SB1_R, which is extracted from sub-bias circuits SB1_R to SB3_R.

[0103] Furthermore, the main bias circuit MB and bias control circuit BCC shown in Figure 8 are identical to those shown in Figure 6.

[0104] The sub-bias circuit SB1_R shown in Figure 8 incorporates the voltage adjustment function of the adjustment circuit VCN shown in Figure 6 into the LV / HV conversion circuit COV.

[0105] In other words, the sub-bias circuit SB1_R shown in Figure 8 is the same as the configuration shown in Figure 6, but with transistors R1 and R2, and transistors Q3 to Q5 and switch circuits SW1 to SW3 included in the adjustment circuit VCN removed. However, in the sub-bias circuit SB1_R shown in Figure 8, the LV / HV conversion circuit COV2 is used as the level conversion circuit instead of the LV / HV conversion circuit COV shown in Figure 6, and the other circuit configurations are the same as those shown in Figure 6.

[0106] The LV / HV conversion circuit COV2 includes N-channel transistors h1 and h2 as level conversion circuits responsible for LV / HV conversion, and a selector SL and N-channel transistors r0 to r4 as adjustment circuits VCN2.

[0107] Transistor h1, which constitutes the level conversion circuit, receives a predetermined clamp voltage Vc1p at its gate and a reference current IB_1 based on the high power supply voltage HV sent from the main bias circuit MB at its drain, converting it into a current based on the low power supply voltage LV. Transistor h2 receives the clamp voltage Vc1p at its gate and converts the adjustment current based on the low power supply voltage LV generated by the adjustment circuit VCN2 into an adjustment current I2 based on the high power supply voltage HV, outputting it as a sink current from its drain and supplying it to transistor Q1. Note that the clamp voltage Vc1p has the same voltage value as, for example, the low power supply voltage LV, which is the power supply voltage for logic. Furthermore, transistors h1 and h2 only act as a bridge for the current between the LV circuit and the HV circuit, which are composed of element withstand voltages corresponding to the power supply voltage, and do not affect the current value. Transistors h1 and h2 are composed of high-voltage transistors that correspond to the high power supply voltage HV.

[0108] Transistor r0, which constitutes the adjustment circuit VCN2, has its gate and drain connected to each other, and the ground voltage AVSS is applied to its source. Transistors r1 to r4, which also constitute the adjustment circuit VCN2, have their gates commonly connected to the gate of transistor r0, and the ground voltage AVSS is commonly applied to their sources. The drain of transistor r1 is connected to the source of transistor h2, and the drains of transistors r2 to r4 are connected to selector SL. In other words, transistors r0 to r4 constitute a current mirror that generates four currents by current mirroring the reference current received through transistor h1.

[0109] Selector SL includes first to third switches that are individually turned on or off according to the bias control signal group PWRC. One end of each of the first to third switches is commonly connected to the source of transistor h2, and the other end of each of the first to third switches is individually connected to the drains of transistors r2 to r4. Selector SL receives the bias control signal group PWRC, based on the low supply voltage LV, transmitted from the bias control circuit BCC via the wiring group BL0. Selector SL adjusts the magnitude of the current flowing to the source of transistor h2 (sink current) by turning on a number of switches from the first to third switches according to the bias control signal group PWRC.

[0110] Furthermore, in Figure 8, the main bias circuit MB may be configured to operate in response to a low supply voltage LV and generate a reference current IB_1 based on the low supply voltage LV. In this case, the low supply voltage LV is used not only for logic circuits but also for analog circuits, and the N-channel transistor h1 responsible for LV / HV conversion in the LV / HV conversion circuit COV2 becomes unnecessary.

[0111] In other words, the LV / HV conversion circuit COV2 has an adjustment circuit VCN2 and a level conversion section. The adjustment circuit VCN2 generates an adjustment current based on a low power supply voltage of a magnitude obtained by current mirroring the reference current using a current mirror ratio based on the bias control signal PWRC. The level conversion section includes at least a transistor h2 that receives a predetermined clamp voltage Vclp at its gate, and transistor h2 converts the adjustment current based on the low power supply voltage to an adjustment current (I2) based on the high power supply voltage and outputs it as a sink current from its drain. At this time, in the LV / HV conversion circuit COV2, transistor h2 performs LV / HV conversion, converting the current adjusted according to the bias control signal PWRC based on the low power supply voltage LV to an adjustment current (I2) based on the high power supply voltage HV.

[0112] Here, in the sub-bias circuit SB1_R, a current mirror consisting of transistors Q1 and Q2 outputs an adjustment current It based on the high power supply voltage HV, which is a current mirror of the adjustment current (I2). Then, a current-voltage conversion circuit consisting of transistors R3~R10 and Q6~Q12 generates a group of bias voltages (VBH1~VBH3, VBL1~VBL3) based on the adjustment current It.

[0113] Incidentally, the LV / HV conversion circuit COV2 employs a regulating circuit VCN2 that operates at a low power supply voltage LV, as shown in Figure 8. Therefore, the circuit configuration of the sub-bias circuit SB1_R shown in Figure 8 allows for space savings compared to using a bias adjustment circuit (SW1~SW3, Q3~Q5) that operates at a high power supply voltage HV, as shown in Figure 6.

[0114] Thus, each of the sub-bias circuits SB1_R to SB3_R shown in Figure 8 includes the following level conversion circuit and current-voltage conversion circuit.

[0115] In other words, the level conversion circuit (COV2) includes the following adjustment circuit and level conversion section. The adjustment circuit (VCN2) generates a first adjustment current based on the low power supply voltage by mirroring the current using a current mirror ratio based on a bias control signal (PWRC) based on a reference current (e.g., IB_1). The level conversion section includes a transistor (h2) that receives a predetermined clamp voltage (Vclp) at its gate, converts the first adjustment current based on the low power supply voltage to a second adjustment current (I2) based on the high power supply voltage, and outputs it from its drain. The current-voltage conversion circuit (R3~R10, Q6~Q12) generates a voltage corresponding to the magnitude of the second adjustment current as a bias voltage (VBH1~VBH3, VBL1~VBL3).

[0116] [Example 3] Figure 9 is a block diagram showing the configuration of the output amplifier section 133a as a third embodiment.

[0117] Furthermore, the output amplifier section 133a is identical to that shown in Figure 3, except that it employs sub-bias circuits SB1_Ra to SB3_Ra instead of sub-bias circuits SB1_R to SB3_R, and a common bias voltage generation circuit VG has been newly added.

[0118] The common bias voltage generation circuit VG generates bias voltages VBH2, VBH3, VBL2, and VBL3, which have fixed voltage values, as bias voltages other than the bias voltages VBH1 and VBL1 mentioned above, and supplies them to amplifiers APx to APn, respectively.

[0119] In other words, in the output amplifier section 133a, of the bias voltage group supplied to each of the amplifiers APx to APn, only the bias voltages VBH1 and VBL1, which control the tail current of the differential pair directly related to the driving capability, are generated by the sub-bias circuits SB1_Ra to SB3_Ra, respectively.

[0120] Therefore, in each of the sub-bias circuits SB1_Ra to SB3_Ra, it is no longer necessary to generate the bias voltages VBL2, VBL3, VBH2, and VBH3. In other words, in each of the sub-bias circuits SB1_Ra to SB3_Ra, the transistors Q7, Q8, Q11, Q12, R5, R6, R9, and R10 shown in Figure 6 or Figure 8 become unnecessary. Consequently, the output amplifier section 133a allows for area savings compared to the case where the circuits shown in Figure 6 or Figure 8 are used as each sub-bias circuit.

[0121] [Example 4] Figure 10 is a block diagram showing the configuration of the output amplifier section 133b as a fourth embodiment.

[0122] Furthermore, the output amplifier section 133b is identical to that shown in Figure 6, except that the bias control circuit BCCa is used instead of the bias control circuit BCC.

[0123] Figure 11 is a block diagram showing an example of the internal configuration of the bias control circuit BCCa.

[0124] As shown in Figure 11, the bias control circuit BCCa includes a setting register RG1 and a PWRC signal generation circuit PGC, similar to the bias control circuit BCCa shown in Figure 6. Furthermore, the bias control circuit BCCa includes output buffers BF1 to BF3.

[0125] Output buffer BF1 amplifies the bias control signal group PWRC output from the PWRC signal generation circuit PGC and supplies the resulting signal as bias control signal group PWRC1 to the sub-bias circuit SB1_R via wiring group y1. Output buffer BF2 amplifies the same bias control signal group PWRC and supplies the resulting signal as bias control signal group PWRC2 to the sub-bias circuit SB2_R via wiring group y2. Output buffer BF3 amplifies the same bias control signal group PWRC and supplies the resulting signal as bias control signal group PWRC3 to the sub-bias circuit SB3_R via wiring group y3. Note that each of the wiring groups y1 to y3 is composed of independent wiring that is electrically non-contact with each other.

[0126] As a result, as shown in Figure 3, compared to transmitting the bias control signal group PWRC to each of the sub-bias circuits SB1_R to SB3_R via a common wiring group BL0, it is possible to suppress variations in the timing at which the bias control signal group reaches each sub-bias circuit.

[0127] Furthermore, this disclosure is not limited to the embodiments described in Examples 1 to 4 above, and various improvements and design modifications are possible without departing from the spirit of this disclosure.

[0128] [Note] This specification discloses the following configuration:

[0129] (Composition 1) Each of the output amplifier circuits includes: a plurality of amplifiers that receive a predetermined high power supply voltage and an input signal, and generate an output voltage by amplifying the input signal with an operating current generated based on the high power supply voltage; a first to K (K is an integer of 2 or more) sub-bias circuit provided corresponding to each of the first to K amplifier groups (K is an integer of 2 or more) which divide the plurality of amplifiers into predetermined numbers, and which generates a bias voltage for setting the magnitude of the operating current based on the high power supply voltage and supplies the bias voltage to each amplifier belonging to the corresponding first to K amplifier group; and a bias control circuit which generates a bias control signal that indicates the voltage value of the bias voltage at a signal level based on a low power supply voltage lower than the high power supply voltage, and transmits the bias control signal to each of the first to K sub-bias circuits via wiring, wherein each of the first to K sub-bias circuits includes a level conversion circuit that obtains a high-voltage bias control signal by converting the signal level of the bias control signal it receives from a signal level based on the low power supply voltage to a signal level based on the high power supply voltage, and generates the bias voltage having a voltage value based on the high-voltage bias control signal.

[0130] (Configuration 2) The output amplifier circuit according to configuration 1, comprising a common bias voltage generation circuit that generates a common bias voltage with a fixed voltage value and supplies it to each of the plurality of amplifiers, wherein the operating current of each of the plurality of amplifiers is set by the bias voltage and the common bias voltage.

[0131] (Composition 3) The output amplifier circuit according to configuration 1 or 2, wherein the bias control circuit transmits the bias control signal individually to the first to K sub-bias circuits via first to K wirings that are electrically non-contact with each other.

[0132] (Composition 4) The output amplifier circuit according to any one of the above configurations 1 to 3, wherein the plurality of amplifiers, the main bias circuit, the first to K sub-bias circuits, and the bias control circuit are formed on a single semiconductor IC chip, the first to K sub-bias circuits are arranged in a row along one side of the semiconductor IC chip, and the main bias circuit and the bias control circuit are located in the central part of the semiconductor IC chip.

[0133] (Composition 5) A display driver comprising: a gradation voltage generation circuit that generates a plurality of gradation voltages, each having a voltage value corresponding to the brightness level of each pixel based on a video signal; and an output unit that includes an output amplifier circuit as described in any one of the above configurations 1 to 4, and supplies the plurality of output voltages obtained by individually amplifying each of the plurality of gradation voltages as the input signal using the plurality of amplifiers of the output amplifier circuit to a plurality of data lines of the display panel.

[0134] (Composition 6) Each of the following is provided corresponding to each of the first to K (K is an integer of 2 or more) amplifier groups, which divide the plurality of amplifiers into predetermined numbers, and generates a bias voltage for setting the magnitude of the operating current based on the high power supply voltage, and supplies the generated bias voltage to each amplifier belonging to the corresponding first to K amplifier group, and each of the first to K sub-bias circuits, which receive a low power supply voltage lower than the high power supply voltage and set the voltage value of the bias voltage based on the signal level of the low power supply voltage Output amplifier circuit including a bias control circuit that generates a bias control signal and transmits the generated bias control signal to each of the first to K sub-bias circuits via wiring, each of the first to K sub-bias circuits including an adjustment circuit that generates a current of a magnitude obtained by current mirroring the reference current with a current mirror ratio based on the bias control signal as a first adjustment current based on the low power supply voltage, a level conversion section including a transistor that receives a predetermined clamp voltage at its own gate and converts the first adjustment current into a second adjustment current based on the high power supply voltage, and a current-voltage conversion circuit that generates a voltage corresponding to the magnitude of the second adjustment current as the bias voltage.

[0135] (Composition 7) The output amplifier circuit according to configuration 6, which includes a common bias voltage generation circuit that generates a common bias voltage with a fixed voltage value and supplies it to each of the plurality of amplifiers, wherein each of the plurality of amplifiers receives the common bias voltage along with the bias voltage to set the operating current.

[0136] (Composition 8) The output amplifier circuit according to configuration 6 or 7, wherein the bias control circuit transmits the bias control signal individually to the first to K sub-bias circuits via first to K wirings that are electrically non-contact with each other.

[0137] (Composition 9) The output amplifier circuit according to any one of the above configurations 6 to 8, wherein the plurality of amplifiers, the main bias circuit, the first to K sub-bias circuits, and the bias control circuit are formed on a single semiconductor IC chip, the first to K sub-bias circuits are arranged in a row along one side of the semiconductor IC chip, and the main bias circuit and the bias control circuit are located in the central part of the semiconductor IC chip.

[0138] (Composition 10) A display driver comprising: a gradation voltage generation circuit that generates a plurality of gradation voltages, each having a voltage value corresponding to the brightness level of each pixel based on a video signal; and an output unit that includes an output amplifier circuit as described in any one of the above configurations 6 to 9, and supplies the plurality of output voltages obtained by individually amplifying each of the plurality of gradation voltages as the input signal using the plurality of amplifiers of the output amplifier circuit to a plurality of data lines of the display panel. [Explanation of Symbols]

[0139] 13 Data Driver 133 Output Amplifier Section 100 display device APx~APn Amplifier BCC, BCCa bias control circuits COV, COV2 LV / HV conversion circuit IG_1, IG_2 Bias control current generation section MB Main Bias Circuit SB1_R~SB3_R Sub-bias circuit VCN, VCN2 adjustment circuit

Claims

1. Each of the multiple amplifiers receives a predetermined high power supply voltage and an input signal, and generates an output voltage by amplifying the input signal using an operating current generated based on the high power supply voltage. The above-mentioned plurality of amplifiers are divided into groups of a predetermined number, and each of the first to K (K is an integer of 2 or more) amplifier groups is provided corresponding to the first to K sub-bias circuits which generate a bias voltage for setting the magnitude of the operating current based on the high power supply voltage and supply the bias voltage to each amplifier belonging to the corresponding first to K amplifier groups, A bias control circuit is included which generates a bias control signal indicating the voltage value of the bias voltage at a signal level based on a low power supply voltage lower than the high power supply voltage, and transmits the bias control signal to each of the first to K sub-bias circuits via wiring, Each of the above-mentioned sub-bias circuits 1 to K is: An output amplifier circuit includes a level conversion circuit that obtains a high-voltage bias control signal by converting the signal level of the bias control signal it receives from a signal level based on the low power supply voltage to a signal level based on the high power supply voltage, and generates the bias voltage having a voltage value based on the high-voltage bias control signal.

2. It includes a common bias voltage generation circuit that generates a common bias voltage with a fixed voltage value and supplies it to each of the plurality of amplifiers, The output amplifier circuit according to claim 1, wherein each of the plurality of amplifiers has its operating current set by the bias voltage and the common bias voltage.

3. The output amplifier circuit according to claim 1, wherein the bias control circuit transmits the bias control signal individually to the first to K sub-bias circuits via first to K wirings that are electrically non-contact with each other.

4. The plurality of amplifiers, the main bias circuit, the first to K sub-bias circuits, and the bias control circuit are formed on a single semiconductor IC chip. The first to K sub-bias circuits are arranged in a line along one side of the semiconductor IC chip. The output amplifier circuit according to claim 1, wherein the main bias circuit and the bias control circuit are arranged in the central part of the semiconductor IC chip.

5. A gradation voltage generation circuit generates multiple gradation voltages, each having a voltage value corresponding to the brightness level of each pixel based on the video signal. A display driver comprising an output amplifier circuit as described in claim 1, and an output unit that supplies the plurality of output voltages obtained by individually amplifying each of the plurality of gradation voltages as input signals using the plurality of amplifiers of the output amplifier circuit to a plurality of data lines of a display panel.

6. Each of the multiple amplifiers receives a predetermined high power supply voltage and an input signal, and generates an output voltage by amplifying the input signal using an operating current generated based on the high power supply voltage. A main bias circuit that generates a reference current having a predetermined constant current value, The above-mentioned plurality of amplifiers are divided into groups of a predetermined number, and each of the first to K (K is an integer of 2 or more) amplifier groups is provided corresponding to the first to K sub-bias circuits which generate a bias voltage for setting the magnitude of the operating current based on the high power supply voltage and supply the generated bias voltage to each amplifier belonging to the corresponding first to K amplifier groups, A bias control circuit that receives a low power supply voltage lower than the high power supply voltage, generates a bias control signal that indicates the voltage value of the bias voltage at a signal level based on the low power supply voltage, and transmits the generated bias control signal to each of the first to K sub-bias circuits via wiring, Each of the above-mentioned sub-bias circuits 1 to K is: A level conversion circuit having: an adjustment circuit that generates a current of a magnitude obtained by current mirroring based on the reference current using a current mirror ratio based on the bias control signal, as a first adjustment current based on the low power supply voltage; and a level conversion unit including a transistor that receives a predetermined clamp voltage at its own gate and converts the first adjustment current into a second adjustment current based on the high power supply voltage, An output amplifier circuit including a current-voltage conversion circuit that generates a voltage corresponding to the magnitude of the second adjustment current as the bias voltage.

7. It includes a common bias voltage generation circuit that generates a common bias voltage with a fixed voltage value and supplies it to each of the plurality of amplifiers, The output amplifier circuit according to claim 6, wherein each of the plurality of amplifiers receives the common bias voltage along with the bias voltage to set the operating current.

8. The output amplifier circuit according to claim 6, wherein the bias control circuit transmits the bias control signal individually to the first to K sub-bias circuits via first to K wirings that are electrically non-contact with each other.

9. The plurality of amplifiers, the main bias circuit, the first to K sub-bias circuits, and the bias control circuit are formed on a single semiconductor IC chip. The first to K sub-bias circuits are arranged in a line along one side of the semiconductor IC chip. The output amplifier circuit according to claim 6, wherein the main bias circuit and the bias control circuit are located in the central part of the semiconductor IC chip.

10. A gradation voltage generation circuit generates multiple gradation voltages, each having a voltage value corresponding to the brightness level of each pixel based on the video signal. A display driver comprising an output unit which includes an output amplifier circuit as described in claim 6, and supplies the plurality of output voltages obtained by individually amplifying each of the plurality of gradation voltages as input signals using the plurality of amplifiers of the output amplifier circuit to a plurality of data lines of a display panel.

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