Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same that can increase the dielectric breakdown voltage between electrodes provided in a semiconductor layer. [Solution] The semiconductor device comprises a first electrode, a second electrode, a semiconductor layer, a third electrode extending in a first direction within the semiconductor layer and containing silicon, a fourth electrode extending in a first direction within the semiconductor layer and having a first side facing the side of the third electrode in a second direction and a second side located on the opposite side of the first side in a second direction, an insulating film provided between the second side of the fourth electrode and the semiconductor layer, and a nitride film in contact with the side of the third electrode. The nitride film is located at least in the portion of the side of the third electrode facing the corner between the first side and the bottom surface of the fourth electrode.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device in which a gate electrode and a field plate electrode are provided in the same trench formed in a semiconductor layer is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device and a method for manufacturing the same that can increase the breakdown voltage between electrodes provided in a semiconductor layer.

Means for Solving the Problems

[0005] According to the embodiment, the semiconductor device comprises a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode in a first direction, a third electrode extending in the first direction within the semiconductor layer and containing silicon, a fourth electrode extending in the first direction within the semiconductor layer and having a first surface facing the side surface of the third electrode in a second direction perpendicular to the first direction, and a second surface located on the opposite side of the first surface in the second direction, an insulating film provided between the second surface of the fourth electrode and the semiconductor layer, and a nitride film in contact with the side surface of the third electrode, wherein the nitride film is located at least in the portion of the side surface of the third electrode facing the corner between the first surface and the bottom surface of the fourth electrode. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic plan view of a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view of a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view of a semiconductor device according to the second embodiment. [Figure 4] This is a schematic cross-sectional view of a semiconductor device according to the third embodiment. [Figure 5] This is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 6] This is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 7] This is a schematic cross-sectional view of a semiconductor device according to the sixth embodiment. [Figure 8] This is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment. [Figure 9] This is a schematic plan view of a semiconductor device according to the eighth embodiment. [Figure 10] This is a schematic cross-sectional view of a semiconductor device according to the eighth embodiment. [Figure 11] (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12](a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 13] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 14] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 15] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 16] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 17] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 18] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the seventh embodiment. [Figure 19] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the seventh embodiment. [Figure 20] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the seventh embodiment. [Figure 21] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to the seventh embodiment. [Figure 22] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to a modified example of the seventh embodiment. [Figure 23] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a modified example of the seventh embodiment. [Figure 24] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the eighth embodiment. [Figure 25] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the eighth embodiment. [Figure 26] (a) and (b) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the eighth embodiment. [Figure 27]It is a schematic cross-sectional view of a semiconductor device according to a comparative example.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals.

[0008] [First Embodiment] FIG. 1 is a schematic plan view showing the arrangement relationship of the main components in the semiconductor device 1 according to the first embodiment. The cross-section shown in FIG. 2 corresponds to the A-A cross-section in FIG. 1.

[0009] In each drawing, the direction along the Z-axis is the first direction Z, the direction along the X-axis is the second direction X, and the direction along the Y-axis is the third direction Y. The first direction Z, the second direction X, and the third direction Y are perpendicular to each other. For example, the arrow direction of the Z-axis is relatively upward.

[0010] As shown in FIG. 2, the semiconductor device 1 according to the first embodiment includes a first electrode 21, a second electrode 22, and a semiconductor layer 10. The first electrode 21 and the second electrode 22 are located apart from each other in the first direction Z.

[0011] The semiconductor layer 10 is located between the first electrode 21 and the second electrode 22 in the first direction Z. As the material of the semiconductor layer 10, for example, silicon can be used. Alternatively, as the material of the semiconductor layer 10, for example, silicon carbide, gallium nitride, etc. may be used. In this embodiment, the first conductivity type in the semiconductor layer 10 is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0012] The semiconductor layer 10 comprises an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than that of the first semiconductor layer 11. The semiconductor layer 10 also comprises a fourth semiconductor layer 14 provided between the first electrode 21 and the first semiconductor layer 11, and a p-type fifth semiconductor layer 15 provided on the second semiconductor layer 12. The p-type impurity concentration of the fifth semiconductor layer 15 is higher than that of the second semiconductor layer 12.

[0013] The semiconductor device 1 has, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. In the MOSFET, the first electrode 21 is the drain electrode, the second electrode 22 is the source electrode, the first semiconductor layer 11 is the drift layer, the second semiconductor layer 12 is the base layer, the third semiconductor layer 13 is the source layer, and the fourth semiconductor layer 14 functions as an n-type drain layer with a higher n-type impurity concentration than the first semiconductor layer 11.

[0014] Alternatively, the semiconductor device 1 may have a vertical IGBT (Insulated Gate Bipolar Transistor) structure. In the IGBT, the first electrode 21 functions as a collector electrode, the second electrode 22 as an emitter electrode, the first semiconductor layer 11 as a drift layer, the second semiconductor layer 12 as a base layer, the third semiconductor layer 13 as an emitter layer, and the fourth semiconductor layer 14 as a p-type collector layer. In the IGBT, an n-type buffer layer with a higher n-type impurity concentration than the first semiconductor layer 11 may be provided between the fourth semiconductor layer 14 (collector layer) and the first semiconductor layer 11 (drift layer).

[0015] The first electrode 21 is in contact with the fourth semiconductor layer 14 and is electrically connected to the fourth semiconductor layer 14.

[0016] The second electrode 22 is in contact with the third semiconductor layer 13 and is electrically connected to the third semiconductor layer 13. Furthermore, the second electrode 22 is in contact with the fifth semiconductor layer 15 and is electrically connected to the fifth semiconductor layer 15.

[0017] The semiconductor device 1 further comprises a field plate electrode 40 as a third electrode and a gate electrode 30 as a fourth electrode. The gate electrode 30 and the field plate electrode 40 extend in a first direction Z within the semiconductor layer 10 from the upper surface located on the second electrode 22 side of the semiconductor layer 10. The gate electrode 30 and the field plate electrode 40 are located within the same trench T formed in the semiconductor layer 10. For example, two gate electrodes 30 and one field plate electrode 40 are located within one trench T. Within one trench T, the field plate electrode 40 is located between two gate electrodes 30 that are spaced apart in a second direction X.

[0018] The lower end of the field plate electrode 40 is located on the first electrode 21 side, below the lower end of the gate electrode 30. The shortest distance in the first direction Z between the lower end of the field plate electrode 40 and the first electrode 21 is shorter than the shortest distance in the first direction Z between the lower end of the gate electrode 30 and the first electrode 21. The lower end of the gate electrode 30 is located below the pn junction between the second semiconductor layer 12 and the first semiconductor layer 11. The lower end of the field plate electrode 40 does not reach the fourth semiconductor layer 14.

[0019] The gate electrode 30 has a first side surface 30A that faces the side surface 40A of the field plate electrode 40 in the second direction X, and a second side surface 30B that is located on the opposite side of the first side surface 30A in the second direction X. A single field plate electrode 40 has two side surfaces 40A that are located opposite each other in the second direction X.

[0020] As shown in Figure 1, the gate electrode 30 and field plate electrode 40 extend in the third direction Y. The configuration shown in Figure 2 is repeated in the second direction X. Multiple gate electrode 30s and multiple field plate electrodes 40s extending in the third direction Y are arranged in a stripe pattern.

[0021] The gate electrode 30 and the field plate electrode 40 are conductive. The gate electrode 30 and the field plate electrode 40 contain silicon. The gate electrode 30 and the field plate electrode 40 are, for example, polycrystalline silicon layers.

[0022] The semiconductor device 1 further comprises a gate insulating film 70. The gate insulating film 70 is provided between the second side surface 30B of the gate electrode 30 and the semiconductor layer 10. The second side surface 30B of the gate electrode 30 faces the second semiconductor layer 12 via the gate insulating film 70. In this embodiment, the gate insulating film 70 is, for example, a silicon oxide film.

[0023] The semiconductor device 1 further comprises a first insulating film 51. The first insulating film 51 is provided between the side surface 40A of the field plate electrode 40 and the semiconductor layer 10, and between the lower end of the field plate electrode 40 and the semiconductor layer 10. The first insulating film 51 is, for example, a silicon oxide film.

[0024] The semiconductor device 1 further comprises a nitride film 60. The nitride film 60 is provided on the side surface 40A of the field plate electrode 40. The nitride film 60 is in direct contact with the side surface 40A of the field plate electrode 40. In this embodiment, the nitride film 60 is provided on the side surface 40A of the field plate electrode 40 in the portion facing the first side surface 30A of the gate electrode 30 in the second direction X. The nitride film 60 extends further downward from the portion facing the first side surface 30A of the gate electrode 30 in the second direction X. The lower end of the nitride film 60 provided on the side surface 40A of the field plate electrode 40 is located below the corner 30C between the first side surface 30A and the bottom surface of the gate electrode 30. The nitride film 60 is also provided in contact with the upper surface of the field plate electrode 40. The nitride film 60 is a silicon nitride film (SiN) or a silicon oxynitride film (SiON).

[0025] The semiconductor device 1 further comprises a second insulating film 52. The second insulating film 52 is provided between the first side surface 30A of the gate electrode 30 and the nitride film 60 provided on the side surface 40A of the field plate electrode 40. The second insulating film 52 is in contact with the first side surface 30A of the gate electrode 30. The second insulating film 52 is, for example, a silicon oxide film.

[0026] The semiconductor device 1 further comprises a third insulating film 53. The third insulating film 53 is provided between the upper surface of the gate electrode 30 and the second electrode 22, and between the field plate electrode 40 and the second electrode 22. The third insulating film 53 is, for example, a silicon oxide film.

[0027] When a first potential (e.g., a positive potential) is applied to the first electrode 21, a second potential (e.g., a ground potential) lower than the first potential is applied to the second electrode 22, and a gate voltage above a threshold is applied to the gate electrode 30, an n-type channel is formed in the region of the second semiconductor layer 12 facing the second side surface 30B of the gate electrode 30. Current flows between the first electrode 21 and the second electrode 22 through the fourth semiconductor layer 14, the first semiconductor layer 11, the channel, and the third semiconductor layer 13, and the semiconductor device 1 is turned on.

[0028] In the off state of the semiconductor device 1, when the application of a voltage above a threshold to the gate electrode 30 is stopped, a depletion layer expands from the pn junction between the second semiconductor layer 12 and the first semiconductor layer 11, and from the boundary between the first insulating film 51 and the first semiconductor layer 11, thereby maintaining the breakdown voltage of the semiconductor device 1.

[0029] The field plate electrode 40 is electrically connected to the second electrode 22. In the off state, the field plate electrode 40 smooths the electric field distribution of the first semiconductor layer 11 (drift layer), improving the breakdown voltage of the semiconductor device 1.

[0030] Now, with reference to Figure 27, a semiconductor device 100 related to a comparative example will be described.

[0031] A configuration in which a field plate electrode 40 and a gate electrode 30 are provided within the same trench T can be formed as shown below.

[0032] After forming a trench T in the semiconductor layer 10, a field plate electrode 40 is embedded in the trench T via a first insulating film 51. After forming the field plate electrode 40, the upper part of the first insulating film 51 is removed. The side walls of the upper region of the trench T formed by removing the upper part of the first insulating film 51 are thermally oxidized to form a second insulating film 52 and a gate insulating film 70. After this, a gate electrode 30 is embedded in the upper region of the trench T.

[0033] In the process of thermally oxidizing the sidewall of the upper region of the trench T described above, the exposed upper part of the side surface 40A of the field plate electrode 40, which is a silicon layer, is accelerated thermal oxidation, and the width of the upper part of the field plate electrode 40 (width in the second direction X) becomes smaller. As shown in Figure 27, a convex portion is formed on the upper part of the field plate electrode 40. A protrusion 40C is easily formed on the surface of the convex portion formed by this accelerated thermal oxidation. The electric field tends to concentrate at the corner 30C of the gate electrode 30 and the protrusion 40C of the field plate electrode 40. If the protrusion 40C is near the corner 30C of the gate electrode 30, the electric field strength between the corner 30C of the gate electrode 30 and the protrusion 40C of the field plate electrode 40 increases, causing dielectric breakdown of the insulating film between the corner 30C and the protrusion 40C. As a result, leakage current is easily generated between the gate electrode 30 and the field plate electrode 40.

[0034] According to this embodiment, by forming a nitride film 60 on the upper part of the side surface 40A of the field plate electrode 40, the upper part of the side surface 40A of the field plate electrode 40 can be protected from thermal oxidation. As a result, no protrusions are formed on the side surface 40A of the field plate electrode 40 that face the corner 30C of the gate electrode 30, and the dielectric breakdown voltage between the gate electrode 30 and the field plate electrode 40 can be increased. As a result, the leakage current between the gate electrode 30 and the field plate electrode 40 can be reduced.

[0035] The nitride film 60 is located at least on the side surface 40A of the field plate electrode 40, in the portion facing the corner 30C between the first side surface 30A and the bottom surface of the gate electrode 30. The nitride film 60 itself functions as an insulating film that increases the dielectric breakdown electric field strength between the corner 30C of the gate electrode 30 and the side surface 40A of the field plate electrode 40. In particular, it is preferable to use a silicon oxynitride film as the nitride film 60. The silicon oxynitride film has a higher dielectric breakdown electric field strength than the silicon oxide film and the silicon nitride film.

[0036] Furthermore, in the semiconductor device 100 according to the comparative example, the thermal oxide film expands in volume laterally (second direction X) above the field plate electrode 40, increasing the surface stress of the wafer and making it prone to wafer warping. In contrast, according to this embodiment, the lateral volume expansion of the oxide film above the field plate electrode 40 can be suppressed, thereby reducing wafer warping.

[0037] Other embodiments will be described below. The other embodiments will primarily be described in terms of their configurations that differ from the first embodiment described above.

[0038] [Second Embodiment] According to the semiconductor device 2 of the second embodiment shown in Figure 3, the nitride film 60 is provided in contact with the entire surface of the side surface 40A of the field plate electrode 40. This reduces the leakage current between the gate electrode 30 and the field plate electrode 40. In this case as well, it is preferable to use a silicon oxynitride film as the nitride film 60.

[0039] Furthermore, according to the second embodiment, the nitride film 60 is also provided in contact with the upper and lower surfaces of the field plate electrode 40.

[0040] [Third Embodiment] According to the semiconductor device 3 of the third embodiment shown in Figure 4, a silicon oxynitride film is provided as the nitride film 60 in the entire region between the first side surface 30A of the gate electrode 30 and the side surface 40A of the field plate electrode 40. The silicon oxynitride film, as the nitride film 60, is in contact with the first side surface 30A of the gate electrode 30 and the side surface 40A of the field plate electrode 40. No silicon oxide film or silicon nitride film is provided between the first side surface 30A of the gate electrode 30 and the side surface 40A of the field plate electrode 40. As a result, the leakage current between the gate electrode 30 and the field plate electrode 40 can be reduced compared to when a silicon oxide film is interposed between the first side surface 30A of the gate electrode 30 and the side surface 40A of the field plate electrode 40.

[0041] The silicon oxynitride film, as the nitride film 60, extends further downward in the second direction X than the portion facing the first side surface 30A of the gate electrode 30. The nitride film 60 is also provided in contact with the upper surface of the field plate electrode 40.

[0042] [Fourth Embodiment] According to the semiconductor device 4 of the fourth embodiment shown in Figure 5, similar to the third embodiment, a silicon oxynitride film is provided as the nitride film 60 in the entire region between the first side surface 30A of the gate electrode 30 and the side surface 40A of the field plate electrode 40. In addition, the nitride film 60 is also provided in contact with the upper surface of the field plate electrode 40.

[0043] Furthermore, according to the fourth embodiment, the gate insulating film 70 is a silicon oxynitride film. When an electric field is applied for a long time, the interatomic bonds of the silicon oxynitride film are less likely to break than those of silicon oxide and silicon nitride films, making it less susceptible to damage during the operation of the semiconductor device. Therefore, by using a silicon oxynitride film as the gate insulating film 70, the interface state between the channel and the gate insulating film 70 is stabilized, threshold fluctuations can be suppressed, and reliability can be improved.

[0044] [Fifth Embodiment] As shown in Figure 6, for semiconductor device 5 according to the fifth embodiment, even if the upper part of the field plate electrode 40 becomes convex due to thermal oxidation, the leakage current between the corner 30C of the gate electrode 30 and the field plate electrode 40 can be reduced by providing the nitride film 60 only on the side surface 40A of the field plate electrode 40 that faces the corner 30C between the first side surface 30A of the gate electrode 30 and the bottom surface. In this case, the breakdown voltage can be improved while suppressing an increase in capacitance between the gate electrode 30 and the field plate electrode 40.

[0045] [Sixth Embodiment] Figure 7 is a schematic plan view showing the arrangement of the main components of the semiconductor device 6 according to the sixth embodiment. The cross-section shown in Figure 8 corresponds to the BB cross-section in Figure 7.

[0046] According to the sixth embodiment, a plurality of columnar field plate electrodes 40 are arranged within the semiconductor layer 10. The gate electrode 30 surrounds the side surface 40A of the field plate electrode 40. A nitride film 60 is provided between the first side surface 30A, which is the inner circumferential surface of the gate electrode 30, and the side surface 40A of the field plate electrode 40, in contact with the first side surface 30A and the side surface 40A of the field plate electrode 40. The semiconductor layer 10 surrounds the second side surface 30B, which is the inner circumferential surface of the gate electrode 30, via the gate insulating film 70.

[0047] The field plate electrode 40 is electrically connected to the second electrode 22 via a field contact portion 91 provided between the upper part of the field plate electrode 40 and the second electrode 22. The gate electrode 30 is electrically connected to gate wiring (not shown) via a gate contact portion 92 connected to the upper part of the gate electrode 30.

[0048] [Seventh Embodiment] According to the semiconductor device 7 of the seventh embodiment shown in Figure 9, the gate electrode 30 is provided above the field plate electrode 40 within the semiconductor layer 10 and extends in the third direction Y. One field plate electrode 40 and one gate electrode 30 are arranged in one trench T. The second side surface 30B of the gate electrode 30 faces the second semiconductor layer 12 via the gate insulating film 70. The width of the gate electrode 30 in the second direction X is greater than the width of the field plate electrode 40 in the second direction X.

[0049] Furthermore, a nitride film 60 is provided in contact with the upper surface 40B of the field plate electrode 40. According to the seventh embodiment, the nitride film 60 is in contact with the bottom surface of the gate electrode 30. The nitride film 60 is provided in the entire region between the bottom surface of the gate electrode 30 and the upper surface 40B of the field plate electrode 40.

[0050] According to this embodiment, by providing a nitride film 60 in contact with the upper surface 40B of the field plate electrode 40, it is possible to prevent the formation of narrow protrusions on the upper surface of the field plate electrode 40 due to thermal oxidation. As a result, the distance between the corner 30D of the gate electrode 30 (the corner between the second side surface 30B of the gate electrode 30 and the bottom surface) and the corner 40D of the field plate electrode 40 (the corner between the side surface 40A of the field plate electrode 40 and the top surface) can be increased compared to the comparative example shown in Figure 27. As a result, the leakage current between the gate electrode 30 and the field plate electrode 40 can be reduced.

[0051] Furthermore, the gate electrode 30 may be separated in a second direction X within a single trench T, as shown in Figure 10.

[0052] [Eighth Embodiment] The semiconductor device 8 according to the eighth embodiment shown in Figure 10 further comprises a silicate glass film 80 provided on the nitride film 60. The silicate glass film 80 is, for example, a BPSG (boro-phospho silicate glass) film containing boron and phosphorus.

[0053] A fourth insulating film 54 is provided between the two gate electrodes 30 above the silicate glass film 80. The fourth insulating film 54 is, for example, a silicon oxide film.

[0054] In the embodiment shown in Figure 9, a silicate glass film 80 may be provided between the lower surface of the gate electrode 30 and the nitride film 60.

[0055] The embodiments described above can be combined in any way, within the limits of what is not technically contradictory.

[0056] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to Figures 11(a) to 14(b).

[0057] As shown in Figure 11(a), trenches T are formed in the semiconductor layer 10. For example, trenches T can be formed by the RIE (Reactive Ion Etching) method using a mask.

[0058] After forming the trench T, a field plate electrode 40 is formed in the trench T via a first insulating film 51, as shown in Figure 11(b). The first insulating film 51 is formed, for example, by a silicon oxide film using CVD (Chemical Vapor Deposition) or thermal oxidation. After forming the first insulating film 51, a polycrystalline silicon layer is formed inside the first insulating film 51 in the trench T as the field plate electrode 40, for example, by CVD. After forming the field plate electrode 40 in the trench T, a silicon oxide film 150 is formed on the upper surface of the semiconductor layer 10, the upper surface of the field plate electrode 40, and the upper surface of the first insulating film 51.

[0059] After forming the silicon oxide film 150, a resist 201 is formed on the silicon oxide film 150 as shown in Figure 12(a). Then, using the resist 201 as a mask, the portion of the first insulating film 51 adjacent to the upper side surface 40A of the field plate electrode 40 is removed by the RIE method, and a void g is formed in the region adjacent to the upper side surface 40A of the field plate electrode 40.

[0060] After forming the void g, the resist 201 and silicon oxide film 150 are removed. Then, as shown in Figure 12(b), a nitride film 60 is formed in the void g. The nitride film 60 is in contact with the upper side surface 40A of the field plate electrode 40. The nitride film 60 is also formed on the upper surface of the semiconductor layer 10, the upper surface of the field plate electrode 40, and the upper surface of the first insulating film 51. The nitride film 60 can be formed, for example, by the CVD method.

[0061] After forming the nitride film 60, the nitride film 60 on the upper surface of the semiconductor layer 10 and the upper surface of the first insulating film 51 is removed. As a result, the upper surface of the semiconductor layer 10 and the upper surface of the first insulating film 51 are exposed, as shown in Figure 13(a). The nitride film 60 on the upper surface of the field plate electrode 40 remains. For example, the nitride film 60 on the upper surface of the semiconductor layer 10 and the upper surface of the first insulating film 51 can be removed by a CDE (Chemical or Conformal Dry Etching) method using a resist formed on the upper surface of the field plate electrode 40 as a mask.

[0062] Through the process described above, a nitride film 60 (first nitride film 60A) is formed on at least the upper side surface 40A of the field plate electrode 40.

[0063] After forming the nitride film 60, the upper part of the first insulating film 51 is removed, and an upper region T1, which is a void, is formed in the trench T, as shown in Figure 13(b). For example, the upper part of the first insulating film 51 can be removed by the RIE method or the CDE method. In the upper region T1, the nitride film 60 provided on the side surface 40A of the field plate electrode 40 is exposed.

[0064] After forming the upper region T1, a silicon oxide film 151 is formed on the sidewall of the upper region T1 and the upper surface of the first insulating film 51, as shown in Figure 14(a). For example, the silicon oxide film 151 can be formed by thermal oxidation or CVD. In the step of forming the silicon oxide film 151 in the upper region T1 of the trench T, a nitride film 60 is provided on the upper side surface 40A of the field plate electrode 40. Therefore, the upper part of the field plate electrode 40 is not subjected to accelerated thermal oxidation, and no protrusions like those in the comparative example shown in Figure 27 are formed on the upper side surface 40A of the field plate electrode 40.

[0065] After forming the silicon oxide film 151, a gate electrode 30 is formed in the upper region T1 adjacent to the nitride film 60 within the trench T, as shown in Figure 14(b). For example, a polycrystalline silicon layer can be formed as the gate electrode 30 by CVD. The silicon oxide film 151 located between the gate electrode 30 and the nitride film 60 becomes the second insulating film 52 described above. The silicon oxide film 151 located between the gate electrode 30 and the semiconductor layer 10 becomes the gate insulating film 70 described above.

[0066] After forming the gate electrode 30, for example, a second semiconductor layer 12, a third semiconductor layer 13, and a fifth semiconductor layer 15 are formed on the semiconductor layer 10 by ion implantation. Furthermore, the process of forming a third insulating film 53 and a second electrode 22 is carried out.

[0067] Before forming the gate electrode 30, in the step of forming a silicon oxide film 151 on the side wall of the upper region T1 of the trench T, a second nitride film may be formed instead of the silicon oxide film 151. This makes it possible to obtain the semiconductor device 4 according to the fourth embodiment shown in Figure 5.

[0068] Next, a method for manufacturing the semiconductor device 2 according to the second embodiment will be described with reference to Figures 15(a) to 17(b).

[0069] As shown in Figure 15(a), a trench T is formed within the semiconductor layer 10, and a first insulating film 51 is formed within the trench T. Subsequently, a nitride film 60 is formed inside the first insulating film 51 within the trench T. The nitride film 60 is also deposited above the upper surface of the semiconductor layer 10 and above the trench T.

[0070] After forming the nitride film 60, a field plate electrode 40 is formed inside the nitride film 60 within the trench T, as shown in Figure 15(b). The field plate electrode 40 is embedded in the trench T and is also deposited on the nitride film 60 above the upper surface of the semiconductor layer 10 and above the trench T.

[0071] After forming the field plate electrode 40, the field plate electrode 40 deposited above the upper surface of the semiconductor layer 10 and above the trench T is removed, for example, by etching. As a result, as shown in Figure 16(a), the nitride film 60 located above the upper surface of the semiconductor layer 10 and above the trench T is exposed. In addition, the upper surface 40B of the field plate electrode 40 in the trench T is exposed.

[0072] As shown in Figure 16(b), an additional nitride film 60 is formed on the nitride film 60 located above the upper surface of the semiconductor layer 10 and above the trench T, and on the upper surface 40B of the field plate electrode 40.

[0073] The nitride film 60 on the upper surface of the semiconductor layer 10 and the upper surface of the first insulating film 51 is removed, for example, by etching. As shown in Figure 17(a), the nitride film 60 on the upper surface 40B of the field plate electrode 40 remains. This results in a structure in which the side surface 40A, the upper surface 40B, and the lower surface of the field plate electrode 40 are covered with nitride film 60.

[0074] Next, the upper part of the first insulating film 51 is removed, and the upper region T1 is formed in the trench T, as shown in Figure 17(b). Thereafter, the same process as in the first embodiment is continued.

[0075] Next, a method for manufacturing the semiconductor device 7 according to the seventh embodiment will be described with reference to Figures 18(a) to 21.

[0076] As shown in Figure 18(a), a field plate electrode 40 is embedded in a trench T formed in the semiconductor layer 10 via a first insulating film 51, and then the upper part of the field plate electrode 40 is removed by etching.

[0077] As shown in Figure 18(b), a nitride film 60 is formed in the region above the field plate electrode 40 within the trench T. The nitride film 60 is formed on the upper surface 40B of the field plate electrode 40, the side walls and upper surface of the first insulating film 51.

[0078] As shown in Figure 19(a), a mask 202 is formed on the nitride film 60 provided on the upper surface 40B of the field plate electrode 40 in the trench T. The mask 202 can be formed, for example, by embedding a silicon oxide film inside the nitride film 60 in the trench T, and then recessing the silicon oxide film by etching.

[0079] The nitride film 60 is etched using a silicon oxide mask 202. As a result, as shown in Figure 19(b), the nitride film 60 formed on the upper surface and side walls of the first insulating film 51 is removed, leaving the nitride film 60 on the upper surface 40B of the field plate electrode 40.

[0080] Next, the first insulating film 51 on the semiconductor layer 10 and the first insulating film 51 formed on the upper side surface of the trench T are removed by etching. At this time, the mask 202 is also removed. As a result, as shown in Figure 20(a), an upper region T2 is formed above the nitride film 60 and the first insulating film 51 in the trench T, which is a space for positioning the gate electrode.

[0081] As shown in Figure 20(b), a gate insulating film 70 is formed on the side surface of the semiconductor layer 10 exposed in the upper region T2. ​​For example, the gate insulating film 70 is formed by thermal oxidation. At this time, since a nitride film 60 is provided on the upper surface of the field plate electrode 40, the upper part of the field plate electrode 40 is not oxidized and does not become convex.

[0082] After forming the gate insulating film 70, a gate electrode 30 is formed in the upper region T2, as shown in Figure 21.

[0083] As shown in Figure 22(a), after forming the first insulating film 51 in the trench T, and before forming the field plate electrode 40, a nitride film 60 may be formed on the bottom surface and side walls of the first insulating film 51 in the trench T.

[0084] Subsequently, as shown in Figure 22(b), the field plate electrode 40 is embedded inside the nitride film 60 within the trench T, and the upper part of the field plate electrode 40 is recessed.

[0085] As shown in Figure 23, an additional nitride film 60 is formed on the upper surface 40B of the field plate electrode 40. Subsequently, the same process as in Figures 19(a) to 21 is continued.

[0086] Next, a method for manufacturing the semiconductor device 8 according to the eighth embodiment will be described with reference to Figures 24(a) to 26(b).

[0087] After the process shown in Figure 19(b) above, the mask 202 is removed. This state is shown in Figure 24(a).

[0088] A silicate glass film 80 is embedded in the region on the nitride film 60 within the trench T, as shown in Figure 24(b).

[0089] The upper part of the silicate glass film 80 and the upper part of the first insulating film 51 are removed by etching to form an upper region T2 above the silicate glass film 80 and above the first insulating film 51 in the trench T, as shown in Figure 25(a), which is a space for arranging the gate electrode.

[0090] A gate insulating film 70 is formed on the side surface of the semiconductor layer 10 exposed in the upper region T2, as shown in Figure 25(b). After forming the gate insulating film 70, a gate electrode 30 is formed in the upper region T2, as shown in Figure 26(a).

[0091] After this, the gate electrode 30 on the silicate glass film 80 may be removed, for example, by the RIE method, thereby separating the gate electrode 30 in the second direction X, as shown in Figure 26(b).

[0092] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0093] 1-8…Semiconductor device, 10…Semiconductor layer, 11…First semiconductor layer, 12…Second semiconductor layer, 13…Third semiconductor layer, 14…Fourth semiconductor layer, 15…Fifth semiconductor layer, 21…First electrode, 22…Second electrode, 30…Gate electrode (Fourth electrode), 30A…First side, 30B…Second side, 30C…Corner, 40…Field plate electrode (Third electrode), 40A…Side of field plate electrode, 51…First insulating film, 52…Second insulating film, 53…Third insulating film, 54…Fourth insulating film, 60…Nitride film, 70…Gate insulating film, 80…Silicate glass film, T…Trench

Claims

1. First electrode and, The second electrode and A semiconductor layer provided between the first electrode and the second electrode in the first direction, A third electrode, which extends in the first direction within the semiconductor layer and contains silicon, A fourth electrode extending in the first direction within the semiconductor layer, having a first surface facing the surface of the third electrode in a second direction perpendicular to the first direction, and a second surface located on the opposite side of the first surface in the second direction, An insulating film is provided between the second side surface of the fourth electrode and the semiconductor layer, A nitride film in contact with the side surface of the third electrode, Equipped with, The nitride film is located at least on the side surface of the third electrode, in a portion facing the corner between the first side surface and the bottom surface of the fourth electrode, in a semiconductor device.

2. The semiconductor device according to claim 1, wherein the nitride film is a silicon nitride film or a silicon oxynitride film.

3. The semiconductor device according to claim 1, wherein the silicon oxynitride film is provided as the nitride film on the entire region between the first side surface of the fourth electrode and the side surface of the third electrode.

4. The semiconductor device according to any one of claims 1 to 3, wherein the nitride film is provided on the entire surface of the side surface of the third electrode.

5. The semiconductor device according to any one of claims 1 to 3, wherein the insulating film is a silicon oxynitride film.

6. First electrode and, The second electrode and A semiconductor layer provided between the first electrode and the second electrode in the first direction, A third electrode, which extends in the first direction within the semiconductor layer and contains silicon, A fourth electrode provided above the third electrode within the semiconductor layer, A nitride film provided in contact with the upper surface of the third electrode, A semiconductor device equipped with the following features.

7. The semiconductor device according to claim 6, further comprising a silicate glass film provided on the nitride film.

8. The semiconductor device according to claim 7, wherein the silicate glass film comprises boron and phosphorus.

9. The semiconductor device according to claim 1 or 6, wherein the third electrode is connected to the second electrode.

10. A process of forming trenches in a semiconductor layer, The process involves forming an electrode containing silicon in the trench via a first insulating film, The process involves forming a first nitride film on at least the upper side surface of the electrode, The steps include forming a gate electrode in the upper region adjacent to the first nitride film within the trench, A method for manufacturing a semiconductor device, comprising:

11. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a second nitride film on the side wall of the upper region in the trench before forming the gate electrode.

12. A process of forming trenches in a semiconductor layer, The process involves forming an electrode containing silicon in the trench via a first insulating film, The step of forming a nitride film on the upper surface of the electrode, A step of forming a gate electrode in the upper region above the nitride film and above the first insulating film within the trench, A method for manufacturing a semiconductor device, comprising:

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