Multilayer ceramic capacitor and method for manufacturing the same

Abstract

This invention provides a highly reliable multilayer ceramic capacitor and a method for manufacturing the same. [Solution] A multilayer ceramic capacitor according to one embodiment includes a capacitor body comprising a plurality of dielectric layers and a plurality of internal electrode layers laminated with the dielectric layers in between; and an external electrode disposed on the outside of the capacitor body, wherein the internal electrode layers include an internal region and an interface region disposed on at least one surface of the internal region in the lamination direction and including an interface with the dielectric layer, the internal region and the interface region contain germanium (Ge), and the average germanium (Ge) content in the interface region is even higher than the average germanium (Ge) content in the internal region.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same.

Background Art

[0002] Examples of electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors, or thermistors. Among such ceramic electronic components, a multilayer ceramic capacitor (MLCC) can be used in various electronic devices due to its advantages of being small in size, having a high capacitance, and being easy to mount.

[0003] For example, a multilayer ceramic capacitor (MLCC) can be used as a chip-shaped capacitor mounted on the substrate of various electronic products such as video equipment like a liquid crystal display (LCD), a plasma display panel (PDP), an organic light-emitting diode (OLED), a computer, a personal mobile terminal, and a smartphone, to charge or discharge electricity.

[0004] Recently, with the development of electronic devices and autonomous vehicles, miniaturization and large capacitance of multilayer ceramic capacitors have been highly demanded. In order to achieve a higher capacitance in the same volume, thinning of the dielectric layer and the internal electrode layer is essential. However, thinning of the dielectric layer and the internal electrode layer increases the electric field strength per unit area, leading to reliability degradation.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment provides a multilayer ceramic capacitor with excellent reliability.

[0006] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor. [Means for solving the problem]

[0007] One embodiment provides a multilayer ceramic capacitor comprising a capacitor body including a plurality of dielectric layers and a plurality of internal electrode layers stacked with the dielectric layers in between; and an external electrode disposed on the outside of the capacitor body, wherein the internal electrode layers include an internal region and an interface region disposed on at least one surface of the internal region in the stacking direction and including an interface with the dielectric layer, the internal region and the interface region contain germanium (Ge), and the average germanium (Ge) content in the interface region is even higher than the average germanium (Ge) content in the internal region.

[0008] The average molar ratio of germanium (Ge) in the interface region to the internal region may be greater than 1 and less than or equal to 5.

[0009] The interface region is a region having a depth of 2 nm from the interface between the internal electrode layer and the dielectric layer into the interior of the internal electrode layer.

[0010] When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer, the interface region can have the maximum molar percentage of germanium (Ge).

[0011] The interface region may further contain germanium oxide (GeO2).

[0012] The internal region and the interface region may further contain nickel (Ni).

[0013] When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer to one point in the internal electrode layer adjacent to the dielectric layer, the internal region can have the maximum molar percentage of nickel (Ni).

[0014] When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer to one point in the internal electrode layer adjacent to the dielectric layer, the interface region is the area from the point where the maximum molar percentage of nickel (Ni) is 1 / 3 to a distance of 2 nm inside the internal electrode layer.

[0015] The average germanium (Ge) content in the interface region may be 0.4 to 12 moles per 100 moles of nickel (Ni) in the interface region.

[0016] The interface region may further include one or more materials selected from titanium (Ti) and barium (Ba).

[0017] The average germanium (Ge) content in the aforementioned internal region may be 0.2 to 10 moles per 100 moles of nickel (Ni) in the aforementioned internal region.

[0018] The interface region may have a thickness of 0.05% to 3% of the total thickness of the internal electrode layer.

[0019] The dielectric layer may include barium (Ba), titanium (Ti), and germanium (Ge).

[0020] The average thickness of the internal electrode layer may be 0.1 μm to 2 μm.

[0021] The average thickness of the dielectric layer may be 0.2 μm to 10 μm.

[0022] Another embodiment includes the steps of mixing nickel (Ni) and germanium (Ge)-based raw materials to produce a conductive paste; manufacturing a dielectric green sheet using a dielectric slurry, and printing the conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets with the conductive paste layer formed thereon to produce a dielectric green sheet laminate; firing the dielectric green sheet laminate to produce a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on the outside of the capacitor body. The internal electrode layer includes an internal region and an interface region disposed on at least one surface of the internal region in the lamination direction and including an interface with the dielectric layer. The internal region and the interface region contain germanium (Ge), and the average content of germanium (Ge) in the interface region is higher than the average content of germanium (Ge) in the internal region. A method for manufacturing a multilayer ceramic capacitor is provided.

[0023] The germanium (Ge)-based raw material may include one or more selected from germanium (Ge), germanium oxide (GeO2), and Ni-Ge alloy.

[0024] The germanium (Ge)-based raw material may be mixed in an amount of 0.3 to 10 parts by mole with respect to 100 parts by mole of the nickel (Ni).

[0025] The firing may be carried out under an oxygen partial pressure condition of 10 -12 atm to 10 -8 atm.

[0026] Another embodiment includes the steps of manufacturing a dielectric slurry by mixing a barium titanate-based compound and a germanium (Ge)-based raw material; manufacturing a dielectric green sheet using the dielectric slurry, and printing a conductive paste on the surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets with the conductive paste layer formed thereon to manufacture a dielectric green sheet laminate; firing the dielectric green sheet laminate to manufacture a capacitor body including a dielectric layer and an internal electrode layer; and forming an external electrode on the outside of the capacitor body. The internal electrode layer includes an internal region and an interface region disposed on at least one surface of the internal region in the lamination direction and including an interface with the dielectric layer. The internal region and the interface region contain germanium (Ge), and the average content of germanium (Ge) in the interface region is higher than the average content of germanium (Ge) in the internal region. A method for manufacturing a multilayer ceramic capacitor is provided.

Advantages of the Invention

[0027] The multilayer ceramic capacitor according to one embodiment can improve reliability by having a high interface resistance.

Brief Description of the Drawings

[0028] [Figure 1] It is a perspective view showing a multilayer ceramic capacitor according to one embodiment. [Figure 2] It is a cross-sectional view of the multilayer ceramic capacitor cut along the line I-I' of FIG. 1. [Figure 3] It is a cross-sectional view of the multilayer ceramic capacitor cut along the line II-II' of FIG. 1. [Figure 4] It is a separated perspective view showing the lamination structure of the internal electrode layer in the capacitor body of FIG. 1. [Figure 5] An Ellingham diagram of nickel (Ni) and germanium (Ge) is shown. [Figure 6]This is an image of the TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) analysis of the internal electrode layer according to Example 5. [Figure 7a] This is an image of the TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) mapping analysis of the internal electrode layer according to Example 5. [Figure 7b] Figure 7a shows the EDS (Energy Dispersive Spectroscopy) line graph for the linear interval. [Modes for carrying out the invention]

[0029] Embodiments of the present invention will be described in detail below with reference to the attached drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. In order to clearly illustrate the present invention, unnecessary parts have been omitted from the drawings, and the same or similar components are denoted by the same reference numerals throughout the specification. Furthermore, some components in the attached drawings are exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect its actual size.

[0030] The accompanying drawings are provided solely to facilitate understanding of the embodiments disclosed herein, and the accompanying drawings are not intended to limit the technical ideas disclosed herein, and should be understood to include all modifications, equivalents, or substitutions that fall within the concept and technical scope of the present invention.

[0031] Terms including ordinal numbers, such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. These terms are used solely for the purpose of distinguishing one component from another.

[0032] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on top of" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on top of" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on top of" or "above" in the opposite direction to gravity.

[0033] Throughout the specification, terms such as “includes” or “having” are intended to indicate the presence of features, figures, stages, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, stages, operations, components, parts, or combinations thereof. Therefore, when a part “includes” a component, this means that it may include other components rather than excluding them, unless otherwise stated.

[0034] Furthermore, throughout the specification, "on a plane" refers to the view of the subject from above, and "on a cross-section" refers to the view of a cross-section obtained by cutting the subject perpendicularly, viewed from the side.

[0035] Furthermore, throughout the specification, the term "connected" does not only mean that two or more components are directly connected, but can also mean that two or more components are indirectly connected through other components, that they are not only physically connected but also electrically connected, or that they are a single unit despite being referred to by different names depending on their position or function.

[0036] A multilayer ceramic capacitor according to one embodiment will be described below with reference to Figures 1 to 4.

[0037] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to one embodiment; Figure 2 is a cross-sectional view of the multilayer ceramic capacitor cut along the line I-I' in Figure 1; Figure 3 is a cross-sectional view of the multilayer ceramic capacitor cut along the line II-II' in Figure 1; and Figure 4 is a separated perspective view showing the laminated structure of the internal electrode layers in the capacitor body of Figure 1.

[0038] The L-axis, W-axis, and T-axis shown in Figures 1 to 4 represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be perpendicular to the broad surface (main surface) of the sheet-shaped component, and can be used as the same concept as the stacking direction in which the dielectric layer 111 is stacked, for example. The length direction (L-axis direction) extends parallel to the broad surface (main surface) of the sheet-shaped component and may be roughly perpendicular to the thickness direction (T-axis direction), for example, the direction in which the first external electrode 131 and the second external electrode 132 are located on both sides. The width direction (W-axis direction) extends parallel to the broad surface (main surface) of the sheet-shaped component and may be roughly perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction), and the length in the length direction (L-axis direction) of the sheet-shaped component may be even longer than the length in the width direction (W-axis direction).

[0039] Referring to Figures 1 to 4, a multilayer ceramic capacitor 100 according to one embodiment includes a capacitor body 110 and external electrodes 131 and 132 disposed outside the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposing ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0040] The capacitor body 110 may, for example, have a roughly hexahedral shape.

[0041] For the convenience of describing one embodiment, the two surfaces of the capacitor body 110 that face each other in the thickness direction (T-axis direction) are defined as the first and second surfaces, the two surfaces connected to the first and second surfaces that face each other in the length direction (L-axis direction) are defined as the third and fourth surfaces, and the two surfaces connected to the first and second surfaces and connected to the third and fourth surfaces that face each other in the width direction (W-axis direction) are defined as the fifth and sixth surfaces.

[0042] For example, the first surface, which is the bottom surface, may be the surface facing the mounting direction. Also, the first to sixth surfaces may be flat, but this is not the only embodiment. For example, the first to sixth surfaces may be curved surfaces with a convex central portion, and the corners that form the boundaries of each surface may be rounded.

[0043] The shape, dimensions, and number of dielectric layers 111 of the capacitor body 110 are not limited to those shown in the drawings of this embodiment.

[0044] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and first internal electrode layers 121 and second internal electrode layers 122 that are alternately arranged in the thickness direction (T-axis direction) with the dielectric layers 111 in between.

[0045] At this time, the boundaries between adjacent dielectric layers 111 of the capacitor body 110 can become so integrated that they are difficult to confirm without using a scanning electron microscope (SEM).

[0046] The capacitor body 110 may include an active region and cover regions 112, 113.

[0047] The active region is a region in which the dielectric layer 111 and the internal electrode layers 121 and 122 are arranged alternately, and is the part that contributes to the formation of capacitance in the multilayer ceramic capacitor 100. Specifically, the active region may be a region in which the first internal electrode layer 121 or the second internal electrode layer 122, which are stacked along the thickness direction (T-axis direction), overlap.

[0048] The cover regions 112 and 113 are thickness-direction margins and can be arranged on the first and second surfaces of the active region in the thickness direction (T-axis direction), respectively. Such cover regions 112 and 113 may consist of a single dielectric layer 111 or two or more dielectric layers 111 laminated on the upper and lower surfaces of the active region, respectively.

[0049] Furthermore, the capacitor body 110 may also include a side margin region.

[0050] The side margin region is a widthwise margin portion and can be located on both opposite ends of the active region in the widthwise direction (W-axis direction), i.e., on the fifth and sixth surfaces, respectively. The side margin region can be formed by applying a conductive paste layer for the internal electrode layer to the surface of the dielectric green sheet, applying the conductive paste layer only to a portion of the surface of the dielectric green sheet, and then stacking dielectric green sheets without the conductive paste layer on both sides of the surface of the dielectric green sheet, followed by firing. However, the formation method is not limited to this method.

[0051] The cover regions 112, 113 and the side margin regions serve to prevent damage to the first internal electrode layer 121 and the second internal electrode layer 122 due to physical or chemical stress.

[0052] The following sections will provide a detailed explanation of the internal electrode layer, dielectric layer, and external electrode.

[0053] internal electrode layer The internal electrode layers 121 and 122, namely the first internal electrode layer 121 and the second internal electrode layer 122, are electrodes having different polarities and are arranged alternately facing each other along the T-axis direction with the dielectric layer 111 in between, with one end of each exposed through the third and fourth surfaces of the capacitor body 110.

[0054] The first internal electrode layer 121 and the second internal electrode layer 122 can be electrically insulated from each other by the dielectric layer 111 placed in between them.

[0055] The ends of the first internal electrode layer 121 and the second internal electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first external electrode 131 and the second external electrode 132, respectively.

[0056] Referring to Figure 2, the internal electrode layers 121 and 122 according to one embodiment may include internal regions 10 and 30, and interface regions 20 and 40 that are located on at least one surface of the internal regions 10 and 30 in the stacking direction and include the interface with the dielectric layer 111. That is, the first internal electrode layer 121 may include the first internal region 10, and the first interface region 20 that is located on at least one surface of the first internal region 10 in the stacking direction and includes the interface with the dielectric layer 111. The second internal electrode layer 122 may include the second internal region 30, and the second interface region 40 that is located on at least one surface of the second internal region 30 in the stacking direction and includes the interface with the dielectric layer 111.

[0057] The internal regions 10, 30 and interface regions 20, 40 of the internal electrode layers 121, 122 may contain germanium (Ge). Specifically, the average germanium (Ge) content in the interface regions 20, 40 may be even higher than the average germanium (Ge) content in the internal regions 10, 30.

[0058] Figure 5 shows the Ellingham diagrams for nickel (Ni) and germanium (Ge).

[0059] During the manufacturing of multilayer ceramic capacitors, the firing process causes oxidation of nickel (Ni), the material of the internal electrode layer, leading to the formation of nickel oxide. This formation of Ni oxide reduces the high-temperature reliability of multilayer ceramic capacitors.

[0060] As can be seen from Figure 5, germanium (Ge) is an element that oxidizes more readily than nickel (Ni). When such germanium (Ge) is applied to the internal electrode layer in a multilayer ceramic capacitor, it acts as a catalyst to promote the reduction of Ni oxide, not only suppressing the oxidation of nickel, but also potentially resulting in the coexistence of Ge and GeO2 during firing. During the process of squeezing out GeO2 into the dielectric layer, some of it may be trapped at the interface between the dielectric layer and the internal electrode layer, while some may remain in a reduced Ge state and exist in the internal electrode layer. In this case, the GeO2 located at the interface between the dielectric layer and the internal electrode layer can have a thin layer form. The GeO2 insulation layer, with a band gap energy of 6.6 eV compared to BaTiO3's band gap energy of 3.4 eV, has the effect of improving interfacial resistance, thereby hindering interfacial electron transfer between the dielectric layer and the internal electrode layer and improving the high-temperature reliability of the multilayer ceramic capacitor.

[0061] In other words, according to one embodiment, if germanium (Ge) is not only present in the internal electrode layers 121 and 122, but also present in a higher germanium (Ge) content in the interface regions 20 and 40 than in the internal regions 10 and 30, the interfacial resistance between the dielectric layer 111 and the internal electrode layers 121 and 122 increases, ensuring a highly reliable multilayer ceramic capacitor. That is, if the average germanium (Ge) content in the interface region is even lower than in the internal regions of the internal electrode layer, an insulating layer of GeO2 that can increase the interfacial resistance is not formed, resulting in reduced reliability.

[0062] The average germanium (Ge) content may be the molar amount of Ge expressed relative to 100 molar parts of nickel (Ni) in each region.

[0063] The interface regions 20 and 40 are regions with a depth of 2 nm extending from the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 into the interior of the internal electrode layers 121 and 122.

[0064] Specifically, when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer 111 to one point in the internal electrode layers 121 and 122 adjacent to the dielectric layer 111, the interface regions 20 and 40 of the internal electrode layers 121 and 122 can have the maximum molar percentage of germanium (Ge).

[0065] More specifically, when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer 111 to one point in the internal electrode layers 121 and 122 adjacent to the dielectric layer 111, the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 is defined as the point where the maximum molar percentage of nickel (Ni) is approximately 1 / 3, and the interface regions 20 and 40 are defined as the regions extending 2 nm into the interior of the internal electrode layers from the point where the maximum molar percentage of nickel (Ni) is approximately 1 / 3.

[0066] The TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis described above can be performed by the following method. After curing the multilayer ceramic capacitor 100 in an epoxy mixture, the W-axis and T-axis planes (WT planes) of the capacitor body 110 are polished to half a depth in the L-axis direction. After polishing, the polished surface is processed by ion milling, and after fixing, it is maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample that allows observation of the active region where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect. Next, the cross-sectional sample is measured with a transmission electron microscope (TEM) so that at least one dielectric layer and at least one internal electrode layer are visible in the active region. For example, when the active region of the cross-sectional sample is divided into three equal parts in the stacking direction into an upper region, a central region, and a lower region, the TEM is measured so that at least one dielectric layer and at least one internal electrode layer are visible in each region. For example, TEM is measured using a Xe-FIB (focused ion beam) at an accelerating voltage of 200kV in an approximately 80nm × 80nm region where at least one dielectric layer and one internal electrode layer are visible in each of the upper, central, and lower regions of the active area. Next, EDS (energy-dispersive spectroscopy) line analysis is performed on each TEM image of the measured cross-sectional sample for a linear section from a point in any dielectric layer to a point in the internal electrode layer adjacent to the dielectric layer. Through this EDS line analysis, it is possible not only to distinguish between the internal regions 10 and 30 and the interface regions 20 and 40, but also to compare the germanium (Ge) content in the two regions.

[0067] Furthermore, the average germanium (Ge) content in each region can be determined as follows. In the TEM images of the upper, central, and lower regions of the active area, at least one internal electrode layer 121, 122 is arbitrarily selected for each region. Multiple points located in the interface regions 20, 40 and multiple points located in the internal regions 10, 30 are specified for each internal electrode layer 121, 122 in each region, and the Ge content at these points is measured via EDS to determine the average value of the Ge content in the interface regions 20, 40 (X) and the average value of the Ge content in the internal regions 10, 30 (Y). For example, one internal electrode layer is selected for each of the upper, central, and lower regions of the active area, and three arbitrary points within the interface region and twelve arbitrary points within the internal region are specified for each internal electrode layer. The Ge content at these points is measured via EDS, and the average values ​​for the interface region and the internal region are determined. Specifically, the average value (X) of Ge content at a total of 9 locations in the interface region (3 locations in the internal electrode layer × 3 locations within the interface region) is calculated, and the average value (Y) of Ge content at a total of 36 locations in the internal region (3 locations in the internal electrode layer × 12 locations within the internal region) is calculated. The measured average Ge content is based on 100 moles of Ni in that region.

[0068] Specifically, the average molar ratio of germanium (Ge) in the interface regions 20 and 40 to the internal regions 10 and 30, i.e., X / Y, may be greater than 1 and less than or equal to 5, for example, 1.2 to 4.8 or 1.4 to 4.6. When the average molar ratio of germanium (Ge) in the interface regions to the internal regions is within the above range, the interfacial resistance between the dielectric layer and the internal electrode layer increases, thereby improving the reliability of the multilayer ceramic capacitor. The average molar ratio of Ge is obtained as the ratio of the average value of Ge content in the internal regions (X) and the average value of Ge content in the interface regions (Y) obtained by the method described above.

[0069] The interface regions 20 and 40 may further contain germanium oxide (GeO2). In this case, the interface region may have insulating layer functionality, which can further increase the interfacial resistance between the dielectric layer and the internal electrode layer.

[0070] The germanium (Ge) in the internal electrode layers 121 and 122 originates from germanium (Ge)-based raw materials mixed with the main component nickel (Ni) during the formation of the internal electrode layers, or it may originate from and diffuse from germanium (Ge)-based raw materials mixed with the main component barium titanate-based compound during the formation of the dielectric layer.

[0071] The internal regions 10, 30 and interface regions 20, 40 of the internal electrode layers 121, 122 may further contain nickel (Ni).

[0072] When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer 111 to one point in the internal electrode layers 121 and 122 adjacent to the dielectric layer 111, the internal regions 10 and 30 can have the maximum molar percentage of nickel (Ni).

[0073] Specifically, the average germanium (Ge) content in the interface regions 20 and 40, i.e., X, may be 0.4 to 12 moles per 100 moles of nickel (Ni) in the interface region, for example, 0.45 to 11 moles, or 0.5 to 10 moles. When the average germanium (Ge) content in the interface region of the internal electrode layer is within the above range, the melting point of the Ni-Ge alloy formed in the internal electrode layer is maintained at an appropriate level, minimizing the balling phenomenon of the electrode and improving reliability.

[0074] Furthermore, the average germanium (Ge) content in the internal regions 10 and 30, i.e., Y, may be 0.2 to 10 moles per 100 moles of nickel (Ni) in the internal regions 10 and 30, for example, 0.3 to 9 moles or 0.5 to 8 moles. When the average germanium (Ge) content in the internal regions of the internal electrode layer is within the above range, the interfacial resistance between the dielectric layer and the internal electrode layer increases, thereby improving the reliability of the multilayer ceramic capacitor.

[0075] The interface regions 20 and 40 may further include one or more elements selected from titanium (Ti) and barium (Ba) in addition to germanium (Ge) and nickel (Ni). Titanium (Ti) and barium (Ba) may originate from and diffuse from barium titanate-based compounds used as the main component when forming the dielectric layer, or from barium titanate powder added as a co-material as needed when forming the internal electrode layer.

[0076] The interface regions 20 and 40 can have a thickness of 0.05% to 3% of the total thickness of the internal electrode layers 121 and 122, which include the internal regions 10 and 30 and the interface regions 20 and 40, in the stacking direction. For example, they can have a thickness of 0.07% to 2.8% or 0.1% to 2.5% of the total thickness of the internal electrode layers. When the thickness of the interface regions is within this range, the interfacial resistance between the dielectric layer and the internal electrode layer is increased, improving the reliability of the multilayer ceramic capacitor.

[0077] The total thickness of the internal electrode layers 121 and 122 can be said to represent the average thickness of the internal electrode layers 121 and 122.

[0078] The average thickness of the internal electrode layers 121 and 122 may be 0.1 μm to 2 μm. When the average thickness of the internal electrode layers is within this range, the multilayer ceramic capacitor can have excellent reliability.

[0079] The thickness of the interface regions 20 and 40 and the thickness of the internal electrode layers 121 and 122 can be measured by the following method.

[0080] After curing the multilayer ceramic capacitor 100 in an epoxy mixture, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to a depth of 1 / 2 in the L-axis direction. After fixing, the sample is maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample that allows observation of the active region where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect. Next, the cross-sectional sample can be measured using a scanning electron microscope (SEM) so that at least one dielectric layer and at least one internal electrode layer, for example, one to five layers, are visible in the active region. For example, using a Thermofisher Scientific Verios G4 SEM, measurements can be taken under 10kV conditions in an approximately 400nm × 400nm region where at least one dielectric layer and at least one internal electrode layer are visible in the active region.

[0081] The thickness of the internal electrode layers 121 and 122 can be determined by using the SEM image of the cross-sectional sample as a reference point, with the center point of the internal electrode layers 121 and 122 in the length direction (L-axis direction) or width direction (W-axis direction) set as the reference point, and measuring the arithmetic mean of the thickness of the internal electrode layers 121 and 122 at 10 points separated by a predetermined interval from the reference point. The interval of the 10 points can be adjusted by the scale of the scanning electron microscope (SEM) image, for example, between 1 μm and 100 μm, 1 μm and 50 μm, or 1 μm and 10 μm. In this case, all 10 points must be located within the internal electrode layers 121 and 122. If all 10 points are not located within the internal electrode layers 121 and 122, the position of the reference point can be changed, or the interval between the 10 points can be adjusted.

[0082] Dielectric layer The dielectric layer 111 may mainly contain a barium titanate-based compound containing barium (Ba) and titanium (Ti).

[0083] Barium titanate compounds are dielectric base materials that have a high dielectric constant and contribute to the formation of the dielectric constant of the multilayer ceramic capacitor 100.

[0084] As an example, barium titanate compounds may include one or more selected from BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, and (Ba,Sr)(Ti,Sn)O3.

[0085] The dielectric layer 111 may contain germanium (Ge) in addition to barium (Ba) and titanium (Ti).

[0086] The germanium (Ge) in the dielectric layer 111 may originate from germanium (Ge)-based raw materials mixed with the nickel main component during the formation of the internal electrode layer, or from germanium (Ge)-based raw materials mixed with the barium titanate-based compound, which is the main component during the formation of the dielectric layer, and may diffuse from these materials.

[0087] The dielectric layer 111 may further contain minor components. These minor components may further contain one or more selected from, for example, manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0088] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 0.2 μm to 10 μm, for example, 0.2 μm to 8.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor is excellent.

[0089] This is a scanning electron microscope (SEM) image of the cross-sectional sample measured as described above. The dielectric layer 111's center point in the length direction (L-axis direction) or width direction (W-axis direction) is used as the reference point, and the arithmetic mean of the dielectric layer 111's thickness can be obtained by taking 10 points located at predetermined intervals from the reference point. The interval between the 10 points can be adjusted by the scale of the scanning electron microscope (SEM) image, for example, between 1 μm and 100 μm, 1 μm and 50 μm, or 1 μm and 10 μm. In this case, all 10 points must be located within the dielectric layer 111. If all 10 points are not located within the dielectric layer 111, the position of the reference point can be changed, or the interval between the 10 points can be adjusted.

[0090] The capacitor body 110 can be formed by firing a laminate in which multiple dielectric layers 111 and internal electrode layers 121 and 122 are stacked.

[0091] external electrode External electrodes 131 and 132, namely the first external electrode 131 and the second external electrode 132, are supplied with voltages of different polarities and can be electrically connected to the exposed portions of the first internal electrode layer 121 and the second internal electrode layer 122, respectively.

[0092] With the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge is accumulated between the first internal electrode layer 121 and the second internal electrode layer 122, which are opposite each other. At this time, the capacitance of the multilayer ceramic capacitor 100 becomes proportional to the superimposed area of ​​the first internal electrode layer 121 and the second internal electrode layer 122, which are superimposed on each other along the T-axis in the active region.

[0093] The first external electrode 131 and the second external electrode 132 may each include a first connecting portion and a second connecting portion, which are arranged on the third and fourth surfaces of the capacitor body 110 and connected to the first internal electrode layer 121 and the second internal electrode layer 122, respectively, and a first band portion and a second band portion, which are arranged at the corners where the third and fourth surfaces of the capacitor body 110 meet the first and second surfaces or the fifth and sixth surfaces.

[0094] The first band portion and the second band portion may extend from the first and second connection portions to a portion of the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, respectively. The first band portion and the second band portion can serve to improve the fixing strength of the first external electrode 131 and the second external electrode 132.

[0095] The external electrodes 131 and 132 may include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer positioned to cover the sintered metal layer, and a plating layer positioned to cover the conductive resin layer.

[0096] The sintered metal layer may contain conductive metals and glass.

[0097] The conductive metal may include one or more selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, copper (Cu) may include copper (Cu) alloys. If the conductive metal includes copper, other metals may be included in amounts of 5 moles or less per 100 moles of copper.

[0098] The glass may contain a composition of mixed oxides, for example, one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metal may be selected from lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metal may be one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0099] Selectively, the conductive resin layer can be formed on top of the sintered metal layer, for example, in a form that completely covers the sintered metal layer. On the other hand, the external electrodes 131 and 132 do not necessarily have to include the sintered metal layer, in which case the conductive resin layer can be in direct contact with the capacitor body 110.

[0100] The conductive resin layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, and the length of the region where the conductive resin layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 (i.e., the band portion) may be longer than the length of the region where the sintered metal layer extends to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110 (i.e., the band portion). In other words, the conductive resin layer can be formed on top of the sintered metal layer and can be formed in a manner that completely covers the sintered metal layer.

[0101] The conductive resin layer contains a resin and a conductive metal.

[0102] The resin contained in the conductive resin layer is not particularly limited as long as it has bonding and shock-absorbing properties and can be mixed with conductive metal powder to form a paste. Examples include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0103] The conductive metal contained in the conductive resin layer serves to electrically connect with the internal electrode layers 121, 122, or the sintered metal layer.

[0104] The conductive metal contained in the conductive resin layer may be spherical, flake-shaped, or a combination thereof. That is, the conductive metal may consist only of flake-shaped elements, only of spherical elements, or a mixture of flake-shaped and spherical elements.

[0105] Here, spherical can include forms that are not perfectly spherical, for example, forms in which the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) is 1.45 or less. Flake powder means powder having a flat and elongated shape, and is not particularly limited, but for example, the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) may be 1.95 or more.

[0106] The external electrodes 131 and 132 may further include a plating layer disposed on the outside of the conductive resin layer.

[0107] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb), either alone or in alloys thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or it may be a configuration in which nickel (Ni) plating layers and tin (Sn) plating layers are sequentially laminated, or it may be a configuration in which tin (Sn) plating layers, nickel (Ni) plating layers, and tin (Sn) plating layers are sequentially laminated. Furthermore, the plating layer may include multiple nickel (Ni) plating layers and / or multiple tin (Sn) plating layers.

[0108] The plating layer can improve the mountability of the multilayer ceramic capacitor 100 on the substrate, structural reliability, durability against external elements, heat resistance, and equivalent series resistance (ESR).

[0109] Manufacturing method for multilayer ceramic capacitors The manufacturing method for the multilayer ceramic capacitor 100 described above will be explained below.

[0110] A multilayer ceramic capacitor 100 can be manufactured by the following steps: mixing nickel (Ni) and germanium (Ge) based raw materials to produce a conductive paste; manufacturing a dielectric green sheet using a dielectric slurry and printing the conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer; stacking the dielectric green sheets on which the conductive paste layer is formed to produce a dielectric green sheet laminate; firing the dielectric green sheet laminate to produce a capacitor body including a dielectric layer and an internal electrode layer; and forming external electrodes on the outside of the capacitor body.

[0111] The germanium (Ge)-based raw material may include one or more selected from germanium (Ge) metal, germanium oxide (GeO2), and Ni-Ge alloys.

[0112] The germanium (Ge)-based raw material may be mixed in an amount of 0.3 to 10 parts per 100 parts per 100 parts per 100 parts per 100 parts nickel (Ni), for example, 0.4 to 9 parts or 0.5 to 8 parts per 10

[0113] In addition to nickel (Ni), conductive paste can be manufactured by further mixing one or more conductive metals selected from copper (Cu), silver (Ag), palladium (Pd), gold (Au), and their alloys, such as Ag-Pd alloys.

[0114] Furthermore, conductive paste can be manufactured by additionally mixing conductive powder, a binder, and a solvent. Barium titanate powder may also be mixed in as a co-material if necessary. The co-material can suppress the sintering of the conductive powder during the firing process.

[0115] Dielectric slurry can be manufactured by selectively mixing a barium titanate-based compound, which is the main component powder, with a secondary component powder. The secondary component powder may be an oxide or salt compound, or it may be used in sol form dispersed in an organic solvent.

[0116] Furthermore, dielectric slurry can be manufactured by additionally mixing additives such as dispersants, binders, plasticizers, lubricants, and antistatic agents with solvents.

[0117] The dispersant may include at least one selected from, for example, phosphate ester-based dispersants and polycarboxylic acid-based dispersants. The dispersant may be mixed in an amount of 0.1 to 5 parts by weight per 100 parts by weight of the barium titanate compound, or for example, 0.3 to 3 parts by weight. When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0118] The binder may be, for example, an acrylic resin, a polyvinyl butyral resin, a polyvinyl acetal resin, or an ethyl cellulose resin. The binder may be added in an amount of 0.1 to 50 parts by weight per 100 parts by weight of the barium titanate compound, for example, 3 to 30 parts by weight. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0119] The plasticizer may be, for example, phthalate compounds such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate; adipic acid compounds such as dihexyl adipic acid and bis(2-ethylhexyl) adipic acid; glycol compounds such as ethylene glycol, diethylene glycol, and triethylene glycol; or glycol ester compounds such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate). The plasticizer may be added in an amount of 0.1 to 20 parts by weight per 100 parts by weight of the barium titanate compound, for example, 1 to 10 parts by weight. When the plasticizer is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0120] The solvent may be an aqueous solvent such as water; an alcoholic solvent such as ethanol, methanol, benzyl alcohol, or 2-methoxyethanol; a glycolic solvent such as ethylene glycol or diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone; an esteric solvent such as butyl acetate, ethyl acetate, carbitol acetate, or butyl carbitol acetate; an etheric solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, or tetrahydrofuran; or an aromatic solvent such as benzene, toluene, or xylene. The solvent can be an alcoholic or aromatic solvent, for example, considering the solubility and dispersibility of various additives contained in the dielectric slurry. The solvent may be mixed in an amount of 50 to 1000 parts by weight per 100 parts by weight of the barium titanate compound, or for example, 100 to 500 parts by weight. When the solvent is mixed within the above content range, the dielectric slurry components are thoroughly mixed, and the solvent can be easily removed thereafter.

[0121] The aforementioned dielectric slurry can be mixed using a wet ball mill or a stirring mill. When using zirconia balls in a wet ball mill, a large number of zirconia balls with diameters from 0.1 mm to 10 mm can be used for wet mixing for 8 to 48 hours, or 10 to 24 hours.

[0122] The manufactured dielectric slurry is formed as a dielectric layer after firing.

[0123] Methods for forming the manufactured dielectric slurry into a sheet shape include tape molding methods such as the doctor blade method and the calender roll method, or, for example, an on-roll molding coater with a head discharge system. A dielectric green sheet can then be obtained by drying the molded body.

[0124] A conductive paste layer is formed by applying a conductive paste in a predetermined pattern to the surface of a dielectric green sheet using various printing methods such as screen printing or transfer methods.

[0125] According to one embodiment, instead of using germanium (Ge)-based raw materials in the production of a conductive paste in which an internal electrode layer is formed, they can also be used in the production of a dielectric slurry in which a dielectric layer is formed. That is, in the multilayer ceramic capacitor 100, a dielectric slurry can be produced by mixing a barium titanate-based compound and a germanium (Ge)-based raw material, a dielectric green sheet can be produced using the dielectric slurry, and a conductive paste containing nickel (Ni) can be printed on the surface of the dielectric green sheet to form a conductive paste layer.

[0126] Next, a dielectric green sheet laminate is manufactured by stacking multiple dielectric green sheets with internal electrode patterns formed on them in layers, and then pressing them in the stacking direction. At this time, the dielectric green sheets and internal electrode patterns can be stacked such that dielectric green sheets are positioned on the upper and lower surfaces of the dielectric green sheet laminate in the stacking direction.

[0127] The manufacturing dielectric green sheet laminate can be selectively cut to predetermined dimensions by dicing or other methods.

[0128] Furthermore, the dielectric green sheet laminate can be solidified and dried to remove plasticizers and other substances as needed, and after solidification and drying, it can be barrel polished using a horizontal centrifugal barrel polishing machine or the like. In barrel polishing, the dielectric green sheet laminate is placed in a barrel container along with media and polishing fluid, and rotational motion or vibration is applied to the barrel container to polish away unwanted parts such as burrs generated during cutting. After barrel polishing, the dielectric green sheet laminate is washed with a cleaning solution such as water and then dried.

[0129] Next, the dielectric green sheet laminate can be debindered and fired to manufacture a capacitor body.

[0130] The debinding treatment conditions can be appropriately adjusted depending on the composition of the dielectric layer and the internal electrode layer. For example, the heating rate during debinding may be 5°C / hour to 300°C / hour, the support temperature 180°C to 400°C, and the temperature maintenance time 0.5 hours to 24 hours. The atmosphere during debinding may be air or a reducing atmosphere.

[0131] The firing conditions can be appropriately adjusted depending on the composition of the main components of the dielectric layer and the internal electrode layer. For example, firing can be carried out at a temperature of 1100°C to 1400°C, or for example, at a temperature of 1200°C to 1350°C. Furthermore, firing can be carried out for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. Also, firing can be carried out in a reducing atmosphere, for example, a humidified atmosphere of a mixed gas of nitrogen and hydrogen. Furthermore, firing can be carried out for 10 -12 atm~10 -8 The firing can be carried out under atm oxygen partial pressure conditions. When firing is performed under oxygen partial pressure conditions within the aforementioned range, a multilayer ceramic capacitor with high interfacial resistance between the dielectric layer and the internal electrode layer and excellent reliability can be obtained.

[0132] After firing, annealing can be performed as needed. Annealing is a process to re-oxidize the dielectric layer, and can be performed when firing is carried out in a reducing atmosphere. The conditions for the annealing process can also be appropriately adjusted depending on the composition of the dielectric layer. For example, the temperature during annealing may be 950°C to 1150°C, the time may be 0 to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen gas (N2) atmosphere, and the oxygen partial pressure may be 1.0 × 10⁻⁶. -9 MPa ~ 1.0 × 10 -5 MPa is also acceptable.

[0133] For debinding, calcination, or annealing processes, a wetter, for example, can be used to humidify nitrogen gas or a mixed gas, in which case the water temperature may be between 5°C and 75°C. Debinding, calcination, and annealing processes can be performed continuously or independently.

[0134] Selectively, the third and fourth surfaces of the manufactured capacitor body 110 can be subjected to surface treatments such as sandblasting, laser irradiation, and barrel polishing. By performing such surface treatments, the edges of the first and second internal electrode layers are exposed on the outermost surfaces of the third and fourth surfaces, thereby improving the electrical connection between the first and second external electrodes and the first and second internal electrode layers, and potentially facilitating the formation of alloy parts.

[0135] Next, an external electrode is formed on one surface of the manufactured capacitor body 110.

[0136] As an example, a sintered metal layer can be formed by applying a paste for forming a sintered metal layer to an external electrode and then sintering it.

[0137] The paste for forming a sintered metal layer may contain conductive metals and glass. The explanation of conductive metals and glass is the same as described above, so repeated explanations will be omitted. The paste for forming a sintered metal layer may also selectively contain binders, solvents, dispersants, plasticizers, oxide powders, etc. Binders can include, for example, ethyl cellulose, acrylic, butyral, and solvents can include organic solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, and toluene, or aqueous solvents.

[0138] Methods for applying the sintered metal layer-forming paste to the outer surface of the capacitor body 110 include various printing methods such as dipping and screen printing, application methods using dispensers, and spraying methods using sprayers. The sintered metal layer-forming paste is applied to at least the third and fourth surfaces of the capacitor body 110, and may also be applied to parts of the first, second, fifth, or sixth surfaces where the band portions of the first and second external electrodes are selectively formed.

[0139] Subsequently, the capacitor body 110 coated with the paste for forming a sintered metal layer is dried and sintered at a temperature of 700°C to 1000°C for 0.1 to 3 hours to form a sintered metal layer.

[0140] Selectively, a conductive resin layer can be formed by applying a conductive resin layer-forming paste to the outer surface of the obtained capacitor body 110 and then curing it.

[0141] The paste for forming a conductive resin layer may contain a resin and, selectively, a conductive metal or a non-conductive filler. The descriptions of conductive metals and resins are the same as those given above, so repeated explanations will be omitted. The paste for forming a conductive resin layer may also selectively contain a binder, solvent, dispersant, plasticizer, oxide powder, etc. Binders can be, for example, ethyl cellulose, acrylic, or butyral, and solvents can be organic solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, or toluene, or aqueous solvents.

[0142] As an example, the conductive resin layer can be formed by dipping the capacitor body 110 into a conductive resin layer forming paste and then curing it, or by printing the conductive resin layer forming paste onto the surface of the capacitor body 110 using a screen printing method or gravure printing method, or by applying the conductive resin layer forming paste to the surface of the capacitor body 110 and then curing it.

[0143] Next, a plating layer is formed on the outside of the conductive resin layer.

[0144] For example, the plating layer can be formed by a plating method, and can also be formed by sputtering or electroplating (electric deposition).

[0145] The embodiments described above will be explained in more detail below through the examples provided. However, the following examples are for illustrative purposes only and do not limit the scope of rights. [Examples]

[0146] (Manufacturing of multilayer ceramic capacitors) Examples 1-10 and Comparative Examples 1 and 2 A conductive paste was prepared by mixing Ni and GeO2. In this process, the GeO2 was mixed in the amount shown in Table 1 below, relative to 100 moles of Ni.

[0147] Next, a dielectric slurry was prepared using barium titanate (BaTiO3) powder. In this process, zirconia balls (ZrO2 balls) were used as the dispersion medium, and the slurry was prepared by mechanical milling after adding ethanol / toluene, a dispersant, and a binder.

[0148] Next, the manufactured dielectric slurry was extruded using a head-dispensing type on-roll molding coater to produce a dielectric green sheet. The manufactured conductive paste was then printed onto the surface of the dielectric green sheet to form a conductive paste layer.

[0149] A dielectric green sheet laminate was manufactured by laminating and pressing dielectric green sheets, each having a conductive paste layer formed on it.

[0150] Each dielectric green sheet laminate undergoes a calcination process at a temperature of 400°C or lower and in a nitrogen atmosphere, followed by firing at a temperature of 1300°C or lower and a hydrogen concentration of 1.0%H2 or lower, with an oxygen partial pressure of 10%. -12 atm~10 -8 The baking process was adjusted within the ATM range.

[0151] Next, the multilayer ceramic capacitor was manufactured through processes such as the formation of external electrodes and plating.

[0152] [Table 1]

[0153] Evaluation 1: TEM-EDS analysis TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) analysis was performed on each manufactured multilayer ceramic capacitor, and the results are shown in Figures 6 and 7 and Table 2 below.

[0154] Specifically, after curing the multilayer ceramic capacitor manufactured in Example 5 in an epoxy mixture, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body were polished to half a depth in the L-axis direction. After polishing, the polished surface was processed by ion milling, and after fixing, it was maintained in a vacuum atmosphere chamber to obtain a cross-sectional sample that allowed observation of the active region where the dielectric layer and the internal electrode layer intersect. Next, the active region of the cross-sectional sample was divided into three equal parts in the stacking direction: an upper region, a central region, and a lower region. Each region was then measured using a transmission electron microscope (TEM) so that at least one dielectric layer and one internal electrode layer were visible. The TEM was measured using a Xe-FIB (focused ion beam) at an acceleration voltage of 200kV in an approximately 80nm × 80nm region where at least one dielectric layer and one internal electrode layer were visible in each of the upper, central, and lower regions of the active region. Next, energy-dispersive spectroscopy (EDS) analysis was performed on each TEM image of the measured cross-sectional sample.

[0155] Figure 6 shows an image of the TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) analysis of the internal electrode layer according to Example 5.

[0156] Referring to Figure 6, in the case of the internal electrode layer of Example 5, it can be seen that the average Ge content is higher at the interface with the dielectric layer than in the interior. In other words, the average Ge content in the interface region, which includes the interface with the dielectric layer, that is, the region with a depth of approximately 2 nm from the interface between the dielectric layer and the internal electrode layer into the interior of the internal electrode layer, is higher than the average Ge content in the remaining interior region.

[0157] Furthermore, EDS (energy-dispersive spectroscopy) line analysis was performed on the TEM image of the measured cross-sectional sample for a linear section from a point in an arbitrary internal electrode layer to a point in a dielectric layer adjacent to the internal electrode layer, and the results are shown in Figures 7a and 7b.

[0158] Figure 7a shows an image of the TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) mapping analysis of the internal electrode layer according to Example 5, and Figure 7b is an EDS (energy dispersive spectroscopy) line graph for the linear section in Figure 7a.

[0159] Referring to Figures 7a and 7b, it can be seen that in the case of the internal electrode layer of Example 5, the molar percentage of Ge is at its maximum value in the interface region. At this time, the interface between the dielectric layer and the internal electrode layer is at a point where the molar percentage of Ni is approximately 1 / 3 of the maximum value, and the interface region can be seen as extending from the point where the molar percentage of Ni is approximately 1 / 3 of the maximum value to a distance of 2 nm inside the internal electrode layer. Furthermore, in the case of the internal electrode layer of Example 1, it can be seen that the average Ge content in the interface region is greater than the average Ge content in the remaining internal region.

[0160] Furthermore, for each TEM image of the upper, central, and lower regions of the measured active area, one internal electrode layer was selected for each region. For each internal electrode layer, three arbitrary points within the interface region and twelve arbitrary points within the internal region were specified, and the Ge content at these points was measured via EDS, and the average values ​​for the interface region and the internal region were calculated. Specifically, the average value (X) of Ge content at a total of nine points in the interface region (3 internal electrode layers × 3 points within the interface region) was calculated, and the average value (Y) of Ge content at a total of 36 points in the internal region (3 internal electrode layers × 12 points within the internal region) was calculated. This is shown in Table 2 below. At this time, the measured average Ge content is shown relative to 100 moles of Ni in that region.

[0161] Referring to Table 2 below, it can be seen that in the case of the internal electrode layers according to Examples 1 to 10, the average Ge content in the interface region is greater than the average Ge content in the internal region.

[0162] Rating 2: Reliability The accelerated lifetime reliability (MTTF) of the multilayer ceramic capacitors manufactured in Examples 1-10 and Comparative Examples 1 and 2 was measured using the method described below, and the results are shown in Table 2.

[0163] The mean time to failure (MTTF) was measured under conditions of 125°C, 9.45V, and 48 hours, and the mean time to failure (hr) was determined.

[0164] In Table 2 below, the MTTF values ​​correspond to the respective ratios based on the results from Example 1.

[0165] [Table 2]

[0166] Referring to Table 2 above, it can be seen that Examples 1 to 10 exhibit superior reliability compared to Comparative Examples 1 and 2. From this, it can be seen that in one embodiment, when the average Ge content in the interface region of the internal electrode layer is even higher than the average Ge content in the internal region, superior reliability is achieved due to the high interface resistance.

[0167] Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and can be implemented in various ways within the scope of the claims, the detailed description of the invention, and the attached drawings, and these also naturally fall within the scope of the present invention. [Explanation of symbols]

[0168] 10: 1st internal area 20: First interface area 30:Second internal area 40:Second interface area 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 112: Coverage Area 113: Coverage Area 121: First internal electrode layer 122: Second internal electrode layer 131: 1st external electrode 132:Second external electrode

Claims

1. A capacitor body comprising multiple dielectric layers and multiple internal electrode layers stacked with the dielectric layers in between; and Includes external electrodes positioned outside the capacitor body, The internal electrode layer includes an internal region and an interface region which is arranged on at least one surface of the internal region in the stacking direction and includes the interface with the dielectric layer. The internal region and the interface region contain germanium (Ge), A multilayer ceramic capacitor in which the average germanium (Ge) content in the interface region is even higher than the average germanium (Ge) content in the internal region.

2. The multilayer ceramic capacitor according to claim 1, wherein the average molar ratio of germanium (Ge) in the interface region to the internal region is greater than 1 and less than or equal to 5.

3. The multilayer ceramic capacitor according to claim 1, wherein the interface region is a region having a depth of 2 nm from the interface between the internal electrode layer and the dielectric layer into the interior of the internal electrode layer.

4. When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer, The multilayer ceramic capacitor according to claim 1, wherein the interface region has the maximum molar percentage of germanium (Ge).

5. The aforementioned interface region is made of germanium oxide (GeO ２ The multilayer ceramic capacitor according to claim 1, further comprising:

6. The multilayer ceramic capacitor according to claim 1, wherein the internal region and the interface region further comprise nickel (Ni).

7. When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer to one point in the internal electrode layer adjacent to the dielectric layer, The multilayer ceramic capacitor according to claim 6, wherein the internal region has the maximum molar percentage of nickel (Ni).

8. When performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the dielectric layer to one point in the internal electrode layer adjacent to the dielectric layer, The multilayer ceramic capacitor according to claim 6, wherein the interface region is a region from a point where the maximum molar percentage of nickel (Ni) is 1 / 3 to a distance of 2 nm inside the internal electrode layer.

9. The multilayer ceramic capacitor according to claim 6, wherein the average germanium (Ge) content in the interface region is 0.4 moles to 12 moles per 100 moles of nickel (Ni) in the interface region.

10. The multilayer ceramic capacitor according to claim 6, wherein the interface region further comprises one or more materials selected from titanium (Ti) and barium (Ba).

11. The multilayer ceramic capacitor according to claim 6, wherein the average germanium (Ge) content in the internal region is 0.2 moles to 10 moles per 100 moles of nickel (Ni) in the internal region.

12. The multilayer ceramic capacitor according to claim 1, wherein the interface region has a thickness of 0.05% to 3% of the total thickness of the internal electrode layer.

13. The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer comprises barium (Ba), titanium (Ti), and germanium (Ge).

14. The multilayer ceramic capacitor according to claim 1, wherein the average thickness of the internal electrode layer is 0.1 μm to 2 μm.

15. The multilayer ceramic capacitor according to claim 1, wherein the average thickness of the dielectric layer is 0.2 μm to 10 μm.

16. The steps include: a step of mixing nickel (Ni) and germanium (Ge) based raw materials to produce a conductive paste; The process involves manufacturing a dielectric green sheet using a dielectric slurry, and printing the conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer; A step of manufacturing a dielectric green sheet laminate by stacking dielectric green sheets on which the conductive paste layer is formed; The steps include: firing the dielectric green sheet laminate to manufacture a capacitor body including a dielectric layer and an internal electrode layer; The steps include: forming an external electrode on the outside of the capacitor body; The internal electrode layer includes an internal region and an interface region which is arranged on at least one surface of the internal region in the stacking direction and includes the interface with the dielectric layer. A method for manufacturing a multilayer ceramic capacitor, wherein the internal region and the interface region contain germanium (Ge), and the average germanium (Ge) content in the interface region is even higher than the average germanium (Ge) content in the internal region.

17. The aforementioned germanium (Ge)-based raw materials include germanium (Ge), germanium oxide (GeO2), and germanium oxide (GeO2). ２ A method for manufacturing a multilayer ceramic capacitor according to claim 16, comprising one or more selected from among ), and Ni-Ge alloys.

18. The method for manufacturing a multilayer ceramic capacitor according to claim 16, wherein the germanium (Ge)-based raw material is mixed in an amount of 0.3 moles to 10 moles per 100 moles of nickel (Ni).

19. The aforementioned firing process is 10 －１２ atm~10 －８ A method for manufacturing a multilayer ceramic capacitor according to claim 16, carried out under the condition of an oxygen partial pressure of atm.

20. The steps include: a step of mixing a barium titanate compound and a germanium (Ge) raw material to produce a dielectric slurry; The steps include: manufacturing a dielectric green sheet using the dielectric slurry, and printing a conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer; A step of manufacturing a dielectric green sheet laminate by stacking dielectric green sheets on which the conductive paste layer is formed; The steps include: firing the dielectric green sheet laminate to manufacture a capacitor body including a dielectric layer and an internal electrode layer; The steps include: forming an external electrode on the outside of the capacitor body; The internal electrode layer includes an internal region and an interface region which is arranged on at least one surface of the internal region in the stacking direction and includes the interface with the dielectric layer. A method for manufacturing a multilayer ceramic capacitor, wherein the internal region and the interface region contain germanium (Ge), and the average germanium (Ge) content in the interface region is even higher than the average germanium (Ge) content in the internal region.

21. The aforementioned germanium (Ge)-based raw materials include germanium (Ge), germanium oxide (GeO2), and germanium oxide (GeO2). ２ A method for manufacturing a multilayer ceramic capacitor according to claim 20, comprising one or more selected from among ), and Ni-Ge alloys.

22. The aforementioned firing process is 10 －１２ atm~10 －８ A method for manufacturing a multilayer ceramic capacitor according to claim 20, carried out under the condition of an oxygen partial pressure of atm.

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