Fan-out type wafer-level packaging unit and packaging composed of the stacking of the same

Abstract

The present invention provides a fan-out type wafer-level packaging unit and a packaging system composed of the stacking of such units. [Solution] The present invention provides a FOWLP unit and a packaging comprising a stack of the same. The FOWLP unit includes a substrate, at least one die, a first dielectric layer, at least one second conductive pillar, a second dielectric layer, a plurality of first conductive wires, a third dielectric layer, and a plurality of metal protective layers. Each of the first conductive wires is manufactured by first filling a recess with metal paste and then polishing it to form a conductive wire, and is manufactured and formed on the second surface of each die. Each of the second solder pads on the first surface of the FOWLP unit is arranged in the same way as each of the first solder pads on the second surface of the FOWLP unit, facilitating mass production.

Description

Technical Field

[0001] The present invention relates to packaging, and particularly to a fan-out wafer level packaging (FOWLP) unit and a packaging constituted by stacking thereof.

Background Art

[0002] In FOWLP, which is an advanced packaging technology, the redistribution layer (RDL) is considered the most important because each conductive wire in the RDL serves to electrically extend and interconnect multiple die pads on the die in the XY plane direction, and can form a plurality of solder pads dispersed around the die, thereby more effectively improving the design space and reliability of each conductive wire. However, in order to maintain or achieve a certain degree of light weight, thinness, and miniaturization of the RDL at the same time, the fabrication of each conductive wire in the RDL becomes the most important.

[0003] However, in the RDL technology applied in the conventional FOWLP packaging technology, as a method for forming each conductive wire, a chemical plating technology or an electroplating formation process is adopted. In such a method, not only the material cost and manufacturing cost become relatively high, but also the process in the conventional technology does not meet the environmental requirements.

[0004] Also, in the FOWLP unit, when packaging constituted by stacking is required to improve performance or computing power, how to enable the FOWLP unit to easily perform stacked packaging and achieve mass production is an important issue to be improved.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] The main object of the present invention is to provide a FOWLP unit and a packaging comprising the stacking of the same. The FOWLP unit includes a substrate, at least one die, a first dielectric layer, at least one second conductive pillar, a second dielectric layer, a plurality of first conductive wires, a third dielectric layer, and a plurality of metal protective layers. Each of the first conductive wires is manufactured by a technique in which a metal paste is first filled into a recess and then polished to form a conductive wire. By manufacturing and forming on the second surface of each die, it is possible to effectively solve the problems of higher manufacturing costs and environmental disadvantages that tend to occur when manufacturing each conductive wire in conventional FOWLP technology modules. Each of the second solder pads on the first surface of the FOWLP unit is arranged in the same way as each of the first solder pads on the second surface of the FOWLP unit, thereby enabling the manufacturer to easily package and mass-produce the stacked FOWLP units. [Means for solving the problem]

[0007] To solve the above-mentioned objectives, the present invention provides a FOWLP unit. It includes one substrate, at least one die, one first dielectric layer, at least one second conductive pillar, one second dielectric layer, a plurality of first conductive wires, one third dielectric layer, and a plurality of metal protective layers.

[0008] The substrate has one first surface and one opposing second surface, and the substrate has a plurality of first conductive pillars that penetrate the first surface and the second surface.

[0009] Each die is divided from a single wafer, and each die has one first surface and one opposing second surface, the first surface being fixedly mounted on the second surface of the substrate, and each die has a plurality of die pads on the second surface, and the vertical range of the chips on the second surface is defined as the die region.

[0010] The first dielectric layer is provided on the second surface of the substrate and covers each die. The first dielectric layer has at least one through-hole, each of which is connected to a corresponding first conductive pillar.

[0011] Each of the second conductive pillars is formed within each of the through-holes, electrically connected to each of the first conductive pillars, and exposed to the outside through each of the through-holes.

[0012] The second dielectric layer is provided on the first dielectric layer, and the second dielectric layer has at least one recess formed by extending horizontally. Each of the recesses is connected to a corresponding second conductive pillar.

[0013] Each of the first conductive wires is provided by filling each recess with metal paste. Each of the first conductive wires is electrically connected to each of the second conductive pillars.

[0014] The third dielectric layer is provided on the second dielectric layer and each of the first conductive wires, and the third dielectric layer has at least one first opening. Each of the first conductive wires is exposed to the outside through each of the first openings, and a first solder pad is formed within each of the first openings.

[0015] Each of the aforementioned metal protective layers is formed within each of the first openings. Each of the aforementioned metal protective layers is electrically connected to each of the first conductive wires.

[0016] Each of the first conductive pillars is exposed to the outside from the first surface of the substrate, and a second solder pad is formed on the first surface of the substrate.

[0017] Each die is electrically connected to the outside world via, in order, each die pad, each first conductive wire, each second conductive pillar, each first conductive pillar, and each second solder pad located on the substrate.

[0018] Each die is electrically connected to the outside, in order, via each die pad, each first conductive wire, each metal protective layer, and each first solder pad around the die region located on the second surface of each die, thereby forming the FOWLP unit.

[0019] The FOWLP unit further has one first surface and one second surface. Each of the second solder pads on the substrate of the FOWLP unit is further located on the first surface of the FOWLP unit. Each of the first solder pads within each of the first openings of the FOWLP unit is further located on the second surface within the FOWLP unit. Each of the second solder pads on the first surface of the FOWLP unit is arranged in the same way as each of the first solder pads on the second surface of the FOWLP unit.

[0020] The method for manufacturing the FOWLP unit includes the following steps:

[0021] Step S1: Provide a substrate. The substrate has one first surface and one opposing second surface, and the substrate has a plurality of first conductive pillars that penetrate the first surface and the second surface. Each of the first conductive pillars is exposed to the outside from the first surface of the substrate, and a second solder pad is formed on the first surface of the substrate.

[0022] Step S2: Multiple dies, separated from at least one wafer, are placed on the substrate at intervals. Each die has one first face and one opposing second face, the first face of each die is fixedly mounted on the second face of the substrate, and each die has multiple die pads on the second face, with the vertical range of the chips on the second face defined as the die region.

[0023] Step S3: Lay a first dielectric layer on the second surface of the substrate and on each die, and the first dielectric layer covers each die. Next, form a plurality of through holes penetrating downward through the first dielectric layer on the first dielectric layer. Further, form a second conductive pillar in each through hole.

[0024] Step S4: First, after filling the recesses with metal paste, use the technique of polishing to form conductive lines to form a plurality of first conductive lines on the second surface of each die. First, lay a second dielectric layer on the second surface of the substrate, then form a plurality of recesses in the horizontal direction on the second dielectric layer, and further each second conductive pillar can be exposed to the outside through each recess. Next, fill each recess with metal paste and make the thickness of the metal paste higher than the surface of the second dielectric layer. Finally, polish the metal paste that is higher than the surface of the second dielectric layer, so that the surface of the metal paste is aligned with the surface of the second dielectric layer, thereby constituting a plurality of the first conductive lines.

[0025] Step S5: Lay a third dielectric layer on the second dielectric layer, and then form a plurality of first openings in the horizontal direction on the third dielectric layer, so that each first conductive line is exposed to the outside from each first opening, and finally form a metal protection layer in each first opening. Each of the first conductive lines forms a first solder pad in each first opening. Each of the metal protection layers is electrically connected to each first conductive line.

[0026] Step S6: Perform a splitting operation to form a plurality of FOWLP units.

[0027] In one preferred embodiment of the present invention, the first surface of the substrate further provides a fourth dielectric layer and a plurality of second conductive lines by using an RDL process. The fourth dielectric layer has at least one second opening formed by extending in the horizontal direction. Each of the second conductive lines is formed by filling metal paste in each second opening. Each of the second conductive lines is electrically connected to each second solder pad.

[0028] Each of the above-mentioned methods for manufacturing the second conductive wire further includes the following steps:

[0029] Step S1: First, a fourth dielectric layer is laid on the first surface of the substrate. Next, a plurality of second openings are formed horizontally on the fourth dielectric layer, so that each of the second solder pads can be exposed to the outside through each of the second openings.

[0030] Step S2: Further fill each of the second openings with metal paste, and make the thickness of the metal paste greater than the surface of the fourth dielectric layer.

[0031] Step S3: Finally, the metal paste that has risen above the surface of the fourth dielectric layer is polished so that the surface of the metal paste is aligned with the surface of the fourth dielectric layer, thereby forming a plurality of the second conductive wires.

[0032] In one best embodiment of the present invention, a further solder ball is provided on each second conductive wire, and each solder ball is electrically connected to each second conductive wire and each first solder pad.

[0033] In one best embodiment of the present invention, the substrate includes a silicon substrate, a glass substrate, or a ceramic substrate. The metal paste used by each of the first and second conductive wires includes a silver paste, a nanosilver paste, a copper paste, or a nanocopper paste.

[0034] In one best embodiment of the present invention, the thickness of the FOWLP unit is 200 μm.

[0035] In one best embodiment of the present invention, the first surface of each die is further attached to the substrate using a die attach film (DAF).

[0036] The present invention can further construct a single package by stacking multiple FOWLP units, the package including at least two FOWLP units and at least one connecting line. Each of the FOWLP units is formed by stacking them in pairs, one above the other. Each second solder pad of each of the upper FOWLP units forms a one-to-one correspondence with each first solder pad of each of the lower FOWLP units.

[0037] Each of the aforementioned connecting lines is provided between the second solder pad of each upper FOWLP unit and the first solder pad of each lower FOWLP unit, and is further electrically connected.

[0038] In one best embodiment of the present invention, each die in each of the upper FOWLP units may be identical or different in specifications and function from each die in each of the lower FOWLP units.

[0039] In one best embodiment of the present invention, each connecting line may be a solder ball. [Effects of the Invention]

[0040] In this invention, each first conductive wire is manufactured by a technique in which a metal paste is first filled into a recess, and then polished to form a conductive wire. By manufacturing and forming each wire on the second surface of the die, it is possible to effectively solve the problems of higher manufacturing costs and environmental disadvantages that tend to occur when manufacturing each conductive wire in conventional FOWLP technology modules. Furthermore, each second solder pad on the first surface of the FOWLP unit has the same arrangement as each first solder pad on the second surface of the FOWLP unit, making mass production easy. [Brief explanation of the drawing]

[0041] [Figure 1] This is a schematic side cross-sectional view of the FOWLP unit of the present invention in use. [Figure 2] This is a schematic side cross-sectional view of the base of the present invention. [Figure 3] Figure 2 is a schematic diagram of the die that will be installed on the substrate shown. [Figure 4] This is a schematic diagram of the first dielectric layer to be placed on the die shown in Figure 3. [Figure 5] This is a schematic diagram of the second conductive pillar, which is placed on the first dielectric layer shown in Figure 4. [Figure 6] This is a schematic diagram of the second dielectric layer, which is placed on top of the first dielectric layer shown in Figure 5. [Figure 7] Figure 6 is a schematic diagram showing how metal paste is filled into the recess of the second dielectric layer. [Figure 8] Figure 7 is a schematic diagram showing the process of polishing the metal paste that has risen above the surface of the second dielectric layer to form the first conductive wire. [Figure 9] This is a schematic diagram showing the placement of a third dielectric layer on top of the second dielectric layer shown in Figure 8. [Figure 10] Figure 9 is a schematic diagram showing the placement of a metal protective layer within the opening of the third dielectric layer. [Figure 11] This is a schematic side cross-sectional view showing a fourth dielectric layer being placed on the packaging unit of the present invention. [Figure 12] Figure 11 is a schematic diagram showing how metal paste is filled into the recess of the fourth dielectric layer. [Figure 13] Figure 12 is a schematic diagram showing the process of polishing the metal paste that has risen above the surface of the fourth dielectric layer to form the second conductive wire. [Figure 14] Figure 13 is a schematic diagram showing the FOWLP unit rotated by one angle. [Figure 15] This is a schematic side cross-sectional view of one embodiment of the packaging of the present invention. [Figure 16] This is a schematic side cross-sectional view of another embodiment of the packaging of the present invention. [Modes for carrying out the invention] [Examples]

[0042] Embodiments of the present invention will now be described with reference to the drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals, and in the description of these embodiments, the descriptions of the same or corresponding parts will be omitted or simplified as appropriate.

[0043] Referring to Figure 1, the present invention provides a FOWLP unit which includes a substrate 10, at least one die 20, one first dielectric layer 30, at least one second conductive pillar 40, one second dielectric layer 50, a plurality of first conductive wires 60, one third dielectric layer 70, and a plurality of metal protective layers 80.

[0044] Referring to Figure 2, the substrate 10 has one first surface 11 and one opposing second surface 12, and the substrate 10 has a plurality of first conductive pillars 13 that penetrate the first surface 11 and the second surface 12. Each of the first conductive pillars 13 is placed in each of the through holes on the substrate 10 after a plurality of through holes are formed on the substrate 10 using a through-silicon via (TSV) process.

[0045] Referring to Figure 3, each die 20 is divided from a single wafer, and each die 20 has one first surface 21 and one opposing second surface 22, the first surface 21 is fixedly mounted on the second surface 12 of the substrate 10, and the second surface 22 has a plurality of die pads 23, and the vertical range of the chips on the second surface 23 is defined as the die region 1a.

[0046] Referring to Figure 4, the first dielectric layer 30 is provided on the second surface 12 of the substrate 10 and covers each die 20. The first dielectric layer 30 has at least one through-hole 31, each through-hole 31 is formed using a through-silicon via (TSV) process, and each through-hole 31 is connected to the corresponding first conductive pillar 13.

[0047] Referring to Figure 5, each second conductive pillar 40 is formed within each through-hole 31, electrically connected to each first conductive pillar 13, and exposed to the outside through each through-hole 31.

[0048] Referring to Figure 6, the second dielectric layer 50 is provided on the first dielectric layer 30, and the second dielectric layer 50 has at least one recess 51 formed by extending horizontally. Each of the recesses 51 is connected to a corresponding second conductive pillar 40.

[0049] Referring to Figure 8, each first conductive wire 60 is provided by filling each recess 51 with metal paste 60a. Each first conductive wire 60 is electrically connected to each second conductive pillar 40.

[0050] Referring to Figure 9, the third dielectric layer 70 is provided on the second dielectric layer 50 and each of the first conductive wires 60, and the third dielectric layer 70 has at least one first opening 71. Referring to Figure 10, each of the first conductive wires 60 is exposed to the outside through each of the first openings 71, and one first solder pad 61 is formed within each of the first openings 71. The FOWLP unit 1 shown in Figure 10 is described using four of the first solder pads 61 as an example, but is not limited thereto.

[0051] Referring to Figure 10, each metal protective layer 80 is formed within each of the first openings 71. Each metal protective layer 80 is electrically connected to each of the first conductive wires 60, which is advantageous for protecting each of the first conductive wires 60 and increasing structural strength.

[0052] Referring to Figure 10, each first conductive pillar 13 is exposed to the outside from the first surface 11 of the substrate 10 and forms a second solder pad 14 on the first surface 11 of the substrate 10. The FOWLP unit 1 shown in Figure 10 is described using four second solder pads 14 as an example, but is not limited thereto.

[0053] Referring to Figure 10, each die 20 is electrically connected to the outside via each die pad 23, each first conductive wire 60, each second conductive pillar 40, each first conductive pillar 13, and each second solder pad 14 located on the substrate 10.

[0054] Referring to Figure 10, each die 20 is electrically connected to the outside via each die pad 23 of each die 20, each first conductive wire 60, each metal protective layer 80, and each first solder pad 61 around the die region 1a located on the second surface 22 of each die 20, thereby forming the FOWLP unit 1.

[0055] Referring to Figure 10, the FOWLP unit 1 further has one first surface 1b and one second surface 1c. Each of the second solder pads 14 of the substrate 10 is further located on the first surface 1b of the FOWLP unit 1. Each of the first solder pads 61 within each of the first openings 71 of the FOWLP unit 1 is further located on the second surface 1c within the FOWLP unit 1. Each of the second solder pads 14 on the first surface 1b of the FOWLP unit 1 is arranged in the same way as each of the first solder pads 61 on the second surface 1c.

[0056] The manufacturing method of the FOWLP unit 1 includes the following steps:

[0057] Step S1: Provide a substrate 10 as shown in Figure 2. The substrate 10 has one first surface 11 and one opposing second surface 12, and the substrate 10 has a plurality of first conductive pillars 13 that penetrate the first surface 11 and the second surface 12. As shown in Figure 10, each of the first conductive pillars 13 is exposed to the outside from the first surface 11 of the substrate 10, and a second solder pad 14 is formed on the first surface 11 of the substrate 10.

[0058] Step S2: As shown in Figure 3, multiple dies 20, separated from at least one wafer, are placed on each substrate 10 at intervals. Each die 20 has one first surface 21 and one opposing second surface 22, the first surface 21 is fixedly placed on the second surface 12 of the substrate 10, and the second surface 22 has multiple die pads 23, and the vertical range of the chips on the second surface 23 is defined as the die region 1a.

[0059] Step S3: A first dielectric layer 30 is laid on the second surface 12 of the substrate 10 and on each die 20, and the first dielectric layer 30 covers each die 20. Next, as shown in Figure 4, a plurality of through holes 31 are formed on the first dielectric layer 30, penetrating downwards through the first dielectric layer 30. Furthermore, as shown in Figure 5, a second conductive pillar 40 is formed in each of the through holes 31.

[0060] Step S4: A plurality of first conductive wires 60 are formed on the second surface 22 of each die 20 using a technique in which metal paste is first filled into the recesses and then polished to form conductive wires. As shown in Figure 6, first a second dielectric layer 50 is laid on the second surface 12 of the substrate 10, then a plurality of recesses 51 are formed horizontally on the second dielectric layer 50, and each second conductive pillar 40 is exposed to the outside through each recess 51. Next, as shown in Figure 7, metal paste 60a is filled into each recess 51, and the thickness of the metal paste 60a is made higher than the surface of the second dielectric layer 50. Finally, as shown in Figure 8, the metal paste 60a that is higher than the surface of the second dielectric layer 50 is polished so that the surface of the metal paste 60a is aligned with the surface of the second dielectric layer 50, thereby forming a plurality of first conductive wires 60.

[0061] Step S5: A third dielectric layer 70 is laid on the second dielectric layer 50, and then a plurality of first openings 71 are formed horizontally on the third dielectric layer 70 so that each first conductive wire 60 is exposed to the outside through each first opening 71, and finally a metal protective layer 80 is formed inside each first opening 71. As shown in Figure 9, each of the first conductive wires 60 forms a first solder pad 61 inside each first opening 71. Each metal protective layer 80 is electrically connected to each of the first conductive wires 60.

[0062] Step S6: Perform a division operation to form multiple FOWLP units 1.

[0063] Step S4 in the manufacturing method of the FOWLP unit 1 can be considered an important step for forming the RDL of the FOWLP unit 1. Since step S4 is an easy and precise process, the process can be simplified, and even when each conductive wire in the RDL is electrically extended and interconnected in the XY plane, a certain degree of lightness, thinness, and compactness can be achieved simultaneously.

[0064] Referring to Figures 13 and 14, the first surface 11 of the substrate 10 is further provided with a fourth dielectric layer 90 and a plurality of second conductive wires 10 using the RDL process. The fourth dielectric layer 90 has at least one second opening 91 formed by horizontal stretching. Each second conductive wire 100 is constructed by filling each second opening 91 with metal paste 100a. Each second conductive wire 100 is electrically connected to each second solder pad 14.

[0065] Each method for manufacturing the second conductive wire 100 further includes the following steps:

[0066] Step S1: Referring to Figure 11, first, a fourth dielectric layer 90 is laid on the first surface 11 of the substrate 10. Next, a plurality of second openings 91 are formed horizontally on the fourth dielectric layer 90, so that each second solder pad 14 can be exposed to the outside through each second opening 91.

[0067] Step S2: Referring to Figure 12, fill each of the second openings 91 with metal paste 100a, and make the thickness of the metal paste 100a greater than the surface of the fourth dielectric layer 90.

[0068] Step S3: Referring to Figure 13, the metal paste 100a, which is higher than the surface of the fourth dielectric layer 90, is polished so that the surface of the metal paste 100a is aligned with the surface of the fourth dielectric layer 90, thereby forming a plurality of second conductive wires 100.

[0069] Referring to Figure 1, a solder ball 110 is provided on each of the second conductive wires 100, and each solder ball 110 is electrically connected to each of the second conductive wires 100 and each of the first solder pads 61. The FOWLP unit 1 can be electrically connected to a PCB 3 via each of the solder balls 110, but is not limited to this.

[0070] Referring to Figure 2, the substrate 10 includes, but is not limited to, a silicon substrate, a glass substrate, or a ceramic substrate.

[0071] Referring to Figure 8, the metal pastes 60a, 100a used by each of the first and second conductive wires 60, 100 include silver paste, nanosilver paste, copper paste, or nanocopper paste.

[0072] Referring to Figure 1, the thickness of the FOWLP unit 1 is 200 μm.

[0073] Referring to Figure 3, the first surface 21 of each die 20 is further attached to the substrate 10 using a die attach film (DAF) 120.

[0074] Referring to Figures 15 and 16, a further number of FOWLP units 1 can be stacked to form a single package 2, which includes at least two FOWLP units 1 and at least one connecting line 2a.

[0075] Each FOWLP unit 1 is formed by stacking them in pairs, one above the other. Each second solder pad 14 of the upper FOWLP unit 1 forms a one-to-one correspondence with each first solder pad 61 of the lower FOWLP unit 1. The packaging 2 in Figures 15 and 16 is explained using three FOWLP units 1 as an example, but is not limited to this.

[0076] Each connecting line 2a is provided between each second solder pad 14 of one of the upper FOWLP units 1 and each first solder pad 61 of one of the lower FOWLP units 1, and by further electrical connection, the upper FOWLP unit 1 and the lower FOWLP unit 1 can be electrically connected to each other via each connecting line 2a. Each connecting line 2a may be, but is not limited to, a solder ball.

[0077] Referring to Figures 15 and 16, each die 20 in each upper FOWLP unit 1 may be identical or different in specifications and function from each die 20 in each lower FOWLP unit 1. The packaging 2 can be electrically connected on a single PCB 3 using each solder ball 110. [Explanation of Symbols]

[0078] 1. Fan-out type wafer-level packaging unit 1a Die area 1b Side 1 1c 2nd side 10 circuit boards 11 Page 1 12 Side 2 13. First conductive pillar 14. Second solder pad 20 di 21 Page 1 22 Side 2 23 Die Pad 30 First Dielectric Layer 31 Through hole 40 Second conductive pillar 50 Second dielectric layer 51 Recess 60 First conductive wire 60a Metal Paste 61 First solder pad 70 Third Dielectric Layer 71 First opening 80 Metal protective layer 90 Fourth dielectric layer 91 Second opening 100 Second conductive wire 100a Metal Paste 110 solder balls 120 Die Touch Film 2 Packaging 2a Connecting line 3 circuit boards

Claims

1. The device comprises a substrate, at least one die, one first dielectric layer, at least one second conductive pillar, one second dielectric layer, a plurality of first conductive wires, one third dielectric layer, and a plurality of metal protective layers. The substrate has one first surface and one opposing second surface, and the substrate has a plurality of first conductive pillars that penetrate the first surface and the second surface, Each die is divided from a single wafer, and each die has one first surface and one opposing second surface, the first surface of each die is fixedly mounted on the second surface of the substrate, and each die has a plurality of die pads on the second surface, and the vertical range of the chips on the second surface is defined as the die region. The first dielectric layer is provided on the second surface of the substrate and covers each die, and the first dielectric layer has at least one through hole, each of which is connected to the corresponding first conductive pillar. Each second conductive pillar is formed within each through-hole, electrically connected to each first conductive pillar, and exposed to the outside through each through-hole. The second dielectric layer is provided on the first dielectric layer, and the second dielectric layer has at least one recess formed by extending horizontally, each of which recess is connected to a corresponding second conductive pillar. Each of the first conductive wires is provided by filling each of the recesses with metal paste, and each of the first conductive wires is electrically connected to each of the second conductive pillars. The third dielectric layer is provided on the second dielectric layer and each of the first conductive wires, the third dielectric layer has at least one first opening, each of the first conductive wires is exposed to the outside through each of the first openings, and a first solder pad is formed within each of the first openings, and, Each of the metal protective layers is formed within each of the first openings, and each of the metal protective layers is electrically connected to each of the first conductive wires. Each of the first conductive pillars is exposed to the outside from the first surface of the substrate, and a second solder pad is formed on the first surface of the substrate. Each of the dies is electrically connected to the outside in order via the die pad of each die, each first conductive wire, each second conductive pillar, each first conductive pillar, and each second solder pad located on the substrate. Each die is electrically connected to the outside, in order, via each die pad, each first conductive wire, each metal protective layer, and each first solder pad around the die region located on the second surface of each die, thereby forming the FOWLP unit. The FOWLP unit further has one first surface and one second surface, each second solder pad on the substrate within the FOWLP unit is further located on the first surface of the FOWLP unit, each first solder pad within each first opening of the FOWLP unit is further located on the second surface within the FOWLP unit, and each second solder pad on the first surface of the FOWLP unit is arranged in the same way as each first solder pad on the second surface of the FOWLP unit. The method for manufacturing the FOWLP unit includes the following steps: Step S1: Provide a substrate having one first surface and one opposing second surface, and having a plurality of first conductive pillars penetrating the first surface and the second surface, each of the first conductive pillars being exposed to the outside from the first surface of the substrate, and forming a second solder pad on the first surface of the substrate. Step S2: Multiple dies, separated from at least one wafer, are placed on each substrate at intervals, each die having one first surface and one opposing second surface, the first surface of each die being fixedly mounted on the second surface of the substrate, and each die having multiple die pads on the second surface, and the vertical range of the chips on the second surface is defined as the die region. Step S3: A first dielectric layer is laid on the second surface of the substrate and on each die, and the first dielectric layer covers each die. Next, a plurality of through holes are formed on the first dielectric layer, penetrating the first dielectric layer downwards. Furthermore, a second conductive pillar is formed in each of the through holes. Step S4: First, a metal paste is filled into the recesses and then polished to form conductive wires, thereby forming a plurality of first conductive wires on the second surface of each die, first, a second dielectric layer is laid on the second surface of the substrate, then a plurality of recesses are formed horizontally on the second dielectric layer, and each second conductive pillar is exposed to the outside through each recess, then, metal paste is filled into each recess and the thickness of the metal paste is made higher than the surface of the second dielectric layer, and finally, the metal paste that is higher than the surface of the second dielectric layer is polished so that the surface of the metal paste is aligned with the surface of the second dielectric layer, thereby forming a plurality of first conductive wires. Step S5: A third dielectric layer is laid on the second dielectric layer, and then a plurality of first openings are formed horizontally on the third dielectric layer so that each first conductive wire is exposed to the outside through each first opening, and finally a metal protective layer is formed in each first opening, so that each first conductive wire forms a first solder pad in each first opening, and each metal protective layer is electrically connected to each first conductive wire, and Step S6: A fan-out type wafer-level packaging (FOWLP) unit characterized by performing a splitting operation to form multiple FOWLP units.

2. The first surface of the substrate is further provided with a redistribution layer (RDL) process, wherein the fourth dielectric layer has at least one second opening formed by horizontal stretching, each second conductive wire is constructed by filling each second opening with metal paste, and each second conductive wire is electrically connected to each second solder pad. Each of the above-mentioned methods for manufacturing the second conductive wire further includes the following steps: Step S1: First, a fourth dielectric layer is laid on the first surface of the substrate, and then, a plurality of second openings are formed horizontally on the fourth dielectric layer, so that each of the second solder pads can be exposed to the outside through each of the second openings. Step S2: Fill each of the second openings with metal paste, and make the thickness of the metal paste greater than the surface of the fourth dielectric layer, and Step S3: The FOWLP unit according to claim 1, characterized in that the metal paste, which has risen above the surface of the fourth dielectric layer, is polished so that the surface of the metal paste is aligned with the surface of the fourth dielectric layer, thereby forming a plurality of second conductive wires.

3. The FOWLP unit according to claim 2, characterized in that a further solder ball is provided on each of the second conductive wires, and each solder ball is electrically connected to each of the second conductive wires and each of the first solder pads.

4. The FOWLP unit according to claim 1, wherein the substrate includes a silicon substrate, a glass substrate, or a ceramic substrate, and the metal paste used by each of the first conductive wires includes a silver paste, a nanosilver paste, a copper paste, or a nanocopper paste.

5. The FOWLP unit according to claim 1, characterized in that the thickness of the FOWLP unit is 200 μm.

6. The FOWLP unit according to claim 2, characterized in that the metal paste used by each of the second conductive wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

7. The FOWLP unit according to claim 1, characterized in that the first surface 21 of each die is further attached to the substrate using a die attach film (DAF).

8. The FOWLP unit includes at least two of the FOWLP units and at least one connecting line, Each FOWLP unit is the FOWLP unit described in any of claims 1 to 7, and each FOWLP unit is formed by stacking them in pairs, one above the other, and each second solder pad of the upper FOWLP unit forms a one-to-one correspondence with each first solder pad of the lower FOWLP unit, and A packaging comprising a plurality of stacked FOWLP units, characterized in that each connecting line is provided between one upper FOWLP unit and one lower FOWLP unit, and the second solder pad of each upper FOWLP unit is electrically connected to the first solder pad of each lower FOWLP unit, thereby enabling the upper FOWLP units and the lower FOWLP units to be electrically connected to each other via the connecting lines.

9. The packaging according to claim 8, characterized in that each die in each of the upper FOWLP units may be the same as or different from each die in each of the lower FOWLP units in terms of specifications and function.

10. The packaging according to claim 8, characterized in that each of the aforementioned connecting lines may be a solder ball.

Images