Method for manufacturing semiconductor devices and semiconductor manufacturing apparatus

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus that can process the bottom of a hole by selective reactive ion etching. [Solution] The method for manufacturing a semiconductor device according to this embodiment involves preparing a workpiece in which a recess is formed, supplying a material containing a halogen element in a liquid state to the recess, cooling the supplied liquid to solidify it, and then etching the recess using plasma while the solidified material is present in the recess.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus. [Background technology]

[0002] When manufacturing semiconductor devices such as 3D semiconductor memory, recesses are sometimes formed in the workpiece by etching. When forming recesses, the bottom of the recess may shrink, and additional etching may be performed to widen the bottom. In this case, the etching selectivity ratio of the bottom of the recess may be low compared to the surface of the recess. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0020450 [Patent Document 2] Japanese Patent Publication No. 2022-32965 [Patent Document 3] Japanese Patent Publication No. 2016-122774 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] One embodiment of the present invention provides a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus capable of processing the hole bottom by selective reactive ion etching. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor device according to this embodiment involves preparing a workpiece in which a recess is formed, supplying a material containing a halogen element in a liquid state to the recess, cooling the supplied liquid to solidify it, and then etching the recess using plasma while the solidified material is present in the recess. [Brief explanation of the drawing]

[0006] [Figure 1] A cross-sectional view showing the structure of a semiconductor device according to the first embodiment. [Figure 2] A cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] A cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] A cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] A cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A diagram showing an example configuration of a semiconductor manufacturing apparatus according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In Figures 1 to 6, identical or similar components are denoted by the same reference numerals, and redundant descriptions are omitted. The present invention is not limited by these embodiments.

[0008] (First embodiment) Figure 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device in Figure 1 is, for example, a three-dimensional NAND memory.

[0009] Figure 1 shows a semiconductor device 100 of the first embodiment, and shows a portion of the XZ cross-section of the substrate 101, including the X-axis and the Z-axis which is perpendicular to both the X-axis and the Y-axis. As shown in Figure 1, the semiconductor device 100 comprises a substrate 101, a lower layer 102 provided on the substrate 101, insulating layers 104 and conductive layers 110 alternately stacked on the lower layer 102, an upper layer 105, a core insulating film 107, a semiconductor channel layer 108, and a memory film 109.

[0010] The memory film 109 includes a tunnel insulating film 191, a charge storage layer 192, and a block insulating film 193. The memory film 109, the semiconductor channel layer 108, and the core insulating film 107 are formed in this order in a memory hole H described later, and function as a memory layer constituting a memory cell.

[0011] An example of the substrate 101 is a wafer including a semiconductor substrate such as a silicon (Si) substrate.

[0012] Examples of the lower layer 102 are an insulating layer such as a silicon oxide film (SiO2) or a silicon nitride film (SiN), and a conductive layer formed between insulating films. An example of the insulating layer 104 is a silicon oxide film.

[0013] Examples of the upper layer 105 are an insulating film such as a silicon oxide film or a silicon nitride film, and a conductive layer formed between insulating films.

[0014] For example, a silicon oxide film can be used for the core insulating film 107.

[0015] For example, a polysilicon layer can be used for the semiconductor channel layer 108.

[0016] As the tunnel insulating film 191, for example, a laminated film having a silicon oxide film and a silicon oxynitride film (SiON) can be used. For example, a silicon nitride film can be used for the charge storage layer 192. For example, a silicon oxide film can be used for the block insulating film 193.

[0017] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. In the method for manufacturing a semiconductor device according to the first embodiment, it includes forming a memory hole H in which the memory layer described in FIG. 1 is formed.

[0018] FIGS. 2(a) to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0019] First, a semiconductor device 100 with memory holes H formed on it is prepared. Figure 2(a) shows a semiconductor device 100 having memory holes H formed by RIE (Reactive Ion Etching). The memory holes H are formed by transporting the semiconductor device 100 with the multilayer film formed on it into a known dry etching chamber or dry etching apparatus and performing RIE. At this time, etching is performed at a low temperature, for example, below 0°C, using carbon fluoride gas, hydrocarbon fluoride gas, or hydrogen fluoride gas. The semiconductor device 100 shown in Figure 2(a) is obtained by forming a lower layer 102 on a substrate 101, and forming a multilayer film on the lower layer 102 that alternately includes multiple sacrificial layers 103 and insulating layers 104. Furthermore, an upper layer 105 is formed on this multilayer film, and a hard mask layer 106 is formed on the upper layer 105.

[0020] An example of a sacrificial layer 103 is a silicon nitride film.

[0021] An example of the hard mask layer 106 is a carbon film formed by chemical vapor deposition (CVD).

[0022] When memory holes H are formed by RIE, the bottom of the memory hole H may take on a reduced shape, as shown in Figure 2(a). This occurs because by-products generated during etching of the upper and middle parts of the memory hole H adhere to the side walls of the memory hole H, hindering the processing of the bottom. A reduced shape at the bottom of a memory hole H is, for example, a shape in which the diameter of a region R with a height T2 of 1 / 5 or less of the total height T1 of the memory hole H is smaller than the diameter of other regions. Here, the bottom refers to region R. Another example of a reduced shape at the bottom of a memory hole H is a shape in which the diameter of the memory hole H continuously decreases from the top to the bottom. Here, the bottom refers to a region with a diameter less than or equal to an arbitrarily set diameter. A memory hole H is an example of a recess.

[0023] Next, as shown in FIG. 2(b), a material containing a halogen element is supplied to the memory hole H to form the liquid layer L. The formation of the liquid layer L is performed, for example, by a known spin coater. Hereinafter, the method for forming the liquid layer L will be described.

[0024] First, after RIE, the semiconductor device 100 having the memory hole H with a reduced bottom is taken out from the dry etching chamber or the dry etching apparatus. Then, the semiconductor device 100 is carried onto the spin coater stage and fixed to the spin coater stage by suction through the wafer suction path.

[0025] Next, a material containing a halogen element is dropped in a liquid state onto the fixed semiconductor device 100. The halogen element is, for example, fluorine or chlorine, and the material containing a halogen element contains, for example, at least any one of IF5, BrF3, BrF5, IFCl, or CxFy (x represents 5 or more). CxFy (x represents 5 or more.) contains, for example, C5F 10 、C5F 12 、C6F 14 、C7F 16 、C8F 18 or C9F 20 and contains at least any one of them. For example, C5F 10 is more desirable because it has a higher melting point compared to other CxFy. When the material containing a halogen element is IF5, BrF3, BrF5, C5F 10 、C5F 12 、C6F 14 、C7F 16 、C8F 18 or C9F 20 , since it is liquid at normal temperature and normal pressure, the process shown in FIG. 2(b) is performed at normal temperature and normal pressure. On the other hand, when the material containing a halogen element is IFCl, since it is not liquid at normal temperature (25°C), it may be made liquid by adjusting, such as raising the temperature of the material containing a halogen element and the semiconductor device 100.

[0026] Next, as shown in Figure 3(a), spin coating is performed. That is, the spin coater table is rotated with the liquid layer L formed on the semiconductor device 100. This allows the material containing halogen elements to be supplied into the memory holes H, and the excess liquid layer L to be removed from the surface of the semiconductor device 100.

[0027] Next, as shown in Figure 3(b), the semiconductor device 100, in which a material containing halogen elements exists as a liquid layer L within the memory hole H, is cooled to solidify the material containing halogen elements and form a solid layer S. Solidifying the material containing halogen elements has the advantages of increasing the amount of halogen elements per unit volume and making it easier to adjust the height of the solid layer S, which will be described later. In addition, solidification suppresses the reactivity that was present in the liquid phase, preventing unnecessary etching until the second processing described later. Cooling of the semiconductor device 100 is performed, for example, by using a chiller used for cooling the stage to cool the semiconductor device 100 to a temperature below the freezing point of the liquid containing halogen elements. Note that if the viscosity of the liquid layer L is high or there is no need to solidify it, it is not necessary to form a solid layer S, and the liquid layer L may remain as is.

[0028] Next, as shown in Figure 4(a), a first process is performed to adjust the solid layer S to a desired height. The first process is performed by returning the semiconductor device 100 from the spin coater stand to the dry etching chamber or dry etching apparatus.

[0029] The first process is performed using gas G1. Gas G1 is, for example, a noble gas and includes argon or helium. Gas G1 is, for example, oxygen. The choice of gas G1 depends on the material containing halogen elements; for example, if the material is IF5, BrF3, BrF5, or IFCl, ​​a noble gas is used; if it is CxFy, oxygen is used. In the first process, for example, a low voltage is applied to gas G1 to generate plasma P1, which is then irradiated onto the solid layer S to adjust the height of the solid layer S to match the target height. The target height is, for example, the height of the region R in the memory hole H where the diameter is reduced. The low voltage is, for example, several kV to tens of kV.

[0030] Figure 4(b) shows the memory holes H after the solid layer S has been adjusted to the target height by the first process. In the first process, for example, by applying a low voltage, the probability that the material contained in the solid layer S has the energy necessary to etch the lower layer 102, the sacrificial layer 103, or the insulating layer 104 is reduced, so the height of the solid layer S can be adjusted without changing the diameter of the memory holes H.

[0031] Next, a second process is performed to partially etch the sacrificial layer 103 and the insulating layer 104 to widen the bottom of the memory hole H.

[0032] The second treatment is carried out using gas G2. Gas G2 is, for example, a noble gas. Gas G2 includes, for example, argon or helium. Gas G2 may be the same gas as gas G1.

[0033] As shown in Figure 5(a), after adjusting the height of the solid layer S, in the second process, the memory holes H are etched using plasma P2 generated by applying a high voltage to gas G2, while the solid layer S is present at the bottom. The high voltage used is, for example, several tens of kV to several hundred kV.

[0034] In the second process, it is desirable to cool the semiconductor device 100 so that the solid layer S does not dissolve. When IF5 is used as the halogen material, the second process is preferably carried out at a temperature of 9.4 degrees Celsius or lower, which is the melting point of IF5. It is also preferable to cool the device appropriately to a temperature that increases etching efficiency (for example, below 0 degrees Celsius).

[0035] As a result, a memory hole H with a widened bottom is formed, as shown in Figure 5(b). Since the solid layer S is a material containing halogen elements, the presence of the solid layer S supplies halogen elements as etchants to the bottom of the memory hole H. Therefore, even etching by plasma P2 generated from gas G2 that does not contain halogen elements as etchants can widen the bottom of the memory hole H. In other words, the reduced shape of the bottom of the memory hole H is improved, and a memory hole H is formed with a diameter of approximately the same size at the top and bottom, as shown in Figure 5(b).

[0036] The first and second processes may be repeated until the depth and bottom area of ​​the memory hole H reach the desired state.

[0037] Furthermore, over-etching may be performed after these processes.

[0038] After the memory hole H is formed, a memory film 109 and a semiconductor channel layer 108 are formed in the memory hole H, and the sacrificial layer 103 is removed from a groove (not shown) and replaced with a conductive layer 110, thereby manufacturing the semiconductor device 100 shown in Figure 1.

[0039] As described above, a method for manufacturing a semiconductor device according to the first embodiment is provided.

[0040] According to the manufacturing method of a semiconductor device according to the first embodiment, the bottom of a hole can be widened by performing etching while a material containing halogen elements is present at the bottom of the hole. This method provides an etching method with a higher etching selectivity ratio for the mask layer on the surface of the semiconductor device compared to the case where plasma etching is performed for the purpose of widening the bottom of a hole when no material containing halogen elements is present at the bottom of the hole. Therefore, it is possible to reduce the required thickness of the mask layer, and furthermore, a process to protect the mask layer becomes unnecessary. In addition, since the material containing halogen elements is supplied to the semiconductor device in a liquid state, it has a higher density than in a gaseous state, so more halogen elements can be supplied to the bottom of the hole. Furthermore, the time required for phase change to solid is shorter compared to when supplied as a gas, and reactivity is easier to suppress, so unintended reactions can be prevented. In addition, by adjusting the height of the solid layer S in the first process performed at a low voltage, etching in unintended areas can be prevented.

[0041] (Second embodiment) The following describes a semiconductor manufacturing apparatus and a semiconductor device manufacturing method according to a second embodiment.

[0042] In the first embodiment, the formation of the memory hole H and the formation of the liquid layer L were described to be carried out in separate chambers or devices, but in the second embodiment, they are carried out in the same chamber. Parts common to the first embodiment will not be described.

[0043] Figure 6 shows an example of the configuration of a semiconductor manufacturing apparatus 1 that can be used in the semiconductor device manufacturing method according to the second embodiment. As shown in Figure 6, the semiconductor manufacturing apparatus 1 comprises a processing chamber 2 (i.e., a chamber), a lower electrode 3, an upper electrode 4, a liquid supply nozzle 5, a spin coater stand 6, a cooling device 7, and a gas supply unit 8.

[0044] Processing chamber 2 is a space in which the workpiece 10 can be etched (i.e., plasma etched) using RIE with plasma. An example of the workpiece 10 is the semiconductor device 100 shown in Figure 1. In processing chamber 2, holes (i.e., recesses) are formed in the workpiece 10 by etching. These holes can also be called openings. Processing chamber 2 may also have a door (gate) for loading and unloading the workpiece 10.

[0045] The lower electrode 3 functions as a mounting platform for placing the workpiece 10. The lower electrode 3 has a surface 3a on which the workpiece 10 is placed. The semiconductor manufacturing apparatus 1 may have an electrostatic chuck on the surface 3a for holding the workpiece 10.

[0046] The upper electrode 4 has a surface 4a and an opening 4b that penetrates the upper electrode 4 and introduces liquid into the processing chamber 2.

[0047] The liquid supply nozzle 5 is connected to the material supply source 51, the temperature control unit 52, and the mass flow controller 53. Liquid is supplied from the material supply source 51 to the workpiece 10 through the liquid supply nozzle 5.

[0048] The material supply source 51 contains the material that will become the first liquid. The temperature control unit 52 includes, for example, a mechanism capable of adjusting the temperature of a material containing halogen elements, such as a cooler or heater.

[0049] The first liquid is a liquid material containing a halogen element. Examples of halogen-containing liquid materials include IF5, BrF3, or IFCl. Examples of halogen-containing materials include CxFy (where x and y are integers). For example, CxFy (where x and y are integers) is C5F 10 , C5F 12 , C6F 14 , C7F 16 , C8F 18 Or C9F 20 It includes at least one of the following.

[0050] The mass flow controller 53 adjusts the flow rate of the first liquid introduced from the material supply source 51 into the processing chamber 2.

[0051] The spin coater table 6 has a wafer suction table 61 on which a workpiece 10 can be placed. The spin coater table 6 is configured to be movable vertically and to be rotatable about a vertical axis that includes the center of the concentric circles.

[0052] In a plan view, the spin coater base 6 is surrounded by the lower electrodes 3. That is, the spin coater base 6 penetrates vertically through the center of the lower electrodes 3.

[0053] The cooling device 7 includes a chiller 71 and a refrigerant pipe 72 provided inside the lower electrode 3. The chiller 71 cools the workpiece 10 on the lower electrode 3 by circulating a refrigerant through the refrigerant pipe 72.

[0054] The gas supply unit 8 comprises a gas supply source 81 such as a cylinder cabinet and a mass flow controller 82. The gas supply unit 8 supplies gas from the gas supply source 81 to the processing chamber 2.

[0055] The gas supply source 81 contains gas G1 and gas G2. Gases G1 and G2 are each contained in containers such as gas cylinders.

[0056] The mass flow controller 82 adjusts the flow rates of gas G1 and gas G2, respectively, which are introduced from the gas supply source 81 into the processing chamber 2.

[0057] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described.

[0058] In the second embodiment, similar to the first embodiment, after forming the memory holes H (Figure 2(a)), the semiconductor device 100 is loaded into the semiconductor manufacturing apparatus 1 of this embodiment. Thereafter, similar to the first embodiment, a first process is performed to supply a material containing halogen elements, adjust the material containing halogen elements to a desired height, and a second process is performed to etch the bottom of the memory holes H.

[0059] More specifically, the semiconductor device 100, on which memory holes H are formed, is brought into the processing chamber 2 and placed on the spin coater table 6 for spin coating with a halogen-containing material. With the semiconductor device 100 on the spin coater table 6, the spin coater table 6 is rotated, and the halogen-containing material in liquid form is supplied to the semiconductor device 100 from the liquid supply nozzle 5. If the halogen-containing material is solid at room temperature and pressure, the temperature control unit 52 heats the halogen-containing material to liquefy it, and then supplies it to the semiconductor device 100 (Figure 3(a)).

[0060] Next, the semiconductor device 100 is cooled by the cooling device 7 to solidify the liquid halogen-containing material. This operation forms a solid halogen-containing material at the bottom of the memory hole H, which is designated as the solid layer S (Figure 3(b)).

[0061] Next, gas G1 is supplied from the gas supply unit 8 to the processing chamber 2. For example, plasma is generated by applying a low voltage to the upper electrode 4 and the lower electrode 3, and the solid layer S is adjusted to a desired height by irradiating the solid layer S with the generated plasma (Figure 4(a)). After this, a purging process may be performed to exhaust gas G1 from inside the processing chamber 2.

[0062] Next, gas G2 is supplied from the gas supply unit 8 to the processing chamber 2. Plasma is generated by applying a high voltage to the gas G2 from the upper electrode 4 and the lower electrode 3. Using this plasma, the bottom of the memory hole H is etched while a solid layer S is present at the bottom, thereby widening the bottom of the memory hole H (Figure 5(b)).

[0063] Then, by forming the memory film 109, the semiconductor channel layer 108, and the core insulating film 107 in this order in the memory hole H, the semiconductor device shown in Figure 1 can be manufactured.

[0064] According to the method for manufacturing a semiconductor device of the second embodiment, compared to the first embodiment, the movement between the dry etching chamber or apparatus and the spin coater stand can be reduced, making it easier to maintain a constant temperature of the semiconductor device, and thus preventing the melting of materials containing solidified halogen elements.

[0065] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of symbols]

[0066] 1…Semiconductor manufacturing equipment 2…Processing chamber (chamber) 3…Lower electrode 4…Upper electrode 5…Liquid supply nozzle 6…Spin coater stand 7…Cooling device 8…Gas supply unit 10…Workpiece 51…Material supply source 52…Temperature control unit 53, 82…Mass flow controller 61…Wafer suction stand 71…Chiller 72…Refrigerant pipe 81…Gas supply source 100…Semiconductor device 101…Substrate 102…Lower layer 103…Sacrificial layer 104…Insulating layer 105…Upper layer 106…Hard mask layer 107…Core insulating film 108…Semiconductor channel layer 109…Memory film 191…Tunnel insulating film 192…Charge storage layer 193…Block insulating film H…Memory hole L…Liquid layer S…Solid layer P1, P2…Plasma

Claims

1. Prepare a workpiece in which a recess has been formed, A material containing a halogen element is supplied to the recess in a liquid state. The supplied liquid is cooled and solidified. With the solidified material present in the recess, the recess is etched using plasma. A method for manufacturing a semiconductor device.

2. Prepare a workpiece in which a recess has been formed, A material containing a halogen element is supplied to the recess to form the first layer. The height of the first layer is adjusted by the plasma generated by applying a first voltage. After adjusting the height of the first layer, the recess is etched using plasma generated by applying a second voltage higher than the first voltage while the first layer is present in the recess. A method for manufacturing a semiconductor device.

3. The method for manufacturing a semiconductor device according to claim 2, further comprising supplying the material containing the halogen element in a liquid state, cooling the liquid to a solid state, and performing the etching while the material is in a solid state.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the etching of the recess is performed using a rare gas.

5. Materials containing halogen elements are IF ５ , BrF ３ , BrF ５ A method for manufacturing a semiconductor device according to claim 1 or 2, comprising at least one of IFCl or CxFy (x≧5).

6. The material containing a halogen element is C ５ F １０ 、C ５ F １２ 、C ６ F １４ 、C ７ F １６ 、C ８ F １８ Or C ９ F ２０ The method for manufacturing a semiconductor device according to claim 1 or 2, which contains at least any one of them.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the method for supplying the material in a liquid state is spin coating by dropping the liquid onto the workpiece placed on a rotating platform and rotating the platform.

8. A method for manufacturing a semiconductor device according to claim 1 or 2, further comprising forming a memory film comprising a tunnel insulating film, a charge storage layer, and a block insulating film in the recess after the etching has been performed.

9. A processing chamber for housing the object to be processed, A rotatable spin coater table on which the workpiece to be processed is placed, The lower electrode surrounding the spin coater stand, The spin coater stand and the upper electrode positioned above the lower electrode, A liquid supply nozzle capable of supplying liquid to the workpiece, A cooling device comprising a cooling pipe positioned within the lower electrode, The system includes a gas supply unit connected to the processing chamber and capable of supplying gas to the processing chamber. Semiconductor manufacturing equipment.

10. The semiconductor manufacturing apparatus according to claim 9, configured to enable spin coating and dry etching to be performed in the same chamber.

11. A material supply source connected to the aforementioned liquid supply nozzle and containing the material, A temperature adjustment unit connected to the liquid supply nozzle and capable of adjusting the temperature of the material, The semiconductor manufacturing apparatus according to claim 9, further comprising the following:

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