Transfer data generation device, method, and program

Abstract

The present invention provides a transfer data generation device, method, and program that generate transfer data capable of reducing power consumption when a model is implemented in an arithmetic circuit. [Solution] The transfer data generation device 1000 of the present invention is a device that generates transfer data for transferring data to implement a model in an arithmetic circuit. The transfer data is composed of 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 of a power of 2, and the transfer data generation device 1000 converts the data value of the data into one of the first and second data values ​​before and after the data value of the data in the transfer data.

Description

[Technical Field]

[0001] The present invention relates to a data transfer generation device, a data transfer generation method, and a data transfer generation program for generating data to transfer when transferring data for implementing a model in an arithmetic circuit. [Background technology]

[0002] In recent years, so-called artificial intelligence has been researched, developed, and is progressing. For example, when implementing an AI model generated by machine learning into an arithmetic circuit that performs calculations such as arithmetic operations and logical operations, it is necessary to transfer data representing the AI ​​model to the arithmetic circuit. For example, if the model is composed of a neural network, data representing each weight assigned to each edge connecting each node is transferred to the arithmetic circuit.

[0003] On the other hand, in digital circuits, data values ​​are represented in binary. When the data bus for transferring data in the digital circuit is configured as a so-called pull-down, the binary number 0 is represented by a relatively low voltage value (low level, such as the ground voltage or 0[V]), and the binary number 1 is represented by a relatively high voltage value (high level, such as +5[V] or +3.3[V]). When the data bus is configured as a so-called pull-up, the representations of 1 and 0 in binary are reversed from those described above. A technology relating to data transfer using such a data bus in a digital circuit is disclosed, for example, in Patent Document 1. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-218734 [Overview of the project] [Problems that the invention aims to solve]

[0005] Incidentally, the source circuit or device, the destination circuit or device, and the data bus connecting them generally have so-called parasitic capacitance. Therefore, when switching between high and low levels, current flows through this parasitic capacitance, resulting in power consumption. For this reason, there is a demand to reduce this power consumption.

[0006] The present invention has been made in view of the above circumstances, and its purpose is to provide a transfer data generation device, a transfer data generation method, and a transfer data generation program that can generate transfer data that can reduce power consumption when a model is implemented in an arithmetic circuit. [Means for solving the problem]

[0007] As a result of various studies, the inventors have found that the above objective can be achieved by the present invention as described below. That is, a transfer data generation device according to one aspect of the present invention is a transfer data generation device that generates transfer data for transferring data to implement a model in an arithmetic circuit, wherein the transfer data comprises 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 to the power of 2, and includes a data conversion unit that converts the data value of the data to one of the first and second data values ​​before and after the data value of the data in the transfer data. In the above-described transfer data generation device, the data conversion unit converts the data value of the data to the data value of the transfer data that is closest to the data value of the data.

[0008] Such a data transfer generator converts the data into a data value comprising 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 of a power of 2. Since the data of this converted data value is used as the data transfer data, fractions that cannot be expressed as powers of 2 or fractions that cannot be expressed as 1 / 2 of a power of 2 are truncated, thereby aggregating the data into discrete values ​​and reducing the switching between Hi and Low levels. This reduces power consumption when the model is implemented in an arithmetic circuit.

[0009] In another embodiment, in the above-described data transfer device, if the data bus for transferring the data is configured as a pull-down, the data is represented by a low voltage value for the binary 0 and a high voltage value for the binary 1. If the data bus for transferring the data is configured as a pull-up, the data is represented by a high voltage value for the binary 0 and a low voltage value for the binary 1.

[0010] Such a data transfer generator can generate consecutive zeros by representing 0 and 1 as low and high levels respectively in the case of a pull-down data bus, and consecutive ones by representing 0 and 1 as high and low levels respectively in the case of a pull-up data bus. This reduces the switching between high and low levels, and therefore reduces power consumption on the data bus when implementing the model in an arithmetic circuit.

[0011] In another embodiment, in the above-described data transfer generation device, the most significant bit of the data transfer data is used as a bit representing the sign of positive or negative in the data value of the data transfer data.

[0012] Such a data transfer generator can maintain the data transfer data as is by using the most significant bit to represent positive or negative, thus retaining the effect of the data transfer. In other words, when the model is implemented in the arithmetic circuit, the above data transfer generator can reduce power consumption on the data bus.

[0013] In another aspect, in these above-described transfer data generation apparatuses, the data value 1 of the data before the conversion is fixed at a position of any bit in the bit string representing the data value of the transfer data according to the number of digits after the decimal point of the data.

[0014] Such a transfer data generation apparatus fixes the position of the bit in the data value 1 according to the number of digits after the decimal point of the data, so that the decimal data can be represented by the transfer data.

[0015] In another aspect, in these above-described transfer data generation apparatuses, among the bits in the bit string representing the data value of the transfer data, excluding the bits of the data value represented by a power of 2 and the bits of the data value represented by 1 divided by a power of 2, one of the bits is further used as a bit representing a data value.

[0016] Such a transfer data generation apparatus further uses a bit representing a data value, so that it can provide transfer data having more data values than the transfer data that does not further use a bit representing a data value.

[0017] In another aspect, in these above-described transfer data generation apparatuses, the model is a neural network, and the data is each weight of each edge in the neural network.

[0018] Such a transfer data generation apparatus can reduce the power consumption of data transfer when implementing the model of the neural network in an arithmetic circuit. In particular, in the model of the neural network in which weights are generated in machine learning, even if the weights are slightly different, the accuracy of the model does not deteriorate so much, so that truncating the fractional part has little impact on the accuracy of the model even if the weights are different.

[0019] A transfer data generation method according to another aspect of the present invention is a method for generating transfer data of the data when transferring data for implementing a model in an arithmetic circuit. The transfer data is configured to include at least one of 0, a data value represented by a power of 2, and a data value represented by a reciprocal of a power of 2. The method includes a data conversion step of converting a data value of the data into either one of first and second data values before and after in the transfer data that sandwich the data value of the data.

[0020] Such a transfer data generation method can reduce power consumption when implementing a model in an arithmetic circuit.

[0021] A transfer data generation program according to another aspect of the present invention is a program for causing a computer to function as any one of the above-described transfer data generation apparatuses.

[0022] According to this, a transfer data generation program can be provided, and this transfer data generation program exhibits the same operational effects as those of the above-described transfer data generation apparatuses.

Advantages of the Invention

[0023] The transfer data generation apparatus, transfer data generation method, and transfer data generation program according to the present invention can reduce power consumption when implementing a model in an arithmetic circuit.

Brief Description of the Drawings

[0024] [Figure 1] It is a block diagram showing the configuration of a transfer data generation apparatus in an embodiment. [Figure 2] As an example, it is a circuit diagram showing a data bus configured by Pull up. [Figure 3] As an example, it is a diagram showing transfer data generated from original data. [Figure 4] As an example, it is a diagram for explaining the relationship between the data value 1 of original data and the bit position of transfer data. [Figure 5]As another example, this is a diagram illustrating the relationship between the data value 1 in the original data and the bit position in the transferred data. [Figure 6] This diagram shows the operation of the data transfer generation device. [Figure 7] This is a diagram illustrating one embodiment. [Figure 8] This is a diagram illustrating the manner in which data is transferred from the aforementioned data transfer generation device. [Modes for carrying out the invention]

[0025] Hereinafter, one or more embodiments of the present invention will be described with reference to the drawings. However, the scope of the invention is not limited to the disclosed embodiments. In each figure, components denoted by the same reference numerals are identified as identical components, and their descriptions are omitted where appropriate. In this specification, general reference numerals are used without subscripts, while individual components are indicated by subscripts.

[0026] The transfer data generation device in this embodiment is a device that generates transfer data for transferring data to implement a model in an arithmetic circuit. The transfer data comprises 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 to the power of 2, and includes a data conversion unit that converts the data value of the data into one of the first and second data values ​​before and after the data value of the data in the transfer data. Hereinafter, such a transfer data generation device, a transfer data generation method and a transfer data generation program implemented therein will be described in more detail as an example, with the case in which the data conversion unit converts the data value of the data into the data value of the transfer data that is closest to the data value of the data.

[0027] Figure 1 is a block diagram showing the configuration of the data transfer generation device in the embodiment. Figure 2 is a circuit diagram showing a data bus configured with pull-ups as an example. Figure 3 is a diagram showing data transfer generated from the original data as an example. Figure 4 is a diagram illustrating the relationship between data value 1 of the original data and the bit position of the data transfer as an example. Figure 5 is a diagram illustrating the relationship between data value 1 of the original data and the bit position of the data transfer as yet another example.

[0028] In the embodiment, the transfer data generation device 1000 comprises, for example, a control processing unit 1 and a storage unit 5, as shown in Figure 1. In the example shown in Figure 1, it further comprises an input unit 2, an output unit 3, and an interface unit (IF unit) 4.

[0029] The input unit 2 is connected to the control processing unit 1 and is a device that inputs various commands such as commands to instruct the start of calculations, as well as various data necessary for operating the data transfer generation device 1000, such as the original data before conversion to transfer data (original data), the name of the original data, the name of the transfer data, and data bus configuration information representing the configuration of the data bus. For example, the input unit 2 is a keyboard, a mouse, or a plurality of input switches to which predetermined functions are assigned. The output unit 3 is connected to the control processing unit 1 and is a device that outputs commands, data and transfer data input from the input unit 2 according to the control of the control processing unit 1. For example, the output unit 3 is a display device such as a CRT display, LCD (liquid crystal display device), and organic EL display, or a printing device such as a printer.

[0030] The input unit 2 and output unit 3 may be configured as touch panels. In this configuration, the input unit 2 is a position input device that detects and inputs the operating position, such as a resistive or capacitive touch panel, and the output unit 3 is a display device. In this touch panel, a position input device is provided on the display surface of the display device, and one or more candidate input contents that can be input to the display device are displayed. When the user touches the display position that displays the input content they want to input, the position input device detects that position, and the display content displayed at the detected position is input to the transfer data generation device 1000 as the user's operation input. With such a touch panel, the user can easily understand the input operation intuitively, thus providing a user-friendly transfer data generation device 1000.

[0031] The IF unit 4 is connected to the control processing unit 1 and, in accordance with the control of the control processing unit 1, is a circuit that inputs and outputs data to and from external devices, for example. Examples include an RS-232C serial communication interface circuit, an interface circuit using the Bluetooth® standard, and an interface circuit using the USB standard. Alternatively, the IF unit 4 may be a communication interface circuit that sends and receives communication signals to and from external devices, such as a data communication card or a communication interface circuit conforming to the IEEE 802.11 standard.

[0032] The memory unit 5 is connected to the control processing unit 1 and is a circuit that stores various predetermined programs and various predetermined data in accordance with the control of the control processing unit 1.

[0033] The various predetermined programs mentioned above include, for example, a control processing program, which includes, for example, a control program and a data conversion program. The control program is a program that controls each of the parts 2 to 5 of the transfer data generation device 1000 according to the function of each part. The data conversion program is a program that converts the data value of the transfer data to the data value closest to the data value of the data (original data) for implementing the model in the arithmetic circuit.

[0034] The various predetermined data mentioned above include, for example, the original data before conversion to transfer data, the name of the original data, various information processing results during information processing, the transfer data obtained by converting the data values ​​of the original data, the name of the transfer data, and the data bus configuration information, as well as other data necessary for executing each of these programs. Such a storage unit 5 includes, for example, a non-volatile memory element such as ROM (Read Only Memory) or a rewritable non-volatile memory element such as EEPROM (Electrically Erasable Programmable Read Only Memory). The storage unit 5 also includes RAM (Random Access Memory), which serves as the working memory of the control processing unit 1, storing data generated during the execution of the predetermined program. Furthermore, the storage unit 5 may be configured to include a hard disk drive or solid-state drive (SSD) with a relatively large storage capacity.

[0035] The storage unit 5 functionally comprises a data information storage unit 51 and a transfer data information storage unit 52. The data information storage unit 51 stores data information representing data (original data) for implementing the model in the arithmetic circuit. The transfer data information storage unit 52 stores transfer data information representing transfer data having data values ​​obtained by converting the data values ​​of the original data. The transfer data consists of 0 and a data value 2, which is expressed as a power of 2. n and the data value 2, which is represented as 1 divided by 2. -n It includes at least one of the following (where n is a non-negative integer).

[0036] The original data (data information) may, for example, be input from the input unit 2 to the transfer data generation device 1000 and stored in the data information storage unit 51 of the storage unit 5. Alternatively, the original data may be stored (recorded) on a storage medium such as a USB memory or SD card (registered trademark), or on a recording medium such as a CD-R (Compact Disc Recordable) or DVD-R (Digital Versatile Disc Recordable), input to the transfer data generation device 1000 via the IF unit 4, and stored in the data information storage unit 51. Alternatively, the original data may be downloaded from a management server that manages it, for example, via the IF unit 4 to the transfer data generation device 1000, and stored in the data information storage unit 51.

[0037] Furthermore, the data bus configuration (data bus configuration information) may be defined, for example, during the design phase and stored in the storage unit 5 beforehand, or it may be input by a user (operator) from the input unit 2 and stored in the storage unit 5.

[0038] The control processing unit 1 is a circuit that controls each of the parts 2 to 5 of the transfer data generation device 1000 according to the function of each part, and generates transfer data from the original data. The control processing unit 1 is configured, for example, with a CPU (Central Processing Unit) and its peripheral circuits. When the control processing program is executed, the control unit 11 and the data conversion unit 12 are functionally configured in the control processing unit 1.

[0039] The control unit 11 controls each of the parts 2 to 5 of the data transfer generation device 1000 according to the function of each part, and is in charge of the overall control of the data transfer generation device 1000.

[0040] The data conversion unit 12 converts the data value of the transferred data to the data value that is closest to the data value of the data (original data) for implementing the model in the arithmetic circuit. For example, if the data value of the transferred data is 0, 1, 2, 4, 8 (0, 2 0 , 2 1 , 2 2 , 23 If the original data value is 0.7 in decimal, the original data value 0.7 is represented as the data value 2, which is the power of 2 closest to 0.7. 0 It is converted to =1, and this converted data value of 1 is used as the transferred data (original data value 0.7 → transferred data value 1). Alternatively, for example, if the original data value is 9.4 in decimal, the data value 9.4 of the original data is represented by the data value 2, which is the power of 2 closest to 9.4. 3 It is converted to =8, and this converted data value of 8 is used as the transferred data (original data value 9.4 → transferred data value 8).

[0041] Such transferred data may, for example, be represented by a low-level voltage value for a binary 0 and a high-level voltage value for a binary 1, if the data bus that transfers the data is configured as a pull-down.

[0042] Alternatively, for example, if the data bus that transfers the transfer data is configured with pull-up resistors, the transfer data may be represented by a high-level voltage value for the binary 0 and a low-level voltage value for the binary 1.

[0043] An example of a circuit when the data bus is configured with a pull-up is shown in FIG. 2. The circuit shown in FIG. 2 is a circuit related to one wiring in a parallel data bus DB having a plurality of wirings, or a circuit related to a single-wire serial data bus DB. In FIG. 2, the transmission-side circuit (transmission circuit, transmission device) TC includes a p-type MOS (Metal-oxide-Semiconductor) transistor Tr1 and an n-type MOS transistor Tr1. A power supply +Vdd is connected to the source terminal of the p-type MOS transistor Tr1, and its drain terminal is connected to the drain terminal of the n-type MOS transistor Tr2. The source terminal of the n-type MOS transistor Tr2 is grounded. Control signals are input to the gate terminal of the p-type MOS transistor Tr1 and the gate terminal of the n-type MOS transistor Tr2 from a higher-level circuit (device) not shown. The connection point PT between the drain terminal of the p-type MOS transistor Tr1 and the drain terminal of the n-type MOS transistor Tr2 becomes the output of the transmission circuit TC and is connected to the data bus DB (substrate wiring, etc.). A parasitic capacitance C1 of the transmission circuit TC is associated between the connection point PT and the data bus DB. A parasitic capacitance C2 is associated with the data bus DB. The reception-side circuit (reception circuit, reception device) RC is configured to include an amplifier Amp. The data bus DB is connected to the input of the amplifier Amp, and further connected to the power supply +Vdd via a termination resistor (pull-up resistor) Rt. A parasitic capacitance C3 of the reception circuit RC is associated between the data bus DB and the amplifier Amp. A lower-level circuit (device) not shown is connected to the output of the amplifier Amp.

[0044] And in this embodiment, the most significant bit (MSB) of the transfer data is used as a bit (sign bit) representing the positive or negative in the data value of the transfer data.

[0045] An example of the data value of the transfer data generated in this way is shown in FIG. 3. In FIG. 3, -16384 (=-2 14 ) to 16384 (=2 14Within the range of ), the possible values ​​for the data values ​​of the transferred data are represented in binary and decimal. In this example, the exponents of powers of 2 are consecutive integers. In a plan view, the upper left column of Figure 3 shows positive numbers when the data bus is configured as a Pull Down, and the lower left column of Figure 3 shows negative numbers when the data bus is configured as a Pull Down. In a plan view, the upper right column of Figure 3 shows positive numbers when the data bus is configured as a Pull Up, and the lower right column of Figure 3 shows negative numbers when the data bus is configured as a Pull Up. When the data bus is configured as a Pull Down, the sign bit indicating that the data value of the transferred data is positive is set to binary 0, and the sign bit indicating that the data value of the transferred data is negative is set to binary 1, so that there are consecutive zeros. When the data bus is configured as a Pull Up, the sign bit representing a positive data value is binary 1, and the sign bit representing a negative data value is binary 0, so that there are consecutive ones. For example, the decimal number 8 becomes 0000000000001000 in binary when the data bus is configured as a Pull Down, and 1111111111110111 in binary when the data bus is configured as a Pull Up. Alternatively, for example, the decimal number -8 becomes 1000000000001000 in binary when the data bus is configured as a Pull Down, and 01111111111110111 in binary when the data bus is configured as a Pull Up.

[0046] In the example shown in Figure 3, the data bus is composed of 16 wires and the transferred data is represented by 16 bits. However, the number of wires in the data bus and the number of bits in the transferred data can be arbitrary.

[0047] Furthermore, in the example shown in Figure 3, the range was -16384 to 16384 in decimal, but the range of data values ​​for the transferred data may be set appropriately according to the range of data values ​​for the original data. For example, if the data values ​​for the original data are in the range of -1000 to 1000 in decimal, the range of data values ​​for the transferred data may be, for example, -1024 (=-2 10 )~1024(=2 10 The value is set to within the range of ). In this case, the number of bits of the transferred data can be represented by 12 bits, including the bit for the data value 0 and the sign bit. However, if the number of bits of the transferred data is greater than 12 bits, for example 16 bits, then decimal data values ​​can also be represented. Note that even if the number of bits of the transferred data is greater than 12 bits, for example 16 bits, the transferred data does not have to include decimal data values ​​(i.e., the four upper bits below the most significant bit are 0000).

[0048] When representing this decimal data value, the original data's data value 1 may be fixed to one of the bit positions (bit position) in the bit sequence representing the data value of the transferred data, depending on the number of decimal digits in the data. For example, as shown in Figure 4, if the original data contains a data value with 4 decimal digits, the original data's data value 1 may be fixed to the 5th bit position out of 16 bits (second embodiment (Q4 notation [B])), or, for example, if the original data contains a data value with 8 decimal digits, the original data's data value 1 may be fixed to the 9th bit position out of 16 bits (third embodiment (Q8 notation [C])), or, for example, if the original data contains a data value with 12 decimal digits, the original data's data value 1 may be fixed to the 13th bit position out of 16 bits (fourth embodiment (Q12 notation [A])). Figure 4 also shows the first embodiment (Q0 notation [A]), as shown in Figure 3, which does not contain decimal data, where the original data's data value 1 is fixed to the 1st bit position out of 16 bits.

[0049] In such cases, the possible data values ​​of the transferred data include decimal data values ​​represented as 1 / 2 to the power of 2, depending on the bit position in the transferred data corresponding to the data value 1 of the original data. Therefore, even if the values ​​are the same in binary, they will be different in decimal depending on the bit position in the transferred data corresponding to the data value 1 of the original data. In these first to fourth embodiments, for example, 0000000000000100 in binary becomes 4 in decimal in the first embodiment, and 0.25 (=1 / 2) in decimal in the second embodiment. 2 ) and in the third aspect, it becomes 0.015625 in decimal (=1 / 2 6 ) and in the fourth aspect, 0.0009765625 = (1 / 2 10 ) Or for example, the binary number 0000000010000000 becomes 128 in decimal in the first mode, 4 in decimal in the second mode, and 0.5 (=1 / 2) in decimal in the third mode. 1 ) and in the fourth aspect, it becomes 0.03125 in decimal (=1 / 2 5 )

[0050] Furthermore, as described above, for example, as shown in Figure 5, one bit from the bit string representing the data value of the transfer data, excluding the bits representing the data value expressed as a power of 2 and the bits representing the data value expressed as 1 / 2, may be further used as a bit representing the data value (modified form). For example, the least significant bit (LSB) of the transfer data may be further used as a bit representing the data value. Note that the bit position of the bit representing the data value is not limited to the least significant bit, but may be any other bit position. Since such a transfer data generation device 1000 further uses a bit representing the data value, it can provide transfer data with a larger data value than transfer data that does not further use a bit representing the data value.

[0051] The possible data values ​​of such transferred data are determined (defined) by determining (defining) the number of bits in the transferred data and the bit position of the data value 1. Its representation using 0s and 1s is determined (defined) by the configuration of the data bus, and its sign is represented by the sign bit of the most significant bit.

[0052] On the other hand, the source data for implementing a model in a computational circuit is usually multiple. For example, if the model is a neural network, the neural network comprises multiple nodes and multiple edges connecting the multiple nodes, and each edge is assigned a weight. The source data consists of the weights of each edge in the neural network.

[0053] More specifically, the data conversion unit 12 first determines the numerical range of the source data for implementing the model in the arithmetic circuit. Next, the data conversion unit 12 determines the bit position of data value 1 according to the number of decimal places in the source data. The number of decimal places can be determined by multiplying the absolute value of the source data by 10, finding an integer that does not exceed the absolute value of the source data multiplied by 10, subtracting the found integer from the absolute value of the source data multiplied by 10, repeating this subtraction result as the new source data until the subtraction result becomes 0, and counting the number of repetitions of the process. For example, in the case of 0.25 in decimal, in the first process, |0.25|×10-INT(|0.25|×10)=0.5, and in the second process, |0.5|×10-INT(|0.5|×10)=0, resulting in 2 decimal places. Note that INT(x) is an operator that finds an integer that does not exceed x. The data conversion unit 12 then determines the number of bits (digits in binary) in the bit sequence representing the data value of the transferred data, based on the numerical range of the original data and the bit position of data value 1. This determines the bit position and the number of bits (bit count) of data value 1 in the transferred data, and thus determines the data values ​​that the transferred data can take. For example, the data conversion unit 12 finds the maximum absolute value in the numerical range of the original data, finds a number that exceeds the maximum value and is closest to the maximum value, and adds 1 to the exponent of the found number (2 0 (Because it includes =1), the number of bits up to the bit position of the data value 1 is added to this addition result (first addition result), and 1 for the sign bit is further added to this addition result (second addition result). This addition result (third addition result) is the number of bits (number of digits in binary) of the data to be transferred. For example, if the exponent is 8 and the number of bits up to the bit position of the data value 1 is 2, the number of bits (number of digits in binary) of the data to be transferred is 8+1+2+1=12. Alternatively, for example, the data conversion unit 12 may find the maximum value in absolute value within the numerical range of the original data, find a power of 2 that is closest to the maximum value and does not exceed the maximum value, and obtain the first addition result by adding 1 to the exponent of the found number.

[0054] In the above example, the bit position of data value 1 was determined by the data conversion unit 12, but it may also be set (determined) by the user (operator) by inputting it from the input unit 2. Also, in the above example, there is no limit to the number of bits in the transferred data, but the number of bits in the transferred data may be limited. The limit on the number of bits in the transferred data may be specified (defined) at the design stage and stored in the storage unit 5 in advance, or it may be input by the user (operator) from the input unit 2 and stored in the storage unit 5. In this case, for example, from the limited number of bits in the transferred data, 2 0 A total of 2 is subtracted, consisting of 1 for the sign bit and 1 for the sign bit. The result of this subtraction is divided according to the ratio of the exponent of the calculated number to the number of bits up to the bit position of data value 1, thereby rearranging the bit position of data value 1 and determining the data value that the transferred data can take. Alternatively, for example, the bit position of data value 1 takes precedence, and the bit position of data value 1 is determined as is, thereby determining the data value that the transferred data can take. Alternatively, for example, the exponent of the calculated number takes precedence, and the bit position of data value 1 is rearranged according to the exponent of the calculated number, thereby determining the data value that the transferred data can take.

[0055] Next, once the possible data values ​​for the data to be transferred are determined (defined), the data conversion unit 12 converts the data value of the data to the data value of the transferred data that is closest to the data value of the data. More specifically, the data conversion unit 12 obtains the sign of positive or negative in the data value of the data and finds a data value that is closest in absolute value to the data value of the data, expressed as a power of 2 or 1 / 2 of a power of 2.

[0056] Then, the data conversion unit 12 determines (specifies) whether to represent the binary 0 in the transfer data with a Low-level voltage value or a High-level voltage value, depending on the configuration of the data bus, and generates transfer data having a data value obtained by converting the data value of the data based on the obtained positive or negative sign and the data value obtained which is the nearest 0, power of 2, or 1 / 2 of the data value.

[0057] The data value of the transferred data can be determined (certified) based on the value of the sign bit (MSB), the configuration of the data bus, and the bit position of data value 1.

[0058] The control processing unit 1, input unit 2, output unit 3, IF unit 4, and storage unit 5 in such a data transfer device 1000 can be configured by, for example, a desktop or notebook computer.

[0059] Next, the operation of this embodiment will be described. Figure 6 is a flowchart showing the operation of the data transfer generation device.

[0060] When the power is turned on, the data transfer generator 1000 with this configuration performs the initialization of each necessary part and starts operating. The control processing unit 1 is functionally configured with a control unit 11 and a data conversion unit 12 through the execution of its control processing program.

[0061] In Figure 6, first, the data transfer generation device 1000, through the data conversion unit 12 of the control processing unit 1, determines the numerical range of the original data for implementing the model in the arithmetic circuit, which is stored in the data information storage unit 51 of the storage unit 5, and stores it in the storage unit 5 (S1).

[0062] Next, the data transfer generator 1000 uses the data conversion unit 12 to determine the bit position of data value 1 and stores it in the storage unit 5 (S2). Note that if the bit position of data value 1 is already stored in the storage unit 5, this process S2 can be omitted.

[0063] Next, the data transfer generation device 1000 determines the possible data values ​​of the data transfer data using the data conversion unit 12 (S3).

[0064] Next, the data transfer generation device 1000 uses the data conversion unit 12 to obtain the k-th original data from the original data stored in the data information storage unit 51 of the storage unit 5 (S4). k is a counter variable that counts the number of original data, and is initialized to 1 during the initialization. Note that each original data is assigned a serial number from 1 as an identifier (original data ID) to identify and distinguish the original data, and k may be a variable representing the original data ID.

[0065] Next, the data transfer generation device 1000 uses the data conversion unit 12 to obtain the sign of the acquired original data, finds a data value that is closest in absolute value to the data value of the data, expressed as 0, a power of 2, or 1 / 2 of a power of 2, and stores it in the storage unit 5 (S5).

[0066] Next, the transfer data generation device 1000 generates transfer data (S6) with a data value obtained by converting the data value of the data based on the processing result of process S5 and the configuration of the data bus, using the data conversion unit 12. For example, if the numerical range of the original data is -17000 to 17000, the bit position of data value 1 is the least significant bit, the data bus configuration is Pull Down, and the original data is 893 in decimal, the decimal original data 893 is converted to the binary transfer data 0000010000000000.

[0067] Next, the transfer data generation device 1000 determines, via the data conversion unit 12, whether or not transfer data has been generated for all the original data stored in the data information storage unit 51 (S7). If the result of this determination is that transfer data has been generated for all the original data (Yes), the transfer data generation device 1000 outputs each of the converted transfer data to the output unit 3 via the data conversion unit 12, stores it in the transfer data information storage unit 52 of the storage unit 5 (S8), and terminates this process. On the other hand, if the result of the above determination is that transfer data has not been generated for all the original data (No), the transfer data generation device 1000 increments the counter variable k by 1 via the data conversion unit 12 (S9, k←k+1), and returns to process S4 in order to convert the next original data into transfer data. Note that in process S8, the data conversion unit 12 may, if necessary, output each of the converted transfer data to an external device via the IF unit 4.

[0068] In this way, when transferring data (original data) for implementing the model into an arithmetic circuit, the transfer data of the aforementioned data (original data) is generated.

[0069] An embodiment will be described. Figure 7 is a diagram illustrating an embodiment. In Figure 7, the column on the left side of the page (column 1) shows each original data in decimal, the column adjacent to column 1 on the right side of the page (column 2) shows each transferred data in decimal, obtained by converting each original data in column 1, the column adjacent to column 2 on the right side of the page (column 3) shows each transferred data in column 2 in binary (i.e., a bit string to represent the data value of the transferred data), and the column adjacent to column 3 on the right side of the page (column 4) shows the number of switches between 0 and 1 when transferring data sequentially from the first row of transferred data to the last row of transferred data (not shown) on a parallel data bus. In this embodiment, when transferring data that represents the original data as is in binary, the number of switches between 0 and 1 was 1727, but when transferring transferred data, the number of switches between 0 and 1 was reduced to 284. This reduces the current flowing through parasitic capacitances, for example, thereby reducing power consumption.

[0070] As described above, the transfer data generation device 1000 and the transfer data generation method and transfer data generation program implemented therein in the embodiment convert the data value of the original data into a data value comprising 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 of a power of 2, and uses this converted data value as the transfer data. By truncating fractions that cannot be expressed as powers of 2 or fractions that cannot be expressed as 1 / 2 of a power of 2, the original data is aggregated into discrete values, resulting in the transfer data with reduced switching between Hi and Low levels. Therefore, when implementing the model in an arithmetic circuit on a parallel data bus or a serial data bus, power consumption can be reduced. Even when transferring the transfer data alone, the switching is reduced, and power consumption can be reduced.

[0071] The above-described data transfer device 1000, data transfer method, and data transfer program can reduce the switching between high and low levels, as they can reduce power consumption on the data bus when implementing a model in an arithmetic circuit. This is because, in the case of a pull-down data bus, 0 and 1 can be represented as low and high levels respectively, allowing for a continuous sequence of 0s, and in the case of a pull-up data bus, 0 and 1 can be represented as high and low levels respectively, allowing for a continuous sequence of 1s.

[0072] The above-described data transfer generation device 1000, data transfer generation method, and data transfer generation program maintain the data transfer data as is by using the most significant bit as a sign bit representing positive or negative, thereby obtaining the benefits of the data transfer. In other words, the above-described data transfer generation device 1000, data transfer generation method, and data transfer generation program can reduce power consumption on the data bus when the model is implemented in the arithmetic circuit.

[0073] The above-described transfer data generation device 1000, transfer data generation method, and transfer data generation program fix the bit position in the data value 1 of the data according to the number of decimal digits of the data, so that decimal data can be represented in the transfer data.

[0074] Since the above-described transfer data generation device 1000, transfer data generation method, and transfer data generation program further use bits that represent data values, they can provide transfer data with more data values ​​than transfer data that does not further use bits that represent data values.

[0075] The above-described data transfer generation device 1000, data transfer generation method, and data transfer generation program can reduce power consumption during data transfer when a neural network model is implemented in an arithmetic circuit. In particular, in a neural network model in which weights are generated by machine learning, the accuracy of the model does not deteriorate significantly even if the weights are slightly different, so truncating the fractional parts and having different weights has little effect on the accuracy of the model. Therefore, the above-described data transfer generation device 1000, data transfer generation method, and data transfer generation program can reduce power consumption during weight data transfer while suppressing deterioration of the model's accuracy.

[0076] The following describes the case in which a model is implemented in an arithmetic circuit using the transfer data generated by the above-described transfer data generation device 1000, transfer data generation method, and transfer data generation program.

[0077] Figure 8 is a diagram illustrating the mode of transferring data from the data transfer generation device. Figure 8A shows the first mode of data transfer, and Figure 8B shows the second mode of data transfer.

[0078] When a model is implemented in an arithmetic circuit using transferred data, for example, as shown in Figure 8A, the transferred data generated by the transferred data generation device 1000 is stored in the external memory circuit EM of the arithmetic circuit AC. The arithmetic circuit AC is a circuit that performs calculations such as arithmetic operations and logical operations, and is composed of an integrated circuit such as an inference LSI or FPGA (Field Programme Gate Array) and its peripheral circuits. The external memory circuit EM is connected to the arithmetic circuit AC by a data bus, stores predetermined data, and outputs predetermined data to the arithmetic circuit AC. The external memory circuit EM is composed of a memory element (memory circuit) such as a rewritable non-volatile memory element such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a volatile memory element such as a RAM (Random Access Memory) and its peripheral circuits. When a model is implemented in the arithmetic circuit AC, the external memory circuit EM transfers the transferred data stored as the predetermined data to the arithmetic circuit AC. As a result, the arithmetic circuit AC implements a model, and the arithmetic circuit AC uses the model to infer (predict) the output for a given input.

[0079] Alternatively, as shown in Figure 8B, for example, the data transfer generator 1000 is connected to the arithmetic circuit AC by a data bus. When a model is implemented in the arithmetic circuit AC, the data transfer generator 1000 transfers the data transfer stored in the data transfer information storage unit 52 to the arithmetic circuit AC. As a result, the model is implemented in the arithmetic circuit AC, and the arithmetic circuit AC uses the model to infer (predict) the output for a given input, for example. The data transfer generator 1000 may also function as an external memory circuit EM for the arithmetic circuit AC.

[0080] Alternatively, for example, as shown by the dashed line in Figure 1, the transfer data generation device 1000 may functionally further include a model unit 13 for implementing a model in the control processing unit 1. In this case, the transfer data is read from the transfer data information storage unit 52 to the control processing unit 1, and the model is implemented in the model unit 13. As a result, the transfer data generation device 1000 uses the model unit 13 to infer (predict) the output for a given input. The transfer data generation device 1000 may also function as an arithmetic circuit AC and an external memory circuit EM.

[0081] In the above embodiment, the data conversion unit 12 converted the data value of the transferred data to the data value of the original data that was closest to the original data's data value. However, it may also convert the data value of the original data to either the first or second data value before or after the original data value in the transferred data ((first data value) < (second data value)). More specifically, for a data value A of a single transferred data, a lower limit Nd and an upper limit Nu are set in the numerical range RG that includes this data value A. If the data value a of the original data exceeds the lower limit Nd and is less than or equal to the upper limit Nu (or if the data value a of the original data is greater than or equal to the lower limit Nd and less than the upper limit Nu), the data value a of the original data is converted to the data value A of the transferred data. Each numerical range RGk in each of the data values ​​Ak of ​​a plurality of consecutive k transferred data is set to be consecutive without overlapping with each other. By setting the lower limit Nu and upper limit Nd such that the first subtraction result (obtained by subtracting the data value A of the transferred data from the upper limit Nu) and the second subtraction result (obtained by subtracting the lower limit Nd from the data value A of the transferred data) are different ((value of the first subtraction result) ≠ (value of the second subtraction result)), the designer (user) can design whether to convert the data value of the original data to the first data value of the transferred data, or to convert the data value of the original data to the second data value of the transferred data, according to their intentions. This is expected to improve inference accuracy when the model is a neural network. Note that the above embodiment assumes that the data value A of the transferred data is located in the middle of the numerical range RG, and that the first subtraction result and the second subtraction result are the same.

[0082] To illustrate the present invention, the embodiments have been adequately and fully described above with reference to the drawings. However, those skilled in the art should recognize that it is easy to modify and / or improve upon the embodiments described above. Therefore, unless such modifications or improvements implemented by those skilled in the art fall outside the scope of the claims, such modifications or improvements shall be considered to be included within the scope of the claims. [Explanation of Symbols]

[0083] EM external memory circuit AC Calculation Circuit 1000 Transfer Data Generation Device 1 Control Processing Unit 5 Storage section 11 Control Unit 12 Data conversion section 13 Model Section 51 Data Information Storage Unit 52 Transfer data information storage unit

Claims

1. A data transfer generation device that generates data for transferring data when transferring data to implement a model in an arithmetic circuit, The aforementioned transfer data comprises 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 to the power of 2. The system includes a data conversion unit that converts the data value of the aforementioned data into either one of the first or second data values ​​before or after the data value of the aforementioned data in the transferred data. Data transfer generation device.

2. The data conversion unit converts the data value of the data to the data value of the transferred data that is closest to the data value of the data. The data transfer generation device according to claim 1.

3. If the data bus that transfers the aforementioned data is configured as a Pull Down, the aforementioned data is represented by a Low-level voltage value for the binary 0 and a High-level voltage value for the binary 1. If the data bus that transfers the aforementioned data is configured as a pull-up, the aforementioned data is represented by a high-level voltage value for the binary 0 and a low-level voltage value for the binary 1. The data transfer generation device according to claim 1.

4. The most significant bit of the aforementioned transferred data is used as a bit representing the sign of positive or negative in the data value of the transferred data. The data transfer generation device according to claim 1.

5. The data value 1 of the data before conversion is fixed at the position of one of the bits in the bit sequence representing the data value of the transferred data, according to the number of decimal places in the data. The data transfer generation device according to claim 1.

6. In the bit sequence representing the data value of the aforementioned transferred data, one bit, excluding the bits representing the data value expressed as a power of 2 and the bits representing the data value expressed as 1 / 2, is further used as a bit representing the data value. The data transfer generation device according to claim 1.

7. The aforementioned model is a neural network, The aforementioned data is the weight of each edge in the neural network, The data transfer generation device according to claim 1.

8. A method for generating transfer data to generate data for implementing a model in an arithmetic circuit, wherein the data is transferred to generate the data to be transferred. The aforementioned transfer data comprises 0 and at least one of a data value expressed as a power of 2 and a data value expressed as 1 / 2 to the power of 2. The data conversion step includes converting the data value of the aforementioned data into either one of the first and second data values ​​before or after the data value of the aforementioned data in the transferred data. Method for generating transfer data.

9. A transfer data generation program for causing a computer to function as a transfer data generation device according to claims 1 to 7.

Images