Semiconductor equipment

Abstract

The objective is to provide a technology that can increase the effective area of ​​semiconductor devices and reduce gate signal delay. [Solution] The semiconductor device 100 comprises a semiconductor substrate 1 having defined active region 2 and termination region 3 which is the region outside the active region 2; a first gate pad 4 located in the center of the first side of the active region 2; a first gate wiring 5 connected to the first gate pad 4 and extending in a first direction; first gate signal lines 6, 7 connected to the first gate pad 4 or the first gate wiring 5 and extending in a second direction; a second gate pad 14 located at the corner of the first side of the active region 2; a second gate wiring 15 connected to the second gate pad 14 and having a portion extending in a first direction; and second gate signal lines 16, 17 connected to the second gate pad 14 or the second gate wiring 15 and extending in a second direction. The second gate wiring 15 extends along the boundary between the active region 2 and the termination region 3.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] For example, in a conventional semiconductor device described in Patent Document 1 or the like, an active region in which semiconductor elements are formed, a gate pad arrangement region formed at a position adjacent to the active region, and a termination region which is an outer region of the active region and the gate pad arrangement region are defined on a semiconductor substrate. A first gate pad is arranged at one end in a first direction of the gate pad arrangement region, and a first gate wiring extending in a second direction which is a direction intersecting the first direction is connected to the first gate pad. Also, a second gate pad is arranged at the other end in the first direction of the gate pad arrangement region, and a second gate wiring extending in the second direction is connected to the second gate pad. Further, a first gate signal line extending in the first direction is connected to the first gate wiring, and a second gate signal line extending in the first direction is connected to the second gate wiring.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, since the first and second gate signal lines are not arranged in the gate pad arrangement region defined in the conventional semiconductor device and no output current flows, the gate pad arrangement region becomes an ineffective region. Therefore, due to the small effective area of the conventional semiconductor device, there is a problem that the on-resistance becomes large and the conduction loss becomes large.

[0005] Furthermore, the first and second gate pads, first and second gate wiring, and first and second gate signal lines form a comb shape when viewed from above. Because the first and second gate signal lines extend from one end to the other in the first direction within the active region, the gate resistance of the first and second gate signal lines increases. As a result, there was a problem of large delay in each gate signal from the first and second gate pads to the ends of the first and second gate signal lines.

[0006] Therefore, the present disclosure aims to provide a technology that can increase the effective area of ​​a semiconductor device and reduce the delay of gate signals. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises a semiconductor substrate having an active region on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a termination region which is an area outside the active region; a first gate pad disposed in the center of the first side of the active region; a first gate wiring connected to the first gate pad and extending in a first direction; a first gate signal line connected to the first gate pad or the first gate wiring and extending in a second direction which intersects the first direction; a second gate pad disposed at the corner of the first side of the active region; a second gate wiring connected to the second gate pad and having a portion extending in the first direction; and a second gate signal line connected to the second gate pad or the second gate wiring and extending in the second direction, wherein the second gate wiring extends along the boundary between the active region and the termination region. [Effects of the Invention]

[0008] According to this disclosure, first and second gate pads are arranged in the active region, and first and second gate signal lines are also arranged between the first and second gate pads. As a result, output current flows between the first and second gate pads, making the region between the first and second gate pads an effective region. Therefore, the effective region of the semiconductor device is expanded.

[0009] Furthermore, since the first gate pad is located in the center of the first side of the active region and the second gate pad is located at the corner of the first side of the active region, the length of the first and second gate signal lines placed between the first and second gate pads is shorter compared to the case where the first and second gate signal lines extend from one end to the other in the first direction of the active region. As a result, the gate resistance of the first and second gate signal lines is reduced, and the delay of each gate signal from the first and second gate pads to the ends of the first and second gate signal lines can be reduced. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic top view illustrating each region defined on the semiconductor substrate of the semiconductor device according to Embodiment 1. [Figure 2] This is a schematic top view of a semiconductor device according to Embodiment 1. [Figure 3] This is an enlarged view corresponding to area A in Figure 2 in a modified example of Embodiment 1. [Figure 4] This is an enlarged view of region B in Figure 2. [Figure 5] This is a schematic top view of a semiconductor device according to Embodiment 2. [Figure 6] This is an enlarged view of region C in Figure 5. [Figure 7] This is a schematic top view of a semiconductor device according to a modified example of Embodiment 2. [Figure 8] This is a schematic top view of a semiconductor device related to the relevant technology. [Modes for carrying out the invention]

[0011] <Embodiment 1> Embodiment 1 will be described below with reference to the drawings. Figure 1 is a schematic top view illustrating each region defined on the semiconductor substrate 1 of the semiconductor device 100 according to Embodiment 1.

[0012] In FIG. 1, the X direction, the Y direction, and the Z direction are orthogonal to each other. The X direction, the Y direction, and the Z direction shown in the following figures are also orthogonal to each other. In the following, the direction including the X direction and the -X direction which is the opposite direction of the X direction is also referred to as the "X-axis direction". Also, in the following, the direction including the Y direction and the -Y direction which is the opposite direction of the Y direction is also referred to as the "Y-axis direction". Also, in the following, the direction including the Z direction and the -Z direction which is the opposite direction of the Z direction is also referred to as the "Z-axis direction".

[0013] As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 1. In the semiconductor substrate 1, an active region 2 and a termination region 3 are defined. The active region 2 is a region where semiconductor elements (not shown) are formed. The active region 2 is formed in a rectangular shape in a top view, and the top view contour of the active region 2 includes a side in the -Y direction (corresponding to the first side), a side in the Y direction (corresponding to the second side), a side in the -X direction (corresponding to the third side), and a side in the X direction (corresponding to the fourth side). The termination region 3 is an outer region of the active region 2, in other words, an outer region of the first side, the second side, the third side, and the fourth side, and is formed in a frame shape.

[0014] Here, the semiconductor element is an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like.

[0015] Next, the details of the semiconductor device 100 will be described. FIG. 2 is a schematic top view of the semiconductor device 100 according to Embodiment 1. As shown in FIG. 2, the semiconductor device 100 further includes a first gate pad 4, a first gate wiring 5, first gate signal lines 6, 7, a second gate pad 14, a second gate wiring 15, and second gate signal lines 16, 17.

[0016] The first gate pad 4 is disposed at the center of the -Y direction side of the active region 2. The first gate wiring 5 is connected to the first gate pad 4 and extends from the first gate pad 4 in the Y-axis direction (corresponding to the first direction) to the vicinity of the Y-direction side of the active region 2. The first gate signal line 6 is connected to the first gate pad 4 and extends in the X-axis direction (corresponding to the second direction), which is a direction intersecting the Y direction. The first gate signal line 7 is connected to the first gate wiring 5 and extends in the X-axis direction.

[0017] The second gate pad 14 is disposed at the corner of the -Y direction side of the active region 2. The corner of the -Y direction side of the active region 2 is the connection portion between the -Y direction side and the -X direction side or the X direction side of the active region 2. In FIG. 2, the second gate pad 14 is disposed at the -X direction corner, but it may be disposed at the X direction corner instead. The second gate wiring 15 is connected to the second gate pad 14, has a portion extending in the Y-axis direction, and extends along the boundary between the active region 2 and the termination region 3. In other words, the second gate wiring 15 extends along the -X direction side, the Y direction side, the X direction side, and the -Y direction side of the active region 2. The second gate signal line 16 is connected to the second gate pad 14 and extends in the X-axis direction. The second gate signal line 17 is connected to the second gate wiring 15 and extends in the X-axis direction.

[0018] The first gate pad 4, the first gate wiring 5, the second gate pad 14, and the second gate wiring 15 are all composed of a polysilicon thin film and a metal thin film. With this configuration, the gate resistance connected between the first gate pad 4 and the first gate wiring 5 and between the second gate pad 14 and the second gate wiring 15 can be reduced. Also, although not shown, gate resistances may be built in between the first gate pad 4 and the first gate wiring 5 and between the second gate pad 14 and the second gate wiring 15.

[0019] The first gate signal line 6 and the second gate signal line 16 are alternately arranged in the Y-axis direction between the first gate pad 4 and the second gate pad 14, and between the first gate pad 4 and the second gate wiring 15. Furthermore, the first gate signal line 7 and the second gate signal line 17 are alternately arranged in the Y-axis direction between the first gate wiring 5 and the portion of the second gate wiring 15 that extends along the -X-direction side.

[0020] Figure 3 is an enlarged view corresponding to area A in Figure 2 in a modified example of Embodiment 1. As shown in Figure 3, a dummy gate signal line 27 may be placed between the first gate signal line 7 and the second gate signal line 17, which are positioned between the first gate wiring 5 and the portion of the second gate wiring 15 that extends along the -X direction. The dummy gate signal line 27 is connected to an emitter electrode (ground potential), which is not shown.

[0021] Figure 4 is an enlarged view of region B in Figure 2. As shown in Figure 4, the distance A2 between the first gate pad 4 and the second gate wiring 15 is 10 μm or more. This is to suppress interference between the gate signal flowing through the first gate pad 4 and the gate signal flowing through the second gate wiring 15.

[0022] Next, the operation and effects of Embodiment 1 will be explained in comparison with the case of related technologies. Figure 8 is a schematic top view of a semiconductor device 101 related to the related technology.

[0023] As shown in Figure 8, in the semiconductor device 101 relating to the related technology, the semiconductor substrate 1 is defined as having an active region 2, a gate pad placement region 10 formed adjacent to the active region 2, and a termination region 3 which is the region outside the active region 2 and the gate pad placement region 10. A first gate pad 4 is placed at the X-direction end of the gate pad placement region 10, and a first gate wiring 5 extending in the Y-axis direction is connected to the first gate pad 4. A second gate pad 14 is placed at the -X-direction end of the gate pad placement region 10, and a second gate wiring 15 extending in the Y-axis direction is connected to the second gate pad 14. Furthermore, a first gate signal line 7 extending in the X-axis direction is connected to the first gate wiring 5, and a second gate signal line 17 extending in the X-axis direction is connected to the second gate wiring 15.

[0024] Since the first and second gate signal lines 7 and 17 are not located in the gate pad placement area 10 and no output current flows through it, the gate pad placement area 10 becomes an inactive area. Therefore, the small effective area of ​​the semiconductor device 101 resulted in a large on-resistance and high conduction loss.

[0025] In contrast, as shown in Figure 2, in Embodiment 1, the semiconductor device 100 comprises a semiconductor substrate 1 on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a termination region 3 which is the region outside the active region 2; a first gate pad 4 located in the center of the -Y direction side of the active region 2; a first gate wiring 5 connected to the first gate pad 4 and extending in the Y-axis direction; first gate signal lines 6, 7 connected to the first gate pad 4 or the first gate wiring 5 and extending in the X-axis direction which intersects the Y-axis direction; a second gate pad 14 located at the corner of the -Y direction side of the active region 2; a second gate wiring 15 connected to the second gate pad 14 and having a portion extending in the Y-axis direction; and second gate signal lines 16, 17 connected to the second gate pad 14 or the second gate wiring 15 and extending in the X-axis direction. The second gate wiring 15 extends along the boundary between the active region 2 and the termination region 3.

[0026] Therefore, the first and second gate pads 4 and 14 are located in the active region 2, and the first and second gate signal lines 6 and 16 are also located between the first gate pad 4 and the second gate pad 14. As a result, the cell structure of the semiconductor element can be arranged in the region where the first and second gate signal lines 6 and 16 are located, and output current flows between the first gate pad 4 and the second gate pad 14. Consequently, the region between the first gate pad 4 and the second gate pad 14 also becomes an effective region. Thus, the effective region of the semiconductor device 100 is expanded. By expanding the effective region of the semiconductor device 100, the conduction voltage of the semiconductor element at the same output current becomes lower, and conduction loss can be reduced.

[0027] Next, we will explain the effect of reducing gate signal delay. When a trench is formed in the active region 2 and the semiconductor device is a trench IGBT, the first and second gate wirings 5 ​​and 15 are composed of a polysilicon thin film. In addition, the first and second gate wirings 5 ​​and 15 may also be composed of a polysilicon thin film and a metal thin film.

[0028] On the other hand, the first and second gate signal lines 6, 7, 16, and 17 are composed of polysilicon thin films embedded in trenches. However, if a dummy gate signal line 27 is present, the dummy gate signal line 27 is also composed of a polysilicon thin film embedded in a trench. The polysilicon thin films constituting the first and second gate wirings 5 ​​and 15 and the polysilicon thin films constituting the first and second gate signal lines 6, 7, 16, and 17 are formed in the same polysilicon deposit process and have the same resistivity. The cross-sectional area of ​​the polysilicon thin films constituting the first and second gate wirings 5 ​​and 15 is much larger than the cross-sectional area of ​​the polysilicon thin films constituting the first and second gate signal lines 6, 7, 16, and 17, so the resistance per unit length of the first and second gate wirings 5 ​​and 15 is small. The cross-sectional area of ​​a typical gate wiring is 10 2 μm 2 The typical cross-sectional area of ​​a gate signal line is 5 μm². 2 6 μm or more 2 The following applies:

[0029] Furthermore, if the first and second gate wirings 5 ​​and 15 are composed of a polysilicon thin film and a metal thin film, the resistance becomes even smaller. In other words, with respect to the gate signal delay, the resistance component of the first and second gate signal lines 6, 7, 16, and 17 is more dominant than the resistance component of the first and second gate wirings 5 ​​and 15. Also, as shown in Figure 2, the second gate wiring 15 has a closed-loop shape, but even if the second gate wiring 15 does not have a closed-loop shape, the resistance component of the second gate wiring 15 is relatively small, so as mentioned above, the resistance components of the first and second gate signal lines 6, 7, 16, and 17 are dominant. Therefore, when considering the following delays, we will approximately focus only on the first and second gate signal lines 6, 7, 16, and 17.

[0030] As shown in Figure 8, in the semiconductor device 101 relating to the related technology, the first and second gate pads 4 and 14, the first and second gate wirings 5 ​​and 15, and the first and second gate signal lines 7 and 17 form a comb shape when viewed from above. Because the first and second gate signal lines 7 and 17 extend from one end to the other in the X-axis direction of the active region 2, the gate resistance of the first and second gate signal lines 7 and 17 increases. As a result, the delay of each gate signal from the first and second gate pads 4 and 14 to the ends of the first and second gate signal lines 7 and 17 is large. In other words, this is the delay difference within the same gate signal line. Furthermore, this delay within the gate signal line also causes a delay difference in the gate signals between the first gate signal line 7, which is close to the first gate wiring 5, and the second gate signal line 17, which is also close to the first gate wiring 5. In other words, this is the delay difference between the first gate signal line 7 and the second gate signal line 17.

[0031] In contrast, as shown in Figure 2, in the semiconductor device 100 according to Embodiment 1, the first gate pad 4 is located in the center of the -Y direction edge of the active region 2, and the second gate pad 14 is located at the corner of the -Y direction edge of the active region 2. Therefore, the length of the first and second gate signal lines 6 and 16 located between the first gate pad 4 and the second gate pad 14 is shorter compared to the case where the first and second gate signal lines 6 and 16 extend from one end to the other in the X-axis direction of the active region 2. As a result, the gate resistance of the first and second gate signal lines 6 and 16 is reduced, and the delay of each gate signal from the first and second gate pads 4 and 14 to the ends of the first and second gate signal lines 6 and 16 can be reduced. With this configuration, not only can the delay difference on the same gate signal line be reduced, but the delay difference between the first gate signal line 6 and the second gate signal line 16 can also be reduced.

[0032] Furthermore, since the first gate signal lines 6 and 7 and the second gate signal lines 16 and 17 are arranged alternately in the Y-axis direction, the carrier concentration control effect caused by double-gate operation can be made uniform.

[0033] Furthermore, if a dummy gate signal line 27 is placed between the first gate signal line 7 and the second gate signal line 17, no current flows in the region where the dummy gate signal line 27 is placed, thus suppressing the output current of the semiconductor device 100.

[0034] Furthermore, since the first gate pad 4, the first gate wiring 5, the second gate pad 14, and the second gate wiring 15 are all composed of a polysilicon thin film and a metal thin film, the gate resistance connected between the first gate pad 4 and the first gate wiring 5, and between the second gate pad 14 and the second gate wiring 15 can be reduced.

[0035] <Embodiment 2> Next, Embodiment 2 will be described. Figure 5 is a schematic top view of the semiconductor device 100A according to Embodiment 2. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0036] As shown in Figure 5, in Embodiment 2, the placement of the second gate pad 14 and the shape of the first gate wiring 5 are different from those in Embodiment 1.

[0037] The first gate pad 4 is located in the center of the -Y direction edge of the active region 2. The second gate pad 14 is located adjacent to the first gate pad 4 in the center of the -Y direction edge of the active region 2. In Figure 5, the second gate pad 14 is located in the -X direction of the first gate pad 4, but it may also be located in the X direction of the first gate pad 4.

[0038] The first gate wiring 5 is connected to the first gate pad 4 and has a portion that extends from the first gate pad 4 in the Y-axis direction to the vicinity of the Y-axis edge of the active region 2, and a portion that partially surrounds the outer periphery of the second gate pad 14 in the Y-axis and -X-axis directions. The first gate signal line 6 is connected to the first gate pad 4 and extends in the X-axis direction, which is the direction that intersects the Y-axis direction. The first gate signal line 7 is connected to the first gate wiring 5 and extends in the X-axis direction.

[0039] The second gate wiring 15 is connected to the second gate pad 14 and has a portion that extends in the Y-axis direction, extending along the boundary between the active region 2 and the termination region 3. In other words, the second gate wiring 15 extends along the -X-direction side, the Y-direction side, the X-direction side, and the -Y-direction side of the active region 2. The second gate signal line 17 is connected to the second gate wiring 15 and extends in the X-axis direction. In this embodiment 2, the second gate signal line 16 connected to the second gate pad 14 is not provided.

[0040] Figure 6 is an enlarged view of region C in Figure 5. As shown in Figure 6, the spacing A1 between the first gate pad 4 and the second gate pad 14, the spacing A2 between the first gate pad 4 and the second gate wiring 15, the spacing B1 between the second gate pad 14 and the first gate wiring 5, and the spacing C1 between the first gate wiring 5 and the second gate wiring 15 are all 10 μm or more. This is to suppress interference between the gate signals flowing through each part. Although the spacings other than A2 are not mentioned in Embodiment 1, the spacings A1, B1, and C1 are also 10 μm or more in Embodiment 1.

[0041] Next, a modified example of Embodiment 2 will be described. Figure 7 is a schematic top view of the semiconductor device 100A according to a modified example of Embodiment 2.

[0042] As shown in Figure 7, the first gate wiring 5 branches off from the first gate pad 4 in two directions, the X direction and the -X direction, and then extends in the Y direction. In other words, it has a portion that branches off from the first gate pad 4 in the X direction and a portion that branches off from the first gate pad 4 in the -X direction. The second gate wiring 15 is connected to the second gate pad 14 and extends along the boundary between the active region 2 and the termination region 3. Furthermore, the second gate wiring 15 has a portion that extends in the -Y direction from the Y-direction side of the active region 2 between the portion that branches off from the first gate pad 4 in the X direction and the portion that branches off from the first gate pad 4 in the -X direction.

[0043] In this modified example of Embodiment 2, the intervals A1, A2, B1, and C1 are 10 μm or more.

[0044] Next, the operation and effects of Embodiment 2 and its modified form will be described. Embodiment 2 and its modified form include a semiconductor substrate 1 on which a semiconductor element is formed and which has a rectangular shape when viewed from above, and a termination region 3 which is the region outside the active region 2; a first gate pad 4 located in the center of the -Y direction side of the active region 2; a first gate wiring 5 connected to the first gate pad 4 and having a portion extending in the Y direction; first gate signal lines 6 and 7 connected to the first gate pad 4 or the first gate wiring 5 and extending in the X direction which intersects the Y direction; a second gate pad 14 located adjacent to the first gate pad 4 in the center of the -Y direction side of the active region 2; a second gate wiring 15 connected to the second gate pad 14 and having a portion extending in the Y direction; and a second gate signal line 17 connected to the second gate wiring 15 and extending in the X direction. The second gate wiring 15 extends along the boundary between the active region 2 and the termination region 3. A portion of the first gate wiring 5 partially surrounds the outer perimeter of the second gate pad 14.

[0045] Therefore, similar to Embodiment 1, the effective area of ​​the semiconductor device 100A is expanded. By expanding the effective area of ​​the semiconductor device 100A, the conduction voltage of the semiconductor element at the same output current becomes lower, and conduction loss can be reduced.

[0046] Furthermore, as shown in Figures 5 and 7, in the semiconductor device 100 according to Embodiment 2 and its modified version, the first gate pad 4 is located in the center of the -Y direction edge of the active region 2, and the second gate pad 14 is located adjacent to the first gate pad 4 in the center of the -Y direction edge of the active region 2. As a result, the lengths of the first and second gate signal lines 6, 7, and 17, which are located between the first and second gate pads 4 and 14 and the second gate wiring 15, are shorter compared to the case where the first and second gate signal lines 6, 7, and 17 extend from one end to the other in the X-axis direction of the active region 2. Consequently, the gate resistance of the first and second gate signal lines 6, 7, and 17 is reduced, and the delay of each gate signal from the first and second gate pads 4 and 14 to the ends of the first and second gate signal lines 6, 7, and 17 can be reduced. This configuration not only reduces the delay difference on the same gate signal line, but also reduces the delay difference between the first gate signal lines 6 and 7 and the second gate signal line 17.

[0047] Next, we will explain the effect of suppressing gate signal interference. When different gate signals are input to the first gate pad 4 and the second gate pad 14, if the spacing between the first and second gate pads 4 and 14 and the spacing between the first and second gate wirings 5 ​​and 15 is too close, gate signal interference may occur due to parasitic capacitance of the interlayer film between the first and second gate wirings 5 ​​and 15. If gate signal interference occurs, the semiconductor device may malfunction and be destroyed.

[0048] As shown in Figure 6, in the semiconductor device 100A according to Embodiment 2 and its modified version, the spacing A1 between the first gate pad 4 and the second gate pad 14, the spacing A2 between the first gate pad 4 and the second gate wiring 15, the spacing B1 between the second gate pad 14 and the first gate wiring 5, and the spacing C1 between the first gate wiring 5 and the second gate wiring 15 are all 10 μm or more, so interference of gate signals can be suppressed. Since Embodiment 1 has a similar configuration, the same effect can be obtained.

[0049] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0050] The various aspects of this disclosure are summarized below as an appendix.

[0051] (Note 1) A semiconductor substrate having a defined active region on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a terminal region which is the region outside the active region, A first gate pad is positioned in the center of the first side of the active region, A first gate wiring connected to the first gate pad and extending in the first direction, A first gate signal line connected to the first gate pad or the first gate wiring, extending in a second direction which intersects the first direction, A second gate pad is positioned at the corner of the first side of the active region, A second gate wiring connected to the second gate pad and having a portion extending in the first direction, A second gate signal line connected to the second gate pad or the second gate wiring and extending in the second direction, A semiconductor device wherein the second gate wiring extends along the boundary between the active region and the termination region.

[0052] (Note 2) A semiconductor substrate having a defined active region on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a terminal region which is the region outside the active region, A first gate pad is positioned in the center of the first side of the active region, A first gate wiring connected to the first gate pad and having a portion extending in a first direction, A first gate signal line connected to the first gate pad or the first gate wiring, extending in a second direction which intersects the first direction, In the central part of the first side of the active region, a second gate pad is positioned adjacent to the first gate pad, A second gate wiring connected to the second gate pad and having a portion extending in the first direction, The system comprises a second gate signal line connected to the second gate wiring and extending in the second direction, The second gate wiring extends along the boundary between the active region and the termination region, A semiconductor device in which a portion of the first gate wiring partially surrounds the outer periphery of the second gate pad.

[0053] (Note 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein the first gate signal line and the second gate signal line are arranged alternately in the first direction.

[0054] (Note 4) The semiconductor device according to Appendix 3, wherein a dummy gate signal line is arranged between the first gate signal line and the second gate signal line.

[0055] (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the distance between the first gate pad and the second gate pad, the distance between the first gate pad and the second gate wiring, the distance between the second gate pad and the first gate wiring, and the distance between the first gate wiring and the second gate wiring are all 10 μm or more.

[0056] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein the first gate pad, the first gate wiring, the second gate pad, and the second gate wiring are all composed of a polysilicon thin film and a metal thin film.

[0057] (Note 7) A semiconductor device according to any one of the appendices 1 to 6, wherein gate resistors are built into both the first gate pad and the first gate wiring, and the second gate pad and the second gate wiring.

[0058] (Note 8) The active region further comprises a trench formed in the active region, The semiconductor device according to Appendix 4, wherein the first gate signal line, the second gate signal line, and the dummy gate signal line are embedded in the trench and are made of a polysilicon thin film. [Explanation of Symbols]

[0059] 1 Semiconductor substrate, 2 Active region, 3 Termination region, 4 First gate pad, 5 First gate wiring, 6,7 First gate signal lines, 14 Second gate pad, 15 Second gate wiring, 16,17 Second gate signal lines, 27 Dummy gate signal line, 100,100A Semiconductor device.

Claims

1. A semiconductor substrate having a defined active region on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a terminal region which is the region outside the active region, A first gate pad is positioned in the center of the first side of the active region, A first gate wiring connected to the first gate pad and extending in the first direction, A first gate signal line connected to the first gate pad or the first gate wiring, extending in a second direction which intersects the first direction, A second gate pad is positioned at the corner of the first side of the active region, A second gate wiring connected to the second gate pad and having a portion extending in the first direction, A second gate signal line connected to the second gate pad or the second gate wiring and extending in the second direction, The semiconductor device wherein the second gate wiring extends along the boundary between the active region and the termination region.

2. A semiconductor substrate having a defined active region on which semiconductor elements are formed and which has a rectangular shape when viewed from above, and a terminal region which is the region outside the active region, A first gate pad is positioned in the center of the first side of the active region, A first gate wiring, which is connected to the first gate pad and has a portion extending in the first direction, A first gate signal line connected to the first gate pad or the first gate wiring, extending in a second direction which intersects the first direction, In the central part of the first side of the active region, a second gate pad is positioned adjacent to the first gate pad, A second gate wiring connected to the second gate pad and having a portion extending in the first direction, The system comprises a second gate signal line connected to the second gate wiring and extending in the second direction, The second gate wiring extends along the boundary between the active region and the termination region, A semiconductor device in which a portion of the first gate wiring partially surrounds the outer periphery of the second gate pad.

3. The semiconductor device according to claim 1 or claim 2, wherein the first gate signal line and the second gate signal line are arranged alternately in the first direction.

4. The semiconductor device according to claim 3, wherein a dummy gate signal line is arranged between the first gate signal line and the second gate signal line.

5. The semiconductor device according to claim 1 or claim 2, wherein the distance between the first gate pad and the second gate pad, the distance between the first gate pad and the second gate wiring, the distance between the second gate pad and the first gate wiring, and the distance between the first gate wiring and the second gate wiring are all 10 μm or more.

6. The semiconductor device according to claim 1 or claim 2, wherein the first gate pad, the first gate wiring, the second gate pad, and the second gate wiring are all composed of a polysilicon thin film and a metal thin film.

7. The semiconductor device according to claim 1 or claim 2, wherein gate resistors are built into both the space between the first gate pad and the first gate wiring, and between the second gate pad and the second gate wiring.

8. The active region further comprises a trench formed in the active region, The semiconductor device according to claim 4, wherein the first gate signal line, the second gate signal line, and the dummy gate signal line are embedded in the trench and are made of a polysilicon thin film.

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