Device, semiconductor device, and method for manufacturing a semiconductor device.

Abstract

The present invention provides a capacitive element with a large capacitance, or a transistor with good electrical characteristics, or a transistor with a large on-current, or a transistor with low parasitic capacitance. [Solution] The device comprises a first insulating layer, a first conductive layer on the first insulating layer, a second insulating layer on the first insulating layer and the first conductive layer, and a capacitive element on the first conductive layer, wherein the second insulating layer reaches the first conductive layer and has an opening that narrows at the top, and the lower electrode, upper electrode, and dielectric of the capacitive element have portions located within the opening, and the lower electrode has a portion that contacts the upper surface of the first conductive layer and a portion that is provided along the opening.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a device, a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include devices, semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have semiconductor devices. [Background technology]

[0004] The technology of constructing transistors using semiconductor thin films formed on insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] In addition, transistors using oxide semiconductors are known to have extremely small leakage currents in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that applies the characteristic of having a small leakage current. Also, for example, Patent Document 2 discloses a memory device that can retain stored content over a long period of time.

[0006] Also, the use of In2O3 in thin film transistors has been reported (Non-Patent Document 1).

[0007] Examples of oxide semiconductors applicable to the active layer of transistors include indium oxide and indium gallium zinc oxide. Non-Patent Document 2 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0009]

Non-Patent Document 1

Non-Patent Document 2

[0010] One aspect of the present invention aims to provide a capacitive element with high capacitance. One aspect of the present invention aims to provide a capacitive element with good electrical characteristics. One aspect of the present invention aims to provide a device having a capacitive element with high capacitance. One aspect of the present invention aims to provide a device with good electrical characteristics. One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with high on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a highly reliable capacitive element, device, transistor, semiconductor device, memory device, or display device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device, memory device, or display device with low power consumption. One aspect of the present invention aims to provide a memory device with a fast operating speed. One aspect of the present invention aims to provide a display device with high resolution or high aperture ratio. One aspect of the present invention aims to provide a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention includes a first insulating layer, a first conductive layer on the first insulating layer, a second insulating layer on the first insulating layer and the first conductive layer, and a capacitive element on the first conductive layer, wherein the capacitive element includes a second conductive layer, a third insulating layer, and a third conductive layer, the second insulating layer having an opening that reaches the first conductive layer and is tapered at the top, the second insulating layer having a first portion that protrudes inward from the opening at the top of the opening, and the second conductive layer having the first conductive layer The device has a second portion that contacts the upper surface, a third portion that contacts the side surface of the opening of the second insulating layer, and a fourth portion that contacts the lower surface of the first portion. The third insulating layer has a fifth portion that contacts the third portion of the second conductive layer within the opening, and a sixth portion that contacts the fourth portion. The third conductive layer has a portion located within the opening, and the fifth and sixth portions of the third insulating layer are sandwiched between the second conductive layer and the third conductive layer.

[0013] In the above embodiment, the second insulating layer has a laminated structure of a first layer and a second layer on the first layer, and in the opening, the width of the opening in the first layer is wider than the width of the opening in the second layer, and the first portion of the second insulating layer is preferably included in the second layer.

[0014] In the above embodiment, it is preferable that the first layer has silicon oxide and the second layer has silicon nitride.

[0015] In the above embodiment, the opening is narrowed at the bottom, the second insulating layer has a seventh portion that protrudes inward at the bottom of the opening, the second insulating layer has a laminated structure of a first layer, a second layer on the first layer, and a third layer on the second layer, and in the opening, the width of the opening of the second layer is wider than the width of the opening of the first layer and the width of the opening of the third layer, the first portion of the second insulating layer is included in the third layer, and the seventh portion of the second insulating layer is included in the first layer, which is preferable.

[0016] In the above embodiment, it is preferable that the second layer has silicon oxide, and the first and third layers have silicon nitride.

[0017] Alternatively, one aspect of the present invention comprises a first insulating layer, a transistor on the first insulating layer, and a second insulating layer on the first insulating layer, wherein the transistor comprises a first conductive layer on the first insulating layer, a semiconductor layer, a second conductive layer on the second insulating layer, a third insulating layer, and a third conductive layer, wherein the second insulating layer has a first opening that reaches the first conductive layer and is tapered at the top and bottom, the second conductive layer has a second opening that overlaps the first opening in a plan view, the second insulating layer has a first portion that protrudes inward from the first opening at the top of the first opening, and a second portion that protrudes inward from the first opening at the bottom of the first opening, and the semiconductor layer is in contact with the upper surface of the first conductive layer. The semiconductor device comprises a third portion, a fourth portion in contact with the side surface of the first opening of the second insulating layer, a fifth portion in contact with the lower surface of the protruding first portion of the second insulating layer, a sixth portion in contact with the upper surface of the protruding second portion of the second insulating layer, and a seventh portion in contact with the side surface of the second opening of the second conductive layer, wherein the third insulating layer has a portion in contact with the semiconductor layer within the first opening, the third conductive layer has a portion in contact with the semiconductor layer within the first opening with the third insulating layer in between, and the second conductive layer has a laminated structure of a first layer and a second layer on the first layer, the first layer has one or more of a metal, a metal alloy, and a metal nitride, and the second layer has an oxide.

[0018] In the above embodiment, the second insulating layer has a laminated structure comprising a third layer, a fourth layer on the third layer, and a fifth layer on the fourth layer, wherein, in the first opening, the width of the opening in the fourth layer is wider than the width of the opening in the third layer and the width of the opening in the fifth layer, the first portion of the second insulating layer is included in the fifth layer, and the second portion of the second insulating layer is included in the third layer.

[0019] In the above embodiment, it is preferable that the fourth layer has silicon oxide, and the third and fifth layers have silicon nitride.

[0020] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first conductive layer on a first insulating layer; sequentially forming a second insulating layer, a third insulating layer, and a fourth insulating layer on the first insulating layer and the first conductive layer; forming a second conductive layer on the fourth insulating layer; forming openings in the second conductive layer, the fourth insulating layer, the third insulating layer, and the second insulating layer using a first etching process to reach the first conductive layer; etching the third insulating layer using a second etching process such that the width of the opening in the third insulating layer is wider than the width of the opening in the second insulating layer and the width of the opening in the fourth insulating layer, thereby forming a semiconductor layer; forming a fifth insulating layer on the semiconductor layer; forming a third conductive layer on the fifth insulating layer; and the first etching process being an anisotropic etching process and the second etching process being an isotropic etching process.

[0021] Furthermore, in the above embodiment, it is preferable that the first etching process is a dry etching process and the second etching process is a wet etching process. [Effects of the Invention]

[0022] According to one aspect of the present invention, a capacitive element with high capacitance can be provided. According to one aspect of the present invention, a capacitive element with good electrical characteristics can be provided. According to one aspect of the present invention, a device having a capacitive element with high capacitance can be provided. According to one aspect of the present invention, a device with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with high on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable capacitive element, device, transistor, semiconductor device, memory device, or display device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a fast operating speed can be provided. According to one aspect of the present invention, a display device with high resolution or high aperture ratio can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device can be provided.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims. [Brief explanation of the drawing]

[0024] [Figure 1] Figure 1(A) is a plan view showing an example of a semiconductor device. Figures 1(B) to 1(D) are cross-sectional views showing an example of a semiconductor device. [Figure 2] Figures 2(A) and 2(B) are cross-sectional views showing an example of a semiconductor device. [Figure 3] Figures 3(A) and 3(B) are cross-sectional views showing an example of a semiconductor device. [Figure 4] Figure 4 is a cross-sectional view showing an example of a semiconductor device. [Figure 5]Figure 5(A) is a plan view showing an example of a semiconductor device. Figure 5(B) is a cross-sectional view showing an example of a semiconductor device. [Figure 6] Figures 6(A) and 6(B) are cross-sectional views showing an example of a semiconductor device. [Figure 7] Figure 7(A) is a plan view showing an example of a semiconductor device. Figure 7(B) is a cross-sectional view showing an example of a semiconductor device. [Figure 8] Figure 8 is a cross-sectional view showing an example of a semiconductor device. [Figure 9] Figures 9(A) and 9(B) are cross-sectional views showing an example of a semiconductor device. [Figure 10] Figures 10(A) and 10(B) are cross-sectional views showing an example of a semiconductor device. [Figure 11] Figure 11 is a cross-sectional view showing an example of a semiconductor device. [Figure 12] Figure 12 is a cross-sectional view showing an example of a semiconductor device. [Figure 13] Figure 13 is a cross-sectional view showing an example of a semiconductor device. [Figure 14] Figures 14(A) and 14(B) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 15] Figures 15(A) and 15(B) are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 16] Figure 16 is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 17] Figures 17(A) and 17(B) are cross-sectional views showing an example of a semiconductor device. [Figure 18] Figures 18(A) and 18(B) show examples of storage device configurations. [Figure 19] Figures 19(A) and 19(B) show examples of storage device configurations. [Figure 20] Figure 20 shows an example of a storage device configuration. [Figure 21] Figure 21 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 22]Figures 22(A) through 22(H) illustrate examples of memory cell circuit configurations. [Figure 23] Figures 23(A) through 23(C) are perspective views of semiconductor devices. [Figure 24] Figures 24(A) and 24(B) are perspective views of a semiconductor device. [Figure 25] Figure 25 is a perspective view of a semiconductor device. [Figure 26] Figures 26(A) and 26(B) show examples of electronic components. [Figure 27] Figures 27(A) through 27(C) show examples of large-scale computers. Figure 27(D) shows an example of space equipment. Figure 27(E) shows an example of a storage system applicable to data centers. [Figure 28] Figures 28(A) and 28(B) illustrate the carrier concentration dependence of hole mobility. Figure 28(C) is a cross-sectional view illustrating an indium oxide film. [Figure 29] Figures 29(A) and 29(B) show cross-sectional STEM images. [Figure 30] Figures 30(A) and 30(B) show cross-sectional STEM images. [Figure 31] Figures 31(A) and 31(B) show cross-sectional STEM images. [Figure 32] Figures 32(A) and 32(B) show cross-sectional STEM images. [Figure 33] Figures 33(A) and 33(B) show cross-sectional STEM images. [Modes for carrying out the invention]

[0025] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0026] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0027] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0028] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0029] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0030] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0031] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a channel-forming region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and the drain. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0032] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0033] In semiconductors, impurities refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic% can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors. Specifically, these include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also written as) may be formed.

[0034] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0035] For the analysis of the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. When the content rate of the target element is high (for example, 0.5 atomic% or more, or 1 atomic% or more), XPS is suitable. On the other hand, when the content rate of the target element is low (for example, 0.5 atomic% or less, or 1 atomic% or less), SIMS is suitable. When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0036] Note that in this specification, etc., the content rate indicates the ratio of the components contained in the film. For example, if the oxide semiconductor layer contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the oxide semiconductor layer is A X 、A Y 、A Z respectively, the content rate of metal element X can be expressed as A X / (A X +A Y +A Z ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the oxide semiconductor layer is B X :B Y :B Z respectively, the content rate of metal element X can be expressed as B X / (B X +B Y +B Z ).

[0037] Note that the words "film" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0038] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0039] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to describe the connection relationships of circuit elements as physical objects. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; however, wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0040] For example, assuming a circuit containing A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0042] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0043] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0044] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, this can be rephrased as, for example, A has a region located on B. Similarly, when it is stated that A is adjacent to B, or A overlaps with B, at least a portion of A is adjacent to B, or overlaps with B. Therefore, this can be rephrased as, respectively, A has a region adjacent to B, or A has a region overlapping with B. Similarly, when it is stated in this specification, etc., that A covers B, at least a portion of A covers B. Therefore, this can be rephrased as, for example, A has a region covering B.

[0045] In this specification, devices fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or an FMM may be referred to as MML (Metal Maskless) structured devices.

[0046] In this specification, a structure in which different light-emitting layers are created using light-emitting elements (also called light-emitting devices) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0047] In this specification, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the aforementioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0048] In this specification, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Examples of the layers (also called functional layers) of the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, one of the pair of electrodes may be referred to as a pixel electrode and the other as a common electrode.

[0049] In this specification, the sacrificial layer (which may also be called the mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0050] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0051] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other.

[0052] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention and a method for manufacturing the same.

[0053] <Example 1 of semiconductor device configuration> The configuration of a semiconductor device according to one embodiment of the present invention will be explained using Figures 1(A) to 4.

[0054] [Capacitive element 100] Figure 1(A) is a plan view of a device having a capacitive element 100. Figure 1(B) is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 1(A). Note that in plan views such as Figure 1(A), some elements have been omitted for clarity. Some elements may also be omitted in subsequent plan views.

[0055] The configurations shown in Figures 1(A) and 1(B) can be described as a laminate having a conductive layer and an insulating layer. Alternatively, they can be described as a device having a conductive layer and an insulating layer. Alternatively, they can be described as an electronic device having a conductive layer and an insulating layer.

[0056] Although Figures 1(A) and 1(B) show the capacitive element 100 as a component, a semiconductor device according to one aspect of the present invention may have semiconductor elements in addition to the capacitive element, such as transistors, diodes, photodiodes, etc., and the capacitive element can be used in connection with these semiconductor elements. Therefore, Figures 1(A) and 1(B) may be referred to as semiconductor devices.

[0057] The capacitive element 100 has a conductive layer 115, an insulating layer 130, and a conductive layer 120. A conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110. The conductive layer 120 functions as one of a pair of electrodes (sometimes called the upper electrode), the conductive layer 115 functions as the other of a pair of electrodes (sometimes called the lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitive element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0058] The semiconductor device shown in Figures 1(A) and 1(B) comprises a substrate 101, an insulating layer 140 on the substrate 101, and a capacitive element 100 on the insulating layer 140. It is also possible to configure the semiconductor device without the substrate 101.

[0059] A conductive layer 110 is provided on the insulating layer 140, and a conductive layer 115 and an insulating layer 180 are provided on the conductive layer 110.

[0060] The insulating layer 180 has an opening 190 that reaches the conductive layer 110. The conductive layer 115 has a region within the opening 190 that is in contact with the upper surface of the conductive layer 110 and a region within the opening 190 that is in contact with the side surface of the insulating layer 180. The insulating layer 130 is arranged such that at least a portion of it is located within the opening 190. The conductive layer 120 is arranged such that at least a portion of it is located within the opening 190.

[0061] Figure 2(A) shows the insulating layer 140, conductive layer 110, and insulating layer 180 extracted from Figure 1(B).

[0062] The opening 190 has a shape that narrows at the top. In other words, the opening 190 can be said to have a bottleneck shape.

[0063] As shown in Figures 1(B) and 2(A), in the opening 190, the width R11 of the portion located below the narrowed upper part (sometimes described as the portion deeper than the upper part) can be made wider than the width R12 of the upper part. By making the width R11 wider than the width R12, the surface area of ​​the side of the opening 190 of the insulating layer 180 can be increased.

[0064] Furthermore, in the configuration examples shown in Figures 1(B) and 2(A), the opening 190 has a shape that is narrowed at the top and bottom. In Figures 1(B) and 2(A), the width of the bottom of the opening 190 is approximately the same as the width R12 of the top. In the opening 190, the narrowed portion at the top is designated as opening 190_u, the narrowed portion at the bottom is designated as opening 190_d, and the portion that includes the midpoint between the highest and lowest positions of the insulating layer 180 is designated as opening 190_m.

[0065] Furthermore, since the opening 190 of the insulating layer 180 has a shape that is narrowed at the top and bottom, the insulating layer 180 has a portion that protrudes inward from the opening 190 at the top of the opening 190 and a portion that protrudes inward from the opening 190 at the bottom of the opening 190. Region 67 shown in Figure 2(A) is the lower surface of the portion that protrudes at the top of the opening 190, and region 68 is the upper surface of the portion that protrudes at the bottom of the opening 190.

[0066] The conductive layer 115 has a portion that contacts the upper surface of the conductive layer 110 within the opening 190, and a portion that contacts the side surface of the opening 190 of the insulating layer 180. The conductive layer 115 also contacts regions 67 and 68.

[0067] As shown in Figure 1(B), in the portion of the insulating layer 180 located between the upper and lower parts of the opening 190, the width of the opening 190 is increased, and the surface area of ​​the sides of the opening 190 of the insulating layer 180 is also increased. Furthermore, the presence of protruding portions of the insulating layer 180 at the upper and lower parts of the opening increases the surface area of ​​the opening 190 of the insulating layer 180.

[0068] As the surface area of ​​the opening 190 in the insulating layer 180 increases, the surface area of ​​the conductive layer 115 covering the opening 190 also increases. Therefore, the capacitance value of the capacitive element 100 can be increased.

[0069] Figures 1(C) and 1(D) are modified examples of the configuration shown in Figure 1(B), illustrating different configurations of the area enclosed by the dashed line in Figure 1(B).

[0070] Figure 1(B) shows an example where the upper edge of the conductive layer 115 is aligned with the upper surface of the insulating layer 180. However, as shown in Figure 1(C), by making the upper edge of the conductive layer 115 lower than the upper edge of the opening 190 of the insulating layer 180, the electric field concentration between the conductive layer 115 and the conductive layer 120 can be mitigated. Furthermore, if the upper edge of the conductive layer 115 is rounded, the electric field concentration may be further reduced.

[0071] Alternatively, as shown in Figure 1(D), the conductive layer 115 can be provided not only within the opening 190 of the insulating layer 180 but also on the insulating layer 180. In Figure 1(D), the insulating layer 130 covers the edge of the conductive layer 115 on the insulating layer 180. The conductive layer 120 covers the edge of the conductive layer 115 with the insulating layer 130 in between. On the insulating layer 180, the edge of the conductive layer 120 is located outside the edge of the conductive layer 115 when viewed from the center of the opening 190. In the configuration shown in Figure 1(D), the conductive layer 115 covers the upper surface of the insulating layer 180.

[0072] As shown in Figure 2(B), the opening 190 may have a narrowed shape only at the top, and the bottom may not be narrowed.

[0073] The upper part of the opening 190 can be rephrased as being above the midpoint between the highest and lowest points of the insulating layer 180. In the insulating layer 180, the narrowed portion of the opening 190 can be configured to be located in a region less than 50% of the thickness of the insulating layer 180 from the top surface, preferably less than 40%, more preferably less than 30%, and even more preferably less than 20%.

[0074] Furthermore, the lower part of the opening 190 can be described as being below the midpoint between the highest and lowest points of the insulating layer 180. In the insulating layer 180, the narrowed portion of the opening 190 can be configured to be located in a region less than 50% of the thickness of the insulating layer 180 from the bottom surface, preferably less than 40%, more preferably less than 30%, and even more preferably less than 20%.

[0075] Let θu be the angle between the side wall of opening 190_u and the plane parallel to the surface of the substrate 101, let θd be the angle between the side wall of opening 190_d and the plane parallel to the surface of the substrate 101, and let θm be the angle between the side wall of opening 190_m and the plane parallel to the surface of the substrate 101. Figure 1(B) shows an example where angles θu, θd, and θm are all 90 degrees. In this case, the upper, lower, and central parts of the opening 190 each have a cylindrical shape. Here, for example, the upper surface of a layer provided on the substrate 101 can be used as the plane parallel to the surface of the substrate 101.

[0076] In Figure 1(B), angles θu, θd, and θm are preferably between 45 degrees and 90 degrees. For example, if angle θu is between 80 degrees and 90 degrees, device integration can be achieved. Also, by setting angle θm to less than 80 degrees, the coverage of the side surface of the opening 190_m of the conductive layer 115 may be improved.

[0077] Furthermore, the angle θm may be greater than 90 degrees. In such cases, the side surface of the opening 190m can be well covered by forming a conductive layer 115, etc., using a film formation method with high coverage.

[0078] Since the opening 190 has a narrowed shape, it is preferable to form the conductive layer 115, the insulating layer 130, and the conductive layer 120 using a film formation method that provides high coverage to the inner wall of the opening 190. For example, they can be formed using atomic layer deposition (ALD) method.

[0079] The conductive layer 110 can be extended to function as wiring. Figure 1(A) shows an example in which the conductive layer 110 extends in the X direction. The conductive layer 110 may also be provided in a planar manner, and when multiple capacitive elements 100 are arranged in a matrix in the X and Y directions, the conductive layer 110 can be shared by multiple capacitive elements 100.

[0080] The conductive layer 120 is provided in contact with a portion of the upper surface of the insulating layer 130. In Figures 1(B) and 2(B), the conductive layer 120 is provided to fill the opening 190 and has a portion that is higher than the upper surface of the insulating layer 180. By extending the conductive layer 120 on the insulating layer 180, it can function as wiring. Figure 1(A) shows an example in which the conductive layer 120 extends in the Y direction.

[0081] The conductive layer 110, conductive layer 115, and conductive layer 120 can each be arranged in a laminated structure.

[0082] For example, the conductive layer 120 can be formed in a laminated structure by combining a film deposition method that provides high coverage and a film deposition method that offers high deposition speed and excellent productivity. In the examples shown in Figures 1(B) and 2(B), the conductive layer 120 has a laminated structure of conductive layer 120a and conductive layer 120b on conductive layer 120a. By using a film deposition method that provides high coverage for conductive layer 120a and a film deposition method that offers high deposition speed for conductive layer 120b, the coverage of the conductive layer 120 on the insulating layer 130 can be improved, and the conductive layer 120 can be well embedded in the opening 190. Furthermore, by using a highly conductive material for the thick conductive layer 120b, the conductivity of the conductive layer 120 can be improved, making it suitable for use as wiring.

[0083] Furthermore, it is preferable to use a conductive material that is resistant to oxidation as the conductive layer 120a. This makes it possible to suppress oxidation of the conductive layer 120b by the insulating layer 130 when an oxide is used for the insulating layer 130.

[0084] The conductive layers of a semiconductor device according to one aspect of the present invention, such as the conductive layer 110, conductive layer 115, and conductive layer 120 described above, will now be explained.

[0085] It is preferable to use a metallic element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metallic elements, or an alloy combining the aforementioned metallic elements. Alternatively, nitrides of alloys containing the aforementioned metallic elements, or oxides of such alloys, may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0086] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, silicon-containing indium tin oxide (also called In-Si-Sn oxide, or ITSO), indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0087] Conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

[0088] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0089] As the conductive layer 110, a highly conductive material such as tungsten can be used. By using such a highly conductive material, the conductivity of the conductive layer 110 can be improved, allowing it to function adequately as wiring.

[0090] Furthermore, it is preferable to use a conductive material that is resistant to oxidation, or a conductive material that has the function of suppressing oxygen diffusion, as the conductive layer 115, either as a single layer or in a laminated form. For example, titanium nitride or ITSO can be used. Alternatively, for example, a structure in which titanium nitride is laminated on tungsten can be used. Alternatively, for example, a structure in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten can be used. By using such a structure, if an oxide is used for the insulating layer 130, oxidation of the conductive layer 110 by the insulating layer 130 can be suppressed. Also, if an oxide is used for the insulating layer 180, oxidation of the conductive layer 110 by the insulating layer 180 can be suppressed.

[0091] For example, one or more materials selected from tantalum nitride and titanium nitride can be used as the conductive layer 120a, and tungsten can be used as the conductive layer 120b.

[0092] An insulating layer, such as insulating layer 180 and insulating layer 130, of a semiconductor device according to one aspect of the present invention will be described.

[0093] An inorganic insulating film can be used as an insulating layer. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidogenic nitride insulating films, and nitride oxide insulating films. Examples of materials applicable to oxide insulating films include oxides such as silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of materials applicable to nitride insulating films include nitrides such as silicon nitride and aluminum nitride. Examples of materials applicable to oxidogenic nitride insulating films include oxidogenic nitrides such as silicon nitride, aluminum nitride, gallium nitride, yttrium nitride, and hafnium nitride. Examples of materials applicable to nitride oxide insulating films include nitride oxides such as silicon nitride and aluminum nitride.

[0094] It is preferable to use a material with a high dielectric constant (high-k) as the insulating layer 130. By using a high-k material as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, while also ensuring sufficient capacitance of the capacitive element 100.

[0095] The insulating layer 180 functions as an interlayer film. By using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulating layer. Note that materials with a low dielectric constant also tend to have high dielectric strength.

[0096] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0097] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having voids is another example. These silicon oxides may contain nitrogen.

[0098] An organic insulating film can also be used as the insulating layer.

[0099] Furthermore, a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material can be used as the insulating layer 130. For example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulating layer 130. Alternatively, an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulating layer with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0100] Furthermore, a material capable of ferroelectricity may be used as the insulating layer 130. Details of materials capable of ferroelectricity will be described later.

[0101] Ferroelectric materials are insulators that exhibit internal polarization when an external electric field is applied, and this polarization remains even when the electric field is removed. Therefore, non-volatile memory elements can be formed using capacitive elements (sometimes referred to as ferroelectric capacitors) that utilize this material as a dielectric. Non-volatile memory elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory) or ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, with one of the transistor's sources and drains connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

[0102] As the insulating layer 180, it is preferable to use an insulating layer containing a material with a low dielectric constant. Silicon oxide and silicon oxynitride can be suitably used because they are thermally stable. Furthermore, when the insulating layer 180 has a laminated structure, it is preferable to use one or more materials selected from silicon oxide and silicon oxynitride in one or more of the insulating layers constituting the laminated structure.

[0103] As shown in Figure 3(A), etc., by making the insulating layer 180 a laminated structure, an insulating layer 180 having a narrowed portion can be formed.

[0104] The capacitive element 100 shown in Figure 3(A) differs from that in Figure 1(B) mainly in that the insulating layer 180 has a laminated structure consisting of insulating layer 180a, insulating layer 180b on insulating layer 180a, and insulating layer 180c on insulating layer 180b. It is preferable that the width of the opening 190 in insulating layer 180b is larger than the width of the opening 190 in insulating layer 180a. It is also preferable that the width of the opening 190 in insulating layer 180b is larger than the width of the opening 190 in insulating layer 180c. Here, the width of the opening 190 in insulating layer 180a and the width of the opening 190 in insulating layer 180c can be represented, for example, by the width R12 mentioned earlier, and the width of the opening 190 in insulating layer 180b can be represented, for example, by the width R11 mentioned earlier. In other words, it is preferable that the width R11 is larger than the width R12. Furthermore, Figure 3(A), etc., shows an example where the width of the opening 190 in insulating layer 180a and the width of the opening 190 in insulating layer 180c are approximately the same, but the width of the opening 190 may be different for insulating layer 180a and insulating layer 180c, respectively.

[0105] As will be explained in more detail later, after forming openings in insulating layers 180a, 180b, and 180c, etching is performed only on insulating layer 180b to widen the opening width, thereby making the insulating layer 180 have a shape with a narrowed portion.

[0106] The thickness of the insulating layer 180b is preferably greater than that of the insulating layers 180a and 180c. This configuration allows for a larger capacitance value of the capacitive element 100.

[0107] For example, a material with a lower dielectric constant than insulating layers 180a and 180c can be used as insulating layer 180b.

[0108] Furthermore, when etching is performed to widen the opening width in the insulating layer 180b, it is preferable to select the materials of insulating layer 180a, insulating layer 180b, and insulating layer 180c such that insulating layer 180a and insulating layer 180c are not etched during the etching process, or the etching rate is kept sufficiently low.

[0109] Inorganic materials can be used as insulating layers 180a, 180b, and 180c, respectively. Alternatively, organic materials can be used for one or more of insulating layers 180a, 180b, and 180c. It is preferable to use materials for insulating layers 180a and 180c that sufficiently suppress the etching rate during the etching process of insulating layer 180b. As an example, one or more materials selected from silicon nitride and silicon nitride / oxide can be used for insulating layer 180a and insulating layer 180c, and one or more materials selected from silicon oxide and silicon oxynitride can be used for insulating layer 180b.

[0110] Figures 3(B) and 4 show examples in which multiple wide sections are provided in the opening 190 of the insulating layer 180.

[0111] Figure 3(B) shows an example in which two sets of insulating layers 180b and insulating layer 180c are alternately stacked on insulating layer 180a in the capacitive element 100. In Figure 3(B), the openings 190 provided in insulating layer 180a, insulating layer 180b, and insulating layer 180c are referred to as opening 190_a, opening 190_b, and opening 190_c, respectively. Opening 190_b is wider than openings 190_a and 190_c.

[0112] By having multiple wide sections in the opening 190, the surface area of ​​the opening 190 can be increased.

[0113] Figure 3(B) shows an example where the opening 190 of the insulating layer 180 has two wide sections, but the opening 190 can also have three or more wide sections. Figure 4 shows an example where there are four insulating layers 180b and four insulating layers 180c, and four sets of insulating layers 180b and 180c are alternately laminated on the insulating layer 180a. In Figure 4, the opening 190 has four wide sections.

[0114] While an example has been shown where the opening 190 is circular in plan view, the present invention is not limited to this. In plan view, the opening 190 can be, for example, a circle, an ellipse or other approximately circular shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon or other polygon with rounded corners, or any of these polygons. The polygon may be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less). As shown in Figure 1(A), etc., in plan view, it is preferable that the opening 190 is circular. By making it circular, the processing accuracy when forming the opening can be improved, and a fine-sized opening can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0115] Furthermore, the shape and size of the opening 190 in plan view may differ for each layer. Also, when the upper surface shape of the opening 190 is circular, the openings in each layer may or may not be concentric.

[0116] <Example of semiconductor device configuration 2> A semiconductor device according to one aspect of the present invention has a transistor. In the transistor according to one aspect of the present invention, the source electrode and the drain electrode are located at different heights (for example, heights in a direction perpendicular to the substrate surface or insulating plane on which the transistor is mounted), and the current flowing through the semiconductor layer flows in the height direction. That is, the channel length direction has a component in the height direction (vertical direction), so the transistor according to one aspect of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel type transistor.

[0117] In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode can be arranged in a stacked manner, thus significantly reducing the occupied area compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar manner.

[0118] Furthermore, the channel length of the transistor according to one embodiment of the present invention can be controlled by the thickness of the first insulating layer, etc. Therefore, it is possible to realize a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor. As a result, it is possible to realize a transistor with a small footprint and a large on-current.

[0119] Furthermore, because transistors using oxide semiconductors have a low off-current, they can retain stored data for long periods of time, for example, when used in memory devices. In other words, they do not require refresh operations, or require very infrequent refresh operations, thus significantly reducing the power consumption of the memory device. By using a transistor according to one aspect of the present invention in a memory device, it is possible to achieve high integration and low power consumption of the memory device.

[0120] [Transistor 200] The configuration of a semiconductor device according to one embodiment of the present invention will be explained using Figures 5(A) to 13.

[0121] Figure 5(A) is a plan view of a semiconductor device having transistor 200. Figure 5(B) is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 5(A). Figure 6(A) is a cross-sectional view between the dashed lines B3 and B4 shown in Figure 5(A). Figure 6(B) is a cross-sectional view between the dashed lines B5 and B6 shown in Figures 5(B) and 6(A). Figure 6(B) is a view from the Z direction.

[0122] The semiconductor device shown in Figures 5(A) to 6(B) comprises an insulating layer 210 on a substrate 101, a transistor 200 on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. The insulating layers 210 and 280 can function as interlayer films. Therefore, it is preferable that the insulating layers 210 and 280 each have a material with a low dielectric constant.

[0123] The transistor 200 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0124] In transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of the source electrode and drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode. Furthermore, the conductive layer 260 has a region that functions as gate wiring. The conductive layer 220 also has a region that functions as one of the source wiring and drain wiring, and the conductive layer 240 has a region that functions as the other of the source wiring and drain wiring. By using a material with a high dielectric constant as the insulating layer 250, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. Additionally, a material that can possess ferroelectric properties can be used as the insulating layer 250.

[0125] As shown in Figures 5(B) and 6(A), the insulating layer 280 and the conductive layer 240 are provided with openings 290 that reach the conductive layer 220.

[0126] Furthermore, as shown in Figures 5(B) and 6(A), the conductive layer 220 is provided with a recess that overlaps with the opening 290.

[0127] Furthermore, the shape and size of the opening 290 in plan view may differ for each layer. Also, when the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0128] At least a portion of the components of the transistor 200 are arranged within the opening 290. Specifically, at least a portion of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is arranged to be located within the opening 290. Furthermore, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are located within the opening 290 are provided to reflect the shape of the opening 290.

[0129] The oxide semiconductor layer 230 is provided so as to cover the bottom and side walls of the opening 290. The oxide semiconductor layer 230 also has recesses that reflect the shape of the opening 290.

[0130] The conductive layer 240 can function as wiring for a semiconductor device. By increasing the conductivity of the conductive layer 240, the characteristics of the semiconductor device can be improved. For example, the operating speed can be increased. Therefore, it is preferable to use a highly conductive material for the conductive layer 240.

[0131] Furthermore, the conductive layer 240 can function as either the source or the drain of the transistor. The conductive layer 240 has a region that is in contact with the oxide semiconductor layer 230. Therefore, it is preferable that the conductive layer 240 has low contact resistance with the oxide semiconductor layer 230.

[0132] Figures 5(B) and 6(A) show an example in which the conductive layer 240 has a two-layer structure consisting of conductive layer 240a and conductive layer 240b on conductive layer 240a. Also, an example is shown in which the conductive layer 220 has a laminated structure consisting of conductive layer 220a, conductive layer 220b on conductive layer 220a, and conductive layer 220c on conductive layer 220b. For example, highly conductive materials can be used as conductive layer 240a and conductive layer 220b.

[0133] Furthermore, for example, materials with low contact resistance with the oxide semiconductor layer 230 can be used as the conductive layer 240b and conductive layer 220c, which are layers in contact with the oxide semiconductor layer 230. Also, for example, indium tin oxide can be suitably used as the conductive layer 220c. When silicon oxide or silicon oxynitride is used as the insulating layer 280b, for example, it is easier to increase the selectivity ratio with indium tin oxide when performing wet etching to recede the insulating layer 280b. Here, a high selectivity ratio means that in wet etching, the etching rate of indium tin oxide can be sufficiently lower than the etching rate of the insulating layer 280b.

[0134] On the other hand, a suitable material for use as the conductive layer 240b is an oxygen-containing conductive material. An oxygen-containing conductive material can maintain a stable state even when in contact with the oxide semiconductor layer 230, and oxygen extraction from the oxide semiconductor layer 230 by the conductive layer 240b is unlikely to occur.

[0135] Furthermore, as the conductive layer 220a, which is the layer in contact with the insulating layer 210, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be used.

[0136] The insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. Furthermore, the insulating layer 250 is provided on the insulating layer 280 so as to cover the upper and side surfaces of the oxide semiconductor layer 230. The insulating layer 250 also has recesses that reflect the shape of the recesses in the oxide semiconductor layer 230.

[0137] The conductive layer 260 is provided so as to fill at least a portion of the recess in the insulating layer 250. The conductive layer 260 also has a region within the opening 290 that faces the oxide semiconductor layer 230 with the insulating layer 250 in between.

[0138] Figures 5(B) and 6(A) show an example in which the conductive layer 260 has a laminated structure consisting of conductive layer 260a and conductive layer 260b on conductive layer 260a. For example, conductive layer 260a can be formed using a film deposition method with high coverage, and conductive layer 260b can be formed using a film deposition method with a higher film deposition rate. For example, a material with high conductivity can be used for conductive layer 260b, and a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion can be used for conductive layer 260a. As an example, titanium nitride can be used for conductive layer 260a and tungsten can be used for conductive layer 260b. For example, conductive layer 120a and conductive layer 120b can be referenced as materials that can be used for conductive layer 260a and conductive layer 260b, respectively.

[0139] The oxide semiconductor layer 230 has a region facing the conductive layer 260 with an insulating layer 250 in between. At least a portion of this region functions as the channel formation region of the transistor 200. The region of the oxide semiconductor layer 230 near the conductive layer 220 functions as one of the source region and the drain region, and the region of the oxide semiconductor layer 230 near the conductive layer 240 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0140] The oxide semiconductor layer 230 is provided inside the opening 290. Furthermore, the transistor 200 has a configuration in which current flows vertically, with one of the source and drain electrodes (in this case, the conductive layer 220) located downwards and the other source and drain electrode (in this case, the conductive layer 240) located upwards. In other words, a channel is formed along the side surface of the opening 290.

[0141] In the oxide semiconductor layer 230, for example, at least a portion of the region in contact with the conductive layer 240 can function as the other of the source region and drain region of the transistor.

[0142] In the oxide semiconductor layer 230, for example, the region in contact with the insulating layer 280, in other words, at least a portion of the region not in contact with the conductive layer 240 and the conductive layer 220, can function as a channel formation region of the transistor. In particular, the region in contact with the insulating layer 280b is preferably a channel formation region of the transistor.

[0143] Transistor 200 has an oxide semiconductor layer 230 in the channel formation region. In other words, transistor 200 can be called an OS transistor.

[0144] OS transistors are prone to electrical property fluctuations and unreliability if oxygen vacancies and impurities are present in the channel formation region of the oxide semiconductor. Furthermore, defects where hydrogen is present in an oxygen vacancy (hereinafter referred to as V) can also occur. O This can form an oxygen vacancy (sometimes called H) and generate electrons that act as carriers. Therefore, if the channel formation region in an oxide semiconductor contains oxygen vacancies, the OS transistor is likely to exhibit normally-on characteristics. Consequently, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of an oxide semiconductor is reduced and that it is i-type (intrinsic) or substantially i-type.

[0145] Figures 5(B) and 6(A) show examples in which the insulating layer 280 has a laminated structure consisting of insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Furthermore, an example is shown in which the insulating layer 280a has a laminated structure consisting of insulating layer 280a1 and insulating layer 280a2 on insulating layer 280a1.

[0146] As insulating layer 280b, an insulating layer with a high oxygen supply can be used, and as insulating layers 280a and 280c, insulating layers with a lower oxygen supply than insulating layer 280b can be used. In the region of the oxide semiconductor layer 230 in contact with insulating layer 280b, the oxygen supply is high, and oxygen deficiency can be suitably reduced. On the other hand, in the region of the oxide semiconductor layer 230 in contact with insulating layers 280a and 280c, the amount of oxygen supplied from insulating layer 280 etc. is less compared to the region in contact with insulating layer 280b. Therefore, in the region of the oxide semiconductor layer 230 in contact with insulating layers 280a and 280c, the oxide semiconductor layer 230 may become less resistive. This less resistive region can function as either a source region or a drain region.

[0147] The channel length of transistor 200 is the distance between the source region and the drain region. When the region in contact with the insulating layer 280a and insulating layer 280c of the oxide semiconductor layer 230 has low resistance, the channel length of transistor 200 can be considered, for example, as the thickness of the insulating layer 280b. In Figure 5(B), the channel length L of transistor 200 is shown by a dashed double arrow.

[0148] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of transistor 200 can be set by the thickness of the insulating layer 280. Therefore, the channel length of transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less is preferable, 50 nm or less is more preferable, 40 nm or less is even more preferable, 30 nm or less is even more preferable, 20 nm or less is even more preferable, and 10 nm or less is even more preferable. On the other hand, 0.1 nm or more is preferable, 1 nm or more is more preferable, and 5 nm or more is even more preferable). This increases the on-current of transistor 200, improving the frequency characteristics.

[0149] Furthermore, since the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, preferably 500 nm or less, and more preferably 300 nm or less, productivity and yield can be improved in the formation of the insulating layer 280 and the formation of the opening 290 into the insulating layer 280.

[0150] Based on the above, the channel length of the transistor in a semiconductor device according to one embodiment of the present invention can be 0.1 nm or more, preferably 1 nm or more, more preferably 5 nm or more, and 1 μm or less, preferably 500 nm or less, and even more preferably 300 nm or less.

[0151] The channel length L of transistor 200 can be, for example, smaller than the channel width W of transistor 200. The channel length L of transistor 200 can be, for example, 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, relative to the channel width W of transistor 200. This configuration makes it possible to realize a transistor with good electrical characteristics and high reliability.

[0152] As shown in Figure 6(B), the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the oxide semiconductor layer 230 via the insulating layer 250. In other words, in a plan view, the entire perimeter of the oxide semiconductor layer 230 becomes the channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the length of the outer perimeter of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be said to be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view). Figures 5(A), 5(B), and 6(A) show the width R of the opening 290, and Figure 6(B) shows the channel width W of the transistor 200.

[0153] By increasing the width of the opening 290 in the insulating layer 280 that is in contact with the region where the channel is formed in the oxide semiconductor layer 230, the channel width per unit area can be increased, and the on-current can be increased. When the opening 290 is circular in a plan view, the channel width W is the product of "the width of the opening 290 in the insulating layer 280 that is in contact with the region where the channel is formed in the oxide semiconductor layer 230" and "pi (π)".

[0154] The width of the opening 290 may vary in the depth direction. The width of the opening 290 can be the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these positions, or the average of these three widths. Furthermore, the width of each opening in each layer where the opening 290 is provided can be, for example, the width of the opening at the highest position of the layer, the width of the opening at the lowest position, the width of the opening at the midpoint between these positions, or the average of these three widths.

[0155] When forming the aperture 290 using photolithography, the width of the aperture 290 may be limited, for example, by the exposure limit of the photolithography. The width R of the aperture 290 is determined by the film thickness of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided within the aperture 290. The width of the aperture 290 can be, for example, 5 nm or more, preferably 10 nm or more, more preferably 20 nm or more, and 100 nm or less, preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and even more preferably 30 nm or less.

[0156] As described above, by forming the opening 290 so that it is circular in plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. As a result, the distance between the conductive layer 260 and the oxide semiconductor layer 230 becomes approximately uniform, so that the gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0157] In this embodiment, an example is shown where the opening 290 is circular in plan view, but the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle, an ellipse or other approximately circular shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon or other polygon with rounded corners, or any of these polygons. The polygon may be either a concave polygon or a convex polygon. As shown in Figure 1(A), etc., in plan view, it is preferable that the opening 290 is circular. By making it circular, the processing accuracy when forming the opening can be improved, and it is possible to form an opening of a fine size.

[0158] As the conductive layer 240b, conductive materials containing oxygen and conductive materials containing nitrogen can be used. A conductive metal oxide (also called an oxide conductor) can preferably be used as the conductive layer 240b. For example, indium tin oxide (In-Sn oxide, also called ITO), indium tin oxide containing titanium oxide, ITSO, indium zinc oxide (In-Zn oxide, also called IZO®) can preferably be used as the conductive layer 240b.

[0159] It is preferable to use a conductive material with low electrical resistance as the conductive layer 240a. As the conductive layer 240a, metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the aforementioned metal elements, or alloys combining the aforementioned metal elements can be used. Using a conductive material with low electrical resistance as the conductive layer 240a is preferable because it increases the speed of circuit operation when the conductive layer 240 is used for wiring, etc. For example, it is preferable to use a conductive material for the conductive layer 240a that has lower electrical resistance compared to the conductive layer 240b. For example, tungsten, copper, aluminum, alloys containing aluminum, etc., can be suitably used as the conductive layer 240a.

[0160] By having a recess in the conductive layer 220 at a position overlapping the opening 290, the height of the lower surface of the insulating layer 250 and the lower surface of the conductive layer 260 within the opening 290 can be made lower than the height of the upper surface of the conductive layer 220 that is in contact with the insulating layer 280, relative to the upper surface of the insulating layer 210, compared to the case where there is no recess. Here, the height of each surface can be determined relative to the surface on which the transistor is formed. Here, the upper surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is formed. For example, the upper surface of the substrate on which the transistor or semiconductor device is provided may be used as the reference.

[0161] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recesses in the conductive layer 220, as well as the top surface of the conductive layer 240b. The presence of recesses in the conductive layer 220 increases the contact area between the oxide semiconductor layer 230 and the conductive layer 220. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220 can be reduced.

[0162] Figures 5(B) and 6(A) show a configuration in which the edges of the conductive layer 240 and the oxide semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. Therefore, it is preferable that the number of masks required to manufacture the semiconductor device can be reduced. However, the present invention is not limited to this. For example, in the X direction or Y direction, the edges of the oxide semiconductor layer 230 or the conductive layer 240 may be located inward or outward compared to the others.

[0163] As described above, a channel formation region, a source region, and a drain region can be formed within the opening 290. This allows the transistor 200 to reduce its occupied area compared to a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when a semiconductor device according to one aspect of the present invention is used as a memory device, the storage capacity per unit area can be increased. Furthermore, when a semiconductor device according to one aspect of the present invention is used as a display device, the resolution of the display can be increased.

[0164] <Example 3 of semiconductor device configuration> A portion of the transistor 200 in the semiconductor device is provided within an opening 290 in the insulating layer 280 and the conductive layer 240. By providing a narrowed portion in the opening 290, the channel width of the transistor 200 can sometimes be increased.

[0165] Figures 7(A) to 8 show an example of a semiconductor device having a transistor 200. The semiconductor device shown in Figures 7(A) to 8 differs from those in Figures 5(A) to 6(A) mainly in that the width of the upper and lower parts of the opening in the insulating layer 280 is narrower.

[0166] It is preferable that the width of the opening 290 in the insulating layer 280b is greater than the width of the opening 290 in the insulating layer 280c. Furthermore, it is preferable that the width of the opening 290 in the insulating layer 280b is greater than the width of the opening 290 in the insulating layer 280a.

[0167] In Figures 7(A) to 8, the openings 290 of the insulating layer 280a, insulating layer 280b, insulating layer 280c, and conductive layer 240 are shown as opening 290_d, opening 290_m, opening 290_u, and opening 290_b, respectively. In the configuration shown in Figures 7(A) to 8, the width of opening 290_m is shown as width R13, and the widths of openings 290_d and 290_u are shown as width R14. Width R13 is greater than width R14. Also, Figures 7(A) to 8 show an example where the widths of opening 290_d and opening 290_u are approximately the same, but the widths of opening 290_d and opening 290_u may be different. Here, if the thickness of the oxide semiconductor layer 230 is d

[0230] , the thickness of the insulating layer 250 is d

[0250] , and the thickness of the conductive layer 260a is d[260a], then the width R14 is, for example, greater than or equal to the value expressed by (d

[0230] + d

[0250] + d[260a]) × 2 (R14 ≥ (d

[0230] + d

[0250] + d[260a]) × 2). Similarly, if the thickness of the insulating layer 280b is d[280b], then d[280b] is also greater than or equal to the value expressed by (d

[0230] + d

[0250] + d[260a]) × 2 (d[280b] ≥ (d

[0230] + d

[0250] + d[260a]) × 2).

[0168] Furthermore, the width R14 can be made smaller than, for example, the thickness d[280b]. By reducing the width R14, the transistor can be miniaturized. Also, in a semiconductor device according to one aspect of the present invention, even if the width R14 is reduced, the on-current of the transistor can be made sufficiently high by increasing the width R13 of the opening in the insulating layer 280b.

[0169] Let θu2 be the angle between the side wall of opening 290_u and the plane parallel to the surface of the substrate 101, let θd2 be the angle between the side wall of opening 290_d and the plane parallel to the surface of the substrate 101, and let θm2 be the angle between the side wall of opening 290_m and the plane parallel to the surface of the substrate 101. Figure 7(B) shows an example where angles θu2, θd2, and θm2 are all 90 degrees. In this case, the upper, lower, and central parts of the opening 290 each have a cylindrical shape. Here, for example, the upper surface of a layer provided on the substrate 101 can be used as the plane parallel to the surface of the substrate 101.

[0170] In Figure 7(B), angles θu2, θd2, and θm2 are preferably between 45 degrees and 90 degrees. For example, if angle θu2 is between 80 degrees and 90 degrees, device integration can be achieved. Furthermore, by setting angle θm2 to less than 80 degrees, the coverage of the sides of the openings 290_m in the oxide semiconductor layer 230, insulating layer 250, etc., may be improved.

[0171] Furthermore, the angle θm2 may be greater than 90 degrees. In such cases, the sides of the opening 290_m can be well covered by forming the oxide semiconductor layer 230, insulating layer 250, etc., using a film formation method with high coverage.

[0172] When etching to widen the aperture width in insulating layer 280b, it is preferable to select materials for insulating layers 280a, 280b, and 280c such that insulating layers 280a and 280c are not etched during the etching process, or the etching rate is kept sufficiently low. As mentioned above, insulating layer 280b can be an insulating layer with a high oxygen supply, and insulating layers 280a and 280c can be insulating layers with a lower oxygen supply than insulating layer 280b.

[0173] For example, one or more materials selected from silicon nitride and silicon nitride oxide are used as insulating layers 280a and 280c, and one or more materials selected from silicon oxide and silicon oxide nitride are used as insulating layer 280b. Silicon nitride and silicon nitride oxide have a higher relative permittivity than silicon oxide and silicon oxide nitride. Therefore, by increasing the ratio of the thickness of insulating layer 280b to the insulating layer 280, the relative permittivity of insulating layer 280 can be lowered, and the parasitic capacitance between conductive layer 220 and conductive layer 240 can be reduced.

[0174] Regarding the materials, composition, thickness, etc., that can be used for insulating layer 280a, insulating layer 280b, and insulating layer 280c, you may refer to the descriptions for insulating layer 180a, insulating layer 180b, and insulating layer 180c.

[0175] In Figure 5(B), etc., an example is shown in which the insulating layer 280a has a laminated structure of insulating layer 280a1 and insulating layer 280a2, and the upper surface of insulating layer 280a2 is flattened. The insulating layer 280a1 can be formed using, for example, a film deposition method with high coverage, and it is preferable to form it using, for example, the ALD method. The insulating layer 280a2 can be formed using, for example, a method with a high film deposition rate, and it is preferable to form it using, for example, the sputtering method.

[0176] The insulating layer 280a1 and the insulating layer 280a2 can be constructed using the same material, for example. Alternatively, the insulating layer 280a1 and the insulating layer 280a2 may be constructed using different materials.

[0177] By positioning the channel formation region in contact with the wider portion of the opening 290 in the insulating layer 280, the channel width of the transistor can be increased.

[0178] When the region of the insulating layer 280 that is in contact with the region where the channel is formed in the oxide semiconductor layer 230 is the insulating layer 280b, the channel width W of the transistor 200 can be expressed as “width R13 × π”. Compared with the configurations shown in Figures 5(A) to 6(B), the channel width of the transistor 200 can be increased in the configurations shown in Figures 7(A) to 8.

[0179] Furthermore, when conductive layers 240 and 260 are used as wiring, their wiring widths depend on the opening width at the top of the opening 290, in this case, for example, the width R14 of opening 290_u. On the other hand, even if the width R13 of opening 290_m is increased, the wiring width does not need to be increased. In other words, even if the width R13 is increased, the area occupied by transistor 200 does not need to be increased.

[0180] Therefore, in the configurations shown in Figures 7(A) to 8, the channel width can be increased while keeping the area occupied by transistor 200 small.

[0181] In Figure 7(B), etc., the oxide semiconductor layer 230 has a portion that contacts the side surface of the opening 290_m of the insulating layer 280b, a portion that contacts the side surface of the opening 290_u of the insulating layer 280c, a portion that contacts the lower surface of the insulating layer 280c within the opening 290, a portion that contacts the side surface of the opening 290_d of the insulating layer 280a, a portion that contacts the upper surface of the insulating layer 280a within the opening 290, and a portion that contacts the upper surface of the conductive layer 220. The oxide semiconductor layer 230 also has a portion that contacts the side surface of the opening 290_b of the conductive layer 240 and a portion that contacts the upper surface of the conductive layer 240.

[0182] In the oxide semiconductor layer 230, the portion in contact with the lower surface of the insulating layer 280c and the portion in contact with the upper surface of the conductive layer 240 overlap each other, with the insulating layer 280c and the conductive layer 240 sandwiched between them.

[0183] The insulating layer 250 has portions facing the openings of the insulating layer 280 and the conductive layer 240, with the oxide semiconductor layer 230 sandwiched between them. In the configuration shown in Figure 7(B), etc., the portion of the insulating layer 250 that covers the lower surface of the insulating layer 280c and the portion that covers the upper surface of the conductive layer 240 overlap each other with the oxide semiconductor layer 230, the insulating layer 280c, and the conductive layer 240 sandwiched between them.

[0184] The conductive layer 260 has portions facing the openings of the insulating layer 280 and the conductive layer 240, with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched between them. In the configuration shown in Figure 7(B), etc., the portion of the conductive layer 260 that covers the lower surface of the insulating layer 280c and the portion that covers the upper surface of the conductive layer 240 overlap each other, with the insulating layer 250, oxide semiconductor layer 230, insulating layer 280c, and conductive layer 240 sandwiched between them.

[0185] Figures 9(A) and 9(B) show modified examples of Figures 7(B) and 8, respectively.

[0186] In addition, while Figures 7(B) and 8 show an example where the insulating layer 280a has a laminated structure consisting of insulating layer 280a1 and insulating layer 280a2, and the upper surface of insulating layer 280a2 is flattened, as shown in Figures 9(A) and 9(B), the insulating layer 280a may have a single-layer structure and may not be flattened.

[0187] The configuration shown in Figure 10(A) illustrates an example where the widths of the openings 290 in insulating layers 280a1 and 280a2 are different. The configuration in Figure 10(A) can be formed, for example, by creating openings in insulating layers 280a1, 280a2, 280b, and 280c, and then performing etching to widen the widths of the openings in insulating layers 280a1 and 280b.

[0188] For example, a material applicable to insulating layer 280b can be used as insulating layer 280a1. Similarly, a material applicable to insulating layer 280c can be used as insulating layer 280a2.

[0189] In the configuration shown in Figure 10(A), the width of the opening 290 of the insulating layer 280a1 in contact with the conductive layer 220 is large, which allows for a larger contact area between the oxide semiconductor layer 230 and the upper surface of the conductive layer 220.

[0190] In Figure 10(A), the oxide semiconductor layer 230 has a portion that contacts the side surface of the opening 290 of the insulating layer 280b, a portion that contacts the side surface of the opening 290 of the insulating layer 280c, a portion that contacts the lower surface of the insulating layer 280c within the opening 290, a portion that contacts the side surface of the opening 290 of the insulating layer 280a2, a portion that contacts the upper surface of the insulating layer 280a2 within the opening 290, a portion that contacts the lower surface of the insulating layer 280a2 within the opening 290, a portion that contacts the side surface of the opening 290 of the insulating layer 280a1, and a portion that contacts the upper surface of the conductive layer 220. The oxide semiconductor layer 230 also has a portion that contacts the side surface of the opening 290 of the conductive layer 240 and a portion that contacts the upper surface of the conductive layer 240.

[0191] In Figure 10(A), as an example, a configuration is shown where the edges of the oxide semiconductor layer 230 and the conductive layer 240 do not coincide. The conductive layer 240 has its edges outside the opening 290, and these edges are located outside the oxide semiconductor layer 230 when viewed from the opening 290 side.

[0192] The semiconductor device shown in Figure 10(B) differs from that in Figure 7(B) mainly in that an insulating layer 277 is provided between the portion of the conductive layer 260 located above the upper surface of the conductive layer 240 and the upper surface of the conductive layer 240.

[0193] The semiconductor device shown in Figure 10(B) has an insulating layer 277. The insulating layer 277 is provided on an insulating layer 250. The insulating layer 277 covers the upper surface of the conductive layer 240 with the insulating layer 250 in between.

[0194] The insulating layer 277 can be formed on the insulating layer 250 after the insulating layer 250 has been formed to cover the opening 290, the sides of the conductive layer 240, and the top surface of the conductive layer 240. By forming the insulating layer 277 using an anisotropic film deposition method, the insulating layer 277 can be selectively formed in the region covering the top surface of the conductive layer 240, while not being formed in the region covering the sides of the opening. For example, sputtering can be used as an anisotropic film deposition method.

[0195] The semiconductor device shown in Figure 10(B) has an insulating layer 277, which allows for a larger distance between the conductive layer 240 and the conductive layer 260. This reduces the parasitic capacitance between the conductive layer 240 and the conductive layer 260. Furthermore, using a material with a low dielectric constant as the insulating layer 277 can further reduce the parasitic capacitance.

[0196] As shown in Figure 11, the openings 290 of the insulating layer 280 may have multiple wide portions. In the configuration shown in Figure 11, an example is shown in which three sets of insulating layers 280b and insulating layers 280c are alternately stacked on insulating layer 280a in the insulating layer 280. The width of the openings 290 of insulating layer 280b is wider than the width of the openings 290 of insulating layer 280a and insulating layer 280c. If the portion of the oxide semiconductor layer 230 in contact with insulating layers 280a and 280c is a low-resistance region, then by using such a configuration, for example, the oxide semiconductor layer 230 can be divided into multiple channel-forming regions, such as "low-resistance region" - "channel-forming region" - "low-resistance region" - "channel-forming region" - "low-resistance region", with low-resistance regions sandwiched in between. Using such a configuration may improve the reliability of the transistor, for example.

[0197] Figure 11 shows an example where the insulating layer 280 has three wide sections, but there may be two or more wide sections.

[0198] Furthermore, while Figure 11 shows an example where the width of the opening 290 does not change with respect to the depth of the opening 290, the etching speed may slow down when etching to widen the opening width of the insulating layer 280b as the opening 290 is deeper. For example, as shown in Figure 12, the width of the opening 290 located on the side of the insulating layer 280b may become narrower as the opening 290 is deeper.

[0199] Here, in etching to widen the opening width of the insulating layer 280b by reducing the thickness of the insulating layer 280b at a deeper position of the opening 290, the etching rate may increase. As shown in Figure 13, in the three sets of insulating layers 280b and insulating layer 280c, the insulating layers are labeled 280b(1), 280b(2), and 280b(3) in order from closest to the conductive layer 220. By making insulating layer 280b(2) thinner than insulating layer 280b(3) and insulating layer 280b(1) thinner than insulating layer 280b(2), it may be possible to reduce the difference in the width of the opening 290 in insulating layer 280b(1), insulating layer 280b(2), and insulating layer 280b(3). Therefore, the difference in the width of the opening at the top and bottom (bottom) of the opening can be mitigated.

[0200] [Insulating layer] It is preferable to use inorganic insulating films for the insulating layers of a semiconductor device (insulating layer 180, insulating layer 130, insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 277, etc.). Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of materials applicable to oxide insulating films include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of materials applicable to nitride insulating films include silicon nitride and aluminum nitride. Examples of materials applicable to oxidative nitride insulating films include silicon oxidative nitride, aluminum oxidative nitride, gallium oxidative nitride, yttrium oxidative nitride, and hafnium oxidative nitride. Examples of materials applicable to nitride oxide insulating films include silicon nitride and aluminum nitride. In addition, organic insulating films may be used for the insulating layers of a semiconductor device.

[0201] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0202] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies is another example. These silicon oxides may contain nitrogen.

[0203] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Another example of a ferroelectric material is a material obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to it. Another example of a ferroelectric material is a material obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. Furthermore, the ratio of zirconium atoms to element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. Also, as a material that can possess ferroelectric properties, lead titanate (PbTiO) X ), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate may also be used.

[0204] Furthermore, metal nitrides containing element M1, element M2, and nitrogen can be cited as materials that may possess ferroelectricity. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Also, metal oxides containing element M1 and nitrogen may possess ferroelectricity even without element M2. Furthermore, materials in which element M3 is added to the above-mentioned metal nitrides can be cited as materials that may possess ferroelectricity. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.

[0205] Furthermore, materials that may possess ferroelectric properties include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0206] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, may be used.

[0207] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in Embodiment 3 can be a laminated structure consisting of multiple materials selected from the materials listed above. Incidentally, the crystal structure (properties) of the materials listed above may change not only depending on the film formation conditions but also on various processes, so in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0208] Metal oxides containing either or both hafnium and zirconium can exhibit ferroelectric properties even in thin films of a few nanometers. Furthermore, metal oxides containing either or both hafnium and zirconium can exhibit ferroelectric properties even in minute areas. Therefore, the miniaturization of semiconductor devices can be achieved by using metal oxides containing either or both hafnium and zirconium.

[0209] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0210] Ferroelectricity is believed to be exhibited when oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this is preferable because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having both an amorphous structure and a crystalline structure.

[0211] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and enhances remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0212] Metal oxides containing one or both of hafnium and zirconium are preferred because they can possess ferroelectric properties even in thin films of a few nanometers. When used as an insulating layer 130, the film thickness is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). Furthermore, for example, a film thickness of 8 nm to 12 nm is preferred. By using a ferroelectric layer that can be made into a thin film, the capacitive element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0213] Furthermore, metal oxides containing either or both hafnium and zirconium are preferred because they can exhibit ferroelectric properties even over a minute area. For example, if the area (occupied area) of the ferroelectric layer in a plan view is 100 μm² 2 The following is preferably 10 μm 2 More preferably, 1 μm 2More preferably 0.1 μm 2 Even if the following is true, it can still possess ferroelectric properties. Also, 10000nm 2 The following is preferably 1000 nm 2 Even in the following cases, ferroelectric properties may be present. By using a ferroelectric layer with a small area, the occupied area of ​​the capacitive element 100 can be reduced.

[0214] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or multilayer configuration. Specifically, as materials for the insulating layer that has the function of suppressing the permeation of impurities and oxygen, oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, nitrides such as aluminum nitride and silicon nitride, and nitride oxides such as silicon nitride can be used.

[0215] Specifically, materials for insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also, examples include nitrides such as aluminum nitride, titanium aluminum nitride, and silicon nitride. Furthermore, examples include nitride oxides such as silicon nitride.

[0216] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that have regions containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). For example, by having an insulating layer having regions containing excess oxygen in contact with the oxide semiconductor layer or located near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layer materials that easily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with vacancies.

[0217] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer.

[0218] Examples of insulating layer materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, aluminum and hafnium-containing oxides (hafnium aluminate), and hafnium and silicon-containing oxides (hafnium silicate). Furthermore, these metal oxides may also contain zirconium; for example, an oxide containing hafnium and zirconium is an example.

[0219] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0220] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0221] Furthermore, the above insulating layer may have, in part, a crystalline region and / or a grain boundary.

[0222] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as barrier properties.

[0223] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, "barrier property" refers to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to, for example, a hydrogen atom, a hydrogen molecule, and water molecules and OH groups. - This refers to at least one substance bonded with hydrogen, such as [specific examples of hydrogen-containing substances]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, and refers to at least one of the following: hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc.

[0224] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide.

[0225] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0226] It is preferable to use a hydrogen barrier insulating layer for the insulating layer 210. The insulating layer 210, located below the oxide semiconductor layer 230, has hydrogen barrier properties, thereby suppressing the diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230. For example, it is preferable to use a silicon nitride film as the insulating layer 210.

[0227] Furthermore, it is preferable to use an insulating layer 210 that has the function of capturing or fixing hydrogen. Because the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 can diffuse into the insulating layer 210 via the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0228] Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 210 is reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0229] The insulating layer 210 can have a laminated structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, it is preferable to use a hydrogen barrier insulating layer as the first insulating layer and an insulating layer having the function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0230] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0231] Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. This makes it possible to suppress the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0232] For example, an insulating layer having regions containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. In this way, by depositing at least a portion of the layers constituting the insulating layer 280 using the sputtering method, oxygen is supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby eliminating oxygen vacancies and V O This can help reduce H.

[0233] It is preferable to use a hydrogen barrier insulating layer for the insulating layer 250. The insulating layer 250 provided on the oxide semiconductor layer 230 has hydrogen barrier properties, thereby suppressing the diffusion of hydrogen contained in the conductive layer 260 into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has high hydrogen barrier properties.

[0234] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer that has the function of capturing or fixing hydrogen. This allows for more effective capture or fixing of hydrogen contained in the oxide semiconductor layer 230. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (especially the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V in the channel formation region O By reducing H, the channel-forming region can be made i-type or substantially i-type.

[0235] Furthermore, it is preferable to use an insulating layer 250 that has a region containing excess oxygen. This allows oxygen to be supplied from the insulating layer 250 to the oxide semiconductor layer 230, thereby reducing oxygen deficiencies in the oxide semiconductor layer 230. Silicon oxide films or silicon oxynitride films are suitable as insulating layers 250 because they have a thermally stable structure.

[0236] The insulating layer 250 can be a laminated structure of two or more layers. In this case, it is preferable that the insulating layer 250 is formed from two or more types of films. By making the insulating layer 250 from two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of functions that the insulating layer 250 may have include the function of extracting hydrogen from the oxide semiconductor layer 230 and the function of suppressing the diffusion of hydrogen into the oxide semiconductor layer 230.

[0237] For example, the insulating layer 250 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having the function of capturing or fixing hydrogen as the first insulating layer, and a hydrogen barrier insulating layer as the second insulating layer. With such a configuration, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0238] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer, and a hydrogen barrier insulating layer as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer, and an insulating layer having the function of capturing or fixing hydrogen as the second insulating layer. By adopting such a configuration, the amount of oxygen vacancy and hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0239] Furthermore, for example, the insulating layer 250 may have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 may have a three-layer structure consisting of a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0240] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer made of a material with a low dielectric constant as the third insulating layer, an insulating layer having the function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. It is preferable to use a silicon oxide film or a silicon oxynitride film as the third insulating layer. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, by providing a second insulating layer, the diffusion of oxygen contained in the third insulating layer into the conductive layer 260 can be suppressed, thereby suppressing oxidation of the conductive layer 260. In addition, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0241] Furthermore, for example, the insulating layer 250 may have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure consisting of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0242] As the fourth insulating layer, it is preferable to use an insulating layer having barrier properties against oxygen. Regarding the first to third insulating layers, the same configuration as the layers used in the above-described three-layer structure can be applied. The fourth insulating layer is a layer that contacts the oxide semiconductor layer 230 and the conductive layer 240. Since the fourth insulating layer has barrier properties against oxygen, it is possible to suppress the desorption of oxygen from the oxide semiconductor layer 230. In addition, it is possible to suppress the oxidation of the side surface of the conductive layer 240 and the formation of an oxide film on the side surface. Thereby, it is possible to suppress a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0243] As the fourth insulating layer, for example, an aluminum oxide film may be used. Since the aluminum oxide film has a function of capturing or fixing hydrogen, it is suitable as the fourth insulating layer that contacts the oxide semiconductor layer 230. Specifically, it is preferable to use a four-layer structure in which the insulating layer 250 is laminated in the order of an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film from the oxide semiconductor layer 230 side.

[0244] The insulating layer 250 is preferably a thin film. For example, by setting the film thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, it is possible to reduce the subthreshold swing value (also referred to as the S value), which is one of the transistor characteristics. The S value refers to the change amount of the gate voltage when the drain voltage is constant and the drain current is changed by one digit in the subthreshold region.

[0245] In addition, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Each layer constituting the insulating layer 250 only needs to have a film thickness region as described above at least partially.

[0246] Typically, the film thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This configuration allows for good electrical characteristics even when the transistor is miniaturized or highly integrated.

[0247] Furthermore, in the four-layer insulating layer 250, a configuration without a second insulating layer is also possible. For example, it is possible to use an insulating layer having barrier properties against oxygen as the fourth insulating layer, an insulating layer having a low dielectric constant as the third insulating layer, and an insulating layer having the function of capturing or fixing hydrogen as the first insulating layer. Specifically, it is possible to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the oxide semiconductor layer 230 side.

[0248] Furthermore, in forming the insulating layer 250 having a laminated structure of multiple insulating films, it is preferable to use the ALD process two or more times. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 250 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 250 can be improved. In addition, productivity can be increased by continuously forming two or more films, for example, two or more insulating films, using the ALD process.

[0249] Organic materials can also be used as the insulating layer. Preferably, a photosensitive resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin may be used. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0250] Organic materials are not limited to those listed above. For example, acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, silicone resins, siloxane resins, benzocyclobutene resins, phenolic resins, or precursors of these resins may be used. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resins may be used. Furthermore, for example, photoresists may be used as photosensitive resins. Photosensitive resins may include positive-type materials or negative-type materials.

[0251] [Conductive layer] It is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy composed of the aforementioned metal elements, or an alloy combining the aforementioned metal elements, etc., for the conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 220, conductive layer 240, conductive layer 260, etc.) of a semiconductor device. Alternatively, nitrides of alloys composed of the aforementioned metal elements, or oxides of such alloys, may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0252] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, ITSO, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0253] Conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

[0254] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0255] The conductive layer 260 has a region that functions as gate wiring. It is preferable to use a highly conductive material such as tungsten for the conductive layer 260. It is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. As mentioned above, such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This makes it possible to suppress a decrease in the conductivity of the conductive layer 260.

[0256] Furthermore, it is preferable to use a conductive material containing metal elements and oxygen from the metal oxide in which the channels are formed for the conductive layer 260. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channels are formed. Alternatively, it may be possible to capture hydrogen that is mixed in from the outer insulating layer, etc.

[0257] [substrate] As the substrate for forming the transistor (e.g., substrate 101), for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0258] The above describes the materials that can be used in the semiconductor device of this embodiment.

[0259] <Examples of semiconductor device fabrication methods> The method for manufacturing a semiconductor device will be explained using Figures 14(A) to 16. Here, as an example, the method for manufacturing the configuration shown in Figure 7(B) will be explained. Note that explanations of the materials and formation methods of each element may be omitted if they are the same as those explained earlier.

[0260] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), ALD, pulsed laser deposition (PLD), molecular beam epitaxy (MBE), vacuum deposition, and other methods.

[0261] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. There is also RF superimposed DC sputtering, which superimposes RF and DC. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also form insulating films by performing reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used mainly when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. RF superimposed DC sputtering allows for control of the ion energy during film deposition and control of the target side potential. Therefore, compared to RF sputtering, damage during film deposition is reduced, and a higher quality film can be obtained.

[0262] Sputtering is a film deposition method that uses the deposition of particles emitted from a target, and it can be said that it is a film deposition method in which the deposition rate tends to be anisotropic.

[0263] For example, ionization sputtering can be used as a sputtering method. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and a film is deposited with high anisotropy due to self-bias, etc.

[0264] Also, as a sputtering method, for example, by using a long-throw sputtering method, a collimator sputtering method, etc., a film with higher anisotropy can also be formed. The long-throw sputtering method is a technique for forming a film with high anisotropy by increasing the distance between the sputtering target and the substrate.

[0265] The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

[0266] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, the thermal CVD method does not use plasma, so it is a film formation method that can reduce plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0267] Also, as the ALD method, a thermal ALD (Thermal ALD) method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD (Plasma Enhanced ALD) method that uses a plasma-excited reactant, etc. can be used.

[0268] Furthermore, the ALD method allows for the deposition of atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. The PEALD method, by utilizing plasma, allows for even lower temperatures and is sometimes preferable. Note that precursors used in the ALD method may contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that in one embodiment of the present invention, the ALD method is used for depositing metal oxide films, but because high substrate temperatures are used during film formation, and or both impurity removal treatments are applied, the amount of carbon and chlorine contained in the film may be lower compared to when the ALD method is used without these treatments.

[0269] Unlike film deposition methods where particles emitted from a target or other source are deposited, ALD and CVD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. Furthermore, the ALD method enables isotropic film deposition. The ALD method can also be described as a film deposition method with low anisotropy in deposition rate. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as sputtering or CVD. For example, when a metal oxide is formed as a laminated structure of a first metal oxide and a second metal oxide, one method is to deposit the first metal oxide using sputtering and then deposit the second metal oxide on top of the first metal oxide using the ALD method. For example, if the first metal oxide has a crystalline portion, the second metal oxide may grow crystals using the crystalline portion as a nucleus.

[0270] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because the time required for transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0271] Furthermore, in the ALD method, films of any composition can be deposited by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse duration). In addition, films of any composition can be deposited in the ALD method by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0272] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film deposition methods such as spin coating, dip coating, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0273] Furthermore, lithography or the like can be used when processing the thin films that constitute the semiconductor device. Alternatively, the thin films may be processed by nanoimprint lithography, sandblasting, lift-off lithography, or the like. In addition, island-shaped thin films may be directly formed by a film deposition method using a shielding mask such as a metal mask.

[0274] There are two main lithography methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0275] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0276] Thin film etching can be performed using methods such as dry etching, wet etching, ashing, plasma treatment, and reverse sputtering. Sandblasting may also be used for etching thin films.

[0277] For dry etching, for example, a gas containing halogens can be used as the etching gas.

[0278] As halogen-containing gases, etching gases containing one or more of fluorine, chlorine, and bromine can be used. Fluorocarbon gases, hydrofluorocarbon gases, SF6 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used individually or in mixtures of two or more gases. As for fluorocarbon gases, C x F y Gases represented by (y ≤ 2x + 2) can be used. Examples of fluorocarbon gases that satisfy y = 2x + 2 include CF4, C2F6, C3F8, and C4F. 10 , C5F 12 Examples of saturated fluorocarbon compounds include C2F4, C2F2, C3F7, C3F4, C4F8, C4F6, C4F4, C4F2, and C5F. 10Examples include unsaturated fluorinated carbon compounds such as C5F8, C5F6, and C5F4. Examples of hydrofluorocarbon gases include CHF3 gas and CH2F2 gas.

[0279] Furthermore, when using halogen-containing gases as etching gases, oxygen (O2), carbon dioxide, nitrogen (N2), helium, argon, hydrogen, or hydrocarbon gases can be added as appropriate.

[0280] Furthermore, gases that do not contain halogen gases but contain hydrocarbon gases or hydrogen gases can be used as etching gases.

[0281] Examples of hydrocarbon gases include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H6). 10 One or more of the following can be used: ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4).

[0282] Furthermore, when using hydrocarbon gases as etching gases, nitrogen gas, helium gas, argon gas, or hydrogen gas can be added as appropriate.

[0283] Furthermore, a capacitively coupled plasma (CCP) etching apparatus with parallel plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus with parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus with a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched.

[0284] First, a conductive layer 220 is formed on the insulating layer 210, and then insulating layers 280a1, 280a2, 280b, 280c, conductive film 240af, and conductive film 240bf are formed sequentially on the conductive layer 220 (Figure 14(A)).

[0285] Furthermore, it is preferable to perform a planarization treatment (also called CMP treatment) using the Chemical Mechanical Polishing (CMP) method after the deposition of the insulating layer 280 to flatten the upper surface of the insulating layer 280. By performing the planarization treatment of the insulating layer 280, the surface on which the conductive layer 240, which functions as wiring, is formed can be made flat, and the step breakage of the conductive layer 240 can be suppressed. However, the planarization treatment is not required, in which case manufacturing costs can be reduced.

[0286] Next, openings are formed in the conductive film 240bf, conductive film 240af, insulating layer 280c, insulating layer 280b, insulating layer 280a2, and insulating layer 280a1 at positions overlapping with the conductive layer 220 (Figure 14(B)). Openings 290_b are formed in the conductive film 240af and conductive film 240bf, openings 290_u are formed in the insulating layer 280c, openings 290_ma are formed in the insulating layer 280b, and openings 290_d are formed in the insulating layer 280a. In subsequent etching, the width of opening 290_ma is widened to become opening 290_m. Also, recesses are formed in the conductive layer 220 at positions overlapping with openings 290.

[0287] In Figure 14(B), it can also be described that an opening with a continuous side surface is formed in the laminated structure from the conductive film 240bf to the insulating layer 280a1. Since this opening has a large aspect ratio, it is preferable to form it using anisotropic etching. In particular, processing by dry etching is preferred because it is suitable for microfabrication. Furthermore, this processing may be carried out under different conditions for each layer.

[0288] Next, a heat treatment may be performed. The heat treatment can be performed, for example, at a temperature of 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. For example, the treatment time can be 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350°C to 550°C.

[0289] The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. By performing the above heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before the oxide semiconductor layer 230 is formed.

[0290] The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture being incorporated into the insulating layer 280 and the like.

[0291] In addition to or instead of heat treatment, microwave plasma treatment may be performed.

[0292] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0293] It is preferable to reduce the impurity concentration in the oxide semiconductor layer 230 by performing microwave plasma treatment in an oxygen-containing atmosphere. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere, the method is not limited to this. For example, microwave plasma treatment may be performed in an oxygen-containing atmosphere on an insulating film, more specifically a silicon oxide film, provided near the metal oxide. Furthermore, the heat generated during microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0294] Microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0295] When performing microwave plasma processing, the substrate may be heated. Preferably, the heating temperature of the substrate should be above room temperature (e.g., 25°C), 100°C, 200°C, 300°C, or 400°C, and below 500°C or 450°C.

[0296] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O2 / (O2+Ar)) in microwave plasma treatment is preferably greater than 0% and 10% or less, preferably between 0.5% and 5%, more preferably between 0.5% and 3%, and typically more preferably 1%.

[0297] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and the oxygen radicals generated by the plasma-generated oxygen gas can act on the oxide semiconductor layer. Through the action of plasma, microwaves, oxygen radicals, etc., hydrogen can be added to oxygen vacancies in the oxide semiconductor layer to create defects (hereinafter referred to as V O V (sometimes called H) can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. O H can be reduced. In addition, carbon that was bonded to oxygen or hydrogen can sometimes be removed at this time. In this way, impurities such as carbon or hydrogen can be reduced by microwave plasma treatment. Furthermore, by supplying the above oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0298] Next, an etching process is performed to widen the opening 290_ma in the insulating layer 280b, thereby forming an opening 290_m in the insulating layer 280b (Figure 15(A)). The etching process performed here is preferably isotropic etching.

[0299] For example, when silicon oxide or silicon oxynitride is used as the insulating layer 280b, and silicon nitride is used as the insulating layers 280a1, 280a2, and 280c, the insulating layer 280b can be selectively etched by performing a wet etching treatment using a solution containing hydrofluoric acid.

[0300] Furthermore, the solution used for wet etching may contain a mixture of hydrofluoric acid and ammonium fluoride, etc.

[0301] Next, an oxide semiconductor film 230f is formed to cover the sides of the openings 290_b of the conductive layer 240a and conductive layer 240b, the sides of the opening 290_u of the insulating layer 280c, the bottom surface of the insulating layer 280c, the sides of the opening 290_m of the insulating layer 280b, the top surface of the insulating layer 280a2, the sides of the opening 290_d of the insulating layer 280a2, and the recesses of the conductive layer 220 (Figure 15(B)). The oxide semiconductor film 230f is the layer that becomes the oxide semiconductor layer 230.

[0302] The oxide semiconductor film 230f can also be formed by stacking multiple layers.

[0303] Furthermore, it is preferable that the oxide semiconductor film 230f has a high aspect ratio and high coverage of the side walls and bottom of the small aperture 290. Therefore, it is preferable that at least some of the layers of the multiple layers formed as the oxide semiconductor film 230f are formed using a method that provides excellent coverage. Here, the oxide semiconductor film 230f is formed using the ALD method.

[0304] Following the formation of the oxide semiconductor film 230f, a heat treatment may be performed. By performing the heat treatment, for example, impurities in the oxide semiconductor film 230f can be reduced. In addition, the crystallinity of the oxide semiconductor film 230f may be increased. Alternatively, microwave plasma treatment may be performed following the formation of the oxide semiconductor film 230f. By performing the microwave plasma treatment, for example, impurities in the oxide semiconductor film 230f can be reduced. In addition, the crystallinity of the oxide semiconductor film 230f may be increased.

[0305] Next, the oxide semiconductor film 230f, the conductive film 240bf, and the conductive film 240af are processed into island-like structures to form the oxide semiconductor layer 230, the conductive layer 240b, and the conductive layer 240a (Figure 16). Here, the oxide semiconductor layer 230, the conductive layer 240b, and the conductive layer 240a can be processed simultaneously using the same mask.

[0306] Furthermore, the processes for processing the oxide semiconductor film 230f, the conductive film 240bf, and the conductive film 240af into island-like structures can be carried out independently.

[0307] Next, an insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0308] Furthermore, a heat treatment may be performed following the formation of the insulating layer 250. Alternatively, microwave plasma treatment may be performed following the formation of the insulating layer 250.

[0309] Next, a conductive layer 260 is formed on the insulating layer 250.

[0310] Based on the above, the semiconductor device shown in Figure 7(B) can be fabricated.

[0311] <Example 1 of a semiconductor device> A modified example of the semiconductor device will be explained using Figures 17(A) and 17(B).

[0312] The semiconductor device shown in Figure 17(A) has a transistor 200. In the manufacturing process shown in Figure 14(A), the conductive film 240bf is not formed on the transistor 200. Instead, openings are made in the insulating layer 280 and the conductive film 240af with reference to Figure 14(B), and then the conductive film 240bf is formed inside the openings and on the conductive film 240af. In this case, if a highly anisotropic film deposition method is used to form the conductive film 240bf, the conductive film 240bf is less likely to form on the sides of the openings in the insulating layer 280, and the conductive film 240bf is formed on the conductive film 240af and at the bottom of the openings.

[0313] By using the above manufacturing method, the transistor 200 shown in Figure 17(A) can be formed. In Figure 17(A), a conductive layer 240_3b is formed on the conductive layer 220. When the conductive film 240bf is formed, the portion formed on the conductive film 240af becomes the conductive layer 240b shown in Figure 17(A), and the portion formed on the conductive layer 220 at the bottom of the opening becomes the conductive layer 240_3b shown in Figure 17(A).

[0314] Depending on the depth and width of the opening, the conductive film 240bf may not be formed at the bottom of the opening.

[0315] Furthermore, as shown in Figure 17(B), when the conductive film 240bf is formed, the conductive film 240bf may also be formed on the sides of the openings of the conductive film 240af. In this case, the conductive layer 240b covers not only the top surface of the conductive layer 240a but also the sides.

[0316] Furthermore, in Figure 17(B), the conductive layer 240b covers not only the sides of the conductive layer 240a but also the sides of the insulating layer 280c.

[0317] When using a conductive layer that is easily oxidized as conductive layer 240a, oxidation of conductive layer 240a can be suppressed by using a conductive layer that is not easily oxidized as conductive layer 240b and covering the sides of conductive layer 240a.

[0318] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be appropriately combined.

[0319] (Embodiment 2) In this embodiment, a memory device according to one aspect of the present invention will be described with reference to Figures 18(A) to 20. The memory device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element.

[0320] <Example of storage device configuration 1> The configuration of a memory device having transistors and capacitive elements will be explained using Figures 18(A) and 18(B). Figure 18(A) is a plan view of a memory device having transistors 200 and capacitive elements 100. Figure 18(B) is a cross-sectional view corresponding to the dashed line C1-C2 shown in Figure 18(A). Figure 18(A) is a plan view showing an example in which four memory cells 150 are arranged in two rows in the Y direction and two columns in the X direction.

[0321] Each memory cell 150 has a capacitive element 100 and a transistor 200 on the capacitive element 100.

[0322] The memory device shown in Figures 18(A) and 18(B) comprises an insulating layer 140 on a substrate 101, a conductive layer 110 on the insulating layer 140, a plurality of memory cells 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 280.

[0323] The conductive layer 110 functions as wiring. Furthermore, the conductive layer 110 is shared by multiple memory cells 150.

[0324] The memory cell 150 includes a capacitive element 100 on a conductive layer 110 and a transistor 200 on the capacitive element 100.

[0325] The capacitive element 100 has a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The capacitive element 100 shown in the previous embodiment can be used as the capacitive element 100.

[0326] An insulating layer 280 is placed on the capacitive element 100.

[0327] The transistor 200 shown in the previous embodiment can be used as the transistor 200. In Figure 18(B), an example is shown in which the conductive layer 120 of a capacitive element is used instead of the conductive layer 220 of the transistor 200 shown in Embodiment 1. Alternatively, the conductive layer 220 can be formed by layering the conductive layer 220 on top of the conductive layer 120 without omitting the conductive layer 220.

[0328] As shown in Figure 18(B), the transistor 200 is provided so as to overlap with the capacitive element 100. Furthermore, the opening 290, through which part of the transistor 200's structure is provided, has a region that overlaps with the opening 190 through which part of the capacitive element 100's structure is provided. In particular, the conductive layer 120 functions as both the source electrode and drain electrode of the transistor 200, and as the upper electrode of the capacitive element 100; therefore, the transistor 200 and the capacitive element 100 share a portion of their structure. This configuration allows the transistor 200 and the capacitive element 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, allowing for a higher density arrangement of the memory cell 150 and thus increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0329] Furthermore, by positioning the transistor 200 above the capacitive element 100, the transistor 200 is not affected by the heat treatment during the manufacturing of the capacitive element 100. Therefore, in the transistor 200, fluctuations in the threshold voltage, deterioration of electrical characteristics such as an increase in parasitic resistance, and an increase in variations in electrical characteristics due to the deterioration of electrical characteristics can be suppressed.

[0330] <Example of storage device configuration 2> The configuration of a memory device having two transistors will be explained using Figures 19(A) and 19(B). Figure 19(A) is a plan view of a memory device having two transistors 200. Figure 19(B) is a cross-sectional view corresponding to the dashed line D1-D2 shown in Figure 19(A). Figure 19(A) is a plan view showing an example in which four memory cells 151 are arranged in two rows in the Y direction and two columns in the X direction.

[0331] Each memory cell 151 has two transistors 200 (transistor 200, transistor 200(2)).

[0332] The storage device shown in Figures 19(A) and 19(B) comprises an insulating layer 210 on a substrate 101, a plurality of memory cells 151 on the insulating layer 210, an insulating layer 180 on the insulating layer 210, and an insulating layer 280.

[0333] The memory cell 151 has a transistor 200 on the insulating layer 210 and a transistor 200(2) on the transistor 200.

[0334] The transistor 200 shown in the previous embodiment can be used as transistor 200 and transistor 200(2).

[0335] An insulating layer 280(2) is placed on the transistor 200. The composition and materials of the insulating layer 280(2) can be found in the description of insulating layer 280.

[0336] The oxide semiconductor layer 230, conductive layer 240, conductive layer 260, and insulating layer 250 of transistor 200(2) are denoted as oxide semiconductor layer 230(2), conductive layer 240(2), conductive layer 260(2), and insulating layer 250(2), respectively. The oxide semiconductor layer 230(2), insulating layer 250(2), and conductive layer 260(2) each have portions located within the openings 290(2) of the insulating layer 280(2) and conductive layer 240, respectively.

[0337] In the transistor 200(2) shown in Figure 19(B), the conductive layer 260 of transistor 200 is used instead of the conductive layer 220 shown in Embodiment 1. Alternatively, the conductive layer 220 of transistor 200(2) can be formed on top of the conductive layer 260 of transistor 200 without omitting the conductive layer 220 of transistor 200(2).

[0338] As shown in Figures 19(A) and 19(B), the two transistors 200 are arranged to overlap. Furthermore, the opening 290, through which part of the structure of transistor 200 is provided, has an overlapping region with the opening 290(2), through which part of the structure of transistor 200(2) is provided. With this configuration, two transistors 200 can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 151 can be reduced, allowing for a high-density arrangement of the memory cell 151 and increasing the storage capacity of the storage device.

[0339] <Example of storage device configuration 3> A device according to one embodiment of the present invention will be described using Figure 20. The device shown in Figure 20 has a memory cell 80A. For example, the configuration of the memory cell 150 shown in Figures 18(A) and 18(B) can be applied to the configuration of the memory cell 80A.

[0340] The memory device shown in Figure 20 has a memory cell 80A above the Si transistor 900. The Si transistor 900 is, for example, one of the transistors in the peripheral circuitry of the memory cell.

[0341] This section describes the Si transistor 900. The Si transistor 900 is a Fin-type transistor. Figure 20 shows a schematic cross-sectional view in the channel length direction.

[0342] The Si transistor 900 is provided on the substrate 901 and has a conductive layer 908a that functions as a gate electrode, an insulating layer 907 that functions as a gate insulating film, a semiconductor region 903 that functions as a channel formation region, and a low-resistance region 904 that functions as a source region or drain region.

[0343] For example, the substrate 901 can be a silicon substrate, an SOI substrate, or the like.

[0344] A device isolation layer 902, an insulating layer 905, and dummy gate electrodes 908b and 908c are provided on the substrate 901. The insulating layer 905 functions as a sidewall. In addition, insulating layers 906, 909, 910, 911, 913, 915, and 916 are provided, and these insulating layers function as interlayer insulating films. In addition, insulating layers 909, 911, and 915 function as barrier films. Conductive layers 912 and 914 function as plugs, electrodes, or wiring.

[0345] One of the sources or drains of the Si transistor 900 (in this case, the low-resistance region 904) is connected to the memory cell 80A via a conductive layer.

[0346] A portion of the conductive layer 54a is provided so as to be embedded in the insulating layer 916. The conductive layer 54a is connected to the Si transistor 900 via the conductive layer 914.

[0347] The insulating layers 813 and 814 are provided on the memory cell 80A. It is preferable to use insulating films for the insulating layers 813 and 814 that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating films that have the function of capturing or fixing hydrogen, insulating films that have barrier properties against hydrogen, or insulating films that have barrier properties against oxygen. By using these insulating films, the diffusion of hydrogen into the semiconductor layer of the transistor in the memory cell 80A can be suppressed.

[0348] The conductive layers 815a and 815d are provided so as to be embedded in the insulating layers 813 and 814. The conductive layers 815a and 815d can be formed as a single layer or a laminate. For example, the conductive layers 815a and 815d can be a two-layer structure using tungsten on titanium nitride. Because highly conductive materials such as tungsten can be used, the wiring resistance of the conductive layers 815a and 815d can be reduced. Alternatively, the conductive layers 815a and 815d can use a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Alternatively, the conductive layers 815a and 815d can use a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer.

[0349] The conductive layer 812a is provided to connect the conductive layer 815a and the conductive layer 54a.

[0350] The conductive layer 812d is provided to connect the conductive layer 815d and the conductive layer 240.

[0351] This embodiment can be appropriately combined with other embodiments or examples.

[0352] (Embodiment 3) This embodiment describes an oxide semiconductor layer that can be used as a semiconductor layer in a transistor.

[0353] This section describes materials that can be used in the semiconductor layer of a transistor.

[0354] The semiconductor material is not particularly limited. For example, semiconductors made of elemental materials or compound semiconductors can be used. Examples of semiconductors made of elemental materials include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0355] The crystallinity of the semiconductor material is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0356] The semiconductor layer can be made of, for example, silicon. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0357] This paper describes metal oxides suitable for use as the oxide semiconductor layer in OS transistors.

[0358] The crystallinity of the metal oxide is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) may be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0359] OS transistors have oxygen vacancies (V) in the channel formation region of metal oxides. O) and impurities can cause electrical properties to fluctuate easily, potentially leading to poor reliability. In addition, defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) can also occur. O This can form an oxygen vacancy (sometimes called H) and generate electrons that act as carriers. Therefore, if the channel-forming region in the metal oxide contains oxygen vacancies, the OS transistor is likely to become normally-on. Consequently, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel-forming region of the metal oxide. In other words, it is preferable that the carrier concentration in the channel-forming region of the metal oxide is reduced and that it is i-type (intrinsic) or substantially i-type.

[0360] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the region has a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or metallic elements, which increases the carrier concentration and lowers the resistance. In other words, it is preferable that the source and drain regions of an OS transistor are n-type regions with a higher carrier concentration and lower resistance compared to the channel formation region.

[0361] The bandgap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher. By using a metal oxide with a large bandgap in the oxide semiconductor layer, the off-current of the transistor can be reduced. Because OS transistors have a small off-current, the power consumption of semiconductor devices can be significantly reduced. In addition, because OS transistors have high frequency characteristics, semiconductor devices can be operated at high speeds.

[0362] For example, indium oxide is a metal oxide that can be used in the semiconductor layer of an OS transistor.

[0363] Furthermore, examples of metal oxides that can be used in the semiconductor layer of an OS transistor include oxides containing one or more elements selected from In, Sn, Zn, Ga, Al, W, and Ti. In these oxides, the content of one or more elements selected from In, Sn, Zn, Ga, Al, W, and Ti is preferably, for example, 1 atomic% or more.

[0364] In addition to the aforementioned indium oxide, the metal oxides in question include zinc oxide, tin oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium tungsten oxide (In-W oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), and aluminum zinc oxide (Al-Zn oxide, "AZ"). Other materials that can be used include indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0365] The composition of the In-Zn oxide can be specifically In:Zn = 1:1 [atomic ratio] or a composition close to that, In:Zn = 2:1 [atomic ratio] or a composition close to that, or In:Zn = 4:1 [atomic ratio] or a composition close to that. Note that a composition close to the desired atomic ratio includes a range of ±30%.

[0366] Specifically, the composition of the In-M-Zn oxide can be any metal oxide with the following atomic ratios: In:M:Zn=1:1:1 or close to it, In:M:Zn=1:1:1.2 or close to it, In:M:Zn=1:1:0.5 or close to it, In:M:Zn=1:1:2 or close to it, In:M:Zn=4:2:3 or close to it, In:M:Zn=1:3:2 or close to it, or In:M:Zn=1:3:4 or close to it. Alternatively, the composition can include trace amounts of element M, such as In:M:Zn=4:0.1:1 [atomic ratio] or close to it, In:M:Zn=2:0.1:1 [atomic ratio] or close to it, or In:M:Zn=1:0.1:1 [atomic ratio] or close to it. Here, element M can be aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0367] For the analysis of the composition of metal oxides, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0368] Examples of crystal structures for metal oxides that function as semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0369] Furthermore, by increasing the ratio of zinc atoms to the sum of the atoms of the metal elements among the main constituent elements contained in the metal oxide, a highly crystalline metal oxide can be obtained, suppressing the diffusion of impurities in the metal oxide. Therefore, fluctuations in the electrical properties of the transistor can be suppressed, and reliability can be improved.

[0370] Furthermore, by increasing the ratio of element M atoms to the sum of the atoms of metal elements among the main constituent elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0371] By increasing the ratio of indium atoms to the sum of all metal element atoms in a metal oxide, the field-effect mobility of a transistor can be improved. Typically, using single-crystal or polycrystalline indium oxide in the semiconductor layer significantly increases the field-effect mobility of a transistor. Furthermore, transistors using single-crystal or polycrystalline indium oxide in the semiconductor layer can achieve excellent frequency characteristics.

[0372] An oxide semiconductor layer according to one aspect of the present invention may, for example, have a crystalline metal oxide. Examples of structures of the crystalline metal oxide include CAAC structure, polycrystalline structure, and nc structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer according to one aspect of the present invention can be improved, and the reliability of a semiconductor device on which the transistor is mounted can be improved.

[0373] Furthermore, the semiconductor device of this embodiment may also be a transistor using other semiconductor materials in the channel formation region. Examples of such other semiconductor materials include semiconductors made of elemental elements or compound semiconductors.

[0374] Examples of semiconductors composed of single elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0375] Examples of compound semiconductors that can be used in semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in semiconductor layers preferably contains an amorphous structure. Boron arsenide that can be used in semiconductor layers preferably contains a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0376] The semiconductor layer can also utilize a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Layered materials have high electrical conductivity within a single layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0377] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable as channel formation regions in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0378] An indium oxide film that can be used in the semiconductor layer of a transistor in a display device according to one aspect of the present invention will be described.

[0379] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0380] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0381] This section describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. Figure 28(A) shows the carrier concentration dependence of silicon (Si) and indium oxide (InO X Figure 28(B) is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0382] First, as indicated by the arrows in Figure 28(B), IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 28(A), indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 28(A) are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 28(A).

[0383] In Figure 28(A), the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is such that the carrier concentration value is 1 × 10⁻⁶. 15 cm -3 This range includes, for example, 1 × 10 14 cm -3 The above is 1 x 10 18 cm -3 The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. 2 It can be expected to be raised to the level of (V·s).

[0384] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0385] On the other hand, the range R2, where the carrier concentration is high, has low electrical resistance and is suitable for applications such as the source and drain regions of a transistor, resistors, or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. 20 cm -3 This range includes, for example, 1 × 10 19 cm -3 The above is 1 x 10 22 cm -3 The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. -4 It is expected that the level can be reduced to below Ω·cm.

[0386] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0387] Thus, in indium oxide, the region with a low carrier concentration is used for the transistor's channel formation region, while the region with a high carrier concentration is used for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with the IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 28(A) within the indium oxide film, a so-called nin junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived.

[0388] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0389] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films (also called microcrystalline films) containing crystal grains. In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it offers excellent effects such as suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0390] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0391] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0392] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0393] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0394] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0395] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0396] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². 2 / (V·s) or more, preferably 100cm 2 / (V·s) or more, more preferably 150cm 2 / (V·s) or more, more preferably 200cm 2 / (V·s) or more, more preferably 250cm 2 It can be set to (V·s) or more.

[0397] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 28(C), indium oxide films (InO X Oxygen (O) diffusing into an oxygen vacancy (V) permeates the indium oxide membrane and is released as oxygen molecules (O2). It may also be released as water molecules (H2O) by reacting with hydrogen contained in the membrane. Furthermore, oxygen vacancies (V) in the membrane... O If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films can be said to be more efficient at filling oxygen deficiencies compared to IGZO films because oxygen diffuses easily.

[0398] Thus, because indium oxide films are more prone to reducing oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0399] Furthermore, as shown in Figure 28(C), the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules (H2). Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0400] A transistor using an indium oxide film is a storage-type transistor that uses electrons as the majority carrier. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0401] Table 1 shows the effective masses of single-crystal indium oxide (here, In2O3) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-response) can be realized. In addition, because of the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. -15 A) Less than or equal to, or 1aA(1 × 10 -18 A) is less than or equal to 1aA(1 × 10) under room temperature (25°C) conditions. -18 A) Less than or equal to 1zA(1×10) -21 A) The following is possible. Furthermore, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0402] [Table 1]

[0403] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0404] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] between the crystals of the seed layer and the crystals of the formed film (indium oxide film in this case) is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length of the unit cell vector or lattice constant of the crystals of the formed film, and L2 is the length of the unit cell vector or lattice constant of the crystals of the seed layer.

[0405] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably 0. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0406] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0407] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For instance, by setting the crystal orientation of the surface of the seed layer to

[0001] and the crystal orientation of the underside of the indium oxide film to

[0111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and modified forms thereof. An example of a crystal having a YbFe2O4-type or Yb2Fe3O7-type structure is IGZO.

[0408] This embodiment can be appropriately combined with other embodiments or examples.

[0409] (Embodiment 4) This embodiment describes a semiconductor device 8000 according to one aspect of the present invention. The semiconductor device 8000 can function as a memory device.

[0410] Figure 21 shows a block diagram illustrating an example configuration of the semiconductor device 8000. The semiconductor device 8000 shown in Figure 21 includes a drive circuit 8110 and a memory array 8120. The memory array 8120 has one or more memory cells 8130. Figure 21 shows an example in which the memory array 8120 has multiple memory cells 8130 arranged in a matrix.

[0411] The memory cell 8130 can be a memory device as described in Embodiment 2.

[0412] The drive circuit 8110 includes a PSW8001 (power switch), a PSW8002, and a peripheral circuit 8003. The peripheral circuit 8003 includes a peripheral circuit 8004, a control circuit 8005, and a voltage generation circuit 8006.

[0413] In semiconductor device 8000, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0414] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 8005.

[0415] The control circuit 8005 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 8000. For example, the control circuit 8005 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 8000 (e.g., write operation, read operation). Alternatively, the control circuit 8005 generates control signals for the peripheral circuit 8004 so that this operating mode is executed.

[0416] The voltage generation circuit 8006 has the function of generating a negative voltage. The WAKE signal has the function of controlling the input of the CLK signal to the voltage generation circuit 8006. For example, when a high-level signal is given as the WAKE signal, the CLK signal is input to the voltage generation circuit 8006, and the voltage generation circuit 8006 generates a negative voltage.

[0417] The peripheral circuit 8004 is a circuit for writing and reading data to and from the memory cell 8130. The peripheral circuit 8004 includes a row decoder 8007, a column decoder 8008, a row driver 8009, a column driver 8010, a sense amplifier 8011, an input circuit 8012, and an output circuit 8013.

[0418] The row decoder 8007 and column decoder 8008 have the function of decoding the signal ADDR. The row decoder 8007 is a circuit for specifying the row to access, and the column decoder 8008 is a circuit for specifying the column to access. The row driver 8009 has the function of selecting the row specified by the row decoder 8007. The column driver 8010 has the function of writing data to the memory cell 8130, reading data from the memory cell 8130, and holding the read data.

[0419] The input circuit 8012 has the function of holding the signal WDA. The data held by the input circuit 8012 is output to the column driver 8010. The output data of the input circuit 8012 is the data (Din) to be written to the memory cell 8130. The data (Dout) read by the column driver 8010 from the memory cell 8130 is output to the output circuit 8013. The output circuit 8013 has the function of holding Dout. In addition, the output circuit 8013 has the function of outputting Dout to the outside of the semiconductor device 8000. The data output from the output circuit 8013 is the signal RDA.

[0420] PSW8001 provides V to peripheral circuit 8003. DD It has a function to control the supply. PSW8002 is V to line driver 8009. HM It has a function to control the supply. Here, the high power supply potential of semiconductor device 8000 is V DD Therefore, the low power supply potential is GND (ground potential). Also, V HM This is a high power supply potential used to raise the word line to a high level, V DDIt is higher than. Signal PON1 controls the on / off state of PSW8001, and signal PON2 controls the on / off state of PSW8002. In Figure 21, in peripheral circuit 8003, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0421] Using Figures 22(A) through (H), other examples of memory cell configurations applicable to memory cell 8130 will be explained.

[0422] [DOSRAM] Figure 22(A) shows an example of the circuit configuration of a memory cell in a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 8131 has a transistor M1 and a capacitive element CA.

[0423] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0424] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0425] The BIL wiring functions as a bit line, and the WOL wiring functions as a word line. The CAL wiring functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL wiring.

[0426] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0427] Furthermore, the memory cell that can be used in memory cell 8130 is not limited to memory cell 8131, and the circuit configuration can be changed. For example, the memory cell 8132 can be configured as shown in Figure 22(B). Memory cell 8132 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0428] In memory cell 8132, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0429] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the memory cell refresh operation can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8131 and 8132.

[0430] [NOSRAM] Figure 22(C) shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 8133 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0431] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0432] Wiring WBL functions as the write bit line, wiring RBL functions as the read bit line, and wiring WOL functions as the word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0433] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the gate of transistor M3.

[0434] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0435] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 22(D). Memory cell 8134 is configured such that the wiring WBL and wiring RBL of memory cell 8133 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to this wiring BIL. In other words, memory cell 8134 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0436] The memory cell 8135 shown in Figure 22(E) is an example where the capacitive element CB and wiring CAL in memory cell 8133 are omitted. Similarly, the memory cell 8136 shown in Figure 22(F) is an example where the capacitive element CB and wiring CAL in memory cell 8134 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0437] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

[0438] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. Furthermore, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8133, 8134, 8135, and 8136.

[0439] Memory cells 8133, 8134, 8135, and 8136, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0440] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0441] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0442] Figure 22(G) also shows a gain cell type memory cell 8137 with three transistors and one capacitance element. The memory cell 8137 has transistors M4 to M6 and a capacitance element CC.

[0443] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0444] The BIL wire functions as a bit line, the WOL wire functions as a write word line, and the RWL wire functions as a read word line. The GNDL wire provides a low level potential.

[0445] Data writing is performed by applying a high-level potential to the WOL wiring, turning on transistor M4, and creating a conductive state between the BIL wiring and the first terminal of the CC capacitor. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the first terminal of the CC capacitor and the gate of transistor M5. Subsequently, a low-level potential is applied to the WOL wiring, turning off transistor M4, thereby maintaining the potential of the first terminal of the CC capacitor and the gate of transistor M5.

[0446] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0447] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0448] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0449] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0450] [OS-SRAM] Figure 22(H) shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification, SRAM using an OS transistor is referred to as OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 8138 shown in Figure 22(H) is a memory cell of a backup-capable SRAM.

[0451] The memory cell 8138 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0452] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0453] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0454] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0455] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0456] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the on and off states of transistors M9 and M10.

[0457] Wiring VDL is a wire that provides a high potential, and wiring GNDL is a wire that provides a low potential.

[0458] Data is written by applying a high-level potential to the WOL wiring and also to the BRL wiring. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in the BIL wiring is applied, and this potential is written to the second terminal side of transistor M10.

[0459] Incidentally, since the memory cell 8138 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is ON, the inverted signal of the potential applied to wiring BIL, i.e., the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are held.

[0460] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 8138 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 8138 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0461] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether.

[0462] Note that Si transistors may be used as transistors MS1 through MS4.

[0463] Figures 23(A) and 23(C) show perspective views of the semiconductor device 8200A. The semiconductor device 8200A has a layer 8220 on which memory arrays are provided on the arithmetic unit 8210. Memory arrays 8120L1, 8120L2, and 8120L3 are provided on layer 8220. The arithmetic unit 8210 and each memory array have overlapping regions. To make the configuration of the semiconductor device 8200A easier to understand, Figure 23(B) shows the arithmetic unit 8210 and layer 8220 separately. The arithmetic unit 8210 can be, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc.

[0464] By stacking the layer 8220 containing the memory array and the arithmetic unit 8210, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0465] As a method for stacking the layer 8220 having the memory array and the arithmetic unit 8210, one may use a method in which the layer 8220 having the memory array is directly stacked on the arithmetic unit 8210 (also called monolithic stacking), or one may use a method in which the arithmetic unit 8210 and the layer 8220 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0466] Here, the arithmetic unit 8210 does not have a cache, and the memory arrays 8120L1, 8120L2, and 8120L3 provided in layer 8220 can each be used as caches. In this case, for example, memory array 8120L1 can be used as an L1 cache (also called a level 1 cache), memory array 8120L2 can be used as an L2 cache (also called a level 2 cache), and memory array 8120L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 8120L3 has the largest capacity and the lowest access frequency. Also, memory array 8120L1 has the smallest capacity and the highest access frequency.

[0467] Furthermore, when the cache provided in the arithmetic unit 8210 is used as the L1 cache, each memory array provided in layer 8220 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0468] Furthermore, as shown in Figure 23(B), drive circuits 8110L1, 8110L2, and 8110L3 are provided. Drive circuit 8110L1 is connected to memory array 8120L1 via connection electrode 8230L1. Similarly, drive circuit 8110L2 is connected to memory array 8120L2 via connection electrode 8230L2, and drive circuit 8110L3 is connected to memory array 8120L3 via connection electrode 8230L3.

[0469] Note that while this example shows three memory arrays functioning as a cache, it can also use one, two, or four or more.

[0470] When the memory array 8120L1 is used as a cache, the drive circuit 8110L1 may function as part of the cache interface, or the drive circuit 8110L1 may be configured to be connected to the cache interface. Similarly, the drive circuits 8110L2 and 8110L3 may also function as part of the cache interface, or be configured to be connected to it.

[0471] In Figures 23(A) and 23(B), an example is shown in which one layer 8220 with a memory array is provided on the arithmetic unit 8210. However, as shown in Figure 23(C), multiple layers 8220 with memory arrays may be provided, such as two or more layers.

[0472] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0473] (Embodiment 5) A semiconductor device according to one aspect of the present invention will now be described. Figure 24(A) is a schematic perspective view of a semiconductor device 8310 according to one aspect of the present invention. Figure 24(B) is a schematic perspective view of a part of the semiconductor device 8310. Figure 25 is a schematic perspective view illustrating the configuration of the semiconductor device 8310.

[0474] In Figures 24(A), 24(B), and 25, the semiconductor device 8310 has an element layer 8370 below an element layer 8320 which includes a substrate 8322 that is a semiconductor substrate, and a support substrate 8340 above the element layer 8320 via an insulating layer 8341. The element layer 8320 has a plurality of transistors 8321 which constitute a functional circuit 8311. The element layer 8370 has a plurality of transistors 8371 which constitute a switch circuit 8315. The transistors 8371 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 8372 which functions as a power line.

[0475] The transistor exemplified in Embodiment 1 can be applied to transistor 8371.

[0476] The transistor 8321 in element layer 8320 is formed on the front side (also called the "first side") of the substrate 8322. The element layer 8370 is formed on the back side (the side opposite the front, also called the "second side") of the substrate 8322. Therefore, the transistor 8371 in element layer 8370 is formed on the second side of the substrate 8322.

[0477] Figure 25 illustrates the functional circuit 8311 as a CPU 8312, GPU 8313, and memory 8314.

[0478] Furthermore, the functional circuit 8311 is not limited to the CPU 8312, GPU 8313, and memory 8314; one or more of these can be used. It is also possible to include circuits with other functions.

[0479] To improve the operating speed, mounting density, and power consumption of the semiconductor device 8310, the functional circuit 8311 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 8315 can control the supply of externally supplied voltage to each circuit of the functional circuit 8311, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0480] Furthermore, the transistors constituting the switch circuit 8315 require high dielectric strength. One effective way to increase the dielectric strength of a transistor is to thicken the gate insulating film. Thus, transistors 8321 and 8371 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 8321 and 8371.

[0481] Furthermore, miniaturization and thinning are required for the functional circuit 8311. Therefore, if the switch circuit 8315 is constructed using the same process node as the functional circuit 8311, not only the routing but also the power supply wiring (power lines) will become thinner, making it impossible to supply sufficient power to the functional circuit 8311. Additionally, if the wiring resistance increases due to miniaturization, voltage drop is likely to cause uneven power potential within the functional circuit 8311. To ensure a stable power supply to the functional circuit 8311, it is preferable that the wiring constituting the switch circuit 8315 has lower wiring resistance than the wiring constituting the functional circuit 8311. In particular, it is preferable that the wiring functioning as power lines has lower wiring resistance than the wiring constituting the functional circuit 8311. One effective means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase either the width or height of the conductive layer, or both. Thus, it is preferable to use different process nodes for the functional circuit 8311 and the switch circuit 8315.

[0482] In a semiconductor device 8310 according to one aspect of the present invention, by providing the functional circuit 8311 and the switch circuit 8315 on different element layers, different improvement measures can be implemented in the functional circuit 8311 and the switch circuit 8315. Furthermore, the functional circuit 8311 and the switch circuit 8315 can be formed at different process nodes.

[0483] In one aspect of the present invention, a plurality of conductive layers 8372 that function as power lines and a switch circuit 8315 can be arranged below the functional circuit 8311, thereby reducing the occupied area of ​​the semiconductor device 8310. Furthermore, it is preferable that the element layer 8370, which is superimposed on the element layer 8320, be formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 8371 included in the element layer 8370 is preferably a thin-film transistor.

[0484] At least a portion of the multiple conductive layers 8372 of the element layer 8370 can function as power lines. Furthermore, if the element layer 8370 has a clock signal generation circuit, at least a portion of the multiple conductive layers 8372 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 8311 of the element layer 8320 via at least a portion of the multiple conductive layers 8372.

[0485] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 8311 and a die containing the switch circuit 8315 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving alignment accuracy is difficult because the two are bonded mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary locations of the functional circuit 8311.

[0486] According to one aspect of the present invention, an element layer 8370 including a switch circuit 8315 is formed on the back side of the substrate 8322 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 8310 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0487] By forming the element layer 8370 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 8311 over extremely short distances. Therefore, the necessary power can be supplied to the necessary locations of the functional circuit 8311. In addition, in the semiconductor device 8310 according to one aspect of the present invention, since the connection distance between the switch circuit 8315 and the functional circuit 8311 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0488] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0489] (Embodiment 6) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. Because a semiconductor device according to one aspect of the present invention can provide a transistor with high on-current and small footprint, it is suitable for applications such as electronic components, electronic equipment, large computers, space equipment, and data centers.

[0490] [Electronic components] Figure 26(A) shows a perspective view of a circuit board (mounted board 9109) on which the electronic component 9100 is mounted. The electronic component 9100 shown in Figure 26(A) has a semiconductor device 9101 within a mold 9104. Some details are omitted in Figure 26(A) to show the inside of the electronic component 9100. The electronic component 9100 has a land 9105 on the outside of the mold 9104. The land 9105 is electrically connected to an electrode pad 9106, and the electrode pad 9106 is electrically connected to the semiconductor device 9101 via a wire 9107. The electronic component 9100 is mounted, for example, on a printed circuit board 9108. Multiple such electronic components are combined and electrically connected on the printed circuit board 9108 to complete the mounted board 9109.

[0491] Furthermore, the semiconductor device 9101 has a drive circuit layer 9102 and a storage layer 9103. The storage layer 9103 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 9102 and the storage layer 9103 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 9102 and the storage layer 9103, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0492] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-electrodes such as TSV, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0493] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 9103 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 9103, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0494] The semiconductor device 9101 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0495] Next, a perspective view of the electronic component 9110 is shown in Figure 26(B). The electronic component 9110 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 9110 has an interposer 9111 on a package substrate 9112 (printed circuit board), and a semiconductor device 9114 and a plurality of semiconductor devices 9101 are provided on the interposer 9111.

[0496] Electronic component 9110 shows an example where semiconductor device 9101 is used as high-bandwidth memory (HBM). Furthermore, semiconductor device 9114 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0497] The package substrate 9112 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 9111 can be, for example, a silicon interposer or a resin interposer.

[0498] The interposer 9111 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 9111 also has the function of connecting integrated circuits provided on the interposer 9111 to electrodes provided on the package substrate 9112. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 9111, and these through electrodes may be used to connect the integrated circuits and the package substrate 9112. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0499] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0500] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0501] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 9110, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0502] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 9110. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 9111. For example, in the electronic component 9110 shown in this embodiment, it is preferable to align the heights of the semiconductor device 9101 and the semiconductor device 9114.

[0503] To mount the electronic component 9110 onto another substrate, electrodes 9113 may be provided at the bottom of the package substrate 9112. Figure 26(B) shows an example where the electrodes 9113 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 9112, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 9113 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 9112, PGA (Pin Grid Array) mounting can be achieved.

[0504] The electronic component 9110 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0505] [Large computer] Next, a perspective view of the large-scale computer 9200 is shown in Figure 27(A). The large-scale computer 9200 shown in Figure 27(A) has multiple rack-mount type computers 9220 housed in rack 9210. The large-scale computer 9200 may also be referred to as a supercomputer.

[0506] The computer 9220 can have the configuration shown in the perspective view in Figure 27(B), for example. In Figure 27(B), the computer 9220 has a motherboard 9230, which has multiple slots 9231 and multiple connection terminals. A PC card 9221 is inserted into slot 9231. In addition, the PC card 9221 has connection terminals 9223, 9224, and 9225, which are each connected to the motherboard 9230.

[0507] The PC card 9221 shown in Figure 27(C) is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 9221 has a board 9222. The board 9222 also has connection terminals 9223, 9224, 9225, semiconductor device 9226, semiconductor device 9227, semiconductor device 9228, and connection terminal 9229. Note that Figure 27(C) shows semiconductor devices other than semiconductor device 9226, semiconductor device 9227, and semiconductor device 9228, but for information on these semiconductor devices, please refer to the descriptions of semiconductor device 9226, semiconductor device 9227, and semiconductor device 9228 below.

[0508] The connector 9229 has a shape that allows it to be inserted into slot 9231 of the motherboard 9230, and the connector 9229 functions as an interface for connecting the PC card 9221 and the motherboard 9230.

[0509] The semiconductor device 9226 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 9226 and the board 9222 can be connected by inserting these terminals into sockets (not shown) provided on the board 9222.

[0510] Examples of semiconductor device 9227 include FPGAs, GPUs, and CPUs. For example, an electronic component 9110 can be used as the semiconductor device 9227.

[0511] Examples of semiconductor devices 9228 include memory devices. For example, an electronic component 9110 can be used as the semiconductor device 9228.

[0512] The 9200 mainframe computer can also function as a parallel computer. By using the 9200 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0513] [Space equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0514] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used as transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Outer space refers to, for example, an altitude of 100 km or higher, but the outer space described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0515] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0516] Figure 27(D) shows satellite 9300 as an example of space equipment. Satellite 9300 consists of a body 9301, solar panels 9302, an antenna 9303, a secondary battery 9305, and a control device 9306. In Figure 27(D), planet 9304 is shown as an example in outer space.

[0517] Furthermore, although not shown in Figure 27(D), a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 9305. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0518] Furthermore, the control device 9306 has the function of controlling the artificial satellite 9300. The control device 9306 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one aspect of the present invention, for the control device 9306.

[0519] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0520] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0521] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring data immutability. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, and securing cooling equipment necessary for data storage, which necessitates the construction of larger buildings.

[0522] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0523] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0524] Figure 27(E) shows a storage system applicable to a data center. The storage system 9400 shown in Figure 27(E) has multiple servers 9401sb as hosts 9401 (shown as Host Computer). It also has multiple storage devices 9403md as storage 9403 (shown as Storage). The host 9401 and storage 9403 are connected via a storage area network 9404 (shown as SAN: Storage Area Network) and a storage control circuit 9402 (shown as Storage Controller).

[0525] Host 9401 corresponds to a computer that accesses data stored in storage 9403. The hosts 9401 may be connected to each other via a network.

[0526] While the 9403 storage system uses flash memory to shorten data access speed, i.e., the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage system. To address the problem of the long access speed of the 9403 storage system, storage systems typically include cache memory within the storage system to shorten the time required for data storage and retrieval.

[0527] The aforementioned cache memory is used within the storage control circuit 9402 and storage 9403. Data exchanged between the host 9401 and storage 9403 is stored in the cache memory within the storage control circuit 9402 and storage 9403, and then output to the host 9401 or storage 9403.

[0528] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the refresh frequency can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0529] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0530] In this embodiment, a device according to one aspect of the present invention was fabricated, and its structure and other aspects were evaluated.

[0531] <Fabrication of semiconductor devices (S-1 and T-1)> The configuration shown in Figure 3(A) was fabricated using the method described below. However, the insulating layer 140 was omitted, and the conductive layer 110 and the insulating layer 180 were provided on the substrate 101. The samples formed here are referred to as Sample S-1 and Sample T-1.

[0532] First, a conductive layer 110 was formed on the substrate 101. A silicon wafer was used as the substrate 101. A tungsten layer was formed as the conductive layer 110 by sputtering to a thickness of 20 nm.

[0533] Next, a silicon nitride layer was formed on the substrate 101 and the conductive layer 110 as an insulating layer 180a using the ALD method to a thickness of 5 nm. Subsequently, a silicon oxide layer was formed as an insulating layer 180b using the sputtering method to a thickness of 80 nm. Subsequently, a silicon nitride layer was formed as an insulating layer 180c using the sputtering method to a thickness of 10 nm.

[0534] Next, openings were formed in insulating layers 180c, 180b, and 180a using a resist mask. The openings were primarily formed by dry etching using a mixed gas of CH2F2, O2, CHF3, CF4, and Ar. The resist mask can be removed during the dry etching process and the subsequent O2 ashing process.

[0535] Next, in sample S-1, the insulating layer 180b was etched using a buffered hydrofluoric acid solution. The buffered hydrofluoric acid solution used was an aqueous solution of 6.7 wt% ammonium hydrogen fluoride and 12.7 wt% ammonium fluoride. This etching process recedes the insulating layer 180b, forming an opening 190 with a narrowed top and bottom, as shown in Figure 3(A). This etching process was not performed on sample T-1.

[0536] Next, a conductive film, which will become the conductive layer 115, was formed inside the openings of the insulating layer 180 and on the insulating layer 180. A titanium nitride film with a thickness of 6 nm was formed as the conductive film using the metal CVD method. Subsequently, an aluminum oxide film was formed on the conductive film that will become the conductive layer 115. A hard mask can be formed by processing this aluminum oxide film.

[0537] Next, an aluminum oxide layer was formed by processing the aluminum oxide film using a resist mask. Subsequently, the aluminum oxide layer was used as a mask to process a conductive film that would become the conductive layer 115, thereby forming the conductive layer 115. The conductive film that would become the conductive layer 115 was processed using dry etching. Next, the aluminum oxide layer was removed. Here, the conductive layer 115 was configured to also cover a portion of the upper surface of the insulating layer 180, as shown in Figure 1(D).

[0538] Next, an insulating layer 130 was formed. The insulating layer 130 had a three-layer laminated structure consisting of an aluminum oxide layer formed to a thickness of 1 nm using the ALD method, a silicon oxide layer formed on the aluminum oxide layer to a thickness of 4 nm using the ALD method, and a hafnium oxide layer formed on the silicon oxide layer to a thickness of 2 nm using the ALD method.

[0539] Next, a titanium nitride film was formed using the metal CVD method to a thickness of 5 nm as the conductive film to become conductive layer 120a, and a tungsten film was formed using the metal CVD method to a thickness of 100 nm as the conductive film to become conductive layer 120b.

[0540] Next, a silicon oxide nitride layer was formed to a thickness of 100 nm. Subsequently, using this silicon oxide nitride layer as a sacrificial layer, the upper surface of the conductive film that would become conductive layer 120b was planarized by CMP. Then, conductive layer 120b and conductive layer 120a were formed using a resist mask. Samples S-1 and T-1 were formed through the above steps.

[0541] <Cross-sectional observation> The prepared samples were thinned using a focused ion beam (FIB), and the cross-sections were observed using a scanning transmission electron microscope (STEM). A Hitachi High-Tech HD-2300 scanning transmission electron microscope was used for STEM observation, with an acceleration voltage of 200 kV.

[0542] Figure 29(A) shows a STEM image of the cross-section of sample S-1, and Figure 30(A) shows a STEM image of the cross-section of sample T-1. Figures 29(A) and 30(A) are transmission electron images (TE images) at a magnification of 150,000x.

[0543] The observation was performed on a cross-section of an opening with a width of approximately 1 μm. Figures 29(B) and 30(B) show the low-magnification observation results for the locations shown in Figures 29(A) and 30(A), respectively.

[0544] In sample S-1, it was observed that narrowed areas were formed at the top and bottom of the opening in the insulating layer 180. Furthermore, it was observed that the conductive layer 115 and the insulating layer 130 provided good coverage to the protruding upper and lower portions of the insulating layer 180. [Examples]

[0545] In this embodiment, a semiconductor device according to one aspect of the present invention was fabricated, and its structure and other aspects were evaluated.

[0546] <Fabrication of semiconductor devices (S-2)> A portion of the structure shown in Figure 17 was fabricated using the method described below. However, the conductive layer 240a was not formed in this case. The sample formed here is referred to as Sample S-2.

[0547] First, a conductive layer 220 was formed on the substrate 101. A silicon wafer was used as the substrate 101. The conductive layer 220 had a laminated structure consisting of a titanium nitride layer (conductive layer 220a) formed to a thickness of 5 nm by sputtering, and a tungsten layer (conductive layer 220b) formed to a thickness of 20 nm on the titanium nitride layer by sputtering.

[0548] Next, a silicon nitride layer was formed on the substrate 101 and the conductive layer 220 as an insulating layer 280a using the ALD method to a thickness of 5 nm. Subsequently, a silicon oxide layer was formed as an insulating layer 280b using the sputtering method to a thickness of 80 nm. Subsequently, a silicon nitride layer was formed as an insulating layer 280c using the sputtering method to a thickness of 10 nm.

[0549] Next, openings were formed in insulating layers 280c, 280b, and 280a using a resist mask. The openings were primarily formed by dry etching using a mixed gas of CH2F2, O2, CHF3, CF4, and Ar. The resist mask can be removed during the dry etching process and the subsequent O2 ashing process.

[0550] Next, the insulating layer 280b was etched using a buffered hydrofluoric acid solution. This etching process allowed the insulating layer 280b to be recessed.

[0551] Next, a conductive film (referred to as conductive film 240bf in Figure 31(A) below) which will become the conductive layer 240b was formed inside the openings of the insulating layer 280 and on the insulating layer 280, and then an oxide semiconductor film 230f was formed. As the conductive film, an indium tin oxide layer containing silicon was formed to a thickness of 5 nm using the sputtering method. As the oxide semiconductor film 230f, a three-layer laminate was formed consisting of an In-Zn oxide layer with a thickness of 2 nm formed using the ALD method, an In-Sn-Zn oxide layer with a thickness of 5 nm formed on the In-Zn oxide layer using the sputtering method, and an In-Zn oxide layer with a thickness of 3 nm formed on the In-Sn-Zn oxide layer using the ALD method. The In-Zn oxide of the first and third layers was formed so that In:Zn = 2:1 [atomic ratio]. The second layer of In-Sn-Zn oxide was formed using a target with an atomic ratio of In:Sn:Zn = 4:0.1:1.

[0552] Here, the conductive layer 240b and the oxide semiconductor layer 230 can be formed by patterning the conductive film that will become the conductive layer 240b and the oxide semiconductor film 230f, respectively, but in this embodiment, this patterning is omitted.

[0553] Next, an insulating layer 250 was formed. The insulating layer 250 had a three-layer laminated structure consisting of an aluminum oxide layer formed to a thickness of 1 nm using the ALD method, a silicon oxide layer formed on the aluminum oxide layer to a thickness of 4 nm using the ALD method, and a hafnium oxide layer formed on the silicon oxide layer to a thickness of 2 nm using the ALD method.

[0554] Next, a titanium nitride film was formed using the metal CVD method to a thickness of 5 nm as the conductive film to become conductive layer 260a, and a tungsten film was formed using the metal CVD method to a thickness of 100 nm as the conductive film to become conductive layer 260b.

[0555] Next, a silicon oxynitride layer was formed to a thickness of 100 nm. Subsequently, using this silicon oxynitride layer as a sacrificial layer, the upper surface of the conductive film that would become conductive layer 260b was planarized by CMP. Then, conductive layer 260b and conductive layer 260a were formed using a resist mask. Sample S-2 was formed by the above steps.

[0556] <Cross-sectional observation> The prepared samples were thinned using a focused ion beam (FIB), and the cross-sections were observed using a scanning transmission electron microscope (STEM). For STEM observation, a Hitachi High-Tech HD-2300 scanning transmission electron microscope was used, with an acceleration voltage of 200kV.

[0557] Figure 31(A) shows a STEM image of the cross-section of sample S-2. Figure 31(A) is a transmission electron image (TE image) at a magnification of 150,000x.

[0558] The observation was performed on a cross-section of an opening with a width of approximately 1 μm. Figure 31(B) shows the low-magnification observation results of the area shown in Figure 31(A).

[0559] In sample S-2, it was observed that narrowed areas were formed at the top and bottom of the openings in the insulating layer 280. Furthermore, the oxide semiconductor film 230f was observed to provide good coverage to the protruding upper and lower portions of the insulating layer 280. This is thought to be due to the use of the highly covering ALD method for depositing the oxide semiconductor film 230f. On the other hand, the conductive film 240bf appeared to be extremely thin or absent at the openings in the insulating layer 280b. This is thought to be due to the use of the highly anisotropic sputtering method for depositing the conductive film 240bf. [Examples]

[0560] In this embodiment, a semiconductor device according to one aspect of the present invention was fabricated, and its structure and other aspects were evaluated.

[0561] <Fabrication of semiconductor devices (S-3)> A portion of the semiconductor device shown in Figure 17, etc., was fabricated using the method described below. The sample formed here is referred to as Sample S-3.

[0562] First, an insulating layer 210 was formed on a substrate 101, and a conductive layer 220 was formed on the insulating layer 210. A silicon wafer was used as the substrate 101. For the insulating layer 210, a silicon oxide layer with a thickness of 100 nm was formed by thermal oxidation of the silicon wafer. The conductive layer 220 had a laminated structure consisting of a titanium nitride layer (conductive layer 220a) formed with a thickness of 5 nm by sputtering, and a tungsten layer (conductive layer 220b) formed with a thickness of 20 nm by sputtering on the titanium nitride layer.

[0563] Next, a silicon nitride layer was formed as insulating layer 280a on the substrate 101, insulating layer 210, and conductive layer 220 using the ALD method to a thickness of 5 nm. Subsequently, a silicon oxide layer was formed as insulating layer 280b using the sputtering method to a thickness of 80 nm. Subsequently, a silicon nitride layer was formed as insulating layer 280c using the sputtering method to a thickness of 10 nm.

[0564] Next, a tungsten film with a thickness of 10 nm was formed using the sputtering method to become the conductive layer 240a (referred to as conductive film 240af in Figure 32(A) below).

[0565] Next, a three-layer structure consisting of a Spin On Carbon (SOC) layer, a Spin On Glass (SOG) layer on the SOC layer, and a resist layer on the SOG layer was used as a mask layer to form openings in the conductive film that would become the conductive layer 240a, the insulating layer 280c, the insulating layer 280b, and the insulating layer 280a. For the formation of openings in the conductive film that would become the conductive layer 240, dry etching was performed using a mixed gas of Cl2, O2, and CF4. For the formation of openings in the insulating layer 280, dry etching was mainly performed using a mixed gas of CH2F2, O2, CHF3, CF4, and Ar. The mask layer can be removed during the dry etching process.

[0566] Next, the insulating layer 280b was etched using a buffered hydrofluoric acid solution. This etching process allowed the insulating layer 280b to be recessed.

[0567] Next, a conductive film to become conductive layer 240b (referred to as conductive film 240bf in Figure 32(A) below) was formed in the openings of the insulating layer 280, in the openings of the conductive film to become conductive layer 240a, and on the conductive film to become conductive layer 240a, and then an oxide semiconductor film 230f was formed. As the conductive film to become conductive layer 240b, an indium tin oxide layer containing silicon was formed to a thickness of 15 nm using the sputtering method. As the oxide semiconductor film 230f, a two-layer laminated film was used, consisting of an In-Zn oxide layer formed to a thickness of 5 nm using the ALD method, and an In-Sn-Zn oxide layer formed to a thickness of 5 nm on the In-Zn oxide layer using the sputtering method. The first layer of In-Zn oxide was formed with an In:Zn = 4:1 [atomic ratio]. The second layer of In-Sn-Zn oxide was formed using a target with an In:Sn:Zn = 4:0.1:1 [atomic ratio].

[0568] Here, the conductive layer 240b, the conductive layer 240a, and the oxide semiconductor layer 230 can be formed by patterning each of the conductive films that will become the conductive layer 240b, the conductive film that will become the conductive layer 240a, and the conductive film that will become the oxide semiconductor film 230f, but in this embodiment, this patterning is omitted.

[0569] Sample S-3 was formed through the above process.

[0570] <Cross-sectional observation> The prepared samples were thinned using a focused ion beam (FIB), and the cross-sections were observed using a scanning transmission electron microscope (STEM). A Hitachi High-Tech HD-2700 scanning transmission electron microscope was used for STEM observation, with an acceleration voltage of 200kV.

[0571] Figure 32(A) shows a STEM image of the cross-section of sample S-3. Figure 32(A) is a transmission electron image (TE image) at a magnification of 500,000x.

[0572] The observed area was an opening with a narrowed upper section approximately 97 nm wide. Even with a fine opening, it was observed that narrowed sections were formed at the top and bottom of the opening in the insulating layer 280, and that the oxide semiconductor film 230f well covered the protruding upper and lower portions of the insulating layer 280. This is thought to be because the highly covering ALD method was used as the deposition method for the oxide semiconductor film 230f. On the other hand, it was suggested that the conductive film 240bf was extremely thin or not formed at the opening in the insulating layer 280b. This is thought to be because the highly anisotropic sputtering method was used as the deposition method for the conductive film 240bf. The amount of recession of the insulating layer 280b due to etching was also measured. Figure 32(B) shows the measurement results on the STEM image shown in Figure 32(A). The wavelengths were 53.2 nm (left side of the figure) and 50.6 nm (right side of the figure) at the top of insulating layer 280b, 55.0 nm (left side of the figure) and 55.4 nm (right side of the figure) near the middle of the height of insulating layer 280b, and 49.6 nm (left side of the figure) and 49.2 nm (right side of the figure) at the bottom of insulating layer 280b. As a result, the width of the opening in insulating layer 280b could be made approximately twice the width of the openings in insulating layers 280a and 280c. [Examples]

[0573] In this embodiment, a semiconductor device according to one aspect of the present invention was fabricated, and its structure and other aspects were evaluated.

[0574] <Fabrication of semiconductor devices (S-4)> A portion of the semiconductor device shown in Figures 9(A) and 9(B) was fabricated using the method described below. However, the oxide semiconductor layer 230, conductive layer 240a, and conductive layer 240b were not formed. The sample formed here is referred to as Sample S-4.

[0575] First, a conductive layer 220 was formed on the substrate 101. A silicon wafer was used as the substrate 101. The conductive layer 220 had a laminated structure consisting of a titanium nitride layer (conductive layer 220a) formed to a thickness of 5 nm by sputtering, a tungsten layer (conductive layer 220b) formed to a thickness of 50 nm on the titanium nitride layer by sputtering, and an indium tin oxide layer (conductive layer 220c) formed to a thickness of 20 nm on the tungsten layer by sputtering.

[0576] Next, an insulating layer 280a was formed on the substrate 101 and the conductive layer 220. The insulating layer 280a had a laminated structure consisting of a silicon nitride layer formed to a thickness of 5 nm using the ALD method and a silicon nitride layer formed on the silicon nitride layer to a thickness of 10 nm using the sputtering method. Subsequently, as the insulating layer 280b, a silicon oxide layer was formed to a thickness of 80 nm using the sputtering method.

[0577] Next, the material was heat-treated at 400°C for 1 hour in a nitrogen atmosphere.

[0578] Next, a silicon nitride layer was formed as the insulating layer 280c using the sputtering method to a thickness of 10 nm.

[0579] Next, openings were formed in insulating layers 280c, 280b, and 280a using a resist mask. For forming the openings in insulating layer 280, dry etching was primarily performed using a mixed gas of CH2F2, O2, CHF3, CF4, and Ar. The mask layer can be removed during the dry etching process.

[0580] Next, the insulating layer 280b was etched using a buffered hydrofluoric acid solution. This etching process allowed the insulating layer 280b to be recessed.

[0581] Next, an insulating layer 250 was formed inside the openings of the insulating layer 280 and on the insulating layer 280. The insulating layer 250 had a four-layer laminated structure consisting of an aluminum oxide layer formed to a thickness of 1 nm using the ALD method, a silicon oxide layer formed to a thickness of 2 nm on the aluminum oxide layer using the ALD method, a hafnium oxide layer formed to a thickness of 2 nm on the silicon oxide layer using the ALD method, and a silicon nitride layer formed to a thickness of 1 nm on the hafnium oxide layer using the ALD method.

[0582] Next, a titanium nitride film with a thickness of 5 nm was formed as the conductive film to become conductive layer 260a using the metal CVD method, and a tungsten film with a thickness of 100 nm was formed as the conductive film to become conductive layer 260b using the metal CVD method.

[0583] Next, a silicon oxide nitride layer was formed to a thickness of 100 nm. Subsequently, using this silicon oxide nitride layer as a sacrificial layer, the upper surface of the conductive film that would become conductive layer 260b was planarized by CMP. Then, conductive layer 260b and conductive layer 260a were formed using a resist mask. Sample S-4 was formed by the above steps.

[0584] <Cross-sectional observation> The prepared samples were thinned using a focused ion beam (FIB), and the cross-sections were observed using a scanning transmission electron microscope (STEM). A Hitachi High-Tech HD-2300 scanning transmission electron microscope was used for STEM observation, with an acceleration voltage of 200 kV.

[0585] Figure 33(A) shows a STEM image of the cross-section of sample S-4. Figure 33(A) is a transmission electron image (TE image) at a magnification of 250,000x.

[0586] The observation was performed on a cross-section of an opening with a width of approximately 1 μm. Figure 33(B) shows the low-magnification observation results of the area shown in Figure 33(A).

[0587] In sample S-4, it was observed that narrowed areas were formed at the top and bottom of the opening in the insulating layer 280. Furthermore, even after the formation of the opening in the insulating layer 280, the decrease in the thickness of the conductive layer 220c was suppressed, and the conductive layer 220c remained intact. [Explanation of Symbols]

[0588] ADDR: signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitive element, CAL: wiring, CB: capacitive element, CC: capacitive element, CE: signal, CLK: signal, GNDL: wiring, GW: signal, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 54a: conductive layer, 67: region, 68: region, 80A: memory cell, 100: capacitive element, 101: substrate, 110: conductive layer, 115: conductive layer, 120: conductive layer, 120a: conductive layer, 120b: conductive layer, 13 0: insulating layer, 140: insulating layer, 150: memory cell, 151: memory cell, 180: insulating layer, 180a: insulating layer, 180b: insulating layer, 180c: insulating layer, 190: opening, 190_a: opening, 190_b: opening, 190_c: opening, 190_d: opening, 190_m: opening, 190_u: opening, 200: transistor, 210: insulating layer, 220: conductive layer, 220a: conductive layer, 220b: conductive layer, 220c: conductive layer, 230: oxide semiconductor layer, 230f: oxide semiconductor film, 240: conductive layer, 240_3b: conductive layer, 240a: conductive layer, 240a f: conductive film, 240b: conductive layer, 240bf: conductive film, 250: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 277: insulating layer, 280: insulating layer, 280a: insulating layer, 280b: insulating layer, 280c: insulating layer, 290: opening, 290b: opening, 290d: opening, 290m: opening, 290ma: opening, 290u: opening, 812a: conductive layer, 812d: conductive layer, 813: insulating layer, 814: insulating layer, 815a: conductive layer, 815d: conductive layer, 900: Si transistor, 901: substrate, 902: element isolation layer, 903: semi Conductor region, 904: Low resistance region, 905: Insulating layer, 906: Insulating layer, 907: Insulating layer, 908a: Conductive layer, 908b: Dummy gate electrode, 908c: Dummy gate electrode, 909: Insulating layer, 910: Insulating layer, 911: Insulating layer, 912: Conductive layer, 913: Insulating layer, 914: Conductive layer, 915: Insulating layer, 916: Insulating layer, 8000: Semiconductor device, 8001: PSW, 8002: PSW, 8003: Peripheral circuit, 8004: Peripheral circuit, 8005: Control circuit, 8006: Voltage generation circuit, 8007: Row decoder, 8008: Column decoder, 8009: Row driver,8010: Column driver, 8011: Sense amplifier, 8012: Input circuit, 8013: Output circuit, 8110: Drive circuit, 8120: Memory array, 8130: Memory cell, 8131: Memory cell, 8132: Memory cell, 8133: Memory cell, 8134: Memory cell, 8135: Memory cell, 8136: Memory cell, 8137: Memory cell, 8138: Memory cell, 8200A: Semiconductor device, 8210: Arithmetic unit, 8220: Layer, 8310: Semiconductor device, 8311: Functional circuit, 8312: CPU, 8313: GPU, 8314: Memory, 8315: Switch circuit, 8320: Element layer, 8321: Transistor, 8322: Substrate, 8340: Support substrate, 8341: Insulating layer, 8370: Element layer, 8371: Transistor, 8372: Conductive layer, 9100: Electronic component, 9101: Semiconductor device, 9102: Driving circuit layer, 9103: Memory layer, 9104: Mold, 9105: Land, 9106: Electrode pad, 9107: Wire, 9108: Printed circuit board, 9109: Mounted circuit board, 9110: Electronic component, 9111: Interposer, 9112: Package circuit board, 9113: Electrode, 9114: Semiconductor equipment, 9200: Large computer, 9210: Rack, 9220: Computer, 9221: PC card, 9222: Board, 9223: Connector, 9224: Connector, 9225: Connector, 9226: Semiconductor equipment, 92 27: Semiconductor device, 9228: Semiconductor device, 9229: Connector, 9230: Motherboard, 9231: Slot, 9300: Artificial satellite, 9301: Aircraft body, 9302: Solar panel, 9303: Antenna, 9304: Planet, 9305: Rechargeable battery, 9306: Control device, 9400: Storage system, 9401: Host, 9401sb: Server, 9402: Storage control circuit, 9403: Storage, 9403md: Memory device,

Claims

1. It comprises a first insulating layer, a first conductive layer on the first insulating layer, a second insulating layer on the first insulating layer and the first conductive layer, and a capacitive element on the first conductive layer. The capacitive element comprises a second conductive layer, a third insulating layer, and a third conductive layer. The second insulating layer extends to the first conductive layer and has an opening that is narrowed at the top. The second insulating layer has a first portion that protrudes inward from the opening at the top of the opening, The second conductive layer has a second portion in contact with the upper surface of the first conductive layer, a third portion in contact with the side surface of the opening of the second insulating layer, and a fourth portion in contact with the lower surface of the first portion. The third insulating layer has, within the opening, a fifth portion in contact with the third portion of the second conductive layer and a sixth portion in contact with the fourth portion. The third conductive layer has a portion located within the opening, The fifth and sixth portions of the third insulating layer are sandwiched between the second conductive layer and the third conductive layer in the device.

2. In claim 1, The aforementioned second insulating layer has a laminated structure comprising a first layer and a second layer on the first layer. In the aforementioned opening, the width of the opening in the first layer is wider than the width of the opening in the second layer. The first portion of the second insulating layer is included in the second layer, a device.

3. In claim 2, The first layer has silicon oxide, The device has a second layer, which is silicon nitride.

4. In claim 1, The aforementioned opening is narrowed at the bottom, The second insulating layer has a seventh portion that protrudes inward from the opening at the lower part of the opening. The aforementioned second insulating layer has a laminated structure comprising a first layer, a second layer on the first layer, and a third layer on the second layer. In the aforementioned opening, the width of the opening in the second layer is wider than the width of the opening in the first layer and the width of the opening in the third layer, The first portion of the second insulating layer is included in the third layer, The seventh portion of the second insulating layer is included in the first layer, a device.

5. In claim 4, The second layer has silicon oxide, The first and third layers are silicon nitride in the device.

6. It comprises a first insulating layer, a transistor on the first insulating layer, and a second insulating layer on the first insulating layer. The transistor comprises a first conductive layer on the first insulating layer, a semiconductor layer, a second conductive layer on the second insulating layer, a third insulating layer, and a third conductive layer. The second insulating layer extends to the first conductive layer and has a first opening that is narrowed at the top and bottom. The second conductive layer has a second opening that overlaps with the first opening in a plan view. The second insulating layer has a first portion that protrudes inward from the first opening at the upper part of the first opening, and a second portion that protrudes inward from the first opening at the lower part of the first opening. The semiconductor layer has a third portion in contact with the upper surface of the first conductive layer, a fourth portion in contact with the side surface of the first opening of the second insulating layer, a fifth portion in contact with the lower surface of the protruding first portion of the second insulating layer, a sixth portion in contact with the upper surface of the protruding second portion of the second insulating layer, and a seventh portion in contact with the side surface of the second opening of the second conductive layer. The third insulating layer has a portion that contacts the semiconductor layer within the first opening. The third conductive layer has a portion within the first opening that faces the semiconductor layer with the third insulating layer in between. The second conductive layer has a laminated structure comprising a first layer and a second layer on the first layer. The first layer comprises one or more of a metal, a metal alloy, and a metal nitride. The second layer is a semiconductor device having an oxide.

7. In claim 6, The aforementioned second insulating layer has a laminated structure comprising a third layer, a fourth layer on the third layer, and a fifth layer on the fourth layer. In the first opening, the width of the opening of the fourth layer is wider than the width of the opening of the third layer and the width of the opening of the fifth layer. The first portion of the second insulating layer is included in the fifth layer, The second portion of the second insulating layer is included in the third layer, which is a semiconductor device.

8. In claim 7, The fourth layer has silicon oxide, The third and fifth layers are silicon nitride semiconductor device.

9. A first conductive layer is formed on the first insulating layer. A second insulating layer, a third insulating layer, and a fourth insulating layer are formed in order on the first insulating layer and the first conductive layer. A second conductive layer is formed on the fourth insulating layer. Openings reaching the first conductive layer are formed in the second conductive layer, the fourth insulating layer, the third insulating layer, and the second insulating layer using the first etching process. Using a second etching process, the third insulating layer is etched such that the width of the opening in the third insulating layer becomes wider than the width of the opening in the second insulating layer and the width of the opening in the fourth insulating layer. Form a semiconductor layer, A fifth insulating layer is formed on the semiconductor layer. A third conductive layer is formed on the fifth insulating layer. The first etching process described above is an anisotropic etching process, A method for manufacturing a semiconductor device, wherein the second etching process is an isotropic etching process.

10. In claim 9, The first etching process is a dry etching process. A method for manufacturing a semiconductor device, wherein the second etching process is a wet etching process.

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