Semiconductor equipment

Abstract

To provide a semiconductor device that can operate at high speed. [Solution] A first transistor to which a first signal is input, and A first potential is supplied to either the source or the drain, and a second signal is input to the gate. The second transistor and the first electrode are connected to the source and drain of the first transistor. Electrically connected, the second electrode is electrically connected to the source and drain of the second transistor. It has a capacitive element that is connected to it, and the first signal is at a low level, and the second A first period in which the signal is high level, and a second period in which the first signal is high level and the second signal is low It has a second period that is at the U level or high level.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and display devices, etc. [Background technology]

[0002] With the increasing size of display devices such as liquid crystal displays and EL displays, more value-added display devices are being developed. Development is underway. In particular, the driving circuit of the display device uses only single-conductivity transistors. Active technological development is underway to create such a system (see Patent Document 1).

[0003] Figure 16 shows the drive circuit disclosed in Patent Document 1. The drive circuit of Patent Document 1 is It has transistors M1 through M7. When the signal GOUT[N-1] is at a high level... When this happens, transistor M3 turns on. Then the voltage VON is the gateway of transistor M1. As it is supplied to the gate, the potential of transistor M1 begins to rise. As the gate potential of transistor 1 gradually increases, the voltage between the gate and source of transistor M3 The positional difference (hereinafter also called Vgs) gradually decreases. Eventually, the Vgs of transistor M3 This becomes the threshold voltage for transistor M3, and transistor M3 turns off. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2004-103226 [Overview of the project] [Problems that the invention aims to solve]

[0005] In the drive circuit of Patent Document 1, as the gate potential of transistor M1 increases, the transistor The Vgs of transistor M3 was gradually decreasing. In other words, the drain current of transistor M3 was decreasing. It was gradually getting smaller. Therefore, after the signal GOUT[N-1] became high level The time it took for transistor M3 to turn off had increased. On the other hand, the signal CKV was high. Before reaching a certain level, turn off transistor M3 and leave the gate of transistor M1 floating. It was necessary to do so. Therefore, in the drive circuit of Patent Document 1, the drive frequency is increased. That was difficult.

[0006] Furthermore, in the drive circuit of Patent Document 1, the potential of the gate of transistor M1 is raised quickly. Therefore, increase the W (W: channel width) / L (L: channel length) ratio of transistor M3. It was necessary. Therefore, the size of the M3 transistor increased, and the layout area increased. It had become like that.

[0007] Furthermore, in the drive circuit of Patent Document 1, it is necessary to put the gate of transistor M1 into a floating state. On the other hand, the source or drain of the transistor M1 is connected to the gate. Due to the off-current, charge was leaking from the gate of transistor M1. Therefore, It was difficult to extend the period during which the gate of the Grinder M1 remained in a floating state. It was difficult to lower the dynamic frequency.

[0008] Furthermore, as mentioned above, in the drive circuit of Patent Document 1, it is not possible to increase the drive frequency or decrease it. Because this was also difficult, the range of operating frequencies was narrowed.

[0009] In view of the above, one aspect of the present invention provides a drive circuit that can operate even at high drive frequencies. One of the problems is this. Also, to provide a drive circuit that can operate even at a low drive frequency is one of the problems. Also, to provide a drive circuit having a wide range of operable drive frequencies is one of the problems. Also, to reduce the W / L ratio of the transistor is one of the problems. Also to provide a circuit with a novel configuration is one of the problems. Note that the problems and effects are two sides of the same coin and when the effects are described in this specification etc., it is obvious that there are problems corresponding to those effects On the other hand, when the problems are described in this specification etc., it is obvious that the effects corresponding to those problems are achieved

Means for Solving the Problems

[0010] One aspect of the present invention is a semiconductor device having a first transistor to which a first signal is input to one of a source and a drain a second transistor to which a first potential is supplied to one of a source and a drain and a second signal is input to a gate and a capacitor element in which a first electrode is electrically connected to the other of the source and the drain of the first transistor and a second electrode is electrically connected to the other of the source and the drain of the second transistor And the semiconductor device has a first period in which the first signal is at a low level and the second signal is at a high level, and a second period in which the first signal is at a high level and the second signal is at a low level or a high level

[0011] One aspect of the present invention is a first transistor to which a first signal is input to one of a source and a drain a second transistor to which a first potential is supplied to one of a source and a drain and a second signal is input to a gate a first signal is input to one of a source and a drain and a gate ​​A third transistor is electrically connected to the gate of the first transistor, and the first transistor The poles are electrically connected to the source and drain of the first transistor, and the second electrode is A capacitive element electrically connected to the other side of the source and drain of the second transistor, This is a semiconductor device. And, in this semiconductor device, when the first signal is at a low level, the second A first period in which signal 2 is high level, and a second period in which signal 1 is high level and signal 2 is It has a second period in which it is at a low level or a high level.

[0012] In one embodiment of the present invention described above, the semiconductor device has a first source and drain. A potential is supplied, and the source and drain of the first transistor are connected to each other. It is electrically connected to the other side, and the gate is connected to the other side of the source and drain of the second transistor. A fourth transistor is electrically connected, and a first potential is supplied to either the source or the drain. The source and the other drain are electrically connected to the gate of the first transistor. The gate of the fifth transistor is electrically connected to the other side of the source and drain of the second transistor. A second potential is supplied to the source and drain of the lampistor, and the source and drain The other end is electrically connected to the other end of the source and drain of the second transistor, and the gate is It may also have a sixth transistor to which a third signal is input.

[0013] In one embodiment of the present invention described above, the W (W is the channel width) / L ( of the first transistor) The ratio (where L is the channel length) may be greater than the W / L ratio of the second transistor. [Effects of the Invention]

[0014] One aspect of the present invention provides a drive circuit that can operate even at high drive frequencies. Furthermore, it is possible to provide a drive circuit that can operate even at low drive frequencies. It is possible to provide a drive circuit with a wide range of capable drive frequencies. Also, the W of the transistor The / L ratio can be reduced. [Brief explanation of the drawing]

[0015] [Figure 1] A diagram illustrating a basic circuit according to one aspect of the present invention. [Figure 2] A diagram illustrating a basic circuit according to one aspect of the present invention. [Figure 3] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 4] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 5] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 6] A diagram illustrating a basic circuit and a sequential circuit according to one aspect of the present invention. [Figure 7] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 8] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 9] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 10] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 11] A diagram illustrating a sequential circuit according to one aspect of the present invention. [Figure 12] A diagram illustrating a display device according to one aspect of the present invention. [Figure 13] A diagram illustrating a transistor according to one aspect of the present invention. [Figure 14] A diagram illustrating a display device according to one aspect of the present invention. [Figure 15] A diagram illustrating an electronic device according to one aspect of the present invention. [Figure 16] A diagram illustrating a conventional drive circuit. [Modes for carrying out the invention]

[0016] An example of an embodiment illustrating the present invention will be described below with reference to the drawings. The contents of the embodiments may be modified without departing from the spirit and scope of the present invention. This will be easy for those skilled in the art. Therefore, the present invention is not limited to the embodiments described below. It will not be done.

[0017] Furthermore, this invention relates to all semiconductors using transistors, such as integrated circuits, RF tags, and display devices. Conducting devices are included in this category. Integrated circuits include microprocessors and image processing circuits. , DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit) including R, FPGA (Field Programmable Gate Array) and CPLD Programmable logic circuits (PLDs) such as Complex PLDs This category includes (a Logic Device). Furthermore, the display device includes, A light-emitting device that has light-emitting elements in each pixel, such as liquid crystal displays and organic light-emitting elements (OLEDs). Electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi This category includes things like computer displays.

[0018] In this specification, a display device refers to a display element such as a liquid crystal element or a light-emitting element that has a shape in each pixel. A completed panel and a module with an IC including a controller mounted on the panel. This includes "ru" and "to" within that category.

[0019] In this specification, "connection" means an electrical connection, and current, voltage, or potential is... This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes situations where components are indirectly connected. Furthermore, components that appear independent on the circuit diagram are also included. Even when elements are connected to each other, in reality, for example, a part of the wiring acts as an electrode. In some cases, such as when it is possible, a single conductive film may possess the functions of multiple components. In the specification, connection means that one conductive film combines the functions of multiple components. Cases where this is the case are also included in that category.

[0020] The source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to the region, or the source electrode connected to the semiconductor film mentioned above. Similarly, the transistor's Rain refers to a drain region which is part of the semiconductor film, or a region connected to the semiconductor film. It refers to the drain electrode. Similarly, "gate" refers to the gate electrode.

[0021] Furthermore, the source and drain of a transistor are determined by the polarity of the transistor and the input to each terminal. The name changes depending on the level of the potential being generated. Generally, n-channel type transients In a stator, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the dot. It is called rain. Also, in p-channel transistors, the terminal to which a low potential is applied is The terminal to which a high potential is applied is called the source, and is called the drain. Above, assuming the source and drain are fixed, we will explain the connection relationship of the transistor. Although it may be clarified in some cases, in practice the names of source and drain are assigned according to the potential relationship described above. It will change.

[0022] (Embodiment 1) In this embodiment, a basic circuit, a sequential circuit using the basic circuit, and a basic circuit according to one aspect of the present invention are provided. Next, we will describe a shift register circuit using the said sequential circuit.

[0023] First, the configuration of the basic circuit of this embodiment will be explained with reference to Figure 1(A).

[0024] The basic circuit in Figure 1(A) consists of transistor 101, transistor 102, and capacitive element 11 It contains 0.

[0025] The first terminal of transistor 101 is connected to the wiring 11, and the second terminal of transistor 101 The child is connected to wiring 12.

[0026] The first terminal of transistor 102 is connected to wire 13, and the gate of transistor 102 is It is connected to wiring 14.

[0027] The first electrode (also called one electrode) of the capacitive element 110 is connected to the wiring 12, and the capacitive element 1 The second electrode of 10 (also called the other electrode) is connected to the second terminal of transistor 102. ru.

[0028] Furthermore, the second terminal of transistor 102 or the second electrode of capacitive element 110 is considered to be node N1. This is shown. Also, the gate of transistor 101 is shown as node N2.

[0029] It is preferable that transistors 101 and 102 have the same conductivity type. This embodiment describes the case where these transistors are of the N-channel type. .

[0030] In this specification, "connection" refers to an electrical connection, including current, voltage, potential, and signal. This corresponds to a state in which a signal or electric charge can be supplied or transmitted. Therefore, "connected" means In addition to being directly connected, for example, wiring, conductive films, resistors, diodes, and transistors This category also includes situations where connections are made indirectly through elements such as switching elements. .

[0031] Furthermore, the first terminal of the transistor is connected to either the source or drain of the transistor, or the transistor It is also called the first electrode of a transistor. Furthermore, the second terminal of a transistor is called the transistor's saw. It is also called the other side of the drain or the second electrode of the transistor.

[0032] The signal CK is input to wiring 11 (also called the signal line), and wiring 11 transmits the signal CK. Alternatively, it has the function of supplying. The signal CK is a signal that has a high level and a low level. Furthermore, the signal CK corresponds to one of several clock signals input to the shift register circuit. It is a corresponding signal.

[0033] A signal OUT is output from wiring 12 (also called the signal line), and wiring 12 transmits the signal OUT. Alternatively, it has the function of supplying signals. Signal OUT is a signal that has both high and low levels. Furthermore, signal OUT is the output signal of the basic circuit in Figure 1(A). Also, signal OUT is One of the multiple output signals from the autoresistor circuit, or the output signal of the sequential circuit. This is the corresponding signal.

[0034] Wiring 13 (also called the power line) is supplied with a potential VSS (also called the first potential), and wiring 1 Element 3 has the function of transmitting or supplying the potential VSS. The potential VSS is a constant potential.

[0035] A signal SP is input to wiring 14 (also called a signal line), and wiring 14 transmits or supplies the signal SP. It has the function of supplying power. Signal SP is a signal that has high and low levels. Also, Signal SP is a signal that controls the on or off state of transistor 102. Also, signal SP is The start pulse or the sequential pulse one or more steps prior is input to the shift register circuit. This is a signal corresponding to the output signal of the road, etc.

[0036] Transistor 101 has the function of controlling the conduction or non-conductivity between wiring 11 and wiring 12. Furthermore, transistor 101 has the function of supplying the signal CK from wiring 11 to wiring 12. Furthermore, transistor 101 has the function of maintaining the potential difference between wiring 12 and node N2.

[0037] Transistor 102 has the function of controlling the conduction or non-conductivity between wiring 13 and node N1. Furthermore, transistor 102 has the function of supplying the potential VSS of wiring 13 to node N1. ru.

[0038] The capacitive element 110 has the function of maintaining the potential difference between the wiring 12 and node N1.

[0039] Next, regarding the driving method of the basic circuit in Figure 1(A), see the timing chart shown in Figure 1(B). This will be explained with reference to Figure 2.

[0040] Furthermore, the high-level potential of signals CK and SP is the potential VDD (also called the second potential). Yes, and we will explain by assuming that the low-level potential is potential VSS. Note that potential VDD is potential V It has a higher potential than SS.

[0041] Furthermore, the initial potential of node N1 is potential VDD, and the initial potential of node N2 is potential VS The explanation assumes that S is the initial potential of wiring 12 is potential VSS. If the initial potential of N2 is potential VSS, then in the initial state, transistor 101 is off. It is.

[0042] For convenience, the time required for the operation will be explained by dividing it into period Ta and period Tb.

[0043] First, during period Ta, signal SP becomes high level and signal CK becomes low level. When the signal SP becomes high level, transistor 102 turns on. Transistor 102 When it is turned on, the potential VSS of wiring 13 is supplied to node N1. Therefore, node N1 The potential drops to potential VSS. At this time, the capacitive element 110 is connected to node N1 and wiring 12. The potential difference is maintained, and since transistor 101 is off, wiring 12 It is in a floating state. Therefore, as the potential of node N1 decreases, the potential of wiring 12 also decreases. It descends from position VSS. Then, the potential of wiring 12 becomes the potential of node N2 (for example, potential VSS). If the potential falls below the threshold voltage of transistor 101 minus the voltage of transistor 101, then transistor 101 will It turns on (see Figure 2(A)).

[0044] When transistor 101 is turned on, the signal CK from wiring 11 is supplied to wiring 12. Since CK is at a low level, the potential of wiring 12 rises to potential VSS. At this time, The transistor 101 maintains the potential difference between node N2 and wiring 12, and node N2 It is in a floating state. Therefore, as the potential of wiring 12 rises, the potential of node N2 rises. The potential of node N2 is equal to the potential of wiring 11 (e.g., potential VSS) and transistor 101. If the potential exceeds the sum of the threshold voltage and the current potential, transistor 101 will remain on. Therefore, the potential of wiring 12 rises to potential VSS. In other words, signal OUT is low It becomes a bell (see Figure 2(B)).

[0045] Next, during period Tb, signal SP becomes low level and signal CK becomes high level. When signal SP becomes low level, transistor 102 turns off. Also, as described above... Transistor 101 remains ON. Therefore, the signal CK on wiring 11 is on wiring 1 It remains supplied to 2. Since the signal CK is at a high level, the potential of wiring 12 is potential V. It rises from SS. At this time, transistor 101 adjusts the potential difference between node N2 and wiring 12. The current is maintained, and node N2 remains in a floating state. Therefore, the potential of wiring 12 As the potential increases, the potential of node N2 also increases. The potential of node N2 is the potential of wiring 11 (e.g. For example, if the potential exceeds the sum of the potential VDD and the threshold voltage of transistor 101, Therefore, transistor 101 remains on. Consequently, the potential of wiring 12 rises to potential VDD. The signal level rises. In other words, the signal OUT becomes high level (see Figure 2(C)).

[0046] In the basic circuit shown in Figure 1(A), during period Ta, the Vgs of transistor 102 is set to a large value. Because the pressure can be maintained, the drain current of transistor 102 can be kept at a large value. Therefore, the potential of node N1 can be rapidly lowered, Ta can be shortened. In other words, the drive frequency can be increased.

[0047] Furthermore, if the Vgs of transistor 102 can be maintained at a large voltage, the transistor The W / L ratio of the Ta102 can be reduced. Therefore, the layout area can be reduced, and the input capacity can be reduced. This allows for a reduction in quantity, etc.

[0048] Furthermore, a capacitive element may be connected between the gate of transistor 101 and the second terminal. This allows the capacitance value between node N2 and wiring 12 to be increased, so node The potential of N2 can be increased.

[0049] Furthermore, the signal SP may remain at a high level even during period Tb. This way, During period Tb, transistor 102 remains ON, and therefore the potential VSS of wiring 13... This is continuously supplied to node N1. Therefore, the potential of node N1 changes with the potential fluctuation of wiring 12. This can prevent fluctuations.

[0050] Furthermore, during period Tb, signal SP maintained a high level from period Ta, and then a low level This is also acceptable. In this way, transistor 102 remains ON during period Tb. Since it turns off after that, during the period Tb in which the potential of wiring 12 is fluctuating, The potential VSS of wiring 13 continues to be supplied to node N1. Therefore, the potential fluctuation of wiring 12 This prevents the associated potential fluctuations at node N1.

[0051] Furthermore, when a load is connected to wiring 12, the load is driven by transistor 101. Therefore, the W / L ratio of transistor 101 is greater than the W / L ratio of transistor 102. It is preferable.

[0052] Furthermore, a transistor may be used as the capacitive element 110. In this case, the transistor Connect the gate to node N1, and wire the first terminal and / or second terminal of the transistor to node N1. It is preferable to connect to 2. That is, the capacitive element 110 is connected to the wiring 12. The body layer, the gate electrode connected to node N1, and the gate isolation between the semiconductor layer and the gate electrode. It may have a marginal layer. In this case, the potential of node N1 decreases during period Ta. When doing so, the capacitance value between node N1 and wiring 12 can be increased.

[0053] The transistor 102 has its first terminal connected to wiring 13 and its second terminal connected to node N. It may be replaced with a switching element connected to 1.

[0054] Note that the high-level potential of signal SP may be lower than the potential VDD. In this case, the signal Since the amplitude voltage of the SP can be reduced, power consumption can be reduced.

[0055] Furthermore, the low-level potential of signal SP may be lower than the potential VSS. This way, Ensure that transistor 102 is turned off even if it is normally on. It is possible.

[0056] Next, we will explain sequential circuits using the basic circuit shown in Figure 1(A).

[0057] First, the configuration of the sequential circuit in this embodiment will be described with reference to Figure 3. The circuit is configured by adding transistors 103 to 105 to the basic circuit shown in Figure 1(A). That is the case.

[0058] It is preferable that transistors 101 to 105 have the same conductivity type. This embodiment describes the case where these transistors are of the N-channel type. .

[0059] The first terminal of transistor 103 is connected to wire 13, and the second terminal of transistor 103 is connected to wire 13. The child is connected to wiring 12, and the gate of transistor 103 is connected to node N1.

[0060] The first terminal of transistor 104 is connected to the wiring 13, and the second terminal of transistor 104 The child is connected to node N2, and the gate of transistor 104 is connected to node N1.

[0061] The first terminal of transistor 105 is connected to the wire 15, and the second terminal of transistor 105 The child is connected to node N1, and the gate of transistor 105 is connected to wire 16.

[0062] The wire 15 (also called the power line) is supplied with a potential VDD, and the wire 15 transmits the potential VDD. It has the function of supplying.

[0063] The signal RE is input to wiring 16 (also called the signal line), and wiring 16 transmits the signal RE. Alternatively, it has the function of supplying. Signal RE is a signal that has a high level and a low level. Furthermore, signal RE is a signal that controls whether transistor 105 is on or off. RE is the reset pulse input to the shift register circuit, or the one or more stages after the shift register circuit. This signal corresponds to the output signal of a sequential circuit, etc.

[0064] Transistor 103 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 12. Furthermore, transistor 103 has the function of supplying the potential VSS of wiring 13 to wiring 12.

[0065] Transistor 104 has the function of controlling the conduction or non-conductivity between wiring 13 and node N2. Furthermore, transistor 104 has the function of supplying the potential VSS of wiring 13 to node N2. ru.

[0066] Transistor 105 has the function of controlling the conduction or non-conductivity between wiring 15 and node N1. Furthermore, transistor 105 has the function of supplying the potential VDD of wiring 15 to node N1. ru.

[0067] Next, the operation of the sequential circuit in Figure 3 will be explained with reference to the timing chart in Figure 4.

[0068] Furthermore, the high-level potential of signals CK, SP, and RE is potential VDD, and the low-level potential is... Let's explain this assuming that Bell's potential is the potential VSS.

[0069] Furthermore, the initial potential of node N1 is potential VDD, and the initial potential of node N2 is potential VS S is assumed to be the initial potential of wiring 12, and this will be explained assuming that the potential is VSS. Note that node N2 Since the initial potential is potential VSS, transistor 101 is turned off in the initial state. Yes, they are.

[0070] Also, for convenience, the period required for the operation is divided into period Ta, period Tb, period Tc, and period Td. explain.

[0071] First, during period Ta, signal SP becomes high level and signal RE becomes low level. Signal CK becomes low level. When signal RE becomes low level, transistor 105 is It becomes [unclear]. Also, when the signal SP becomes high level, transistor 102 turns on. When the transistor 102 is turned on, the potential VSS of the wiring 13 is supplied to node N1. Then, the potential of node N1 drops to potential VSS. When the potential of node N1 drops, Transistor 103 and transistor 104 turn off. Transistor 104 turns off. Then, node N2 becomes floating. Therefore, the potential of node N2 is maintained at potential VSS. Therefore, transistor 101 remains off.

[0072] Here, when the potential of node N1 is decreasing, the capacitive element 110 is connected to node N1 and wiring 12 The potential difference is maintained, and transistors 101 and 103 are turned off. Therefore, wiring 12 is in a floating state. Consequently, as the potential of node N1 decreases... Then, the potential of wiring 12 decreases from the potential VSS. The potential of wiring 12 is the potential of node N2 ( For example, if the potential falls below the potential obtained by subtracting the threshold voltage of transistor 101 from the potential (VSS), then the transistor... Transistor 101 turns on. When transistor 101 turns on, the signal CK of wiring 11 is activated. This is supplied to wiring 12. Since the signal CK is at a low level, the potential of wiring 12 rises. At this time, transistor 101 maintains the potential difference between node N2 and wiring 12, Because transistor 104 is turned off, node N2 is in a floating state. As the potential of wiring 12 increases, the potential of node N2 also increases. Potential of node N2 This is the sum of the potential of wiring 11 (e.g., potential VSS) and the threshold voltage of transistor 101. If the potential exceeds this, transistor 101 will remain on. Therefore, the voltage of wiring 12 The voltage level rises to the VSS level. In other words, the signal OUT becomes low level.

[0073] Next, during period Tb, signal SP becomes low level, and signal RE remains low level. As a result, the signal CK becomes high level. Since the signal RE remains low level, the transistor 105 remains off. Also, because the signal SP becomes low level, transistor 10 Node 2 turns off. Therefore, node N1 becomes floating, and the potential of node N1 becomes equal to the potential of period Ta. Because the potential is maintained at a certain level, transistors 103 and 104 remain off. It will become.

[0074] Here, because transistor 101 remains ON, the signal CK of wiring 11 is wired It remains supplied to 12. Since the signal CK is at a high level, the potential of wiring 11 The voltage rises. At this time, transistor 101 maintains the potential difference between node N2 and wiring 12. It is held, and since transistor 104 is off, node N2 is in a floating state. Therefore, as the potential of wiring 12 increases, the potential of node N2 also increases. The potential of point 2 is the sum of the potential of wiring 11 (e.g., potential VDD) and the threshold voltage of transistor 101. If the potential exceeds the specified potential, transistor 101 will remain on. Therefore, the wiring... The potential at 12 rises to the potential VDD. In other words, the signal OUT becomes high level.

[0075] Next, during period Tc, signal SP remains at a low level, and signal RE becomes high level. As a result, signal CK becomes low level. Since signal SP remains low level, the transient The st102 remains off. Also, because the signal RE becomes high level, the transistor 105 turns on. When transistor 105 turns on, the potential VDD of wiring 15 becomes neutral. As it is supplied to node N1, the potential of node N1 rises. Eventually, the potential of node N1 reaches The threshold voltage of transistor 105 is obtained from the gate potential of transistor 105 (e.g., potential VDD). When the voltage rises to the potential obtained by subtracting the voltage, transistor 105 turns off. Therefore, node N1 The potential of node N1 is maintained at a high potential as it becomes suspended. When the voltage increases, transistors 103 and 104 turn on. When 104 is turned on, the potential VSS of wiring 13 is supplied to node N2. Therefore, no The potential of node N2 drops to potential VSS. When transistor 103 is turned on, wiring 1 Potential VSS of 3 is supplied to wiring 12. Therefore, the potential of wiring 12 drops to potential VSS. Yes. In other words, the signal OUT becomes low level.

[0076] Next, during period Td, signal SP remains at a low level, and signal RE becomes low. As a result, the signal CK repeatedly switches between high and low levels. The signal SP remains at a low level. Therefore, transistor 102 remains off. Also, signal RE becomes low level. Therefore, transistor 105 remains off. Transistors 102 and 1 Since 05 remains off, node N1 remains in a floating state. Therefore, the power of node N1 Because the position is maintained at the potential during period Tc, transistors 103 and 10 4 remains ON. When transistor 104 remains ON, the potential VS of wiring 13 S remains supplied to node N2. Therefore, the potential of node N2 remains at potential VSS. As a result, transistor 101 remains off. Also, transistor 103 remains on. As a result, the potential VSS of wiring 13 remains supplied to wiring 12. Therefore, wiring 1 The potential at point 2 remains at the VSS potential. In other words, the signal OUT remains at a low level.

[0077] In the sequential circuit of Figure 3, during period Ta, the potential of wiring 12 becomes less than the potential VSS, The source and drain of transistor 103 can be reversed. Therefore, the transistor This can suppress the deterioration of Ta103.

[0078] Furthermore, the sequential circuit in Figure 3 can achieve the same effects as the basic circuit described above.

[0079] Furthermore, when a load is connected to wiring 12, the load is transistor 101 and transistor 12. It is driven by 103. Therefore, the W / L ratio of transistor 101 is transistor 10 2. Preferably, the W / L ratio is greater than that of transistors 104 and 105. Furthermore, the W / L ratio of transistor 103 is the same as that of transistors 102 and 104. It is preferable that the W / L ratio is greater than that of transistor 105.

[0080] Furthermore, both transistor 101 and transistor 103 supply charge to wiring 12. Furthermore, the Vgs of transistor 101 during period Tb is equal to that of transistor 1 during period Tc. It is often smaller than the Vgs of 03. Therefore, the W / L ratio of transistor 101 is It is preferable that the W / L ratio is greater than that of ZISTA 103.

[0081] Furthermore, both transistor 102 and transistor 105 supply charge to node N1. However, while the Vgs of transistor 102 is maintained at a large value during period Ta, Therefore, the Vgs of transistor 105 during period Tc gradually decreases. It is preferable that the W / L ratio of transistor 105 is greater than the W / L ratio of transistor 102.

[0082] Furthermore, the W / L ratio of transistor 102 is greater than that of transistor 104. It is preferable.

[0083] Furthermore, the high-level potential of signal RE may be higher than the potential VDD. This allows for a longer period. In Tc, it is possible to prevent transistor 105 from turning off, so The potential of N1 can be raised to the potential VDD.

[0084] Furthermore, the low-level potential of signal RE may be lower than the potential VSS. This way, Ensure that transistor 105 is turned off even if it is normally on. It is possible.

[0085] Note that a potential lower than VDD may be supplied to wiring 15.

[0086] The transistor 103 has its first terminal connected to wire 13 and its second terminal connected to wire 12 It may also be replaced with a switching element connected to it.

[0087] The transistor 104 has its first terminal connected to wiring 13 and its second terminal connected to node N. It may be replaced with a switching element connected to 2.

[0088] The transistor 105 has its first terminal connected to wiring 15 and its second terminal connected to node N. It may be replaced with a switching element connected to 1.

[0089] Next, we will describe a shift register circuit using the sequential circuit shown in Figure 3.

[0090] First, the configuration of the shift register circuit in this embodiment will be described with reference to Figure 5. The shift register circuit 5 has an N (where N is a natural number) stage sequential circuit 100. However, the figure In step 5, for convenience, the sequential circuits 100 of the N-stage sequential circuit 100 are the first to third stages (sequential Only circuits 100[1] through sequential circuits 100[3] are shown.

[0091] The shift register circuit consists of N wires 21 (indicated as wires 21[1] through 21[N]), It is connected to wiring 22, wiring 23 and wiring 24. Specifically, i (where i is 2 to N-1) In the first stage sequential circuit 100, the first terminal of transistor 101 is connected to wiring 22 It is connected to wiring 23, and the second terminal of transistor 101 is connected to wiring 21[i], The gate of transistor 102 is connected to wiring 21[i-1], and the gate of transistor 105 The wire is connected to wiring 21[i+1].

[0092] Furthermore, the connection relationship of the first stage sequential circuit 100 is the same as the connection relationship of the i-th stage sequential circuit 100. However, since the preceding sequential circuit 100 is not provided, the gate of transistor 102 There is no connection destination. Therefore, in the first stage sequential circuit 100, the gate of transistor 102 is It is connected to line 24.

[0093] Furthermore, the connection relationship of the Nth-stage sequential circuit 100 is the same as the connection relationship of the i-stage sequential circuit 100. However, since a sequential circuit 100 is not provided in the subsequent stage, the gate of transistor 105 There is no connection destination. Therefore, in the Nth stage sequential circuit 100, the gate of transistor 105 is It is connected to line 24. However, in the Nth stage sequential circuit 100, transistor 105 The gate is located in the wiring to which the reset pulse is input, after the Nth stage sequential circuit 100. It may also be connected to the output of a Mie circuit, etc.

[0094] In the odd-numbered sequential circuit 100, the first terminal of transistor 101 is connected to wiring 22 And when connected to one of the wirings 23, in the even-numbered sequential circuit 100, The first terminal of station 101 is connected to the other end of wiring 22 and wiring 23.

[0095] The signal SOUT is output from wiring 21 (also called the signal line), and wiring 21 is signal SO It has the function of transmitting or supplying UT. In the i-th stage sequential circuit 100, i Wiring 21 corresponds to wiring 12, and the i-1 wire 21 corresponds to wiring 14. This is the wiring, and the i+1th wire 21 is the wire corresponding to wire 16. Also, the ith wire The signal SOUT output from wiring 21 is the signal corresponding to signal OUT, i-1 The signal SOUT output from wiring 21 is the signal corresponding to signal SP, i+1 The signal SOUT output from wiring 21 corresponds to the signal RE.

[0096] The signal SCK is input to wiring 22 (also called the signal line), and wiring 22 receives the signal SCK. It has the function of transmitting or supplying. In this case, wiring 22 corresponds to wiring 11, and signal SCK corresponds to signal CK. It's a signal.

[0097] The signal SCKB is input to wiring 23 (also called the signal line), and the signal SCK is input to wiring 23. It has the function of transmitting or supplying B. Furthermore, the other sequential circuit 10 of the odd-numbered and even-numbered stages. In case 0, wiring 23 is the wiring corresponding to wiring 11, and signal SCKB corresponds to signal CK. This is the corresponding signal. Note that signal SCKB is the inverted signal of signal SCK, or derived from signal SCK. It is a signal with a phase shift.

[0098] The signal SSP is input to wiring 24 (also called the signal line), and wiring 24 receives the signal SSP. It has the function of transmitting or supplying. In the first stage sequential circuit 100, the wiring 24 is This wiring corresponds to wiring 14, and signal SSP is the wiring that corresponds to signal SP.

[0099] The shift register circuit in Figure 5 produces the same effect as the basic circuit or sequential circuit described above. It is possible.

[0100] Furthermore, in the i-th stage sequential circuit 100, the gate of transistor 102 is the i-2nd wire It may also be connected to wire 21 or the i-3rd wire 21.

[0101] Furthermore, in the i-th stage sequential circuit 100, the gate of transistor 105 is the i+2th wire It may also be connected to wire 21 or the i+3rd wire 21.

[0102] This embodiment can be implemented in appropriate combination with other embodiments, etc.

[0103] (Embodiment 2) In this embodiment, a basic circuit with a buffer circuit and a sequential circuit using the basic circuit are provided. I will explain about this.

[0104] First, the configuration of the basic circuit of this embodiment will be explained with reference to Figure 6(A). Figure 6( The basic circuit in A) is the same as the basic circuit in Figure 1(A), but with the addition of transistor 201.

[0105] Furthermore, it is preferable that transistor 201 has the same conductivity type as transistor 101. This embodiment describes the case where these transistors are of the N-channel type.

[0106] The first terminal of transistor 201 is connected to the wiring 11, and the second terminal of transistor 201 The child is connected to wiring 31, and the gate of transistor 201 is connected to the gate of transistor 101. Connected.

[0107] Transistor 201 has the function of controlling the conduction or non-conductivity between wiring 11 and wiring 31. Furthermore, transistor 201 has the function of supplying the signal CK from wiring 11 to wiring 31. Furthermore, transistor 201 has the function of maintaining the potential difference between wiring 31 and node N2.

[0108] The signal BOUT is output from wiring 31 (also called the signal line), and wiring 31 is connected to signal BOUT. It has the function of transmitting or supplying. Signal BOUT is a signal having a high level and a low level. Furthermore, signal BOUT is the output signal of the basic circuit in Figure 6(A). Also, signal B OUT is one of several output signals from the shift register circuit, or a sequential circuit. This is the signal corresponding to the output signal.

[0109] Next, we will explain how to drive the basic circuit shown in Figure 6(A).

[0110] Note that the explanation of the driving method, which is common to the basic circuit in Figure 1(A), will be omitted.

[0111] Furthermore, we will explain assuming that the initial potential of wiring 31 is potential VSS.

[0112] Also, for convenience, if the potential of node N2 is the potential at which transistor 101 turns on, then the transistor We will explain assuming that the 'Njista 201' will also be turned on.

[0113] First, during period Ta, the potential of node N2 is equal to the potential of wiring 11 (e.g., potential VSS) and the transistor The potential exceeds the sum of the threshold voltage of transistor 101. Therefore, transistor 20 Because 1 is turned on, the signal CK from wiring 11 is supplied to wiring 31. The signal CK is low level. Because of this, the potential of wiring 31 remains at potential VSS. In other words, the signal BOUT is It becomes U-level.

[0114] Next, during period Tb, the potential of node N2 is different from the potential of wiring 11 (e.g., potential VDD) from the transistor The potential exceeds the sum of the threshold voltage of transistor 101. Therefore, transistor 20 Because 1 remains ON, the signal CK from wiring 11 continues to be supplied to wiring 31. Because voltage CK is at a high level, the potential of wiring 31 rises to potential VDD. That is, The BOUT signal becomes high level.

[0115] In the basic circuit shown in Figure 6(A), the potential of wiring 31 during the period when the signal SP is at a high level. This prevents the voltage from dropping below the VSS potential. Therefore, the basic circuit shown in Figure 6(A) This allows for the output of a more stable signal.

[0116] Furthermore, the basic circuit in Figure 6(A) can achieve the same effects as the basic circuit in Embodiment 1. Cut.

[0117] Furthermore, when a load is connected to wiring 31, the load is driven by transistor 201. Furthermore, the load connected to wiring 31 is often larger than the load connected to wiring 12. Therefore, the W / L ratio of transistor 201 is greater than the W / L ratio of transistor 101. It is preferable.

[0118] Furthermore, the first terminal of transistor 101 and the first terminal of transistor 201 are connected in different ways. It may be connected to a wire.

[0119] Next, we will explain sequential circuits using the basic circuit shown in Figure 6(A).

[0120] First, the configuration of the sequential circuit in this embodiment will be explained with reference to Figure 6(B). Figure 6( The sequential circuit in B) is the sequential circuit in Figure 3 with transistors 201 and 202 added. It has that configuration.

[0121] Note that transistors 201 and 202 have the same conductivity type as transistor 101. It is preferable that these transistors are of the N-channel type. Let me explain the concept of "combination".

[0122] The first terminal of transistor 201 is connected to the wiring 11, and the second terminal of transistor 201 The child is connected to wiring 31, and the gate of transistor 201 is connected to the gate of transistor 101. Connected.

[0123] The first terminal of transistor 202 is connected to wire 13, and the second terminal of transistor 202 is connected to wire 13. The child is connected to wiring 31, and the gate of transistor 202 is connected to node N1.

[0124] Transistor 202 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 31. Furthermore, transistor 202 has the function of supplying the potential VSS of wiring 13 to wiring 31.

[0125] Next, we will explain how to drive the sequential circuit shown in Figure 6(B).

[0126] Note that the explanation of the driving method for the sequential circuit in Figure 3, which is common to both, will be omitted.

[0127] Furthermore, we will explain this by assuming that the initial potential VSS of wiring 31 is the same.

[0128] Also, for convenience, if the potential of node N2 is the potential at which transistor 101 turns on, then the transistor We will explain assuming that the 'Njista 201' will also be turned on.

[0129] Also, for convenience, if the potential of node N1 is the potential at which transistor 103 turns on, then the transistor We will explain assuming that the 'njista 202' is also turned on.

[0130] First, during period Ta, the potential of node N1 becomes potential VSS, so transistor 20 2 turns off. Also, the potential of node N2 is different from the potential of wiring 11 (e.g., potential VSS). The potential exceeds the sum of the threshold voltage of transistor 101. Therefore, transistor 2 Because 01 is turned on, the signal CK from wiring 11 is supplied to wiring 31. The signal CK is low Because it is a bell, the potential of wiring 31 remains at potential VSS. That is, signal BOUT It becomes a low level.

[0131] Next, in period Tb, the potential of node N1 is maintained at the potential in period Ta, Transistor 202 remains off. Also, the potential of node N2 is the potential of wiring 11 (example For example, the potential will exceed the sum of the potential VDD and the threshold voltage of transistor 101. Therefore, transistor 201 turns on, and the signal CK from wiring 11 is supplied to wiring 31. It remains in that state. Because the signal CK is at a high level, the potential of wiring 31 rises to the potential VDD. It rises. In other words, the signal BOUT becomes high level.

[0132] Next, during period Tc, the potential of node N2 becomes potential VSS, so transistor 20 1 turns off. Also, the potential of node N1 rises, and the gate potential of transistor 105 rises. (For example, the potential VDD) minus the threshold voltage of transistor 105 results in this potential. Therefore, Because transistor 202 turns on, the potential of wire 13 is supplied to wire 31. Therefore The potential of wiring 31 drops to potential VSS. In other words, the signal BOUT becomes low level. .

[0133] Next, during period Td, the potential of node N2 remains at potential VSS, so the transient T201 remains off. Also, the potential of node N1 is maintained at the potential during period Tc. Therefore, transistor 202 remains on, and the potential of wiring 13 becomes the same as wiring 31. It remains supplied to it. Therefore, the potential of wiring 31 remains at potential VSS. In other words The BOUT signal remains at a low level.

[0134] The sequential circuit in Figure 6(B) is the same as the basic circuit, the basic circuit and the sequential circuit of Embodiment 1 described above. It can produce the following effects.

[0135] Furthermore, when a load is connected to wiring 31, the load is driven by transistor 201. Furthermore, the load connected to wiring 31 is often larger than the load connected to wiring 12. Therefore, the W / L ratio of transistor 202 is greater than the W / L ratio of transistor 103. It is preferable.

[0136] Furthermore, both transistors 201 and 202 supply charge to wiring 31. Furthermore, the Vgs of transistor 201 during period Tb is equal to that of transistor 2 during period Tc. It is often smaller than the Vgs of 02. Therefore, the W / L ratio of transistor 201 is It is preferable that the W / L ratio is greater than that of ZISTA 202.

[0137] The transistor 202 has its first terminal connected to wire 13 and its second terminal connected to wire 31 It may also be replaced with a switching element connected to it.

[0138] This embodiment can be implemented in appropriate combination with other embodiments, etc.

[0139] (Embodiment 3) In this embodiment, a sequential circuit different from those in Embodiments 1 and 2 will be described. .

[0140] First, the sequential circuit in Figure 7(A) is the second of transistor 105 in the sequential circuit in Figure 3. The terminal is connected to wiring 16.

[0141] In the sequential circuit shown in Figure 7(A), wiring 15 and potential VDD can be omitted.

[0142] Furthermore, in the sequential circuits and shift register circuits, etc., described in Embodiments 1 and 2, The second terminal of the Zista 105 may be connected to the wiring 16.

[0143] Next, the sequential circuit in Figure 7(B) is the second of transistor 105 in the sequential circuit in Figure 3. It is configured such that the terminal is connected to wiring 17.

[0144] A signal CKB is input to the wiring 17 (also referred to as a signal line), and the wiring 17 has a function of transmitting or supplying the signal CKB. The signal CKB is a signal having a high level and a low level and is one of a plurality of clock signals input to the shift register circuit. Also, the signal CKB is an inverted signal of the signal CK, or a signal whose phase is shifted from the signal CK.

[0145] In the sequential circuit of FIG. 7(B), the wiring 15 and the potential VDD can be omitted.

[0146] Note that in the sequential circuit and the shift register circuit described in Embodiments 1 to 2, etc., the second terminal of the transistor 105 may be connected to the wiring 17.

[0147] Next, the sequential circuit of FIG. 8(A) has a configuration in which a capacitive element 301 is provided in the sequential circuit of FIG. 3.

[0148] The first electrode of the capacitive element 301 is connected to the wiring 13, and the second electrode of the capacitive element 301 is connected to the node N1.

[0149] The capacitive element 301 has a function of holding the potential difference between the wiring 13 and the node N1. Also, the capacitive element 301 has a function of maintaining the potential of the node N1.

[0150] During the period Ta, the capacitive element 301 holds the potential difference between the wiring 13 and the node N1 when the potential VSS of the wiring 13 is supplied to the node N1.

[0151] During the period Tb, the capacitive element 301 holds the voltage in the period Ta.

[0152] ​​​​​ During period Tc, the capacitive element 301 ensures that the potential VDD of the wiring 15 is supplied to node N1. The potential difference between wiring 13 and node N1 is maintained.

[0153] During period Td, the capacitive element 301 maintains the voltage during period Tc.

[0154] In the sequential circuit shown in Figure 8(A), during period Tb, the capacitive element 301 is connected to wiring 13 and node N1 Because the potential difference with is maintained, the potential of node N1 rises as the potential of wiring 12 rises. It can be suppressed.

[0155] Furthermore, during period Td, the capacitive element 301 maintains the potential difference between the wiring 13 and node N1. Therefore, fluctuations in the potential of node N1 can be suppressed.

[0156] Note that the connection destination of the first electrode of the capacitive element 301 is not limited to the wiring 13. The first electrode of child 301 may be connected to wiring 11, wiring 14, wiring 15, or wiring 16, etc. stomach.

[0157] Furthermore, the basic circuits, sequential circuits, and shift resistances described in Embodiments 1 and 2 and in this embodiment Capacitive elements 301 may also be provided in circuits such as the TA circuit.

[0158] Next, the sequential circuit in Figure 8(B) is a configuration in which transistor 302 is added to the sequential circuit in Figure 3. be.

[0159] Furthermore, it is preferable that transistor 302 has the same conductivity type as transistor 101. In this embodiment, we will describe the case where these transistors are of the N-channel type.

[0160] The first terminal of transistor 302 is connected to wiring 13, the second terminal of transistor 302 is connected to node N2, and the gate of transistor 302 is

[0161] connected to wiring 16. Transistor 302 has a function of controlling conduction or non-conduction between wiring 13 and node N2.

[0162] During period Ta, period Tb, and period Td, signal RE is at a low level. Therefore, transistor 302 turns off.

[0163] During period Tc, signal RE is at a high level. When signal RE becomes high level, transistor 302 turns on, and the potential VSS of wiring 13 is

[0164] supplied to node N2. In the sequential circuit of FIG. 8(B), by having transistor 302, the timing of supplying the potential VSS of wiring 13 to node N2 can be advanced during period Tc. Therefore, the timing of the potential of

[0165] node N2 decreasing can be advanced, and thus the timing of transistor 101 turning off can be advanced.

[0166] Note that in the basic circuit, sequential circuit, shift register circuit, etc. described in Embodiments 1 to 2 and this embodiment, transistor 302

[0166] may also be provided. Note that transistor 302 may be replaced with a switching element

[0167] Next, the sequential circuit in Figure 9(A) is a configuration in which transistor 303 is added to the sequential circuit in Figure 3. be.

[0168] The first terminal of transistor 303 is connected to wire 13, and the second terminal of transistor 303 is connected to wire 13. The child is connected to wire 12, and the gate of transistor 303 is connected to wire 16.

[0169] Furthermore, it is preferable that transistor 303 has the same conductivity type as transistor 101. In this embodiment, we will describe the case where these transistors are of the N-channel type.

[0170] Transistor 303 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 12. Furthermore, transistor 303 has the function of supplying the potential VSS of wiring 13 to wiring 12.

[0171] During periods Ta, Tb, and Td, the signal RE is at a low level. Therefore, the traction control is The 'njista 303' will be turned off.

[0172] During period Tc, signal RE becomes high level. When signal RE becomes high level, When the inverter 303 is turned on, the potential VSS of wiring 13 is supplied to wiring 12.

[0173] In the sequential circuit shown in Figure 9(A), the presence of transistor 303 allows for the operation during the period Tc. This allows the timing of supplying the potential VSS of wiring 13 to wiring 12 to be accelerated. This allows for a shorter falling edge time for the signal output.

[0174] Furthermore, the basic circuits, sequential circuits, and shift resistances described in Embodiments 1 and 2 and in this embodiment In circuits such as the TA circuit, transistor 303 may also be provided.

[0175] In particular, in the basic circuit and sequential circuit etc. described in Embodiment 2, transistor 303 is provided In this case, the second terminal of transistor 303 may be connected to the wiring 31. Alternatively, A transistor 303 is provided, and the first terminal is connected to the wiring 13, and the second terminal is connected to the wiring A transistor may be provided that is connected to 31 and whose gate is connected to wiring 16. This allows for a shorter falling edge time for the BOUT signal.

[0176] Furthermore, the first terminal of transistor 303 is connected to wire 13, and the second terminal is connected to wire 12 or This may be replaced with a switching element connected to wiring 31.

[0177] Next, the sequential circuit in Figure 9(B) is a configuration in which transistor 304 is added to the sequential circuit in Figure 3. be.

[0178] Furthermore, it is preferable that transistor 304 has the same conductivity type as transistor 101. In this embodiment, we will describe the case where these transistors are of the N-channel type.

[0179] The first terminal of transistor 304 is connected to wire 15, and the second terminal of transistor 304 is connected to wire 15. The child is connected to node N2, and the gate of transistor 304 is connected to wire 14.

[0180] Transistor 304 has the function of controlling the conduction or non-conductivity between wiring 15 and node N2. Furthermore, transistor 304 has the function of supplying the potential VDD of wiring 15 to node N2. Furthermore, after the transistor 304 raises the potential of node N2, it supplies power to node N2. It has the function of stopping the supply of load, electric potential, or signals, etc.

[0181] During period Ta, signal SP becomes high level. When signal SP becomes high level, Transistor 304 turns on. When transistor 304 turns on, the potential VD of wiring 15 D is supplied to node N2. Therefore, the potential of node N2 rises. Potential of node N2 The voltage of transistor 304 is obtained from the gate potential (e.g., potential VDD) of transistor 304. When the potential is equal to the threshold voltage, transistor 304 turns off. When node 4 is turned off, node N2 enters a floating state.

[0182] During periods Tb, Tc, and Td, signal SP is at a low level. When the voltage drops to U level, transistor 304 turns off.

[0183] The sequential circuit in Figure 9(B) has transistor 304, and in period Ta, This ensures that the potential of node N2 is reliably increased. In other words, it ensures that transistor 101 is reliably raised. It can be turned on.

[0184] Furthermore, the basic circuits, sequential circuits, and shift resistances described in Embodiments 1 and 2 and in this embodiment In circuits such as the TA circuit, transistor 304 may also be provided.

[0185] Furthermore, connect the first terminal of transistor 304 to wire 11, wire 14, or wire 17, etc. That's good too.

[0186] Furthermore, the first terminal of transistor 304 is connected to wiring 15 or wiring 11, and the second terminal This may be replaced with a switching element connected to node N2.

[0187] Next, the sequential circuit in Figure 10(A) is a configuration in which transistor 305 is added to the sequential circuit in Figure 3. That is the case.

[0188] Furthermore, it is preferable that transistor 305 has the same conductivity type as transistor 101. In this embodiment, we will describe the case where these transistors are of the N-channel type.

[0189] The first terminal of transistor 305 is connected to wire 16, and the second terminal of transistor 305 is connected to wire 16. The child is connected to the gate of transistor 105, and the gate of transistor 305 is connected to wiring 15. Connected.

[0190] Transistor 305 controls the conduction or non-conduction between wiring 16 and the gate of transistor 105. It has the function of doing so. Also, transistor 305 transmits the signal RE of wiring 16 to transistor 10 It has the function of supplying power to the gate of 5. Also, transistor 305 is a transistor of transistor 105. After increasing the gate potential, the charge, signal, or potential of the gate of transistor 105 is applied. It has the function of stopping the supply.

[0191] Transistor 305 is turned on during periods Ta, Tb, and Td. When transistor 305 is turned on, the signal RE from wiring 16 is supplied to the gate of transistor 105. Since the signal RE is low level, the gate potential of transistor 305 is potential VS It becomes S.

[0192] During period Tc, transistor 305 turns on. Transistor 305 turns on. Then, the signal RE from wiring 16 is supplied to the gate of transistor 105. The signal RE is high-frequency Because it is a bell, the gate potential of transistor 105 rises. When the gate potential rises, transistor 105 turns on. When this happens, the potential VDD of wiring 15 is supplied to node N1, and the potential of node N1 rises. Also, the gate potential of transistor 105 is the gate potential of transistor 305 (example). For example, if the potential obtained by subtracting the threshold voltage of transistor 305 from the potential VDD, then the transistor The transistor 305 turns off. Therefore, the gate of transistor 105 becomes floating. At that time, between the gate of transistor 105 and the second terminal, The potential difference between the terminal and node N1 is maintained. Therefore, as the potential of node N1 rises, Therefore, the gate potential of transistor 105 also rises. If the potential exceeds the sum of the potential VDD of the wiring 15 and the threshold voltage of transistor 105, If the voltage is at this level, transistor 105 will remain on. Therefore, the potential of node N1 is at this level. It becomes VDD.

[0193] In the sequential circuit of Figure 10(A), the presence of transistor 305 allows for the following during the period Tc. Therefore, the potential of node N1 can be raised to potential VDD. The Vgs of transistors 103 and 104 can be increased. Transistor 103 And if the Vgs of transistor 104 can be increased, then transistor 103 and This allows transistor 104 to be turned on more reliably.

[0194] Furthermore, the basic circuits, sequential circuits, and shift resistances described in Embodiments 1 and 2 and in this embodiment In circuits such as the TA circuit, transistor 305 may also be provided.

[0195] Furthermore, the first terminal of transistor 305 is connected to wiring 16, and the second terminal is connected to the transistor It may also be replaced with a switching element connected to the gate of TA105.

[0196] The first electrode is connected to the gate of transistor 105, and the second electrode is connected to the transistor A capacitive element may be provided that is connected to the second terminal of 105. In this way, transistor 1 The capacitance value between the gate and the second terminal of 05 can be increased, so the transistor The gate potential of 105 can be increased.

[0197] Alternatively, the gate of transistor 305 may be connected to wiring 17.

[0198] Next, the sequential circuit in Figure 10(B) is the sequential circuit in Figure 3 with transistor 306 and transistor This configuration includes a 307-type starter.

[0199] Note that transistors 306 and 307 have the same conductivity type as transistor 101. It is preferable that these transistors are of the N-channel type. Let me explain the concept of "combination".

[0200] The first terminal of transistor 306 is connected to wire 15, and the second terminal of transistor 306 is connected to wire 15. The child is connected to the gate of transistor 105, and the gate of transistor 306 is connected to wiring 16. Connected.

[0201] The first terminal of transistor 307 is connected to wire 13, and the second terminal of transistor 307 is connected to wire 13. The child is connected to the gate of transistor 105, and the gate of transistor 307 is connected to wire 14. Connected.

[0202] Transistor 306 controls the conduction or non-conductivity between wiring 15 and the gate of transistor 105. It has the function of doing so. Also, transistor 306 controls the potential VDD of the wiring 15 to transistor 1 It has the function of supplying power to the gate of 05. Also, transistor 306 has the function of supplying power to transistor 105 After increasing the gate potential, the charge, potential, or signal to the gate of transistor 105 It has the function of stopping the supply of such items.

[0203] Transistor 307 controls the conduction or non-conductivity between wiring 13 and the gate of transistor 105. It has the function of doing so. Also, transistor 307 controls the potential VSS of the wiring 13 to transistor 1 It has the function of supplying to gate 05.

[0204] During period Ta, signal SP becomes high level, and signal RE becomes low level. When E becomes low level, transistor 306 turns off. Also, when signal SP becomes high level... When this happens, transistor 307 turns on. When transistor 307 turns on, The potential VSS across line 13 is supplied to the gate of transistor 105. Therefore, the transistor The gate potential of transistor 105 becomes potential VSS, and transistor 105 turns off.

[0205] During period Tb, signal SP becomes low level, and signal RE remains low level. When signal SP becomes low, transistor 306 turns off. Also, when signal RE becomes low If it remains at the U level, transistor 307 will remain off. In this way, the transistor When both transistor 306 and transistor 307 are turned off, the gate of transistor 105 It enters a floating state. Therefore, the gate potential of transistor 105 is maintained at potential VSS. Therefore, transistor 105 remains off.

[0206] During period Tc, signal SP remains at a low level, while signal RE becomes high. If the signal SP remains at a low level, transistor 307 will remain off. Also, When the signal RE reaches a high level, transistor 306 turns on. Transistor 306 When it is turned on, the potential VDD of the wiring 15 is supplied to the gate of transistor 105, The gate potential of transistor 105 rises. Then, transistor 105 turns on. When transistor 105 turns on, wiring 15 The potential VDD is supplied to node N1, and the potential of node N1 rises. Also, the transient The gate potential of transistor 105 is from the gate potential of transistor 306 (e.g., potential VDD). When the potential drops below the threshold voltage of transistor 306, transistor 306 turns off. Therefore, the gate of transistor 105 becomes floating. At this time, the transistor Between the gate of transistor 105 and the second terminal, the gate of transistor 105 and node N1 The potential difference is maintained. Therefore, as the potential of node N1 increases, transistor 10 The gate potential of transistor 5 also rises. The gate potential of transistor 105 is the potential VD of wiring 15. If the potential exceeds the sum of the threshold voltage of D and transistor 105, the transistor Node 105 remains on. Therefore, the potential of node N1 becomes potential VDD.

[0207] During period Td, signal SP remains at a low level, and signal RE becomes low. If the signal SP remains at a low level, transistor 306 will remain off. Also, When the signal RE goes to a low level, transistor 307 turns off. In this way, the transistor When both transistor 306 and transistor 307 are turned off, the gate of transistor 105 It becomes a floating state. Therefore, the gate potential of transistor 105 is the potential during period Tc. Because it is maintained in this state, transistor 105 remains on.

[0208] The sequential circuit in Figure 10(B) has transistors 306 and 307. This allows the potential of node N1 to be raised to potential VDD during period Tc. Therefore, the Vgs of transistors 103 and 104 can be increased. If the Vgs of transistors 103 and 104 can be increased, This allows transistors 103 and 104 to be turned on more reliably.

[0209] Furthermore, transistor 105 can be kept ON during period Td. Therefore, the potential VDD of wiring 15 can be continuously supplied to node N1, so the power of node N1 It is possible to maintain a stable position.

[0210] Furthermore, the basic circuits, sequential circuits, and shift resistances described in Embodiments 1 and 2 and in this embodiment In the circuit and the like, transistors 306 and 307 may also be provided.

[0211] Furthermore, the first terminal of transistor 306 is connected to wiring 15, and the second terminal is connected to the transistor It may also be replaced with a switching element connected to the gate of TA105.

[0212] Furthermore, the first terminal of transistor 307 is connected to wiring 13, and the second terminal is connected to the transistor It may also be replaced with a switching element connected to the gate of TA105.

[0213] The first terminal of transistor 306 may also be connected to wiring 16 or wiring 17, etc.

[0214] Next, the sequential circuit in Figure 11(A) is a configuration in which circuit 308 is added to the sequential circuit in Figure 3.

[0215] The first terminal of circuit 308 is connected to node N1, and the second terminal of circuit 308 is connected to the transistor It connects to gate TA104.

[0216] Circuit 308 outputs a modified version of the potential or signal of the first terminal from the second terminal. It has the ability. Also, circuit 308 controls the potential of the first terminal or the rise time of the signal and / or It has the function of outputting a signal with a longer fall time from the second terminal. Also, circuit 3 08 has the function of outputting a delayed version of the potential or signal from the first terminal through the second terminal. ru.

[0217] During period Ta, as the potential of node N1 decreases, the potential of wiring 12 also decreases. At that time, the gate potential of transistor 104 lags behind or slows down the potential of node N1. Because the voltage is decreasing, transistor 104 is turned on. Therefore, the potential VSS of wiring 13 is... This is supplied to the gate of transistor 101. Then, the gate of transistor 104 The potential decreases, and transistor 104 turns off.

[0218] During period Tc, the potential of node N1 rises. At this time, the gauge of transistor 104 Because the potential of node N1 rises with a lag or more slowly than the potential of node N1, transistor 10 4 is turned off. Then the gate potential of transistor 104 rises, and the transistor Transistor 104 turns on. Therefore, the potential VSS of wiring 13 is equal to the gate of transistor 101. This is supplied to transistor 101, which then turns it off.

[0219] During periods Tb and Td, the potential of node N1 does not rise or fall significantly, The sequential circuit in Figure 11(A) operates similarly to the sequential circuit in Figure 3.

[0220] In the sequential circuit shown in Figure 11(A), during period Ta, when the potential of wiring 12 is decreasing... Therefore, the potential VSS of wiring 13 can be supplied to node N2. Thus, the potential of wiring 12 This prevents the potential of node N2 from decreasing as the other potential decreases. If we can prevent the potential from decreasing, we can raise the potential of node N2. Therefore, the Vgs of transistor 101 can be increased.

[0221] Furthermore, during period Tc, the timing at which transistor 101 turns off can be delayed. Therefore, the signal CK from wiring 11 can be supplied to wiring 12. The signal CK is low Because it is a bell, the falling edge time of the signal OUT can be shortened. In particular, transient Because the W / L ratio of the ST101 is often large, the falling edge time of the signal OUT is significantly reduced. It can be done.

[0222] Here, we will explain a specific example of circuit 308.

[0223] The circuit 308 in Figure 11(B) has a transistor 308a. The first terminal is connected to the first terminal of circuit 308, and the second terminal of transistor 308a is The gate of transistor 308a is connected to the second terminal of circuit 308 and to wiring 11. It can be done.

[0224] The circuit 308 in Figure 11(C) is the same as the circuit 308 in Figure 11(B) but with transistor 308b added. This is the configuration. The first terminal of transistor 308b is connected to the first terminal of circuit 308. The second terminal of transistor 308b is connected to the second terminal of circuit 308, and the transistor The gate of TA308b is connected to the second terminal of circuit 308.

[0225] The circuit 308 in Figure 11(D) is the same as the circuit 308 in Figure 11(B) but with the transistor 308c added. This is the configuration. The first terminal of transistor 308c is connected to wiring 11, and the transistor The second terminal of 308c is connected to the second terminal of circuit 308, and the gate of transistor 308c The terminal is connected to the first terminal of circuit 308.

[0226] The circuit 308 in Figure 11(E) is the same as the circuit 308 in Figure 11(B), but with transistor 308d and The configuration includes transistor 308e. The first terminal of transistor 308d is connected to wiring 11. The second terminal of transistor 308d is connected to the second terminal of circuit 308. The first terminal of transistor 308e is connected to the first terminal of circuit 308, and the transistor The second terminal of transistor 308e is connected to the gate of transistor 308d, and transistor 30 The gate of 8e is connected to wiring 11.

[0227] In circuit 308 of Figure 11(E), the gate potential of transistor 308d is determined from the potential VDD. Since the potential can also be raised to a high potential, the potential of the second terminal of circuit 308 can be raised to potential VDD. It can be raised.

[0228] Furthermore, transistors 308a through 308e use the same conductive material as transistor 101. It is preferable that it be an electric type.

[0229] Note that the gate of transistor 308a, the first terminal of transistor 308c, and the transistor Connect the first terminal of transistor 308d and / or the gate of transistor 308e to wiring 17, etc. You may do so.

[0230] This embodiment can be implemented in appropriate combination with other embodiments, etc.

[0231] (Embodiment 4) Taking an EL display device as an example, the cross-sectional structure of the pixels and driving circuit of a display device according to one aspect of the present invention The construction will be explained using Figure 12. Figure 12 shows a cross-sectional view of the pixel 840 and the drive circuit 841. This is given as an example.

[0232] Pixel 840 comprises a light-emitting element 832 and a transistor that has the function of supplying current to the light-emitting element 832. It has a zista 831. The pixel 840 has a light-emitting element 832 and a transistor 831. In addition, transistors that control the input of the image signal to pixel 840, and the potential of the image signal It may have various semiconductor elements, such as capacitive elements for holding data.

[0233] The drive circuit 841 includes transistor 830 and holds the gate voltage of transistor 830. It has a capacitive element 833 for this purpose. The drive circuit 841 is the basic circuit of Embodiments 1 to 3, sequential It corresponds to the initial circuit and shift register circuit, etc. Specifically, transistor 830 is a transistor This corresponds to transistor 101 or transistor 201, etc. Note that the drive circuit 841 is a transistor In addition to the zista 830 and the capacitive element 833, various semiconductors such as transistors and capacitive elements are also used. It may have elements.

[0234] Transistor 831 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and at a position overlapping with the conductive film 816 A semiconductor film 817 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 815 and 818 located on the semiconductor film 817. The film 816 also functions as a scan line.

[0235] The transistor 830 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and at a position overlapping with the conductive film 812 A semiconductor film 813 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 814 and 819 located on the semiconductor film 813.

[0236] Capacitive element 833 is provided on a substrate 800 having an insulating surface, with a conductive film 812 and on the conductive film 812 The gate insulating film 802 and the conductive film 812 overlap at a position on the gate insulating film 802 It has a conductive film 819 placed on top.

[0237] Furthermore, insulating film 820 is applied to conductive film 814, conductive film 815, conductive film 818, and conductive film 819. The insulating film 821 is arranged to be stacked in order. A conductive film 822 that functions as an anode is provided. The conductive film 822 is an insulating film 820 and connected to the conductive film 818 via contact holes 823 formed in the insulating film 821. It is being done.

[0238] Furthermore, an insulating film 824 having an opening that exposes a portion of the conductive film 822, 1 is provided on. On a part of the conductive film 822 and on the insulating film 824, there is an EL layer 825, A conductive film 826, which functions as a cathode, is arranged in a stacked manner. The region where 2, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. ru.

[0239] In one aspect of the present invention, transistors 830 and 831 are amorphous, micro Semiconductors such as silicon or germanium, which are crystalline, polycrystalline, or single crystals, are used in semiconductor films. It may be used as a semiconductor film, or wide-bandgap semiconductors such as oxide semiconductors may be used as semiconductor films. It's fine if you do that.

[0240] The semiconductor film of transistors 830 and 831 is amorphous, microcrystalline, polycrystalline or When a single crystal semiconductor such as silicon or germanium is used, a single conductive material is added. The impurity elements are added to the semiconductor film to function as source or drain terminals. This forms an impurity region. For example, by adding phosphorus or arsenic to the semiconductor film, An impurity region having n-type conductivity can be formed. Also, for example, boron can be used as described above. By adding it to a semiconductor film, it is possible to form an impurity region with p-type conductivity.

[0241] In cases where oxide semiconductors are used in the semiconductor films of transistors 830 and 831 In addition, a dopant is added to the above semiconductor film to function as a source terminal or drain terminal. An impurity region may be formed. Dopant addition can be performed using ion implantation. Dopants are, for example, noble gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 elements such as arsenic and antimony can be used. For example, nitrogen can be used as dopan. When used as a toner, the concentration of nitrogen atoms in the impurity region is 5 × 10⁻⁶. 19 / cm 3 The above 1× 10 22 / cm 3 The following is preferable:

[0242] Furthermore, silicon semiconductors are produced using vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the annealing method, amorphous silicon subjected to treatments such as laser annealing Hydrogen ions and other substances are implanted into polycrystalline silicon and single-crystal silicon wafers to form a crystallized surface layer. Single-crystal silicon from which a portion has been peeled off can be used.

[0243] The oxide semiconductor film must be at least one or more selected from In, Ga, Sn, and Zn. It contains elements. For example, the In-Sn-Ga-Zn-O system oxide, which is an oxide of a quaternary metal. Monocrystalline semiconductors, and oxide semiconductors such as In-Ga-Zn-O, which are oxides of ternary metals, and In-S n-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors, Sn-Ga-Zn -O-based oxide semiconductors, Al-Ga-Zn-O-based oxide semiconductors, Sn-Al-Zn-O-based acids Iridescent semiconductors, and binary metal oxides such as In-Zn-O oxide semiconductors, Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, and In-Ga-O-based oxide semiconductors. Monocrystalline semiconductors, in-O oxide semiconductors and Sn-O oxide semiconductors, which are oxides of monocrystalline metals. Zn-O-based oxide semiconductors can be used. In addition, In can be added to the above oxide semiconductor. Other elements besides Ga, Sn, and Zn, such as SiO2, may also be included.

[0244] For example, an In-Ga-Zn-O oxide semiconductor is made up of indium (In) and gallium (G a) This means an oxide semiconductor containing zinc (Zn), and its composition is not specified.

[0245] Furthermore, oxide semiconductor films have the chemical formula InMO3(ZnO) m Thin films denoted as (m>0) It can be used. Here, M is one selected from Zn, Ga, Al, Mn and Co. or indicates multiple metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, or Examples include Ga and Co.

[0246] Furthermore, when using an In-Zn-O based material as an oxide semiconductor, the target used The atomic ratio of metal elements is In:Zn = 50:1 to 1:2 (which translates to In2O in mole ratios). 3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (molar ratio) Converted to this ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15:1 to 1.5:1 (Converted to a mole ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming In-Zn-O oxide semiconductors is the atomic ratio. When the ratio of In:Zn:O = X:Y:Z, assume Z > 1.5X + Y. The ratio of Zn is within the above range. By fitting it into this configuration, mobility can be improved.

[0247] Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Purified oxide semiconductors (purified Oxi) are achieved by reducing elemental defects. A de Semiconductor is an i-type (intrinsic semiconductor) or very close to an i-type. Therefore, transistors using the above-mentioned oxide semiconductor have the characteristic of having a remarkably low off-current. It has the following characteristics. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV. More preferably, the voltage is 3 eV or higher. The concentration of impurities such as water or hydrogen is sufficiently reduced. Furthermore, by reducing oxygen deficiency, a highly purified oxide semiconductor film is used. This allows the transistor's off-current to be reduced.

[0248] Specifically, transistors using highly purified oxide semiconductors as semiconductor films have a low off-current. This can be proven through various experiments. For example, if the channel width is 1 × 10⁻⁶ 6 micrometers Even with an element with a channel length of 10 μm, the voltage between the source terminal and the drain terminal (drain voltage) When the voltage is in the range of 1V to 10V, the off-current is measured by a semiconductor parameter analyzer. Below the limit, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, The off-current density, which corresponds to the value obtained by dividing the f-current by the transistor's channel width, is 100 Hz. It can be seen that it is less than / μm. Also, by connecting the capacitive element and the transistor, the capacitive element Using a circuit that controls the charge flowing into or out of a capacitive element with the transistor, Current density was measured. In this measurement, the above transistor was subjected to highly purified oxide semiconductor By using a conductive film as the channel formation region, the change in the amount of charge per unit time of the capacitive element is used to determine the channel The off-current density of the transistor was measured. The results showed the source terminal and drain of the transistor. When the voltage across the terminals is 3V, an even lower off-current density of several tens of yA / μm can be obtained. It was found that a highly purified oxide semiconductor film was used in the channel formation region. The off-current of the transistor is significantly different compared to transistors using crystalline silicon. It's very low.

[0249] Unless otherwise specified, in this specification, off-current refers to the off-current of an n-channel transistor. Therefore, with the drain terminal at a higher potential than the source terminal and gate, the source terminal When the gate potential is 0 or less relative to the potential of the child, the source terminal and drain This refers to the current flowing between terminals. Alternatively, in this specification, off-current refers to p-channel current. In a transistor of this type, the drain terminal is at a lower potential than the source terminal and the gate. In this state, when the gate potential is 0 or greater with respect to the potential of the source terminal, This refers to the current flowing between the source terminal and the drain terminal.

[0250] For example, oxide semiconductor films include In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing zinc. When depositing a Zn-based oxide semiconductor film by sputtering, preferably, the atomic ratio is In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of an In-Ga-Zn oxide system, represented by the ratio 3:1:4, is used. To deposit an oxide semiconductor film using an In-Ga-Zn-based oxide target having the following properties. This makes it easier for polycrystalline or CAAC (Compound Acetate Acetate), as described later, to form.

[0251] Furthermore, the packing density of the target containing In, Ga, and Zn is preferably 90% to 100%. Or it is between 95% and 100%. By using a target with a high filling rate, The oxide semiconductor film that is formed becomes a dense film.

[0252] Specifically, the oxide semiconductor film is processed by holding the substrate in a processing chamber that is kept under reduced pressure, and then processing... While removing residual moisture in the laboratory, sputtered gas from which hydrogen and moisture have been removed is introduced, and the above It can be formed using a film-forming agent. During film formation, the substrate temperature should be between 100°C and 600°C. Alternatively, the temperature may be between 200°C and 400°C. By depositing the film while heating the substrate... This allows for a reduction in the impurity concentration contained in the deposited oxide semiconductor film. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, ion pump, or titanium pump. It is preferable to use a breech pump. Furthermore, a turbopump is preferred as the exhaust means. A cold trap may be added to the system. The deposition chamber is evacuated using a cryopump. Then, for example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (more preferably carbon Because compounds containing elementary atoms are also exhausted, the oxide semiconductor film deposited in the processing chamber contains The concentration of impurities can be reduced.

[0253] Furthermore, in oxide semiconductor films formed by sputtering, etc., there may be water or hydrogen as an impurity. It may contain a large amount of (hydroxyl groups). Water or hydrogen forms donor levels. Because it is easily oxidized, it is an impurity for oxide semiconductors. Therefore, in one aspect of the present invention, To reduce impurities such as water or hydrogen in a semiconductor film (dehydration or dehydrogenation) For oxide semiconductor films, under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas, acid Under a gas atmosphere or in ultra-dry air (CRDS (cavity ring-down laser spectroscopy) The moisture content measured using a dew point meter of the ) type is 20 ppm or less (equivalent to a dew point of -55°C). The heat treatment is performed in an atmosphere (preferably 1 ppm or less, preferably 10 ppb or less of air) To administer.

[0254] By applying heat treatment to the oxide semiconductor film, water or hydrogen is removed from the oxide semiconductor film. This is possible. Specifically, a substrate at 250°C to 750°C, preferably 400°C or higher. The heat treatment should be performed at a temperature below the strain point. For example, 500°C for 3 minutes to 6 minutes. It should be done to a certain extent. If the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time. Therefore, processing can be performed even at temperatures exceeding the strain point of the glass substrate.

[0255] Furthermore, the above heat treatment causes oxygen to be removed from the oxide semiconductor film, and oxygen remains in the oxide semiconductor film. Defects may be formed. Therefore, in one aspect of the present invention, the g An insulating film containing oxygen is used as the insulating film, such as a galvanic insulating film. After forming the film, heat treatment is applied to supply oxygen from the insulating film to the oxide semiconductor film. This configuration reduces the oxygen vacancies that serve as donors and is contained in the oxide semiconductor film. The oxide semiconductor can satisfy the stoichiometric composition. The oxide semiconductor film has a chemical composition. It is preferable that the oxygen content exceeds the stoichiometric composition. As a result, oxide semiconductor film This makes it possible to bring it closer to type i, reducing variations in the electrical characteristics of transistors due to oxygen deficiency. This can reduce the noise and improve electrical characteristics.

[0256] Furthermore, the heat treatment to supply oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or dilute air. In a gaseous atmosphere (such as argon or helium), preferably at a temperature of 200°C to 400°C. The following steps should be performed at a temperature (for example, between 250°C and 350°C). The gas used should have a water content of 20 ppm. The following is preferably 1 ppm or less, and more preferably 10 ppb or less.

[0257] Furthermore, oxide semiconductor films can be single crystals, polycrystalline (also called polycrystals), or amorphous. Which state will it take?

[0258] Preferably, the oxide semiconductor film is CAAC-OS(C Axis Aligned Cr The film is a ystalline oxide semiconductor film.

[0259] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. This is an oxide semiconductor film having a crystalline-amorphous multiphase structure with crystalline and amorphous parts in the amorphous phase. Yes, it exists. Furthermore, the crystalline portion must be small enough to fit within a cube with sides less than 100 nm long. There are many. Also, transmission electron microscopes (TEM) In the image observed using a microscope, the amorphous region contained in the CAAC-OS film and The boundary with the crystalline portion is not clear. Also, TEM revealed grain boundaries in the CAAC-OS film. Also called inboundary. ) cannot be confirmed. Therefore, the CAAC-OS film has grain boundaries. The resulting decrease in electron mobility is suppressed.

[0260] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0261] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0262] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0263] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0264] Furthermore, some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0265] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. In this case, the flat sputtering particles maintain their crystalline state and form a base By reaching the plate, the CAAC-OS film can be deposited.

[0266] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0267] By reducing the inclusion of impurities during film formation, it is possible to suppress the breakdown of crystals due to impurities. For example, reducing the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film deposition chamber. This is what you should do. Also, you should reduce the impurity concentration in the film-forming gas. Specifically, the dew point should be -8 A film-forming gas with a temperature of 0°C or lower, preferably -100°C or lower, is used.

[0268] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particles adheres to the substrate.

[0269] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0270] As an example of a sputtering target, an In-Ga-Zn-O compound target is described below. It is shown below.

[0271] InO X powder, GaO Y powder, and ZnO Z powder are mixed at a predetermined molar ratio and subjected to a pressure treatment After that, a polycrystalline In-G a-Zn-O compound target is obtained by heat treatment at a temperature of 1000 °C or higher and 1500 °C or lower. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powder are 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Note that the type of powder and the molar ratio for mixing can be appropriately changed depending on the sputtering target to be produced. It may be changed as appropriate.

[0272] Next, a specific example of the configuration of the transistor included in the semiconductor device of the present invention will be described. It will be described.

[0273] The transistor shown in FIG. 13(A) has a bottom gate type with a channel etch structure.

[0274] The transistor shown in FIG. 13(A) includes a gate electrode (gate tr) 1602 formed on an insulating surface, a gate insulating film 1603 on the gate electrode 1602, a semiconductor film 1604 overlapping the gate electrode 1602 on the gate insulating film 160 3, and a conductive film 1605 and a conductive film 1606 formed on the semiconductor film 1604. Furthermore, the transistor includes an insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606. ​ It may be included as one of its components.

[0275] Furthermore, the transistor shown in Figure 13(A) is in an insulating position where it overlaps with the semiconductor film 1604. The device may further have a back gate electrode formed on the edge film 1607.

[0276] The transistor shown in Figure 13(B) is a bottom-gate type with a channel protection structure.

[0277] The transistor shown in Figure 13(B) has a gate electrode 161 formed on an insulating surface. 2, the gate insulating film 1613 on the gate electrode 1612, and on the gate insulating film 1613 The semiconductor film 1614 overlaps with the gate electrode 1612, and is formed on the semiconductor film 1614. A channel protective film 1618 and a conductive film 1615 formed on the semiconductor film 1614, conductive The transistor also has a channel protection film 1618 and a conductive film 16 The components may also include 15 and an insulating film 1617 formed on the conductive film 1616. .

[0278] Furthermore, the transistor shown in Figure 13(B) is in an insulating position where it overlaps with the semiconductor film 1614. The device may further have a back gate electrode formed on the edge film 1617.

[0279] By providing the channel protection film 1618, the channel formation region of the semiconductor film 1614 and In subsequent processes, the film formed by plasma or etching agent during etching of certain parts This prevents damage such as wear and tear. Therefore, it improves the reliability of transistors. It is possible.

[0280] The transistor shown in Figure 13(C) is a bottom-gate type with a bottom-contact structure.

[0281] The transistor shown in Figure 13(C) has a gate electrode 162 formed on an insulating surface. 2, the gate insulating film 1623 on the gate electrode 1622, and the conductive film on the gate insulating film 1623 Film 1625, conductive film 1626, and gate electrode 1622 on gate insulating film 1623 The semiconductor film 162 is formed on the conductive film 1625 and conductive film 1626, which are overlapping. It has 4. Furthermore, the transistor has conductive film 1625, conductive film 1626, and semiconductor An insulating film 1627 formed on the film 1624 may also be included as a component.

[0282] Furthermore, the transistor shown in Figure 13(C) is in an insulating position where it overlaps with the semiconductor film 1624. The device may further have a back gate electrode formed on the edge film 1627.

[0283] The transistor shown in Figure 13(D) is a top-gate type with a bottom-contact structure.

[0284] Furthermore, the transistor shown in Figure 13(D) has a conductive film 1645 formed on the insulating surface. A conductive film 1646 and a semiconductor formed on the insulating surface and conductive film 1645 and conductive film 1646. Film 1644 and the semiconductor film 1644, conductive film 1645 and conductive film 1646 formed on the film. The gate insulating film 1643 and the semiconductor film 1644 overlap on the gate insulating film 1643. It has a gate electrode 1642. Furthermore, the transistor has a shape formed on the gate electrode 1642. The formed insulating film 1647 may be included as a component.

[0285] The transistor of this embodiment is used in the basic circuits, sequential circuits, and shift resistors of Embodiments 1 to 3. It can be used in transistors that constitute circuits, etc. In particular, in this embodiment, Transistors using oxide semiconductors have a low off-current. Therefore, this transistor is practical By using it in the basic circuits, sequential circuits, and shift register circuits of the implementation forms 1 to 3, The charge leaking from node N1 and node N2 can be reduced. If the charge leaking from components such as N2 can be reduced, the driving frequency can be lowered. can.

[0286] This embodiment can be implemented in appropriate combination with other embodiments.

[0287] (Embodiment 5) Figure 14 illustrates an example of a panel, which corresponds to one form of display device. The panel consists of a substrate 700, a pixel section 701 on the substrate 700, a signal line driving circuit 702, and a scanning line It has a drive circuit 703 and a terminal 704.

[0288] The pixel unit 701 has multiple pixels, and each pixel has a display element and a control for the operation of the display element. One or more transistors are provided to perform the scan line drive. The scan line drive circuit 703 controls each image By controlling the supply of potential to the scan lines connected to the base, the pixels of the pixel unit 701 are selected. Select. The signal line drive circuit 702 controls the image of the pixel selected by the scan line drive circuit 703. Controls the supply of signals.

[0289] One or both of the signal line drive circuit 702 and the scan line drive circuit 703 are as described in Embodiments 1 to 3. It may include basic circuits, sequential circuits, or shift register circuits, etc. This method can achieve the effects described in Forms 1-3, and also enlarge the pixel portion 701. This is possible. Furthermore, a large number of pixels can be provided in the pixel section 701.

[0290] Furthermore, liquid crystal elements or light-emitting elements can be used as the display elements.

[0291] This embodiment can be implemented in appropriate combination with other embodiments.

[0292] (Embodiment 6) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention And mobile phones, game consoles including portable devices, personal digital assistants, e-books, video cameras and digital cameras Cameras such as still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 15. vinegar.

[0293] Figure 15(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It includes illustration 5008, etc. A semiconductor according to one aspect of the present invention is used in the drive circuit of a portable game console. By using this device, it is possible to provide a portable game console with low power consumption and stable operation. Yes, it is possible. Note that the portable game console shown in Figure 15(A) has two display units 5003 and a display unit While it has 5004, the number of display units a portable game console has is not limited to this. .

[0294] Figure 15(B) shows a display device, which includes a housing 5201, a display unit 5202, a support base 5203, etc. To do so, by using a semiconductor device according to one aspect of the present invention in the drive circuit of a display device, the power consumption is reduced. This allows us to provide a display device with low power consumption and stable operation. Furthermore, the display device includes a part All information display devices, such as those for computer systems, TV broadcast reception, and advertising displays, It is included.

[0295] Figure 15(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It has a keyboard 5403, a pointing device 5404, etc. Notebook personal By using a semiconductor device according to one aspect of the present invention in the drive circuit of a computer, the power consumption is reduced. We can provide a notebook personal computer with low power and stable operation.

[0296] Figure 15(D) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 They are connected by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It is made movable by 5605. The video switching in the first display unit 5603 is connected Switching according to the angle between the first housing 5601 and the second housing 5602 in section 5605 A configuration in which a semiconductor device according to one aspect of the present invention is used in the drive circuit of a portable information terminal. By using this technology, it is possible to provide a portable information terminal with low power consumption and stable operation.

[0297] Figure 15(E) is a mobile phone, consisting of a housing 5801, a display unit 5802, an audio input unit 5803, It has an audio output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the received light into an electrical signal, external images can be captured. By using a semiconductor device according to one aspect of the present invention in the drive circuit of a mobile phone, power consumption is reduced. This allows us to provide mobile phones with stable operation.

[0298] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of Symbols]

[0299] M1 Transistor M3 Transistor M7 Transistor N1 node N2 node 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 21[i] Wiring 21[i-1] Wiring 21[N] Wiring 21[1] Wiring 22 Wiring 23 Wiring 24 Wiring 31 Wiring 100 sequential circuits 100[1] Sequential circuit 100[3] Sequential circuit 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 110 Capacitive elements 201 Transistors 202 transistors 301 Capacitive element 302 Transistors 303 Transistors 304 transistors 305 Transistors 306 transistors 307 transistors 308 circuits 308a transistor 308b Transistor 308c transistor 308d transistor 308e transistor 700 circuit boards 701 pixel section 702 Signal Line Drive Circuit 703 Scan line drive circuit 704 terminal 800 circuit boards 802 Gate Insulator 812 Conductive film 813 Semiconductor film 814 Conductive film 815 Conductive film 816 Conductive film 817 Semiconductor film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive film 830 transistors 831 Transistors 832 Light-emitting element 833 Capacitive element 840 pixels 841 Drive Circuit 1602 Gate Shuttle 1603 Gate Insulator 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Shuttle gate 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protective film 1622 Gate 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Shutdown gate 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Support stand 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 Display section 5803 Voice Input Section 5804 Audio output section 5805 Operation Keys 5806 Light receiving section

Claims

[Claim 1] It comprises a first transistor, a second transistor, and a capacitive element. Either the source or the drain of the first transistor has the function of being able to receive the first signal. The source or drain of the first transistor is electrically connected to the first electrode of the capacitive element. The source or drain of the second transistor has the function of being able to be supplied with a first potential. The source or drain of the second transistor is electrically connected to the second electrode of the capacitive element. A semiconductor device characterized in that the gate of the second transistor has the function of being able to receive a second signal.

Images