Imaging device

Abstract

To provide an imaging device with low power consumption. [Solution] A pixel is provided with a first circuit and a second circuit. The first circuit is for imaging. It can generate data and store the difference data between that data and the data acquired in the initial frame. This is possible. The second circuit compares the difference data with an arbitrarily set voltage range. A path is established. The second circuit supplies a readout signal to the first circuit according to the comparison result. By using this configuration, it is determined that the differential data is within the set voltage range. If this occurs, the pixel will not be read out; the pixel will only be read out if it is determined that the voltage is outside the voltage range. It is possible to make cuts.

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. is related to an object, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operating methods, or their manufacturing methods can be cited as an example.

[0003]

[0004]

Background Art

[0004] Techniques for constructing transistors using oxide semiconductor thin films formed on substrates have been attracting attention. For example, an imaging device having a configuration in which a transistor having an extremely low off-current with an oxide semiconductor is used in a pixel circuit is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] When capturing moving images using a CMOS image sensor, all pixels are acquired for each frame. The operation to read data is performed. In this operation, the same data is read across multiple consecutive frames. Sometimes, data that can be considered identical is obtained for a single pixel.

[0007] For example, a stationary subject outdoors will experience changes in the brightness and darkness of natural light over time. However, at short intervals of less than 1 / 10th of a second, which corresponds to the frame rate of a moving image, it is not possible for a human to make a judgment. There is hardly any change significant enough to warrant it. In other words, the data that can be considered identical across multiple frames is not significant. It can be said that the data has been acquired.

[0008] The data is read frame by frame, consuming power. The data can be considered identical. By doing so, power consumption can be reduced by eliminating the read operation.

[0009] Therefore, one aspect of the present invention aims to provide an imaging device with low power consumption. To do so. Or, to provide an imaging device that can detect changes in the subject. One of the objectives is to provide a highly reliable imaging device. One of the objectives is to provide a novel imaging device, or the operating method of the above imaging device. One of the objectives is to provide a law. Or, to provide a novel semiconductor device, etc. This will be one of the objectives.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention includes a circuit that compares data between adjacent frames and determines which pixel to read out. This relates to an imaging device.

[0012] One aspect of the present invention is an imaging device having a first circuit and a second circuit in a pixel, the first Circuit 1 has a first node, a second node, and a first switch, and the first node The do has the function of holding first image data generated in the first frame period, and the first The node stores the second image data generated during the nth frame period (where n is a natural number greater than or equal to 2). The second node has the function of calculating the difference between the first image data and the second image data. The first switch has the function of holding certain differential data, and the first switch holds the first image data and the second The second circuit has a function to control the output of the image data, and the second circuit has a comparison circuit and an output circuit. The comparison circuit has a function to determine whether the difference data is within an arbitrarily set voltage range. The output circuit has a first switch that turns off when the differential data is within the voltage range. It outputs a voltage, and when the differential data is not within the voltage range, it outputs a voltage to turn on the first switch. It is an imaging device that has the ability to perform certain actions.

[0013] The first circuit includes a photoelectric conversion device, a first transistor, a second transistor, and 3 transistors, 4 transistors, 5 transistors, 6 transistors The photoelectric conversion device comprises a first capacitor and a second capacitor, and one of the powers of the photoelectric conversion device The pole is electrically connected to either the source or drain of the first transistor, and the first The source or drain of one transistor is connected to the source or drain of the second transistor. On the other hand, the gate of the third transistor, one electrode of the first capacitor and the second capacitor It is electrically connected to one electrode of the capacitor and is the source or drain of the third transistor. One end is electrically connected to either the source or drain of the fourth transistor, and the third The source or drain of the transistor is the other of the source or drain of the fifth transistor. One side of the rain is electrically connected, and the other electrode of the second capacitor is connected to the sixth transistor. It can be configured to be electrically connected to either the source or the drain of the power supply. A transistor can act as a first switch.

[0014] The first circuit further has a seventh transistor, and the source or drain of the seventh transistor One side of the rain is the source or drain of the first transistor, and the other side is the second transistor. It is electrically connected to either the source or drain of the zista, and the source of the seventh transistor. Alternatively, the other end of the drain is the gate of the third transistor, and one electrode of the first capacitor. The configuration may also involve an electrical connection to one electrode of the second capacitor.

[0015] The first to seventh transistors have a metal oxide in the channel formation region. Preferably, the metal oxide is In, Zn, and M (where M is Al, Ti, Ga, Ge, S). It can have one or more of n, Y, Zr, La, Ce, Nd, or Hf. ru.

[0016] The comparison circuit has a first sense amplifier and a second sense amplifier, and the first sense amplifier The first element has a third node, the second sense amplifier has a fourth node, and the output circuit is... The fifth node is located, and the first sense amplifier takes the first input voltage at the lower end of the voltage range. The second sense amplifier has a power section, and the second sense amplifier has a second input section that receives a voltage at the upper end of the voltage range. The first sense amplifier and the second sense amplifier are electrically connected at the second node. Each has a third input section, and the third node and the fourth node are electrically connected to the output circuit. The fifth node is connected to the first switch and can be configured to be electrically connected to the first switch. Cut.

[0017] The third input is electrically connected to the second node of one pixel, and the fifth node is connected to, The first switches of multiple pixels may be electrically connected.

[0018] The second circuit further has an inverter circuit, the inverter circuit, the first sense amplifier, the The transistors in the sense amplifier and output circuit of part 2 have silicon in the channel formation region. It can have.

[0019] Alternatively, the first sense amplifier and the second sense amplifier each control the first power switch It has a first power switch and a second power switch, the first power switch is a p-channel transistor The second power switch has an n-channel transistor, and the n-channel transistor The zista may have a metal oxide in the channel-forming region. The metal oxide is In, Zn and M (where M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or H) It is preferable to have one or more of f) and

[0020] The first circuit and the second circuit may have overlapping regions. Or, multiple circuits may have overlapping regions. Circuit 1 and one second circuit may have overlapping regions.

[0021] Another aspect of the present invention is that in a pixel, a first voltage and a second voltage (first voltage Set the second voltage, acquire the first image data during the first frame period, and then the nth frame The second image data is acquired over a period of (n is a natural number greater than or equal to 2), and the first image data and the second image data are combined. The third voltage, which is the difference in image data, is calculated, and the first voltage, second voltage, and third voltage are then calculated. When comparing, if the third voltage is greater than the first voltage and less than the second voltage, the second voltage is obtained from the pixel. If no data is read, and the third voltage is less than the first voltage, or if the third voltage is less than the second voltage This is a method of operation for an imaging device that reads out second data from a pixel when the voltage is greater than the specified voltage. [Effects of the Invention]

[0022] By using one aspect of the present invention, a low-power imaging device can be provided. This allows us to provide an imaging device that can detect changes in the subject. Or, reliable We can provide highly efficient imaging devices. Or, we can provide novel imaging devices, etc. This can be done. Or, a method for operating the above imaging device can be provided. Or, a novel semi-automatic We can provide conductive devices and the like. [Brief explanation of the drawing]

[0023] [Figure 1]Figure 1 is a diagram illustrating pixels. [Figure 2] Figures 2A and 2B are circuit diagrams illustrating circuit 10. [Figure 3] Figure 3 is a circuit diagram illustrating circuit 11. [Figure 4] Figure 4 is a timing chart illustrating the operation of the pixels. [Figure 5] Figure 5 is a diagram illustrating the operation of circuit 11. [Figure 6] Figure 6 is a timing chart illustrating the operation of the pixels. [Figure 7] Figure 7 is a diagram illustrating the operation of circuit 11. [Figure 8] Figure 8 is a diagram illustrating the operation of circuit 11. [Figure 9] Figure 9 is a timing chart illustrating the operation of the pixels. [Figure 10] Figure 10 is a diagram illustrating the operation of circuit 11. [Figure 11] Figure 11 is a timing chart illustrating the operation of the pixels. [Figure 12] Figure 12 is a diagram illustrating the operation of circuit 11. [Figure 13] Figure 13 is a timing chart illustrating the operation of the pixels. [Figure 14] Figure 14 is a block diagram illustrating the imaging device. [Figure 15] Figures 15A to 15D illustrate the structure of a pixel. [Figure 16] Figure 16 is a block diagram illustrating the structure of a pixel. [Figure 17] Figure 17 is a block diagram illustrating the structure of a pixel. [Figure 18] Figures 18A and 18B are circuit diagrams illustrating circuit 10. [Figure 19] Figures 19A to 19E are circuit diagrams illustrating a part of circuit 10. [Figure 20] Figures 20A and 20B are circuit diagrams illustrating circuit 10. [Figure 21] Figures 21A to 21D illustrate the pixel configuration of the imaging device. [Figure 22] Figures 22A to 22C illustrate the configuration of a photoelectric conversion device. [Figure 23] Figure 23 is a cross-sectional view illustrating a pixel. [Figure 24] Figures 24A to 24C illustrate a Si transistor. [Figure 25] Figure 25 is a cross-sectional view illustrating a pixel. [Figure 26] Figure 26 is a cross-sectional view illustrating a pixel. [Figure 27] Figures 27A to 27D illustrate the OS transistor. [Figure 28] Figure 28 is a cross-sectional view illustrating a pixel. [Figure 29] Figure 29 is a cross-sectional view illustrating a pixel. [Figure 30] Figure 30 is a cross-sectional view illustrating a pixel. [Figure 31] Figures 31A to 31C are perspective views (cross-sectional views) illustrating the pixels. [Figure 32] Figures 32A1 to 32A3 and 32B1 to 32B3 are perspective views of the package and module containing the imaging device. [Figure 33] Figures 33A to 33F are diagrams illustrating electronic devices. [Modes for carrying out the invention]

[0024] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0025] Furthermore, even if it is shown as a single element in the circuit diagram, there may be functional inconveniences. If not, the element may consist of multiple units. For example, a transistor that acts as a switch. Multiple zistas may be connected in series or parallel. Also, the capacitor may be divided In some cases, the elements may be divided and placed in multiple locations.

[0026] Furthermore, when a single conductor has multiple functions such as wiring, electrodes, and terminals. In this specification, multiple names may be used for the same element. Even if the elements are shown to be directly connected in the circuit diagram, in reality The elements may be connected via one or more conductors, as specified herein. This configuration is also included in the category of direct connection.

[0027] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention, will be described with reference to the drawings.

[0028] One aspect of the present invention involves comparing data between frames and performing readout according to the results. It has a function to determine whether or not to read the image. Whether or not to read the image can be controlled on a pixel-by-pixel basis. .

[0029] Each pixel is provided with a first circuit and a second circuit. The first circuit generates imaging data. This allows for the storage of differential data, which is the difference between the initial frame data and the current frame data. The second circuit includes a circuit that compares the difference data with an arbitrarily set voltage range. The second circuit supplies a readout signal to the first circuit according to the comparison result.

[0030] By using this configuration, for example, it can be determined that the differential data is within a set voltage range. If this occurs, the pixel will not be read out. If it is determined that the voltage is not within the voltage range, the pixel will not be read out. It is possible to make cuts.

[0031] Therefore, if data that can be considered identical to the data in the initial frame is obtained, read it out. This operation can be omitted, thereby reducing power consumption. In this case, only the data of the pixels that were read is rewritten based on the data of the initial frame. Then you just need to generate the frame data.

[0032] <Pixel Circuit> Figure 1 is a circuit diagram of a pixel in an imaging device according to one aspect of the present invention. The pixel is connected to circuit 10 and It has circuit 11. Circuit 10 has the function of generating and storing imaging data. Furthermore, the data acquired during the period of the first frame (initial frame) and the nth (where n is 2 or greater) are compared. The system also stores difference data, which is the difference between the data acquired during the period of the frame (target frame). Circuit 11 is a determination circuit that determines the magnitude of the difference data, and Circuit 1 It is possible to determine whether or not to read from 0.

[0033] <Circuit 10> Circuit 10 includes a photoelectric conversion device 101, a transistor 102, a transistor 103, and , transistor 104, transistor 105, transistor 106, transistor It has capacitor 107, capacitor 108, and capacitor 109. Note that capacitor 108 is It can also be omitted.

[0034] One electrode of the photoelectric conversion device 101 is the source or drain of the transistor 102. It is electrically connected to one side. The other side of the source or drain of transistor 102 is connected to the transistor. Either the source or drain of transistor 103, the gate of transistor 104, the capacitor It is electrically connected to one electrode of the terminal 108 and one electrode of the capacitor 109. Either the source or drain of transistor 104 is connected to the source or drain of transistor 105. It is electrically connected to one side of the rain. The other side of the source or drain of transistor 104. It is electrically connected to either the source or drain of transistor 106. The other electrode of transistor 109 is electrically connected to either the source or drain of transistor 107. Connected.

[0035] Furthermore, the gate of transistor 106 is electrically connected to circuit 11 via wiring 242. The other electrode of capacitor 109 is electrically connected to circuit 11 via wiring 241. ru.

[0036] Here, the source or drain of transistor 102, and the other side of transistor 103's source One of the electrodes of transistor 104, the gate of transistor 104, or the drain of capacitor 108. And the point (wiring) where one electrode of capacitor 109 is connected is defined as node FD1. Also, the other electrode of capacitor 109, and one of the source or drain of transistor 107. And the point (wiring) where wiring 241 is connected is designated as node FD2. Node FD1 is each frame It can retain data acquired during the frame period. Node FD2 is the initial frame data Alternatively, it stores differential data, which is the difference between the data of the initial frame and the data of the target frame. It is possible to possess it.

[0037] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 121. The source or drain of terminal 103 is electrically connected to wiring 122. The source or drain of terminal 105 is electrically connected to wiring 125. The source or drain of the zista 106 is electrically connected to the wiring 123. The source or drain of the converter 107 is electrically connected to the wiring 124.

[0038] The gate of transistor 102 is electrically connected to wiring 231. Transistor 103 The gate of transistor 105 is electrically connected to wire 232. The gate of transistor 105 is connected to wire 2 It is electrically connected to 34. The gate of transistor 107 is electrically connected to wiring 233. It will be done. Furthermore, wiring 234 is electrically connected to circuit 11.

[0039] Wires 121 to 124 can function as power lines. For example, wire 12 Line 1 can be a low-potential power line, while wires 122, 123, and 124 can be high-potential power lines. In the configuration shown in Figure 1, the cathode side of the photoelectric conversion device 101 is connected to the transistor 102. Since it is a configuration that connects electrically, the power lines are as described above. On the other hand, as shown in Figure 2A In this configuration, the anode side of the photoelectric conversion device 101 is electrically connected to the transistor 102. This is also acceptable. In this case, wiring 122 is a low-potential power line, and wirings 121, 123, and 124 are A high-voltage power line would suffice.

[0040] Wirings 231 to 234 function as signal lines that control the conduction of each transistor. Wiring 125 can function as an output line, for example, in interlayer double layer A reading circuit having a sampling circuit (CDS circuit), A / D conversion circuit, etc. is electrically connected. Connected.

[0041] Transistor 102 has the function of controlling the potential of node FD1. 3 has the function of resetting the potential of node FD1. Transistor 104 is source It functions as an element of a follower circuit. Transistors 105 and 106 are It has a function to select the output of the pixel. Transistor 107 resets the potential of node FD2. It has the function of setting.

[0042] The transistor in circuit 10 has a metal oxide in the channel formation region. It is preferable to use an OS transistor. The OS transistor has an off-current It has extremely low off-current characteristics. In particular, transistors 102, 103, and 107 have low off-current. It is preferable to use transistors. These transistors are called OS transistors. This makes it possible to hold charge at nodes FD1 and FD2 for an extremely long period of time. This allows for the retrieval of image data with minimal degradation.

[0043] Furthermore, transistors 102 to 107 have silicon in the channel formation region. Si transistors (hereinafter referred to as Si transistors) can also be used. Examples of Si transistors include: Transistors with amorphous silicon, crystalline silicon (microcrystalline silicon, low temperature Examples include transistors made of polysilicon (single-crystal silicon). Stas have high mobility and are suitable for high-speed operation.

[0044] Note that if transistors 102 and 103 are Si transistors, then as shown in Figure 2B. It is preferable to further provide a transistor 111 in this configuration. The Ta111 is an OS transistor.

[0045] Either the source or drain of transistor 111 is connected to the source of transistor 102. The other side of the drain, and electrically with either the source or drain of transistor 103. The source or drain of transistor 111 is connected to transistor 104. The gate, one electrode of capacitor 108, and one electrode of capacitor 109 are electrically connected. It connects to the network.

[0046] The gate of transistor 111 is electrically connected to wire 235. Wire 235 is connected to the transistor It can function as a signal line that controls the conductivity of the inverter 111.

[0047] In the configuration shown in Figure 2B, the other side of the source or drain of transistor 111, transistor 1 The gate of 04, one electrode of capacitor 108, and one electrode of capacitor 109 are in contact. The point (wiring) to which it is connected becomes node FD1.

[0048] Because transistor 111 is an OS transistor with a low off-current, node FD1 and The charge retention function of node FD2 can be enhanced. Also, the photoelectric conversion device 101 Because it can be used as an embedded photodiode formed on a silicon substrate, it has low noise. It is possible to form a pixel circuit without pixels.

[0049] <Circuit 11> Figure 3 shows the circuit diagram of circuit 11. Circuit 11 is a comparator circuit consisting of a sense amplifier 11A and It has a sense amplifier 11B. It also has an output circuit 11C. It also has a sense amplifier 11 Some of the signal lines connected to A, 11B and output circuit 11C are inverters 171 and 172 The connections are as follows. For details on the connections of each element constituting circuit 11, please refer to Figure 3. I will omit the explanation.

[0050] The sense amplifier 11A has a power switch (transistor) that connects to the high-potential power line (wiring 127). Inverter latch circuit (transistors 141, 142, 143, 131, 133) 144) is electrically connected, and the inverter latch circuit is connected to transistor 145 and transistor 145. Power switch (transistor) connected to low-voltage power line (wiring 128) via Zistor 146 It has a configuration that electrically connects to (135, 137).

[0051] The gate of transistor 145 is electrically connected to node FD2 of circuit 10 via wiring 241. The gate of transistor 146 is electrically connected to wire 238. Wiring 2 38 is wiring that supplies a constant potential determined by its purpose.

[0052] Furthermore, transistor 147 is electrically connected to node LATNB of the inverter latch circuit. Transistor 148 is then electrically connected to node LATN. 7 has the function of pre-charging node LATNB to the potential of wiring 129. Transis TA148 has the function of pre-charging node LATN to the potential of wiring 129. The potential of 129 should be, for example, approximately midway between the potential of wiring 127 and the potential of wiring 128. It is possible.

[0053] The sense amplifier 11B connects to a power switch (transistor) that is connected to a high-potential power line (wiring 127). Inverter latch circuit (transistors 151, 152, 153, 134) 154) is electrically connected, and the inverter latch circuit is connected to transistor 155 and transistor 155. Power switch (transistor) connected to low-voltage power line (wiring 128) via Zistor 156 It has a configuration that electrically connects to (136, 138).

[0054] The gate of transistor 155 is electrically connected to node FD2 of circuit 10 via wiring 241. The gate of transistor 156 is electrically connected to wire 239. Wiring 2 39 is wiring that supplies a constant potential determined by its purpose.

[0055] Furthermore, transistor 157 is electrically connected to node LATPB of the inverter latch circuit. Transistor 158 is then electrically connected to node LATP. 7 has the function of pre-charging node LATPB to the potential of wiring 129. Transition Station 158 has the function of pre-charging node LATP to the potential of wiring 129.

[0056] The output circuit 11C is a power switch (transistor) connected to a high-potential power line (wiring 127). 161, 162), Power switch (transistor) connected to low-voltage power line (wiring 128) It has transistors 167, 168), and transistors 163, 164, 165, 166, 169. Each transistor is electrically connected to the output node PCTR.

[0057] Additionally, the gates of transistors 164 and 165 are electrically connected to node LATN. The gates of transistors 163 and 166 are electrically connected to node LATPB. The gate of inverter 169 is electrically connected to wiring 236 via inverter 172. The output node PCTR is connected to the transistor 106 of circuit 10 via wiring 242. It is electrically connected to the .

[0058] Wires 236, 234, and 237 are electrically connected to circuit 11. , 237 is a signal line used to control the conduction of the transistor.

[0059] When a high potential ("H") is supplied to wiring 236, the potential of node PCTR is forced to a high potential. This results in (H), and transistor 106 of circuit 10 becomes conductive. In other words, circuit 10 has One of the two selectable transistors, transistor 106, is forced to conduct electricity. It is possible.

[0060] Wiring 236 is electrically connected to the gates of transistors 131, 131, and 161. Yes, it is possible. Also, wiring 236 is connected to transistors 135 and 136 via inverter 172. It can be electrically connected to gates 167 and 169.

[0061] Wiring 234 is connected to the gates of transistors 133, 134, and 162 via inverter 171. It can be electrically connected to the transistors. Also, wiring 234 is connected to transistors 137 and 138. It can be electrically connected to the 168 gates. Low potential ("L") is supplied to wiring 236. When power is supplied and a high potential ("H") is supplied to wiring 234, each power switch is turned ON. It can be done this way.

[0062] Wiring 237 is electrically connected to the gates of transistors 147, 148, 157, and 158. This is possible. When a high potential ("H") is supplied to the wiring 237, transistor 147, Nodes 148, 157, and 158 are conductive, and nodes LATNB, LATN, and LATP are connected. B. Node LATP can be precharged.

[0063] Circuit 11 is a p-channel type transistor (transistors 131, 132, 133, 134 It also has 141, 143, 151, 153, 161, 162, 164, and 169. n-channel transistors (transistors 135, 136, 137, 138, 142, 144, 145, 146, 147, 148, 152, 154, 155, 156, 157, It has 158, 165, 166, 167, and 168.

[0064] It is preferable to use Si transistors for these transistors. Alternatively, n OS transistors may be used as channel transistors. In particular, when configuring a power switch... By using OS transistors for transistors 135, 136, 137, and 138, This reduces unnecessary leakage current between power lines during operation, thereby lowering power consumption. It is possible.

[0065] <Operation of circuits 10 and 11> Next, the operation of circuits 10 and 11 will be described. The operation involves the imaging motion of the initial frame. The operations include image capture and readout, normal imaging, differential calculation, and judgment, which will be explained in order. In the following explanation, the high-potential signal that causes the n-channel transistor to conduct and A high-potential signal that makes a p-channel transistor non-conductive is called "H", and an n-channel transistor... Low-voltage signals that de-conduct a transistor and low-voltage signals that conduct a p-channel transistor This is represented by "L".

[0066] Furthermore, in circuit 11, potential VN is supplied to wiring 238 and potential VP is supplied to wiring 239. Let's assume that the voltage VN is the lower end of the voltage range used for determination, and the voltage VP is the upper end. This is the voltage. The voltage range assumes that the data in the initial frame and the data in the target frame are the same. This corresponds to the range.

[0067] <Initial frame imaging operation> Figure 4 illustrates the initial frame acquisition operation (period T1) and readout operation (period T2). This is a timing chart. Note that [0] through [n] (where n is a natural number) in the diagram represent row numbers. Furthermore, the following explanation will only cover row number [0].

[0068] During period T1, the potential of wiring 231 is set to "H", the potential of wiring 232 is set to "H", and wiring 233 The potential of wire 236 is "H", the potential of wire 237 is "L", and the potential of wire 234[ If the potential at [0:n] is "L", then in circuit 10, transistors 102, 103, 1 07 conducts, and the potential of the cathode and node FD1 of the photoelectric conversion device 101 is connected to wiring 12 The potential of node FD2 is reset to "VRES1". Also, the potential of wiring 124 is reset. The position is reset to "VRES2".

[0069] Next, assuming the potential of wiring 231 is "L", the cathode will change according to the operation of the photoelectric conversion device 101. Charge accumulates in the cord. Also, the potential of wiring 232 is set to "L", and transistor 103 is not The potential of node FD1 is maintained at "VRES1" as a continuity.

[0070] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the photoelectric conversion device 1 The charge accumulated in the cathode of 01 is transferred to node FD1. At this time, node FD1 The potential decreases by an amount corresponding to the amount of charge transferred ("Vref"), and "VRES1- It becomes "Vref". At this time, node FD2 is supplied with "VRES2". do.

[0071] Next, the potential of wiring 231 is set to "L" and the potential of wiring 233 is set to "L", and transistor 102 By making 107 non-conductive, the potential of node FD1 is maintained at "VRES1-Vref". Furthermore, the potential of node FD2 is maintained at “VRES2”. Here, “VRES2” is the initial It can also be said that this is a value that replaces the data of the initial frame. The above describes the imaging operation of the initial frame. This is an explanation.

[0072] <Initial frame reading operation>

[0073] During period T2, the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", and wiring 233 The potential of wire 236 is "L", the potential of wire 237 is "L", and the potential of wire 234[ If the potential at [0:n] is "L", then in circuit 11, as shown in Figure 5, the power switch All of these are turned off, and transistor 169 becomes conductive. Therefore, the output node PCTR The potential becomes "H", and in circuit 10, transistor 106 conducts, and transistor The potential of wiring 123 (power supply potential) is supplied to the other side of the source or drain of 104. Oh, in the diagram, the circles indicate that the transistor is conducting, and the crosses indicate that the transistor is not conducting.

[0074] Next, if the potential of wiring 234[0] is set to "H", transistor 105 will conduct, and the node Data corresponding to the potential of FD1 is output to wiring 125. This completes the reading of the initial frame. This is an explanation of the operation. The data read here is stored, for example, in frame memory. It is possible.

[0075] <Normal imaging operation and differential calculation operation> Figure 6 shows the normal imaging operation and difference following the initial frame readout operation (period T2 in Figure 4). This section explains the minute calculation operation (period T3), the difference determination operation, and the read operation (period T4). This is a ming chart.

[0076] During period T3, the potential of wiring 231 is set to "H", the potential of wiring 232 is set to "H", and wiring 233 The potential of wire 236 is "L", the potential of wire 237 is "L", and the potential of wire 234[ If the potential at [0:n] is set to "L", transistors 102 and 103 conduct, and the photoelectric conversion device The potential of the cathode and node FD1 of chair 101 matches the potential "VRES1" of wiring 122. It will be set.

[0077] At this time, node FD2 is in a floating state, so capacitive coupling of capacitor 109 occurs. As a result, the change in the potential of node FD1 is added to the potential of node FD2. Node FD1 Since the change in potential is "+Vref", the potential of node FD2 is "VRES2 It becomes "+Vref".

[0078] Next, assuming the potential of wiring 231 is "L", the cathode will change according to the operation of the photoelectric conversion device 101. Charge accumulates in the cord. Also, the potential of wiring 232 is set to "L", and transistor 103 is not The potential of node FD1 is maintained at "VRES1" as a continuity.

[0079] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the photoelectric conversion device 1 The charge accumulated in the cathode of 01 is transferred to node FD1. At this time, node FD1 The potential decreases by a potential ("Vtar1") corresponding to the amount of charge transferred, and "VRES1- Vtar1” is achieved. Also, due to the capacitive coupling of capacitor 109, the potential of node FD1 The change is added to the potential of node FD2. The change in the potential of node FD1 is "-Vta Since r1, the potential of node FD2 is "VRES2+Vref-Vtar1" Yes.

[0080] Next, the potential of wiring 231 is set to "L", and transistor 102 is made non-conductive, and node FD The potential of node 1 is maintained at “VRES1-Vtar1”. Also, the potential of node FD2 is set to “VR Stored in "ES2+Vref-Vtar1".

[0081] The above describes the normal imaging operation and the difference calculation operation. As a result of the normal imaging operation, node F D1 will hold "VRES1-Vtar1". Also, as a result of the difference calculation operation The node FD2 will hold “VRES2+Vref-Vtar1”. “VRES2” Vref is the reset potential, but it can be considered as 0. Therefore, "+Vref-Vta r1" is the difference between the initial frame data and the data acquired during normal imaging. ru.

[0082] <Difference detection operation, read operation (no difference exceeded)>

[0083] During period T4, the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", and wiring 233 The potential of wire 236 is set to "L", the potential of wire 237 is set to "H", and the potential of wire 234[ If the potential at [0:n] is "L", then in circuit 11, as shown in Figure 7, the transistor 147, 148, 157, 158 are conductive, node LATNB, node LATN, node The LATPB and node LATP are precharged to the potential of wiring 129.

[0084] Next, if we set the potential of wiring 237 to "L" and the potential of wiring 234[0] to "H", then as shown in Figure 8. As a result, all power switches are turned on, and current begins to flow to the sense amplifier. Here, the gates of transistor 145 and transistor 155 have node F. The potential "VRES2+Vref-Vtar1" is supplied to D2, and the potential "V "N" is supplied, and potential "VP" is supplied to wiring 239.

[0085] At this time, as shown in Figure 6, “VN” < “VRES2 + Vref - Vtar1” < “V If it is P'', then the channel resistance of transistor 145 is equal to the channel resistance of transistor 146. Because it is lower than the precharge potential of node LATNB, the precharge potential of node LATNB is lower than the precharge potential of node LATNB. It decreases preferentially over the potential. Therefore, transistors 142 and 143 conduct, and the wiring Power voltage is supplied from 127 and 128 to the potentials of nodes LATNB and LATNB. This is confirmed.

[0086] Furthermore, the channel resistance of transistor 156 is lower than that of transistor 155. Therefore, the precharge potential of node LATP decreases preferentially over that of node LATPB. Therefore, transistors 151 and 154 conduct, and the power supply voltage is received from wiring 127 and 128. The supply of the current determines the potentials of node LATP and node LATPB.

[0087] At this time, the potential at node LATN is "H" and the potential at node LATPB is "H". Transistors 165 and 166 become conductive, while transistors 163 and 164 become non-conductive. The potential of the output node PCTR becomes "L". Therefore, in circuit 10, transistor 1 Since 06 does not conduct, power is not supplied to transistor 104, and therefore transistor 105 Even if continuity is established, the data from node FD1 is not output to wire 125. In other words, “VN” < “V If RES2 + Vref - Vtar1" < "VP", then data will be output from circuit 10. It will cease to exist.

[0088] Here, the bias transistor (not shown) of the source follower is connected to wiring 125. Therefore, if transistor 104 does not output data, the potential of wiring 125 will be 0V. This is what happens. When reading data, a steady current flows through the bias transistor. Therefore, by not performing the read operation, the power consumption for that steady-state current can be reduced.

[0089] <Difference detection operation, read operation (with positive difference exceeding the limit)> Using the timing chart in Figure 9, when the difference exceeds the set voltage range, Let's explain the process. Note that period T5 involves the same normal imaging and difference calculation operations as period T3. Therefore, the explanation will be omitted. However, the potential of node FD1 due to normal imaging operation is "VRE S1-Vtar2” (Vtar1>Vtar2), and the potential of node FD2 is “VR ES1+Vref-Vtar2" and "VP"<"VRES1+Vref-Vtar Let's set it to 2".

[0090] During period T6, the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", and wiring 233 The potential of wire 236 is set to "L", the potential of wire 237 is set to "H", and the potential of wire 234[ If the potential at [0:n] is "L", then in circuit 11, as shown in Figure 7, the transistor 147, 148, 157, 158 are conductive, node LATNB, node LATN, node The LATPB and node LATP are precharged to the potential of wiring 129.

[0091] Next, if we set the potential of wiring 237 to "L" and the potential of wiring 234[0] to "H", then in Figure 10... As shown, all power switches are turned on, and current begins to flow to the sense amplifier. Here, the gates of transistor 145 and transistor 155 have nodes. The potential "VRES2+Vref-Vtar2" is supplied to FD2, and the potential " "VN" is supplied, and potential "VP" is supplied to wiring 239.

[0092] At this time, as shown in Figure 9, “VN” < “VP” < “VRES2 + Vref - Vtar If it's 2", then the channel resistance of transistor 145 is equal to the channel resistance of transistor 146. Because it is lower than the precharge potential of node LATNB, the precharge potential of node LATNB is lower than the precharge potential of node LATNB. It decreases preferentially over the potential. Therefore, transistors 142 and 143 conduct, and the wiring Power voltage is supplied from 127 and 128 to the potentials of nodes LATNB and LATNB. This is confirmed.

[0093] Furthermore, the channel resistance of transistor 155 is lower than that of transistor 156. Therefore, the precharge potential of node LATPB decreases preferentially over that of node LATP. Therefore, transistors 152 and 153 conduct, and the power supply voltage is received from wiring 127 and 128. The supply of the current determines the potentials of node LATPB and node LATP.

[0094] At this time, the potential of node LATN is "H" and the potential of node LATPB is "L". Transistors 163 and 165 become conductive, while transistors 164 and 166 become non-conductive. The potential of the output node PCTR becomes "H". Therefore, in circuit 10, transistor 1 06 conducts, and power is supplied to transistor 104, so transistor 105 conducts This outputs the data from node FD1 to wiring 125. In other words, “VN” < “VP” <If it is “VRES2+Vref-Vtar2”, then data will be output from circuit 10. It will become that.

[0095] The data output from circuit 10 is a frame memo containing the image data of the initial frame. In the case of the circuit 10, it is stored at the address corresponding to the circuit 10. In other words, the retrieved circuit Only the data at address 10 is rewritten. This operation allows all circuits Compared to rewriting 10 pieces of data, the power consumption for writing can be reduced.

[0096] Even when no read operation is performed, the A / D conversion circuit can handle 0V analog data. Digital data is generated. When such digital data is generated, the frame The solution is to implement a control mechanism that prevents writing operations to the mori.

[0097] <Difference detection operation, read operation (with negative difference exceeding the limit)> Using the timing chart in Figure 11, the difference exceeds the set voltage range. Let's explain the case. Note that period T7 will perform the same normal imaging and difference calculation operations as period T3. Therefore, the explanation will be omitted. However, the potential of node FD1 due to normal imaging operation is "VR ES1-Vtar3”(“Vtar3”>”Vtar1”), and the potential of node FD2. This is "VRES1+Vref-Vtar3" and "VRES1+Vref-Vtar Let 3" < "VN" < "VP".

[0098] During period T8, the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", and wiring 233 The potential of wire 236 is set to "L", the potential of wire 237 is set to "H", and the potential of wire 234[ If the potential at [0:n] is "L", then in circuit 11, as shown in Figure 7, the transistor 147, 148, 157, 158 are conductive, node LATNB, node LATN, node The LATPB and node LATP are precharged to the potential of wiring 129.

[0099] Next, if we set the potential of wiring 237 to "L" and the potential of wiring 234[0] to "H", then in Figure 12... As shown, all power switches are turned on, and current begins to flow to the sense amplifier. Here, the gates of transistor 145 and transistor 155 have nodes. The potential "VRES2+Vref-Vtar3" is supplied to FD2, and the potential " "VN" is supplied, and potential "VP" is supplied to wiring 239.

[0100] At this time, as shown in Figure 11, “VRES2+Vref-Vtar3”<“VN”<“ If it is VP, the channel resistance of transistor 146 is equal to the channel resistance of transistor 145. Because it is lower than the resistor, the precharge potential of node LATN is lower than the precharge potential of node LATNB. It decreases preferentially over the current potential. Therefore, transistors 141 and 144 conduct, and Power voltage is supplied from lines 127 and 128 to nodes LATN and LATNB. The rankings are determined.

[0101] Furthermore, the channel resistance of transistor 154 is lower than that of transistor 155. Therefore, the precharge potential of node LATP decreases preferentially over that of node LATPB. Therefore, transistors 151 and 154 conduct, and the power supply voltage is received from wiring 127 and 128. The supply of the current determines the potentials of node LATP and node LATPB.

[0102] At this time, the potential of node LATN is "L" and the potential of node LATPB is "H". Transistor 164 conducts, while transistors 163 and 165 do not conduct, resulting in no output. The potential of the 106 transistor is "H". Therefore, in circuit 10, transistor 106 leads As power is supplied to transistor 104, the conduction of transistor 105 occurs. The data from node FD1 is output to wiring 125. In other words, "VRES2 + Vref-V If tar3<VN<VP, then data will be output from circuit 10. .

[0103] As explained above, the output of circuit 10 can be controlled by the operation of circuit 11. Furthermore, the longer the time passes, the greater the discrepancy between the data in the initial frame and the data in the target frame. Therefore, the initial frame data should be updated at regular intervals or after a certain number of frames. This is preferable. Alternatively, the initial frame data may be updated every other frame.

[0104] Furthermore, the timing charts in Figures 4, 6, 9, and 11 show the operation of circuit 10 shown in Figure 1. However, in the case of the configuration shown in Figure 2B, the potential supply operation of wiring 235 is added as shown in Figure 13. That's all you need to do. Note that Figure 13 shows the imaging operation of the initial frame (period T1), but normally The same applies to imaging operations (such as the T3 period).

[0105] <Configuration of the imaging device> Figure 14 is a block diagram illustrating an imaging device according to one embodiment of the present invention. This imaging device is a multi-axis imaging device. A pixel array 21 having pixels (circuits 10 and 11) arranged in a trix pattern, and A circuit 22 (low driver) that has the function of selecting a row of the element array 21, and a circuit 10 It has a circuit 23 that has a function to read data and a circuit 28 that supplies power potential. In Figure 14, the number of wires connecting each element is simplified. Also, circuits 22 and 23 , 28 may be multiple.

[0106] Circuit 23 is a circuit for performing correlated double sampling on the output data of circuit 10. Circuit 24 (CDS circuit) and the conversion of analog data output from circuit 24 to digital data. A circuit 25 (such as an A / D conversion circuit) has the function of performing the following, and a function to select the column to output the data to. Circuits 10 and 23 can have a circuit 26 (column driver) and the like. They are electrically connected via wiring 125.

[0107] In Figure 14, the circuit 10 and circuit 11 are shown overlapping. Although details will be described later, by using a stack structure for circuit 10 and circuit 11, the pixel area can be reduced and the resolution can be increased. Also, by forming circuit 11 with Si transistors and forming circuit 10 with OS transistors thereon, a stack structure can be formed without performing processes such as bonding.

[0108] Note that it is not limited to a configuration where one circuit 10 and one circuit 11 overlap. For example, as shown in FIG. 15A, a configuration where two circuits 10 arranged in the horizontal direction (the direction in which the gate line extends) overlap one circuit 11 may be used. Or, as shown in FIG. 15B, a configuration where two circuits 10 arranged in the vertical direction (the direction in which the source line extends) overlap one circuit 11 may be used. Also, as shown in FIG. 15C, a configuration where 2×2 circuits 10 arranged in the horizontal and vertical directions overlap one circuit 11 may be used. Or, as shown in FIG. 15D, a configuration where 3×3 circuits 10 arranged in the horizontal and vertical directions overlap one circuit 11 may be used. Or, the number of circuits 10 overlapping one circuit 11 may be more than 3×3.

[0109] In this way, in a configuration where a plurality of circuits 10 are connected to one circuit 11, the differential data of any one of the circuits 10 may be obtained, and other circuits 10 may perform the same operation according to the determination. An example of this will be described below.

[0110] FIG. 16 is a diagram for explaining the connection form of 3×3 circuits 10 (circuits 10[0,0] to [2,2]) and one circuit 11. Since the three signal lines (wiring 231, 232, 233) in each row are electrically connected, in the 3×3 circuits 10, the read operation ​​​​​​​​Other operations are performed simultaneously. The selection signal lines for each row (wiring 234[0:2]) are OR circuits. It is electrically connected to circuit 11 via 112. Therefore, depending on the selection operation of each row, The road 11 can be operated.

[0111] Here, node FD2 of any one of the circuits 10 is electrically connected to circuit 11. Figure 16 shows an example where node FD2 of circuit 10[0,1] is connected to circuit 11. However, it may be connected to node FD2 of other circuits 10. Also, the output node of circuit 11 The PCTR is electrically connected to all circuits 10. Therefore, one circuit 10 Depending on the value of FD2, it is determined whether or not to read out all circuits 10. In this configuration, the number of circuits 11 can be reduced, thus reducing the sense amplifiers that circuits 11 possess. This can reduce the power required for precharging.

[0112] Figure 17 shows the configuration of Figure 16 with the addition of transistor 113 and the omission of the OR circuit 112. Yes, transistor 113 is provided between the output node PCTR of circuit 11 and the wiring 242. In the configuration shown in Figure 17, node FD2 of circuit 10 and circuit 11 are the first row to be read. Connect the following. The gate of transistor 113 is connected to the wiring 234 that connects to the circuit 10 in that row. Connected.

[0113] In the first row reading operation, the potential of the output node PCTR is determined in circuit 11, The transistor 113 conducts and outputs to each circuit 10. When reading the next line, the transistor Since terminal 113 becomes non-conductive, the potential of wiring 242 is maintained. Therefore, all times The same operation (read or not read) can be performed on path 10.

[0114] In this configuration, the power generated at the output node PCTR of circuit 11 by the selection operation of the first row The position can be maintained. Therefore, the potential of the output node PCTR in the selection operation of other rows. Since it is not necessary to generate [something], the number of operations of circuit 11 can be reduced, and power consumption can be reduced. It can be made to happen.

[0115] In one embodiment of the present invention, as illustrated in Figure 18A, a back gate is provided for the transistor. This configuration may also be provided. In Figure 18A, the back gate is electrically connected to the front gate. This configuration is shown and has the effect of increasing the on-current. Alternatively, as shown in Figure 18B A configuration may be used in which a constant potential can be supplied to the back gate. In this configuration, the transistor The threshold voltage can be controlled. Also, Figures 18A and 18B can be mixed within a single circuit. It may be present. Also, transistors without back gates may be provided. .

[0116] In addition, in circuit 10, transistor 10 is connected in series with wiring 123 and wiring 125. The order of 4, 105, and 106 is as shown in Figure 1, or in the configurations shown in Figures 19A to 19E. That's fine.

[0117] Furthermore, in the configuration of circuit 10 shown in Figure 2B, as shown in Figure 20A, transistor 1 Connect either the source or drain of transistor 03 to the other source or drain of transistor 111. , electrically connected to one electrode of capacitor 108 and the gate of transistor 104 This is also fine. Also, as shown in Figure 20B, the gate of transistor 102 and transistor 1 The 11 gates may be electrically connected to the wiring 231, and the wiring 235 may be omitted.

[0118] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0119] (Embodiment 2) In this embodiment, a structural example of an imaging device according to an aspect of the present invention will be described.

[0120] <Structural example> FIG. 21A is a diagram showing an example of the structure of a pixel of an imaging device, and the layers 561 and 563 can be stacked. It can be a layer structure.

[0121] The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can have a layer 565a and a layer 565b as shown in FIG. 22A. In some cases, the layer may be rephrased as a region. As shown in FIG. 22A, the photoelectric conversion device 101 is a pn junction type photodiode. For example, a p-type semiconductor can be used for the layer 565a and an n-type semiconductor for the layer 565b. Alternatively, an n-type semiconductor can be used for the layer 565a and a p-type semiconductor for the layer 565b. It may be rephrased as a region.

[0122] The pn junction type photodiode shown in FIG. 22A is typically formed using single crystal silicon. It can be formed using a p-type semiconductor for the layer 565a and an n-type semiconductor for the layer 565b. Or, an n-type semiconductor can be used for the layer 565a and a p-type semiconductor for the layer 565b. It may be used.

[0123] The above pn junction type photodiode can typically be formed using single crystal silicon. It can be done.

[0124] Also, the photoelectric conversion device 101 included in the layer 561 may be a stack of a layer 566a, a layer 566b, a layer 566c, and a layer 566d as shown in FIG. 22B. The photoelectric conversion device 101 shown in FIG. 22B is an example of an avalanche photodiode. The layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to the photoelectric conversion part. As shown in FIG. 22B, it may be a stack of a layer 566a, a layer 566b, a layer 566c, and a layer 566d. The photoelectric conversion device 101 shown in FIG. 22B is an example of an avalanche photodiode. The layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to the photoelectric conversion part. The photoelectric conversion device 101 shown in FIG. 22B is an example of an avalanche photodiode. The layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to the photoelectric conversion part. The layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to the photoelectric conversion part.

[0125] Layer 566a is preferably a low-resistance metal layer. For example, aluminum, titanium Tungsten, tantalum, silver, or alloys thereof can be used.

[0126] It is preferable to use a conductive layer with high light transmittance to visible light for layer 566d. For example, Indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc Oxides, indium-gallium-zinc oxide, or graphene can be used. It is also possible to omit layer 566d.

[0127] The photoelectric conversion layers 566b and 566c are pn junctions, for example, using a selenium-based material as the photoelectric conversion layer. This can be configured as a p-type photodiode. Layer 566b is a p-type semiconductor such as selenium. Using a system material, layer 566c can be made of an n-type semiconductor such as gallium oxide. preferable.

[0128] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the incident light is The amplification of electrons in relation to the amount of light can be greatly increased. Also, selenium-based materials have a light absorption coefficient. Due to its high viscosity, it offers production advantages such as the ability to fabricate the photoelectric conversion layer as a thin film. Selenium-based material These thin films can be formed using methods such as vacuum deposition or sputtering.

[0129] Selenium-based materials include crystalline selenium such as single-crystal selenium and polycrystalline selenium, and amorphous selenium. Compounds of selenium, copper, indium, and selenium (CIS), or copper, indium, and gallium A selenium compound (CIGS), for example, can be used.

[0130] n-type semiconductors are formed from materials that have a wide band gap and are transparent to visible light. This is preferable. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, Alternatively, oxides containing a mixture of these materials can be used. Furthermore, these materials can be used for hole implantation. It also functions as a blocking layer, which can reduce dark current.

[0131] Furthermore, the photoelectric conversion device 101 in layer 561 is located in layer 567a, as shown in Figure 22C. Alternatively, the layers 567b, 567c, 567d, and 567e may be stacked. (Figure) The photoelectric conversion device 101 shown in 22C is an example of an organic photoconductive film, and layer 567a is the lower part The electrode, layer 567e is a light-transmitting upper electrode, and layers 567b, 567c, and 567d are light-transmitting. This corresponds to the power conversion unit.

[0132] In the photoelectric conversion section, one of layers 567b and 567d is a hole transport layer, and the other is an electron transport layer. This is possible. Furthermore, layer 567c can be a photoelectric conversion layer.

[0133] For the hole transport layer, for example, molybdenum oxide can be used. For example, C 60 , C 70 Use fullerenes such as, or their derivatives. It is possible.

[0134] The photoelectric conversion layer is a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction). The structure can be used.

[0135] As shown in Figure 21A, layer 563 can be, for example, a silicon substrate. The circuit board has Si transistors, etc. Using these Si transistors, the pixel circuit It can be formed. Also, a circuit that drives the pixel circuit, a readout circuit for the pixel circuit, It can be used to form image processing circuits, neural networks, communication circuits, and the like.

[0136] Also, DRAM (Dynamic Random Access Memory), etc. Memory circuit, CPU (Central Processing Unit), MCU (Mi A cross Controller Unit (cro) and the like may be formed. Now, let's consider the circuits 10 and 11 described in Embodiment 1 as pixel circuits, and the other circuits as described above. It's called a functional circuit.

[0137] For example, circuits 10, 11 and functional circuits (circuits 22, 23, 28, etc.) have a traction In the inverter, some or all of it can be provided in layer 563.

[0138] Furthermore, layer 563 may be a stack of multiple layers, as shown in Figure 21B. Although three layers, 563a, 563b, and 563c, are shown as an example, two layers may also be used. The layer 563 may be a lamination of four or more layers. These layers are, for example, formed in a bonding process. They can be stacked using such a method. With this configuration, the pixel circuit and functional circuit can be stacked multiple Because the pixels and functional circuits can be distributed in layers and stacked on top of each other, a compact and highly functional camera can be created. An imaging device can be fabricated.

[0139] Furthermore, the pixels have a stacked structure of layers 561, 562, and 563, as shown in Figure 21C. It's okay to do so.

[0140] Layer 562 may have OS transistors. For example, circuit 10 can be formed in layer 562. This allows circuit 11 to be formed in layer 563. Furthermore, one or more of the aforementioned functional circuits can be formed. It may be formed with an OS transistor. Alternatively, the Si transistor and layer 563 may be formed. One or more functional circuits may be formed using the OS transistors of 562. Layer 563 is a support substrate such as a glass substrate, and the OS transistors in layer 562 divide the image. Elementary circuits and functional circuits may be formed.

[0141] For example, using OS transistors and Si transistors, a normally-off CPU (" It is possible to implement what is also called "Noff-CPU". Note that Noff-CPU refers to... Normally-off type, which remains in a non-conducting state (also called the off state) even when the gate voltage is 0V. It is an integrated circuit that includes transistors.

[0142] The Noff-CPU stops supplying power to circuits within the Noff-CPU that are not in operation, The circuit can be put into standby mode. When the power supply is cut off and the circuit enters standby mode, No power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU retains information necessary for operation, such as settings, even when the power supply is cut off. The information can be retained for a long period of time. Returning from standby mode requires resuming power supply to the circuit. It only requires a simple operation, and there is no need to rewrite settings or conditions. In other words, it is fast from standby mode. Recovery is possible. In this way, the Noff-CPU can operate without significantly reducing its speed. Power consumption can be reduced.

[0143] Furthermore, layer 562 may be a stack of multiple layers, as shown in Figure 21D. Although two layers, layer 562a and layer 562b, are shown as an example, a stack of three or more layers may also be used. These layers can be formed, for example, by stacking them on top of layer 563. Or, layer 5 The layer formed on layer 63 and the layer formed on layer 561 may be bonded together to form the layer.

[0144] For semiconductor materials used in OS transistors, an energy gap of 2 eV or more is preferred. A metal oxide with a voltage of 2.5 eV or higher, more preferably 3 eV or higher, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC, which will be discussed later. -OS or CAC-OS can be used. CAAC-OS forms a crystal. Its atoms are stable, making it suitable for transistors and other applications where reliability is paramount. Furthermore, CAC-OS is... Because it exhibits high mobility characteristics, it is suitable for transistors and other applications that require high-speed operation.

[0145] OS transistors have a large energy gap in the semiconductor layer, so several yA / μm (channels It exhibits extremely low off-current characteristics (current value per 1 μm of channel width). Furthermore, the OS transition... Sta does not experience impact ionization, avalanche breakdown, or short channel effects. These characteristics differ from those of Si transistors, allowing for the formation of highly reliable circuits with high voltage resistance. This is possible. Furthermore, the electrical characteristics caused by the crystalline non-uniformity that is a problem in Si transistors... Variations are less likely to occur with OS transistors.

[0146] The semiconductor layer of an OS transistor is made of, for example, indium, zinc, and M(aluminum). Titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium , one or more selected from metals such as tin, neodymium or hafnium, etc.) including In - It can be a film represented by an M-Zn-based oxide. The In-M-Zn-based oxide, for example For example, the sputtering method, ALD (Atomic layer deposition) Method, or MOCVD (Metal organic chemical vapor deposition) method or the like can be used to form it.

[0147] When forming the In-M-Zn-based oxide by the sputtering method, the atomic ratio of the metal elements of the sputtering target Preferably satisfies In≥M and Zn≥M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In :M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2: 3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn= 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Z n = 10:1:3, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed is respectively plus or minus 40% of the atomic ratio of the metal elements contained in the above-mentioned sputtering target including fluctuations.

[0148] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 / cm 17 or less, preferably 1×10 3 / cm 15 or less, more preferably 1×10 3 / cm 13 or less, still more preferably 1×10 3 / cm 11 or less, even more preferably 1×10 3 / cm 10 or less, further Preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 The above oxide semiconductors A body can be used. Such oxide semiconductors can be made in high purity intrinsic or substantially high purity. This is called an intrinsic oxide semiconductor. This oxide semiconductor has a low defect level density and possesses stable properties. It can be said to be an oxide semiconductor.

[0149] Furthermore, this is not limited to the semiconductor characteristics and electrical characteristics (field effect) of the transistor as needed. A suitable composition should be used depending on the fruit mobility, threshold voltage, etc. To obtain the semiconductor characteristics of a transistor, the carrier density of the semiconductor layer, impurity concentration, and defects are measured. It is preferable to ensure that the density, the atomic ratio of metal elements to oxygen, the interatomic distance, and other parameters are appropriate. stomach.

[0150] In oxide semiconductors that constitute a semiconductor layer, silicon or carbon, which are one of the Group 14 elements, are used. When elements are present, oxygen vacancies increase, leading to n-type formation. Therefore, the semiconductor layer The concentration of lycon or carbon (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0151] Furthermore, alkali metals and alkaline earth metals generate carriers when they bond with oxide semiconductors. This can occur, and the transistor's off-current may increase. Therefore, half Concentration of alkali metals or alkaline earth metals in the conductive layer (by secondary ion mass spectrometry) The concentration obtained is 1 × 10 18 atoms / cm 3The following is preferably 2 × 10 16 a toms / cm 3 Do the following:

[0152] Furthermore, if nitrogen is present in the oxide semiconductor that makes up the semiconductor layer, the electrons, which are carriers, This increases the carrier density and makes it easier to convert to n-type. As a result, nitrogen-containing oxide semi-oxides Transistors using conductors tend to exhibit normally-on characteristics. Therefore, in the semiconductor layer... The nitrogen concentration (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻⁶ 18 atom / cm 3 The following is preferable:

[0153] Furthermore, if hydrogen is present in the oxide semiconductor that makes up the semiconductor layer, the acid will bond with the metal atom. Because it reacts with elements to form water, it can sometimes form oxygen vacancies in oxide semiconductors. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally-on This can be a characteristic. Furthermore, a defect where hydrogen is present in the oxygen deficiency can function as a donor, Sometimes, electrons, which are carriers, are generated. Also, some of the hydrogen combines with metal atoms. It can combine with other elements to generate electrons, which act as carriers. Therefore, it contains a large amount of hydrogen. Transistors using oxide semiconductors tend to exhibit normally-on characteristics.

[0154] Defects where hydrogen fills an oxygen vacancy can function as donors for oxide semiconductors. However, Therefore, it is difficult to quantitatively evaluate the defect. In oxide semiconductors, In some cases, the evaluation is based on the carrier concentration rather than the acid concentration. Therefore, in this specification, etc., acid As a parameter for the ionized semiconductor, we assume a state where no electric field is applied, rather than the donor concentration. In some cases, a carrier concentration may be used. In other words, the "carrier concentration" described in this specification, etc., is This can sometimes be rephrased as "donor concentration."

[0155] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, In oxide semiconductors, secondary ion mass spectrometry (SIMS) is used. The hydrogen concentration obtained by mass spectrometry is 1 × 10⁻⁶ 20 a toms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 ate / c m 3 It shall be less than. Oxide semiconductors in which impurities such as hydrogen have been sufficiently reduced are used in transistors. By using it in the channel formation region, stable electrical properties can be imparted.

[0156] Furthermore, the semiconductor layer may have, for example, a non-single-crystal structure. The non-single-crystal structure may be, for example, oriented along the c-axis. CAAC-OS (C-Axis Aligned Crystallix) has crystals formed by this process. (Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or non It includes a crystalline structure. In non-single crystal structures, the amorphous structure has the highest defect level density, CAA C-OS has the lowest defect level density.

[0157] Amorphous oxide semiconductor films, for example, have a disordered atomic arrangement and do not contain crystalline components. Alternatively, an amorphous oxide film may have a completely amorphous structure and no crystalline parts. stomach.

[0158] Furthermore, the semiconductor layer consists of regions with an amorphous structure, regions with a microcrystalline structure, regions with a polycrystalline structure, and CAAC. - A mixed film having two or more regions from among the OS region and the single-crystal structure region. The film may have a monolayer structure or a multilayer structure, for example, containing two or more of the regions described above. It may have a structure.

[0159] Below, we will discuss CAC (Cloud-Aligned C), which is one form of a non-single-crystal semiconductor layer. This section describes the OS configuration.

[0160] CAC-OS refers to, for example, an oxide semiconductor in which the elements constituting the semiconductor are between 0.5 nm and 10 nm. Below, preferably, a structure of material that is unevenly distributed with a size of 1 nm to 2 nm or near that size. It is formed. Furthermore, in the following, in oxide semiconductors, one or more metal elements are The region containing the metal element is unevenly distributed and is 0.5 nm to 10 nm, preferably 1 nm. A mixture of particles smaller than or equal to 2 nm in size, or near that size, can appear as a mosaic or patch. It is also said that.

[0161] Furthermore, the oxide semiconductor preferably contains at least indium. In particular, indium It is preferable to include zinc. In addition to these, aluminum, gallium, and t Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, ginger Lumanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Contains one or more elements selected from tantalum, tungsten, or magnesium. It's okay if they're born.

[0162] For example, CAC-OS in In-Ga-Zn oxide (among CAC-OS, In-Ga α-Zn oxide may also be specifically referred to as CAC-IGZO. ) is indium oxide (Hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc acid compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) Let's assume that...) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0) . ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Let Z4 be a real number greater than 0. The material separates into parts such as ), resulting in a mosaic pattern. and a mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it was uniformly distributed within the membrane. This configuration (hereinafter also referred to as cloud-based) is as follows.

[0163] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region is the main component and a region is mixed. In this specification, for example, the atomic ratio of In to element M in the first region. However, the first region is greater than the atomic ratio of In to element M in the second region. Assume that the concentration of In is higher in this region compared to region 2.

[0164] Note that IGZO is a common name and refers to a single compound composed of In, Ga, Zn, and O. There are combinations. A typical example is InGaO3(ZnO). m1(m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is any number) Examples of crystalline compounds include those that are produced.

[0165] The above crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is one in which multiple IGZO nanocrystals have c-axis orientation and in the ab-plane. This is a crystal structure in which the elements are linked without orientation.

[0166] On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is In, G In a material composition containing a, Zn, and O, a portion of it is observed to be in the form of nanoparticles mainly composed of Ga. The region where the substance is suspected and the region where it is observed as nanoparticles mainly composed of In are, respectively This refers to a configuration where elements are randomly distributed in a mosaic-like pattern. Therefore, in CAC-OS, Crystal structure is a secondary factor.

[0167] Furthermore, CAC-OS does not include a layered structure of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is included. do not have.

[0168] Note that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary may not be observable between the principal component region and the surrounding area.

[0169] Note that aluminum, yttrium, copper, vanadium, and beryllium can be used instead of gallium. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more species selected from Cium, etc., are included, CAC-OS will be partially The region is observed to be in the form of nanoparticles mainly composed of the metal element, and a part of it is mainly composed of In. The regions observed in the nanoparticle form are randomly dispersed in a mosaic-like manner. say.

[0170] CAC-OS is formed, for example, by sputtering under conditions where the substrate is not intentionally heated. It is possible. Also, when forming CAC-OS by sputtering, the deposition gas and Then, selected from inert gases (typically argon), oxygen gas, and nitrogen gas. You may use one or more of them. Also, the oxygen in relation to the total flow rate of the deposition gas during film formation. A lower gas flow rate ratio is preferable; for example, a flow rate ratio of oxygen gas of 0% or more and less than 30% is preferable. Alternatively, it is preferable to have a value of 0% or more and 10% or less.

[0171] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan method, which is the only Out-of-plane method, It is characterized by the absence of a clear peak. In other words, from X-ray diffraction measurements, It can be seen that no orientation is observed in the ab-plane direction or the c-axis direction of the region.

[0172] Furthermore, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiation, a ring-shaped region of high brightness (phosphorus) A ring region is observed, and multiple bright spots are observed within this ring region. Therefore, the electron diffraction pattern Therefore, the crystal structure of CAC-OS does not have orientation in the planar and cross-sectional directions. It can be seen that it has an nc (nano-crystal) structure.

[0173] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, energy-dispersive X Linear spectroscopy (EDX: Energy Dispersive X-ray spectrometer) GaO X3 The region in which is the main component And, In X2 Zn Y2 O Z2 , or InO X1 Regions where it is the main component are unevenly distributed and mixed. It can be confirmed that it has the following structure.

[0174] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, It has different properties from ZO compounds. In other words, CAC-OS is GaO X3 These are the main components. In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component, and It exhibits phase separation, and has a mosaic-like structure in which regions composed of each element are the main components.

[0175] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y 20 Z2 , or InOX1 The region where [substance] is the main component exhibits conductivity as an oxide semiconductor due to the flow of carriers. Therefore, In X2 Zn Y2 O Z2 or In O X1 When the region where [substance] is the main component is distributed in a cloud shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0176] On the other hand, the region where [substance] such as GaO is the main component is a region with higher insulation compared to the region where In X3 Zn X2 O Y2 or InO Z2 is the main component. That is, when the region where [substance] such as GaO X is the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and a good etching operation can be realized. X3 etc. When the region where [substance] is the main component is distributed in the oxide semiconductor, the leakage current is suppressed and a good etching operation can be realized.

[0177] Therefore, when CAC-OS is used in a semiconductor device, the insulation X3 caused by [substance] such as GaO and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily, enabling the realization of a high on-current (I on ) and a high field-effect mobility (μ).

[0178] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0179] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the insulating layer shown below And elements such as conductive layers are just examples, and other elements may also be included. Or, Some of the elements shown below may be omitted. Also, the laminated structure shown below may be modified as needed. It can then be formed using processes such as bonding and polishing.

[0180] Figure 23 has layers 560, 561, and 563, and layers 563a and 56 This is an example of a cross-sectional view of a laminate having a bonding surface between 3b.

[0181] <layer 563b> Layer 563b has elements of the circuit 11 provided on the silicon substrate 610. Here, As part of the elements of path 11, the transistor 203 and transistors of inverter 172 This shows transistor 204 and transistor 169.

[0182] Layer 563b consists of silicon substrate 610 and insulating layers 611, 612, 613, 614, and 615. , 616, 617, and 618 are provided. Also, a conductive layer 619 is provided. Insulating layer 61 Layer 1 functions as a protective film. Insulating layers 612, 613, 614, 615, 616, 6 17 has the function of an interlayer insulating film and a planarizing film. Insulating layer 618 and conductive layer 6 Layer 19 functions as a bonding layer. The conductive layer 619 is connected to the transistor 169. They are connected by air.

[0183] Examples of protective films include silicon nitride films, silicon oxide films, aluminum oxide films, etc. It can be used. Examples of interlayer insulating films and planarizing films include silicon oxide films. Inorganic insulating films, organic insulating films such as acrylic resins and polyimide resins can be used. The dielectric layers of the capacitor include silicon nitride film, silicon oxide film, and aluminum oxide film. These can be used. The bonding layer will be discussed later.

[0184] Furthermore, it is intended to be used as wiring, electrodes, and plugs for electrical connections between devices. Conductors that can do this include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Nesium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from thium, lanthanum, etc., or alloys containing the above-mentioned metal elements. Alternatively, an alloy or the like, combining the aforementioned metal elements, may be appropriately selected and used. The conductor is It is not limited to a single layer; it may also consist of multiple layers made of different materials.

[0185] <Layer 563a> Layer 563a has elements of circuit 10. Here, as part of the elements of circuit 10, This shows transistor 102 and transistor 106. In the cross-sectional view shown in Figure 23, both The electrical connections are not shown in the diagram.

[0186] Layer 563a contains a silicon substrate 632 and insulating layers 631, 633, 634, 635, and 637. , 638 is provided. Also, conductive layers 636 and 639 are provided.

[0187] The insulating layer 631 and the conductive layer 639 function as bonding layers. Insulating layer 634 ,635 and 637 have the function of an interlayer insulating film and a planarizing film. The insulating layer 633 is The insulating layer 638 has the function of a protective film. The insulating layer 638 connects the silicon substrate 632 and the conductive layer 639. It has an insulating function. The insulating layer 638 can be formed from the same material as other insulating layers. Furthermore, the insulating layer 638 may be formed from the same material as the insulating layer 631.

[0188] The conductive layer 639 is electrically connected to the gate of transistor 106 and the conductive layer 619. Furthermore, the conductive layer 636 is electrically connected to the wiring 121 (see Figure 1).

[0189] The Si transistor shown in Figure 23 is channeled on a silicon substrate (silicon substrates 610, 632) It is a fin-type with a fin-forming region. Cross-section in the channel width direction (shown in layer 563a in Figure 23) The cross-section of A1-A2 is shown in Figure 24A. Note that the Si transistor is as shown in Figure 24B. It can also be a planar type.

[0190] Alternatively, as shown in Figure 24C, a transistor having a silicon thin-film semiconductor layer 545 It may be present. The semiconductor layer 545 is formed, for example, on the insulating layer 546 on the silicon substrate 632. The resulting single-crystal silicon (SOI (Silicon on Insulator)) It is possible.

[0191] <layer 561> Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 is located in layer 563a It can be formed on top. In Figure 23, the photoelectric conversion device 101 is shown in Figure 22C. This shows a configuration in which an organic photoconductive film is used as the photoelectric conversion layer. Note that here, layer 567a is The cathode is at layer 567e, which is the anode.

[0192] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655. ru.

[0193] The insulating layers 651, 653, and 654 function as interlayer insulating films and planarizing films. Furthermore, the insulating layer 654 is provided covering the end of the photoelectric conversion device 101, and layer 567e and layer 5 It also has the function of preventing short circuits with 67a. The insulating layer 652 has the function of an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0194] The layer 567a, which corresponds to the cathode of the photoelectric conversion device 101, has the transistors of layer 563a It is electrically connected to either the source or drain of the zista 102. Photoelectric conversion device 1 The layer 567e, which corresponds to the anode of 01, is connected to the conductive layer 655 of the conductive layer 563a. It is electrically connected to the electrochemical layer 636.

[0195] <layer 560> Layer 560 is formed on layer 561. Layer 560 is formed on light-shielding layer 671 and optical conversion layer 672. It also has a microlens array 673.

[0196] The light-shielding layer 671 can suppress the inflow of light to adjacent pixels. The light-shielding layer 671 has, Metal layers such as aluminum and tungsten can be used. A dielectric film having the function of an anti-radiation film may be laminated.

[0197] A color filter can be used in the optical conversion layer 672. (Red) Colors such as G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to each pixel. By applying this, a color image can be obtained. For example, the perspective view (cross section) of Figure 31A. As shown in (including), color filter 672R (red), color filter 672G (green) The color filter 672B (blue) can be assigned to different pixels.

[0198] Furthermore, by using a wavelength cut filter in the optical conversion layer 672, images in various wavelength ranges can be obtained. This can be used as an imaging device to obtain the desired result.

[0199] For example, if an infrared filter that blocks light with wavelengths below visible light is used in the optical conversion layer 672, It can be used as an infrared imaging device. In addition, the optical conversion layer 672 can emit light with a wavelength less than or equal to near-infrared light. By using a filter that blocks it, it can be made into a far-infrared imaging device. Also, optical conversion layer 6 If an ultraviolet filter that blocks light with wavelengths greater than visible light is used in 72, it can be made into an ultraviolet imaging device. It is possible.

[0200] Furthermore, multiple different optical conversion layers may be arranged within a single imaging device. For example, in Figure 31B As shown, color filter 672R (red), color filter 672G (green), color filter By assigning filter 672B (blue) and infrared filter 672IR to different pixels, This configuration allows for the simultaneous acquisition of visible light and infrared light images. .

[0201] Alternatively, as shown in Figure 31C, use color filter 672R (red), color filter 672 G (green), color filter 672B (blue), and UV filter 672UV are each different. It can be assigned to pixels. In this configuration, visible light images and ultraviolet light images are captured simultaneously. You can gain it.

[0202] Furthermore, if a scintillator is used in the optical conversion layer 672, the radiation used in X-ray imaging devices, etc. It can be used as an imaging device to obtain images that visualize the intensity of radiation. When a ray of light enters a scintillator, the photoluminescence phenomenon causes visible light or violet light to be emitted. It is converted into light (fluorescence), such as ambient light. This light is then detected by the photoelectric conversion device 101. Image data is acquired by doing so. Furthermore, the imaging device with this configuration is attached to a radiation detector or the like. You may use it.

[0203] When a scintillator is irradiated with radiation such as X-rays or gamma rays, it absorbs that energy. It contains substances that emit visible or ultraviolet light. For example, Gd2O2S:Tb, Gd2O 2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, Ba F2, CeF3, LiF, LiI, ZnO, etc., dispersed in a resin or ceramic. You can use it.

[0204] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of I-673 passes through the optical conversion layer 672 directly below it, and the photoelectric conversion device The light will be directed onto chair 101. By providing the microlens array 673, Since the focused light can be injected into the photoelectric conversion device 101, photoelectric conversion can be performed efficiently. This can be done. The microlens array 673 transmits light of the wavelength of the object to be imaged. It is preferable to form it with a highly durable resin or glass.

[0205] <Bonding> Next, we will explain how layer 563b and layer 563a are bonded together.

[0206] Layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 is an insulating layer. It has a region embedded in layer 618. Furthermore, the surfaces of the insulating layer 618 and the conductive layer 619 are They have all been flattened so that their heights are the same.

[0207] Layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 is an insulating layer. It has a region embedded in layer 631. Furthermore, the surfaces of the insulating layer 631 and the conductive layer 639 are They have all been flattened so that their heights are the same.

[0208] Here, it is preferable that the conductive layer 619 and the conductive layer 639 have the same main component metal element. It is preferable that insulating layer 618 and insulating layer 631 are composed of the same components. It seems so.

[0209] For example, conductive layers 619 and 639 may contain Cu, Al, Sn, Zn, W, Ag, Pt, or A u can be used. Due to ease of joining, Cu, Al, W, or Au is used. In addition, the insulating layers 618 and 631 are silicon oxide, silicon oxide nitride, and nitrogen Silicon oxide, silicon nitride, titanium nitride, etc., can be used.

[0210] In other words, the same metal material as described above is used for both the conductive layer 619 and the conductive layer 639. It is preferable that the insulating layer 618 and insulating layer 631 each have the above-mentioned It is preferable to use the same insulating material. With this configuration, layer 563b and layer 563 It is possible to perform bonding with the boundary of a as the joining position.

[0211] Note that the conductive layer 619 and the conductive layer 639 may have a multilayer structure of multiple layers, in which case... The surface layer (joint surface) only needs to be made of the same metal material. Also, insulating layer 618 and insulating layer 6 31 may also be a multilayer structure of multiple layers, in which case the surface layer (joint surface) is made of the same insulating material. Any amount of money is fine.

[0212] This bonding process provides an electrical connection between the conductive layer 619 and the conductive layer 639. It is possible. Furthermore, it is possible to obtain a connection with mechanical strength between the insulating layer 618 and the insulating layer 631. It is possible.

[0213] For joining metal layers, sputtering is used to remove surface oxide films and impurity adsorption layers. Surface activation bonding is a method that involves removing contaminants, cleaning and activating surfaces, and then bringing them into contact to bond them together. It can be used. Alternatively, diffusion bonding methods that use temperature and pressure in combination to join surfaces together can be used. Both can be used. Since bonding occurs at the atomic level in both cases, it is not only electrical but also mechanical. Mechanically superior bonding can also be achieved.

[0214] Furthermore, for bonding the insulating layers, high flatness is achieved by polishing, etc., followed by oxygen plasma, etc. The hydrophilic treated surfaces are brought into contact to create a temporary bond, and then dewatered by heat treatment to create the permanent bond. Aqueous bonding methods can be used. Hydrophilic bonding methods also involve bonding at the atomic level. This allows for mechanically superior bonding.

[0215] When layer 563b and layer 563a are bonded together, the bonding surfaces of each layer contain an insulating layer and a metal layer. Therefore, for example, a combination of surface activation bonding and hydrophilic bonding methods may be used.

[0216] For example, after polishing, the surface is cleaned, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is applied. Methods such as performing a process to join the metal layers can be used. An oxidizing metal may be used, and hydrophilic treatment may be performed. Furthermore, a joining method other than the one described above may be used. That's fine.

[0217] The above bonding process electrically connects the elements of layer 563b and the elements of layer 563a. It can connect to

[0218] <Modified example of laminated structure 1> Figure 25 shows a modified example of the laminated structure shown in Figure 23, and the photoelectric conversion device 1 in layer 561 The configuration of layer 01 and some of the configuration of layer 563a are different, and there is also a layer attached between layer 561 and layer 563a. It has a configuration that includes a mating surface.

[0219] Layer 561 is the photoelectric conversion device 101, insulating layers 661, 662, 664, 665 and conductive It has electrochemical layers 685 and 686.

[0220] The photoelectric conversion device 101 is a pn junction type photodiode formed on a silicon substrate. It has a layer 565b corresponding to the p-type region and a layer 565a corresponding to the n-type region. The power conversion device 101 is an embedded photodiode, and the surface side of layer 565a (current Dark current is suppressed by a thin p-shaped region (part of layer 565b) provided on the extraction side. It can reduce noise.

[0221] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. Layer 62 functions as an interlayer insulating film and planarizing film. The insulating layer 664 is an element isolation layer. It has the function of suppressing carrier outflow. The insulating layer 665 has the function of suppressing carrier outflow.

[0222] The silicon substrate is provided with grooves to separate pixels, and the insulating layer 665 is on the upper surface of the silicon substrate and The insulating layer 665 is provided in the groove, and the photoelectric conversion device 101 This prevents carriers generated in the pixel from flowing out to adjacent pixels. Layer 665 also has the function of suppressing the intrusion of stray light. Therefore, the insulating layer 665 prevents color mixing. This can be suppressed. Furthermore, an anti-reflective film can be filmed between the upper surface of the silicon substrate and the insulating layer 665. It may be provided.

[0223] The device isolation layer is LOCOS (LOCal Oxidation of Silicon). It can be formed using the method. Alternatively, STI (Shallow Trench I It may be formed using methods such as the solation method. The insulating layer 665 may be, for example, an oxidation Inorganic insulating films such as silicon and silicon nitride, and organic insulating films such as polyimide and acrylic are used. It is possible. The insulating layer 665 may also have a multilayer configuration. The element isolation layer It is also possible to configure the system without including this feature.

[0224] Layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is connected to the conductive layer 685. They are electrically connected. Layer 565b (p-type region, corresponding to the anode) is electrically connected to conductive layer 686. They are connected precisely. The conductive layers 685 and 686 have regions embedded in the insulating layer 661. Furthermore, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are such that their heights are the same. It has been flattened.

[0225] In layer 563a, an insulating layer 638 is formed on the insulating layer 637. Also, transient A conductive layer 683 is electrically connected to either the source or drain of the sta 102, and A conductive layer 684 is formed that is electrically connected to the electrolytic layer 636.

[0226] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. 83 and 684 have regions embedded in the insulating layer 638. Also, the insulating layer 638 and the conductor The surfaces of electrode layers 683 and 684 are flattened so that their heights are the same.

[0227] Here, conductive layers 683, 684, 685, and 686 are the same as the conductive layers 619 and 639 mentioned above. It is a laminated layer. Also, insulating layers 638 and 661 are the same as the insulating layers 618 and 63 mentioned above. This is a bonded layer similar to that in 1.

[0228] Therefore, by bonding conductive layer 683 and conductive layer 685, the layers of the photoelectric conversion device are formed. 565a (n-type region, corresponding to the cathode) and the source or drain of transistor 102 One end can be electrically connected. Also, conductive layer 684 and conductive layer 686 are bonded together. By doing so, the photoelectric conversion device's layer 565b (p-type region, corresponding to the anode) and wiring 121( (See Figure 1) can be electrically connected. Also, insulating layer 638 and insulating layer 661 are attached. By combining them, electrical and mechanical joining of layer 561 and layer 563a can be achieved. can.

[0229] <Laminated structure 2> Figure 26 shows a laminate having layers 560, 561, 562, and 563 and no bonding surface. This is an example of a cross-sectional view. A Si transistor is provided in layer 563. Layer 562 contains O An S-transistor is provided. Note that the configuration of layers 563, 561, and 560 is shown in Figure 2. Since this configuration is identical to that shown in section 3, the explanation will be omitted here.

[0230] <layer 562> Layer 562 is formed on layer 563. Layer 562 has an OS transistor. This shows transistors 102 and 106 as part of the elements of circuit 10. In the cross-sectional view shown in Figure 26, the electrical connection between the two is not shown.

[0231] Layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. Furthermore, a conductive layer 627 is provided. The conductive layer 627 is connected to the wiring 121 (see Figure 1) It can be electrically connected.

[0232] Insulating layer 621 functions as a blocking layer. Insulating layers 622, 623, 625 ,626 and 628 have the function of interlayer insulating film and planarizing film. Insulating layer 624 is It functions as a protective film.

[0233] It is preferable to use a film that has the function of preventing hydrogen diffusion as the blocking layer. In Si devices, hydrogen is required to terminate dangling bonds, Hydrogen near the OS transistor is one of the factors that generate carriers in the oxide semiconductor layer. This leads to a decrease in reliability. Therefore, the layer in which the Si device is formed and the OS transistor It is preferable that a hydrogen blocking film be provided between the layer in which the zista is formed and the other layer.

[0234] Examples of the blocking film include aluminum oxide, aluminum oxide nitride, and oxide Gallium, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafniu oxide Materials such as hafnium oxide nitride and yttria-stabilized zirconia (YSZ) can be used. ru.

[0235] The gate of transistor 106 is electrically connected to transistor 169 via a plug. ru.

[0236] Either the source or drain of transistor 102 is connected to the photoelectric conversion device of layer 561. It is electrically connected to layer 567a of layer 101. The conductive layer 627 is connected to the photoelectric transformer of layer 561. It is electrically connected to layer 567e of the replacement device 101.

[0237] Figure 27A shows details of the OS transistor. The OS transistor shown in Figure 27A is made of oxide An insulating layer is provided on top of a laminate of semiconductor layers and conductive layers, and an opening is provided that reaches the oxide semiconductor layer. A self-aligning structure that forms the source electrode 705 and drain electrode 706 by aligning. It is complete.

[0238] OS transistors have a channel formation region and a source region 703 formed in the oxide semiconductor layer. In addition to the drain region 704, the configuration also includes a gate electrode 701 and a gate insulating film 702. This can be done. The above opening contains at least a gate insulating film 702 and a gate electrode 7 An opening 01 is provided. An oxide semiconductor layer 707 may also be provided in the opening. stomach.

[0239] As shown in Figure 27B, the OS transistor uses the gate electrode 701 as a mask for the semiconductor layer As a self-aligned configuration that forms a source region 703 and a drain region 704 That's good too.

[0240] Alternatively, as shown in Figure 27C, the source electrode 705 or drain electrode 706 and the gate electrode A non-self-aligned top-gate transistor having a region that overlaps with pole 701. It's okay to have it.

[0241] The OS transistor has a structure with a back gate 535, but the back gate It may also be a non-structured one. The back gate 535 is the channel of the transistor shown in Figure 27D. As shown in the cross-sectional view in the width direction of the panel, the front gates of the transistors are arranged opposite each other and electrical They may also be connected in a specific way. Note that Figure 27D shows an example of the cross-section of the transistor B1-B2 in Figure 27A. Although it is shown as such, the same applies to transistors with other structures. Also, back gate 5 The configuration may also allow for supplying a fixed potential to 35 that is different from that of the front gate.

[0242] <Modified example 1 of laminated structure 2> Figure 28 shows a modified example of the laminated structure shown in Figure 26, and the photoelectric conversion device 1 in layer 561 The configuration of layer 01 and some of the configuration of layer 562 are different, and a bond is formed between layer 561 and layer 562. It has a configuration that includes a curved surface.

[0243] The photoelectric conversion device 101 in layer 561 is a pn junction type formed on a silicon substrate. It is a photodiode, and its configuration is the same as that shown in Figure 25.

[0244] In layer 562, an insulating layer 648 is formed on the insulating layer 626. Also, Transis A conductive layer 688 is electrically connected to either the source or drain of the 102, and a conductive layer 688 is electrically connected to either the source or drain of the 102. A conductive layer 689 is formed that is electrically connected to layer 627.

[0245] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. 88 and 689 have regions embedded in the insulating layer 648. Also, the insulating layer 648 and the conductor The surfaces of electrode layers 688 and 689 are flattened so that their heights are the same.

[0246] Here, conductive layers 688 and 689 are bonded layers similar to those described above for conductive layers 619 and 639. Furthermore, the insulating layer 648 is a bonding layer similar to the insulating layers 618 and 631 mentioned above. be.

[0247] Therefore, by bonding conductive layer 688 and conductive layer 685, the layers of the photoelectric conversion device are formed. 565a (n-type region, corresponding to the cathode) and the source or drain of transistor 102 One side can be electrically connected. Also, conductive layer 689 and conductive layer 686 are bonded together. By doing so, the photoelectric conversion device's layer 565b (p-type region, corresponding to the anode) and wiring 121( (See Figure 1) can be electrically connected. Also, insulating layer 648 and insulating layer 661 are attached. By combining them, electrical and mechanical joining of layer 561 and layer 562a can be achieved. can.

[0248] When stacking multiple Si devices, multiple polishing and bonding processes are required. Therefore, there are challenges such as a large number of steps, the need for specialized equipment, and low yield, and manufacturing costs. The cost is also high. OS transistors are formed by stacking them on a silicon substrate on which the device is formed. This allows for a reduction in the bonding process.

[0249] <Modified example 2 of laminated structure 2> Figure 29 shows a modified version of the laminated structure shown in Figure 28, and the configuration of layer 561 and layer 562. The component structure is different, and it has a bonding surface between layer 561 and layer 562.

[0250] This modified configuration has the transistor 102 of the circuit 10 located on layer 561. In 561, transistor 102 is formed from a Si transistor. Either the source or drain of 102 is directly connected to the photoelectric conversion device 101, and the source is The other end of the drain acts as node FD1.

[0251] In this case, layer 562 contains at least one of the transistors that make up circuit 10. Transistors other than transistor 102 are provided. In Figure 29, transistor 104 and An example in which transistor 106 is provided is shown.

[0252] <Laminated structure 3> Furthermore, Figures 25 to 29 illustrate a stacked structure for the configuration of circuit 10 shown in Figure 1. In the case of circuit 10 shown in Figure 2B, the structure can be as shown in Figure 30. In Figure 30, Layer 561 has Si transistors, transistors 102, 103, 104, 105, 106 ( A transistor 105 (not shown) is provided, and an OS transistor is provided in layer 561. This shows an example of a configuration in which Ta 111 is provided. Note that in Figure 30, layers 562 and 563 are attached. Although the combined configuration is shown as an example, similar to Figure 29, the configuration in which layer 561 and layer 562 are bonded together It can be considered a success.

[0253] <Package, Module> Figure 32A1 is a perspective view of the top side of the package containing the image sensor chip. This package is a package for securing the image sensor chip 450 (see Figure 32A3). The device comprises a substrate 410, a cover glass 420, and an adhesive 430 for bonding the two together.

[0254] Figure 32A2 is a perspective view of the bottom side of the package. The bottom of the package has a half It has a BGA (Ball Grid Array) with 440 bumps for the balls. Oh, not just BGA, but LGA (Land grid array) or PGA (Pin It may have a Grid Array, etc.

[0255] Figure 32A3 shows the package with some of the cover glass 420 and adhesive 430 omitted. This is a perspective view of the package substrate 410. Electrode pads 460 are formed on the package substrate 410. The 460 and 440 bumps are electrically connected via through-holes. Electrode pack The 460 is electrically connected to the image sensor chip 450 by wire 470. ru.

[0256] Figure 32B1 shows a camera in which the image sensor chip is housed in a lens-integrated package. This is a perspective view of the top side of the module. The camera module contains an image sensor chip. Package substrate 411, lens cover 421, and o It also has a lens 435, etc. Furthermore, it has a package substrate 411 and an image sensor chip 45 Between 1 is an IC chip 490 which has functions such as the drive circuit and signal conversion circuit of the imaging device. (See Figure 32B3) SiP (System in Package) is also provided. It has the following configuration.

[0257] Figure 32B2 is a perspective view of the lower side of the camera module. Package substrate 41 The bottom and side surfaces of 1 are provided with mounting lands 441 for QFN (Quad flare) It has the configuration of a no-lead package. Note that this configuration is just one example. A QFP (Quad flat package) or the aforementioned BGA is provided. That's good too.

[0258] Figure 32B3 shows the module with the lens cover 421 and part of the lens 435 omitted. This is a perspective view of the ru. Land 441 is electrically connected to electrode pad 461, and electrode pad 4 61 is powered by the image sensor chip 451 or IC chip 490 and wire 471. They are directly connected.

[0259] By housing the image sensor chip in the package described above, printed circuit boards, etc. This makes implementation easier, allowing image sensor chips to be integrated into various semiconductor devices and electronic equipment. It is possible.

[0260] This embodiment can be appropriately combined with descriptions of other embodiments.

[0261] (Embodiment 3) Electronic devices that can use the imaging device according to one aspect of the present invention include display devices and personal computers. Computer, image storage device or image playback device equipped with recording medium, mobile phone, mobile Game consoles including mobile data terminals, e-readers, video cameras, digital still cameras Cameras such as RA, goggle-type displays (head-mounted displays), navigation systems Audio systems, sound reproduction equipment (car audio, digital audio players, etc.), copying Machines, fax machines, printers, multifunction printers, automated teller machines (ATMs), self Examples include vending machines. Specific examples of these electronic devices are shown in Figures 33A to 33F.

[0262] Figure 33A shows an example of a mobile phone, consisting of a casing 981, a display unit 982, operation buttons 983, and an external It has a port connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The band telephone has a touch sensor on the display unit 982. It can be used to make a call or input text. All operations, such as those mentioned above, are performed by touching the display unit 982 with a finger or stylus. This can be done. An imaging device and its operating method according to one aspect of the present invention can be applied to the mobile phone. This allows for reduced power consumption.

[0263] Figure 33B shows a portable data terminal, consisting of a housing 911, a display unit 912, a speaker 913, and a camera. It has 919, etc. Information is input and output by the touch panel function of the display unit 912. It can also recognize characters and other elements from images acquired by the camera 919 and output them through the speaker 913. The character can be output as sound. An imaging device according to one aspect of the present invention can be connected to the mobile data terminal. This method of operation can be applied to reduce power consumption.

[0264] Figure 33C shows a surveillance camera, consisting of a support base 951, a camera unit 952, and a protective cover 953. The camera unit 952 is equipped with a rotating mechanism and the like, and is installed on the ceiling. This enables imaging of the entire surrounding area. The present invention relates to the elements for image acquisition in the camera unit. An imaging device and its operating method can be applied in one embodiment, thereby reducing power consumption. Yes, it is possible. Note that "surveillance camera" is a common term and does not limit its use. For example... Devices that function as surveillance cameras are also called cameras or video cameras.

[0265] Figure 33D shows a video camera, consisting of a first housing 971, a second housing 972, a display unit 973, and an operating unit. It includes a key 974, a lens 975, a connector 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and lens 975 are provided on the first housing 971, and the display unit 973 is It is provided in the second housing 972. The video camera is equipped with an imaging device according to one aspect of the present invention and This operating method can be applied to reduce power consumption.

[0266] Figure 33E shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 963. The digital camera has a light-emitting unit 967, a lens 965, etc. The device and its operating method can be applied to reduce power consumption.

[0267] Figure 33F is a wristwatch-type information terminal, consisting of a display unit 932, a housing / wristband 933, and a camera It has components such as the RA939. The display unit 932 is equipped with a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible, providing excellent wearability to the body. It is being applied to the information terminal in question by applying an imaging device and its operating method according to one aspect of the present invention. This allows for reduced power consumption.

[0268] This embodiment can be appropriately combined with descriptions of other embodiments. [Explanation of Symbols]

[0269] 10: Circuit, 11: Circuit, 11A: Sense amplifier, 11B: Sense amplifier, 11C: Output Circuit, 21: Pixel array, 22: Circuit, 23: Circuit, 24: Circuit, 25: Circuit, 26: Time Road, 28: Circuit, 101: Photoelectric conversion device, 102: Transistor, 103: Trans 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Capacitor, 109: Capacitor, 111: Transistor, 11 2: OR circuit, 113: transistor, 121: wiring, 122: wiring, 123: wiring, 1 24: Wiring, 125: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Tra 132: transistor, 133: transistor, 134: transistor, 13 5: Transistor, 136: Transistor, 137: Transistor, 138: Transis Ta, 141: Transistor, 142: Transistor, 143: Transistor, 144: To Ranjista, 145: Transistor, 146: Transistor, 147: Transistor, 1 48: Transistor, 151: Transistor, 152: Transistor, 153: Transi Sta, 154: Transistor, 155: Transistor, 156: Transistor, 157: Transistor, 158: Transistor, 161: Transistor, 162: Transistor, 163: Transistor, 164: Transistor, 165: Transistor, 166: Transistor Zista, 167: Transistor, 168: Transistor, 169: Transistor, 171 : Inverter, 172: Inverter, 203: Transistor, 204: Transistor, 2 31: Wiring, 232: Wiring, 233: Wiring, 234: Wiring, 235: Wiring, 236: Wiring , 237: wiring, 238: wiring, 239: wiring, 241: wiring, 242: wiring, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover -, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode Pad, 470: Wire, 471: Wire, 490: IC Chip, 535: Backgate , 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a : layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565 a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 5 67a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 610: sili CON substrate, 611: insulating layer, 612: insulating layer, 613: insulating layer, 614: insulating layer, 615 : insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621 : insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626 : insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-shielding layer, 672: Optical conversion layer, 673: Microwave Chlorene array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer , 688: conductive layer, 689: conductive layer, 701: gate electrode, 702: gate insulating film, 70 3: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 932: Display unit, 933: Housing and wristband, 939: Camera, 951: Support 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter Button, 963: Microphone, 965: Lens, 967: Light-emitting part, 971: Housing, 972: Casing Body, 973: Display unit, 974: Operation keys, 975: Lens, 976: Connection unit, 977: S Pika, 978: Microphone, 981: Enclosure, 982: Display unit, 983: Operation buttons, 984 :External connection port, 985:Speaker, 986:Microphone, 987:Camera,

Claims

[Claim 1] The first layer and, The second layer below the first layer, Having a third layer below the second layer, The first layer has a photodiode, The aforementioned second layer has a first transistor and a second transistor, The first transistor has a first oxide semiconductor layer having a channel formation region, The second transistor has a second oxide semiconductor layer having a channel-forming region, The aforementioned third layer has a third transistor, The third transistor is an imaging device having a first silicon having a channel formation region, The photodiode is electrically connected to one of the source electrode and drain electrode of the first transistor. One of the source and drain electrodes of the second transistor is electrically connected to the third transistor. Imaging device.

Images