Semiconductor device and method for manufacturing the same

Abstract

In semiconductor devices where the interlayer insulating film is located inside a trench, we propose a technology to improve the coverage of a metal film covering the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film. [Solution] The semiconductor device comprises a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trench, a gate electrode provided inside the trench and insulated from the semiconductor substrate by the gate insulating film, an interlayer insulating film provided inside the trench and covering the upper surface of the gate electrode, and a metal film. The semiconductor substrate is located below the upper surface of the semiconductor substrate and has a connecting surface that connects the upper surface of the semiconductor substrate and the side surface of the trench. The upper surface of the gate insulating film is located below the connecting surface, the upper surface of the interlayer insulating film is located below the upper surface of the gate insulating film, and the metal film covers the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, a gate insulating film and a gate electrode provided in the trench, and an interlayer insulating film covering the upper surface of the gate electrode. In this semiconductor device, the upper surface of the interlayer insulating film is located below the upper surface of the semiconductor substrate. The range spanning from the upper surface of the semiconductor substrate to the upper surface of the interlayer insulating film is covered with a metal film. In Patent Document 1, since the interlayer insulating film is formed inside the trench, the pitch of the trench can be reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] [[ID=!2]]The semiconductor device of Patent Document 1 has a large step between the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film. Therefore, the coverage of the metal film deteriorates at this step, and a break in the metal film may occur. In this specification, a technology for improving the coverage of a metal film covering the upper surface of a semiconductor substrate and the upper surface of an interlayer insulating film in a semiconductor device where the interlayer insulating film is located inside a trench is proposed.

Means for Solving the Problems

[0005] The semiconductor device (10) disclosed herein comprises a semiconductor substrate (12), a trench (22) provided on the upper surface (12a) of the semiconductor substrate, a gate insulating film (24) covering the inner surface of the trench, a gate electrode (26) provided inside the trench and insulated from the semiconductor substrate by the gate insulating film, an interlayer insulating film (28) provided inside the trench and covering the upper surface of the gate electrode, and a metal film (52). The semiconductor substrate is located below the upper surface of the semiconductor substrate and has a connecting surface (40) connecting the upper surface of the semiconductor substrate and the side surface of the trench. The upper surface (24a) of the gate insulating film is located below the connecting surface. The upper surface (28a) of the interlayer insulating film is located below the upper surface of the gate insulating film. The metal film covers the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film.

[0006] In the semiconductor device described above, the semiconductor substrate has a connecting surface that connects the upper surface of the semiconductor substrate to the side surface of the trench. This connecting surface is located below the upper surface of the semiconductor substrate. Furthermore, the upper surface of the gate insulating film is located below the connecting surface, and the upper surface of the interlayer insulating film is located below the upper surface of the gate insulating film. Thus, in the semiconductor device described above, the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film are arranged to be gradually located downwards in this order. Therefore, the step difference between adjacent components is small, and the coverage of the metal film covering them can be improved.

[0007] A method for manufacturing a semiconductor device (10) disclosed herein includes the steps of: forming a trench (22) on the upper surface (12a) of a semiconductor substrate (12); forming a gate insulating film (24) and a gate electrode (26) insulated from the semiconductor substrate by the gate insulating film within the trench, wherein the gate electrode is formed such that the upper surface of the gate electrode is located below the upper surface of the semiconductor substrate; forming an interlayer insulating film (28) covering an area spanning from the upper surface of the semiconductor substrate to the upper surface of the gate electrode; and etching the interlayer insulating film, the gate insulating film, and the semiconductor substrate using an etching gas capable of etching. The process of etching the gate insulating film, the interlayer insulating film, and the semiconductor substrate is a process that involves etching the gate insulating film, the interlayer insulating film, and the semiconductor substrate such that a connecting surface (40) is formed on the semiconductor substrate which is located below the upper surface of the semiconductor substrate and connects the upper surface of the semiconductor substrate and the side surface (22a) of the trench, the upper surface (24a) of the gate insulating film is located below the connecting surface, and the upper surface (28a) of the interlayer insulating film is located below the upper surface of the gate insulating film; and forming a metal film (52) that covers the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film.

[0008] In this manufacturing method, the gate electrode is formed such that its upper surface is located below the upper surface of the semiconductor substrate, and then an interlayer insulating film is formed covering the area spanning from the upper surface of the semiconductor substrate to the upper surface of the gate electrode. Since the upper surface of the gate electrode is located below the upper surface of the semiconductor substrate, the interlayer insulating film is formed with a substantially constant thickness following the shape of the upper surface of the semiconductor substrate and the upper surface of the gate electrode. That is, the upper surface of the interlayer insulating film is located above the gate electrode, but below other areas. Subsequently, an etching process is carried out using an etching gas capable of etching the interlayer insulating film, the gate insulating film, and the semiconductor substrate. Since the upper surface of the interlayer insulating film is located above the gate electrode, but below other areas, in this process, during the etching of the interlayer insulating film, the trench shoulder (the boundary between the upper surface of the semiconductor substrate and the side surface of the trench) of the semiconductor substrate is exposed first. Since the etching gas is capable of etching the semiconductor substrate, etching the shoulder creates a connection surface on the semiconductor substrate that is located below its upper surface and connects the upper surface to the side surface of the trench. Furthermore, in this process, the gate insulating film and the interlayer insulating film are etched such that the upper surface of the gate insulating film is located below the connection surface, and the upper surface of the interlayer insulating film is located below the upper surface of the gate insulating film. In other words, the upper surface of the semiconductor substrate, the connection surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film are etched in such a way that they are gradually located downwards in that order. Therefore, the step difference between adjacent components is small, and the coverage of the metal film can be improved in the subsequent process of forming the metal film. [Brief explanation of the drawing]

[0009] [Figure 1] Cross-sectional view of the semiconductor device of the example. [Figure 2] Enlarged cross-sectional view of the semiconductor device of the embodiment. [Figure 3] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 4] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 5] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 6] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 7] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 8] A diagram illustrating the manufacturing process of the semiconductor device in the example. [Figure 9] Cross-sectional view of the main part of a modified semiconductor device. [Modes for carrying out the invention]

[0010] In one example semiconductor device disclosed herein, the connection surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film may be inclined such that they are displaced downward toward the center of the trench.

[0011] In this configuration, the connection surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film are gently displaced downward from the upper surface of the semiconductor substrate toward the center of the trench. This improves the coverage of the metal film. Furthermore, in the above configuration, the upper surface of the semiconductor substrate and the side surface of the trench are connected by an inclined connection surface. As a result, the connection points of the upper surface of the semiconductor substrate, the connection surface, and the side surface of the trench become obtuse angles, mitigating electric field concentration. Therefore, gate leakage current can be suppressed.

[0012] In one example semiconductor device disclosed herein, a first step is provided at the boundary between the connection surface and the upper surface of the gate insulating film, and a second step may be provided at the boundary between the upper surface of the gate insulating film and the upper surface of the interlayer insulating film.

[0013] In one example of a semiconductor device disclosed herein, the semiconductor substrate may be made of SiC.

[0014] (Examples) Figure 1 shows a semiconductor device 10 of an embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and has a semiconductor substrate 12, electrodes, an insulating film, etc. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material constituting the semiconductor substrate 12 is not particularly limited, and other semiconductor materials such as Si (silicon) or GaN (gallium nitride) may be used.

[0015] Multiple trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends parallel to each other along a direction perpendicular to the plane of the paper in Figure 1. A connecting surface 40 is provided between the upper surface 12a of the semiconductor substrate 12 and the side surface 22a of the trench 22. The upper surface 12a of the semiconductor substrate 12 and the side surface 22a of the trench 22 are connected by the connecting surface 40. The connecting surface 40 is located below the upper surface 12a of the semiconductor substrate 12. In detail, the connecting surface 40 is inclined to displace downward from the upper surface 12a of the semiconductor substrate 12 toward the center of the trench 22. As shown in Figure 2, the connecting surface 40 is inclined by an angle θ1 with respect to the upper surface 12a of the semiconductor substrate 12. The value of the angle θ1 is not particularly limited, but for example, it is between 10° and 30°.

[0016] The inner surface of each trench 22 is covered with a gate insulating film 24. The upper surface 24a of the gate insulating film 24 is located below the connection surface 40. More specifically, the upper surface 24a of the gate insulating film 24 is inclined to be displaced downward toward the center of the trench 22. As shown in Figure 2, the upper surface 24a of the gate insulating film 24 is inclined at an angle θ2 with respect to the upper surface 12a of the semiconductor substrate 12. The value of the angle θ2 is not particularly limited, but for example, it is between 10° and 30°.

[0017] Inside each trench 22, a gate electrode 26 is disposed. The gate electrode 26 covers a range of the surface of the gate insulating film 24 excluding the upper end portion. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is inclined so as to be displaced downward toward the center side of the trench 22.

[0018] Inside each trench 22, an interlayer insulating film 28 is disposed. The upper surface of the gate electrode 26 is covered by the interlayer insulating film 28. The upper surface 28a of the interlayer insulating film 28 is located below the upper surface 24a of the gate insulating film 24. Specifically, the upper surface 28a of the interlayer insulating film 28 is inclined so as to be displaced downward toward the center side of the trench 22. As shown in FIG. 2, the upper surface 28a of the interlayer insulating film 28 is inclined by an angle θ3 with respect to the upper surface 12a of the semiconductor substrate 12. The value of the angle θ3 is not particularly limited, but for example, it is 10° to 30°. In this embodiment, the angles θ1 to θ3 are substantially equal to each other. However, the angles θ1 to θ3 may be different values.

[0019] The upper surface 12a of the semiconductor substrate 12, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 are covered by a barrier metal layer 52. The barrier metal layer 52 is constituted by, for example, a laminated film of Ti (titanium) and TiN (titanium nitride). The barrier metal layer 52 is provided with a substantially constant thickness along the upper surface 12a of the semiconductor substrate 12, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 following these shapes. An upper electrode 54 is disposed on the upper surface of the barrier metal layer 52. The upper electrode 54 is constituted by, for example, AlSi (aluminum silicon). The barrier metal layer 52 and the upper electrode 54 constitute a source electrode.

[0020] As shown in FIG. 1, inside the semiconductor substrate 12, a plurality of source regions 30, body regions 32, and drift regions 34 are provided.

[0021] Each source region 30 is an n-type region. Each source region 30 is positioned so as to be exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in contact with the barrier metal layer 52. Each source region 30 is in contact with the gate insulating film 24 on the side surface 22a of the corresponding trench 22.

[0022] The body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 has a contact region 32a and a main body region 32b. The contact region 32a has a higher p-type impurity concentration than the main body region 32b. The contact region 32a is sandwiched between the two source regions 30 and is in contact with the barrier metal layer 52. The main body region 32b is located below the source region 30 and the contact region 32a. The main body region 32b is in contact with the gate insulating film 24 on the side surface 22a of the trench 22. The main body region 32b is in contact with the gate insulating film 24 below the source region 30.

[0023] The drift region 34 is an n-type region. The drift region 34 is located below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is in contact with the gate insulating film 24 on the side surface 22a and bottom surface of the trench 22. The drift region 34 is in contact with the gate insulating film 24 below the body region 32.

[0024] Although not shown in the diagram, a drain region with a higher n-type impurity concentration than the drift region 34 is provided below the drift region 34. The drain region is exposed on the lower surface of the semiconductor substrate 12. The lower surface of the semiconductor substrate 12 is covered by the drain electrode.

[0025] When the semiconductor device 10 is in use, the semiconductor device 10, a load (e.g., a motor), and a power supply are connected in series. The power supply voltage is applied in such a way that the drain electrode side of the semiconductor device 10 is at a higher potential than the source electrode side. When a gate-on potential (a potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the main body region 32b in contact with the gate insulating film 24, and the semiconductor device 10 turns on. When a gate-off potential (a potential below the gate threshold) is applied to the gate electrode 26, the channel disappears, and the semiconductor device 10 turns off.

[0026] As described above, in the semiconductor device 10 of this embodiment, the semiconductor substrate 12 has a connecting surface 40 that connects the upper surface 12a of the semiconductor substrate 12 to the side surface 22a of the trench 22. This connecting surface 40 is located below the upper surface 12a of the semiconductor substrate 12. Also, the upper surface 24a of the gate insulating film 24 is located below the connecting surface 40, and the upper surface 28a of the interlayer insulating film 28 is located below the upper surface 24a of the gate insulating film 24. Specifically, the connecting surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 are inclined to gradually displace downward from the upper surface 12a of the semiconductor substrate 12 toward the center of the trench 22. Thus, in the semiconductor device 10 of this embodiment, the upper surface 12a of the semiconductor substrate 12, the connecting surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 are arranged to be located gradually downward in this order. Therefore, the difference in height between adjacent components is small, and the coverage of the barrier metal layer 52 covering them can be improved.

[0027] Furthermore, in the semiconductor device 10 of this embodiment, the upper surface 12a of the semiconductor substrate 12 and the side surface 22a of the trench 22 are connected by an inclined connection surface 40. As a result, the connection portion between the upper surface 12a of the semiconductor substrate 12 and the connection surface 40, and the connection portion between the connection surface 40 and the side surface 22a of the trench 22, are obtuse angles, which reduces electric field concentration. Therefore, gate leakage current can be suppressed.

[0028] Next, the manufacturing method of the semiconductor device 10 will be described with reference to Figures 3 to 8. Note that the structure of the MOSFET inside the semiconductor substrate 12 (source region 30, body region 32, etc.) is not shown in Figures 3 to 8. First, as shown in Figure 3, a trench 22 is formed on the upper surface 12a of the semiconductor substrate 12, and then an insulating film 64 is formed to cover the area from the upper surface 12a of the semiconductor substrate 12 to the inner surface of the trench 22. Next, a polysilicon layer 66 is formed on the entire surface of the insulating film 64, thereby filling the inside of the trench 22 with the polysilicon layer 66. In this process, because the trench 22 has depth, a depression 66a is formed on the upper surface of the polysilicon layer 66 above the trench 22.

[0029] Next, as shown in Figure 4, the polysilicon layer 66 is etched to form a gate electrode 26 inside the trench 22. Here, the polysilicon layer 66 is etched until the position of the upper surface of the polysilicon layer 66 is lower than the position of the upper surface 12a of the semiconductor substrate 12. In this step, since the polysilicon layer 66 before etching has a depression 66a (see Figure 3) above the trench 22, the etching of the polysilicon layer 66 proceeds while maintaining the shape of the depression 66a. As a result, as shown in Figure 4, the upper surface of the polysilicon layer 66 after etching also has the same shape as the depression 66a. That is, the upper surface of the polysilicon layer 66 remaining in the trench 22 has a shape that slopes downward as it moves towards the center of the trench 22. The polysilicon layer 66 remaining in the trench 22 becomes the gate electrode 26.

[0030] Next, as shown in Figure 5, an insulating film 68 is formed that covers the area spanning from the surface of the insulating film 64 to the upper surface of the gate electrode 26. The insulating film 68 is formed along the upper surface of the insulating film 64 and the upper surface of the gate electrode 26, following their shapes and with a substantially constant thickness. As a result, above the gate electrode 26, the upper surface of the insulating film 68 has a shape (a recess 68a) that follows the shape of the upper surface 26a of the gate electrode 26.

[0031] Next, the insulating film 68 is dry-etched. For etching, a mixed gas of C4F8 and O2 is used as the etching gas. Since a depression 68a (see Figure 5) is formed on the upper surface of the insulating film 68, as shown in Figure 6, during the etching process of the insulating film 68, the shoulder portion 22b of the trench 22 of the semiconductor substrate 12 is exposed first. Since the mixed gas of C4F8 and O2 is a gas that can etch both the semiconductor substrate 12 and the insulating film 64, if etching is continued thereafter, as shown in Figure 7, the shoulder portion 22b is etched and the insulating film 64 is etched. In this process, etching is carried out until the insulating film 64 covering the upper surface 12a of the semiconductor substrate 12 is removed (i.e., until the upper surface 12a of the semiconductor substrate 12 is exposed). This forms a connecting surface 40 that connects the upper surface 12a of the semiconductor substrate 12 and the side surface 22a of the trench 22. In addition, the remaining insulating film 64 becomes the gate insulating film 24, and the remaining insulating film 68 becomes the interlayer insulating film 28. In this process, etching of the semiconductor substrate 12, insulating film 64, and insulating film 68 proceeds while maintaining the shape of the depression 68a formed on the upper surface of the insulating film 68. As a result, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 after etching will have a shape that conforms to the depression 68a.

[0032] Next, as shown in Figure 8, a barrier metal layer 52 is formed over the upper surface 12a of the semiconductor substrate 12, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 26a of the interlayer insulating film 28. Since the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 are inclined to be displaced downward toward the center of the trench 22, these surfaces are connected relatively smoothly. Therefore, the upper surface 12a, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 can be covered without gaps by the barrier metal layer 52. After that, the semiconductor device 10 is completed by forming the upper electrode 54, drain electrode, etc.

[0033] In the manufacturing method described above, the steps shown in Figures 3 to 8 may be carried out using a semiconductor substrate 12 on which the MOSFET structure has been formed in advance, or the MOSFET structure may be formed on the semiconductor substrate 12 after the step shown in Figure 7.

[0034] Furthermore, in the above-described embodiment, the connection surface 40, the upper surface 24a of the gate insulating film 24, and the upper surface 28a of the interlayer insulating film 28 were smooth inclined surfaces. However, for example, as shown in Figure 9, a step portion 80 may be provided at the boundary between the connection surface 40 and the upper surface 24a of the gate insulating film 24, and a step portion 82 may be provided at the boundary between the upper surface 24a of the gate insulating film 24 and the upper surface 28a of the interlayer insulating film 28. The semiconductor substrate 12, the gate insulating film 24, and the interlayer insulating film 28 have different etching rates. Specifically, the etching rates increase in the order of semiconductor substrate 12, gate insulating film 24, and interlayer insulating film 28. Therefore, in the dry etching process shown in Figures 6 and 7, step portions 80 and 82 as shown in Figure 9 may occur. The height of each step portion 80 and 82 is, for example, 10 nm or less. Even with such a configuration, the step difference between adjacent components is smaller than in the conventional method, so the coverage of the barrier metal layer 52 can be ensured.

[0035] Furthermore, although the above-described embodiment described the case where the semiconductor device is a MOSFET, the semiconductor device may also be, for example, an IGBT or a diode.

[0036] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0037] 10: Semiconductor device, 12: Semiconductor substrate, 12a: Top surface, 22: Trench, 22a: Side surface, 24: Gate insulating film, 24a: Top surface, 26: Gate electrode, 26a: Top surface, 28: Interlayer insulating film, 28a: Top surface, 40: Connection surface, 52: Barrier metal layer

Claims

1. A semiconductor substrate (12) and A trench (22) is provided on the upper surface (12a) of the semiconductor substrate, A gate insulating film (24) covering the inner surface of the trench, A gate electrode (26) provided inside the trench and insulated from the semiconductor substrate by the gate insulating film, An interlayer insulating film (28) is provided inside the trench and covers the upper surface of the gate electrode, Metal film (52), It is equipped with, The semiconductor substrate is located below the upper surface of the semiconductor substrate and has a connecting surface (40) that connects the upper surface of the semiconductor substrate and the side surface of the trench. The upper surface (24a) of the gate insulating film is located below the connection surface. The upper surface (28a) of the interlayer insulating film is located below the upper surface of the gate insulating film. The metal film covers the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film. Semiconductor device (10).

2. The semiconductor device according to claim 1, wherein the connection surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film are inclined to be displaced downward as they move toward the center of the trench.

3. A first stepped portion (80) is provided at the boundary between the connection surface and the upper surface of the gate insulating film. The semiconductor device according to claim 2, wherein a second stepped portion (82) is provided at the boundary between the upper surface of the gate insulating film and the upper surface of the interlayer insulating film.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is made of SiC.

5. A method for manufacturing a semiconductor device (10), A step of forming a trench (22) on the upper surface (12a) of the semiconductor substrate (12), A step of forming a gate insulating film (24) and a gate electrode (26) insulated from the semiconductor substrate by the gate insulating film in the trench, wherein the gate electrode is formed such that the upper surface of the gate electrode is located below the upper surface of the semiconductor substrate, A step of forming an interlayer insulating film (28) that covers an area spanning from the upper surface of the semiconductor substrate to the upper surface of the gate electrode, A step of etching the interlayer insulating film, the gate insulating film, and the semiconductor substrate using an etching gas capable of etching, wherein a connecting surface (40) is formed on the semiconductor substrate that is located below the upper surface of the semiconductor substrate and connects the upper surface of the semiconductor substrate and the side surface (22a) of the trench, the upper surface (24a) of the gate insulating film is located below the connecting surface, and the upper surface (28a) of the interlayer insulating film is located below the upper surface of the gate insulating film, A step of forming a metal film (52) that covers the upper surface of the semiconductor substrate, the connecting surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film, A manufacturing method that includes the following features.

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