Image forming apparatus

Abstract

To suppress image distortion when changing the magnification in the sub-scanning direction of the image to be formed on the recording medium page by page. [Solution] The image forming apparatus generates a line period signal for each color at a period corresponding to the resolution of the image in the sub-scanning direction. The image forming apparatus controls the period of the line period signal according to the magnification in the sub-scanning direction for each page, and also controls the writing timing of the individual images for each color. In particular, the image forming apparatus switches the period of the line period signal for each page based on the writing timing of the individual images for each color.

Description

Technical Field

[0001] The present invention relates to an image forming apparatus

Background Art

[0002] Conventionally, an image forming apparatus that exposes a photoreceptor using an exposure head with a plurality of LEDs and forms a toner image on the photoreceptor is known. In an image forming apparatus, the image may be magnified or reduced (enlarged or reduced) in the sub-scanning direction. In Patent Document 1, minute magnification in the sub-scanning direction of the image is achieved by changing the generation cycle of a line synchronization signal that defines the exposure timing in the sub-scanning direction

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when printing a plurality of pages, there may be a case where it is desired to change the magnification in the sub-scanning direction for each page. For example, when the first page is an image on the front surface of the sheet and the second page is an image on the back surface of the sheet, it is necessary to change the magnification for each page. Specifically, since the sheet shrinks temporarily due to the heat treatment for fixing the toner image on the front surface, the toner image on the back surface must be reduced accordingly. As a result, when the sheet returns to its original size, the position of the image on the front surface and the position of the image on the back surface will match

[0005] However, in color image forming apparatuses, it has been difficult to change the magnification ratio for each page. In a color image forming apparatus, toner images of different colors are transferred sequentially to an intermediate transfer medium or sheet. In other words, the formation timing of the yellow (Y), magenta (M), cyan (C), and black (K) toner images is different. For example, at a certain time, the second page of the Y color may be output, while the first pages of the M, C, and K colors are being output. If the period of the line synchronization signals for each color of the MCK is changed to match the output timing of the second page of the Y color, the magnification ratio in the sub-scanning direction of the MCK images of each color will change midway through the first page. As a result, the formation position of the Y color image and the formation position of the MCK images of each color will no longer match midway through the first page. Consequently, the resulting color image will be distorted. Therefore, the present invention aims to suppress image distortion when changing the magnification ratio in the sub-scanning direction of the image to be formed on the recording medium page by page. [Means for solving the problem]

[0006] The present invention, for example, A first image forming means that forms a first-color image by exposing one line at a time using a first exposure head, A second image forming means that forms a second-color image by exposing one line at a time using a second exposure head, A third image forming means that forms a third-color image by exposing one line at a time using a third exposure head, A fourth image forming means that forms a fourth-color image by exposing one line at a time using a fourth exposure head, A transfer means for forming a full-color image by sequentially transferring the first color image, the second color image, the third color image, and the fourth color image onto a sheet, A first generation means generates a line period signal for each color with a period corresponding to the resolution of the image in the sub-scanning direction, It includes control means that controls the period of the line period signal according to the magnification in the sub-scanning direction for each page, and also controls the writing timing of individual images for each color, The control means provides an image forming apparatus characterized by switching the period of the line period signal for each page, based on the writing timing of individual images for each color. [Effects of the Invention]

[0007] According to the present invention, image distortion is suppressed when changing the magnification in the sub-scanning direction of the image to be formed on the recording medium page by page. [Brief explanation of the drawing]

[0008] [Figure 1] Diagram illustrating an image forming apparatus. [Figure 2] Diagram illustrating the arrangement of the photoreceptor drum and exposure head. [Figure 3] Diagram explaining a printed circuit board [Figure 4] Diagram illustrating the light-emitting element array. [Figure 5] Diagram explaining the light-emitting element. [Figure 6] Diagram illustrating the arrangement of light-emitting elements. [Figure 7A] Block diagram showing the image controller [Figure 7B] Block diagram showing a printed circuit board [Figure 8] Block diagram showing the digital section [Figure 9] Diagram explaining the timing section [Figure 10] Diagram illustrating the lighting control unit. [Figure 11] Block diagram showing the analog section [Figure 12] Diagram illustrating the drive unit circuit [Figure 13] Diagram explaining the synchronization unit [Figure 14] The LSync generation circuit is explained in the diagram. [Figure 15]Timing chart for explaining the operation of the synchronization unit [Figure 16] Timing chart for explaining the operation of the synchronization unit [Figure 17] Diagram for explaining another exemplary synchronization unit

Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] [Example 1] <Image forming apparatus> FIG. 1 shows an image forming apparatus 1 which is an electrophotographic copying machine. However, the image forming apparatus 1 may be realized as a monochrome printer, a full-color printer, a facsimile communication device, and a multifunction machine.

[0011] The scanner unit 100 is a document reading device that optically reads the image of a document placed on the document table by shining illumination light on it, and converts the reading result into an electrical signal to create image data. The printer engine 103 forms a toner image on the sheet P. The printer engine 103 rotates the photoreceptor drum 102. The charger 107 charges the surface of the photoreceptor drum 102 so that the potential of the surface of the photoreceptor drum 102 becomes uniform. The exposure head 106 exposes the surface of the photoreceptor drum 102 with light corresponding to the image data, and forms an electrostatic latent image on the surface of the photoreceptor drum 102. The developer unit 108 deposits toner onto the electrostatic latent image formed on the photoreceptor drum 102 to form a toner image. As the photoreceptor drum 102 rotates further, the toner image arrives at the transfer nip. At the transfer nip, the sheet P is transported while being held between the photoreceptor drum 102 and the transfer belt 111. This transfers the toner image from the photoconductor drum 102 to the sheet P.

[0012] The printer engine 103 has four image units 101Y, 101M, 101C, and 101K, which correspond to the toner colors YMCK (yellow, magenta, cyan, and black). The four image units 101Y, 101M, 101C, and 101K each transfer toner images of different colors to the sheet P, thereby forming a full-color image on the sheet P.

[0013] The feeding unit 105 feeds the sheet P from one of the feeding devices designated in advance, among the feeding devices 109a and 109b provided on the main body of the image forming apparatus 1, the feeding device 109c provided on the outside of the main body, and the manual feeding type feeding device 109d. The fed sheet P is transported to the register roller 110. The register roller 110 transports the sheet P so that the timing of the arrival of the toner image at the transfer nip coincides with the timing of the arrival of the sheet P. The transfer belt 111 transports the sheet P with the transferred toner image to the fuser 104.

[0014] The fuser 104 fixes the toner image onto the sheet P by applying pressure and heat to the toner image and the sheet P. The paper discharge roller 112 discharges the sheet P to the outside of the image forming apparatus 1.

[0015] When double-sided image formation is performed, the paper discharge roller 112 transports the sheet P, on which the toner image has been formed on the first side, to the feeding unit 105. The feeding unit 105 transports the sheet P to the register roller 110. The register roller 110 transports the sheet P back to the printer engine 103. This forms a toner image on the second side of the sheet P. After that, the fuser unit 104 fixes the toner image onto the sheet P. The paper discharge roller 112 discharges the sheet P to the outside of the image forming apparatus 1.

[0016] <Exposure head> Figure 2(A) is a perspective view of the exposure head 106 that exposes the photoreceptor drum 102. Figure 2(B) is a schematic cross-sectional view of the photoreceptor drum 102 and the exposure head 106. The exposure head 106 includes a group of light-emitting elements 201, a printed circuit board 202, a rod lens array 203, and a housing 204. Light emitted from the group of light-emitting elements 201 mounted on the printed circuit board 202 is focused by the rod lens array 203 and irradiated onto the surface of the photoreceptor drum 102. The printed circuit board 202 and the rod lens array 203 are fixed to the housing 204.

[0017] The exposure head 106 is assembled and adjusted independently. The adjustment process includes adjusting the spot size (focusing) at the focusing position and adjusting the light intensity. In focusing, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light-emitting element group 201 is a predetermined value. In light intensity adjustment, the multiple light-emitting elements included in the light-emitting element group 201 are illuminated one by one in sequence, and the drive current of each light-emitting element is adjusted so that the amount of light focused through the rod lens array 203 becomes a predetermined light intensity.

[0018] <Configuration of the light-emitting element group> Figure 3(A) shows the non-mounted side 301 of the printed circuit board 202. Although no light-emitting elements are mounted on the non-mounted side 301, other electronic components such as the connector 305 are mounted there. Cables (power lines and signal lines) that carry various signals such as clock signals are connected to the connector 305 from the printed circuit board 202.

[0019] As shown in Figure 3(B), the light-emitting element group 201 is mounted on the mounting surface 302 of the printed circuit board 202. The mounting surface 302 is the surface opposite to the non-mounted surface 301. The light-emitting element group 201 has m light-emitting element arrays 300-1 to 300-m arranged in a staggered pattern. The light-emitting element arrays 300-1 to 300-m are sometimes collectively referred to as the light-emitting element array 300.

[0020] As shown in Figure 3(C), each of the light-emitting element arrays 300-1 to 300-m has multiple light-emitting elements 350 arranged along the longitudinal direction of the light-emitting element array 300.

[0021] As shown in Figure 3(B), the light-emitting element array 300 is arranged in two rows. The first row contains light-emitting element array 300-1, light-emitting element array 300-3, ..., and light-emitting element array 300-m-1. The second row contains light-emitting element array 300-2, light-emitting element array 300-4, ..., and light-emitting element array 300-m.

[0022] As shown in Figure 3(C), the distance between two adjacent light-emitting elements 350 in a given light-emitting element array 300 is L. Distance L is the longitudinal distance of the light-emitting element array 300. At a resolution of 1200 dpi, L = approximately 21.16 μm. This distance corresponds to one pixel at 1200 dpi. Note that the distance between the rightmost light-emitting element 350 of the i-th light-emitting element array 300-i and the leftmost light-emitting element 350 of the (i+1)th light-emitting element array 300-i+1 is also L. i is any integer from 1 to m-1. As shown in Figure 3(C), in the short-side direction of the light-emitting element array 300, the distance S between the rightmost light-emitting element 350 of the light-emitting element array 300-i and the leftmost light-emitting element 350 of the light-emitting element array 300-i+1 is approximately 105 μm. This distance corresponds to five pixels at 1200 dpi. Note that distances L and S are just examples.

[0023] <Configuration of the light-emitting element array> Figure 4 is a plan view of the light-emitting element array 300. The X direction indicates the longitudinal direction of the photoreceptor drum 102. The Y direction indicates the rotation direction of the photoreceptor drum 102. The light-emitting element array 300 includes a light-emitting substrate 402, a light-emitting section 404 including a plurality of light-emitting elements 350 mounted on the light-emitting substrate 402, and a WB pad 408 mounted on the light-emitting substrate 402. WB is an abbreviation for wire bonding. The light-emitting substrate 402 has a circuit section 406 built in for controlling the light-emitting section 404. The circuit section 406 includes both an analog drive circuit (analog section) and a digital control circuit (digital section). Power is supplied to the circuit section 406 and signals are input and output to and from the light-emitting element array 300 through the WB pad 408.

[0024] <Light-emitting part> Figure 5 shows a portion of the cross-section of the area where the light-emitting element 350 is provided. Multiple lower electrodes 504 are formed on the light-emitting substrate 402. A light-emitting layer 506 is provided on the lower electrodes 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is a single common electrode for the multiple lower electrodes 504. When a predetermined voltage is applied between the lower electrodes 504 and the upper electrode 508, current flows from the lower electrodes 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. That is, the light-emitting layer 506 corresponding to the area where the lower electrodes 504 are provided emits light. In the following description, the light-emitting element 350 corresponds to the lower electrodes 504, but for example, the light-emitting element may correspond to the light-emitting layer.

[0025] By increasing the length dx relative to the length dz between the lower electrode 504 and the upper electrode 508, the leakage current between adjacent lower electrodes 504 can be suppressed, thereby preventing false light emission from adjacent light-emitting elements 350.

[0026] For example, an organic EL film can be used for the light-emitting layer 506. Alternatively, an inorganic EL film can be used for the light-emitting layer 506. The upper electrode 508 is composed of a transparent electrode, such as indium tin oxide (ITO), so as to transmit the emission wavelength of the light-emitting layer 506. In this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient for the region from which light is emitted from each light-emitting element 350 (corresponding to the lower electrode 504) to transmit light of the emission wavelength.

[0027] In this embodiment, one light-emitting layer 506 is provided for each lower electrode 504 provided in the light-emitting element array 300-i (where i is an integer between 1 and m). That is, the light-emitting layer 506 is common to all lower electrodes 504 provided in the light-emitting element array 300-i, but this is not limited to this. For example, a first group of lower electrodes 504 provided in the light-emitting element array 300-i may be covered by the first light-emitting layer 506. A second group of lower electrodes 504 provided in the light-emitting element array 300-i may be covered by the second light-emitting layer 506. Alternatively, a light-emitting layer 506 may be provided individually for each of the multiple lower electrodes 504 provided in the light-emitting element array 300-i.

[0028] In this embodiment, an organic EL (Electro-Luminescence) was used as the light-emitting mechanism, but an LED (Light Emitting Diode) may also be used as the light-emitting element. When an LED is used as the light-emitting element, the light-emitting element 350 corresponds to one LED.

[0029] Figure 6 shows the array of light-emitting elements (lower electrode array) that constitute the light-emitting section 404. The light-emitting section 404 has n light-emitting elements 350 arranged in a row. Each of the multiple light-emitting elements 350 is arranged at a predetermined pitch (distance L = 21.16 μm) in the X direction.

[0030] In Figure 6, W1 is the length of the light-emitting element 350 in the X direction. dx is the distance between two adjacent light-emitting elements 350 in the X direction. W2 is the length of the light-emitting element 350 in the Y direction. The length W2 is determined considering the scanning speed and resolution in the Y direction. As an example, lengths W1 and W2 are 20.9 μm, and the adjacent spacing dx is 0.26 μm.

[0031] <Control Block> Figure 7A shows the image controller 600. Figure 7B shows the printed circuit boards 202Y, 202M, 202C, and 202K. Note that printed circuit boards 202Y, 202M, 202C, and 202K are common components, so printed circuit board 202Y is described as representative. When explaining features common to YMCK, the letters YMCK at the end of the reference numeral may be omitted.

[0032] The image controller 600 is connected to the higher-level controller 690 and is a control circuit that generates and transmits a set of signals to the printed circuit board 202 for controlling the printed circuit board 202. Such a set of signals includes a clock signal clk, image data data_1 to data_m, a line synchronization signal lsync, and a communication signal com. The clock signal clk is generated by the clock unit 608 and serves as the reference signal for operation in various circuits. Image data data_1 to data_m are image data supplied to the light-emitting element arrays 300-1 to 300-m, respectively. Image data data_1 to data_m are generated for each color of YMCK. The line synchronization signal lsync represents the image writing timing in the sub-scanning direction. The line synchronization signal lsync is generated for each color of YMCK. The image is formed by sequentially exposing different positions in the sub-scanning direction. Generally, one line at a time is exposed, and the spacing between adjacent lines corresponds to the image resolution in the sub-scanning direction. Therefore, the period of the line synchronization signal lsync is a parameter that defines the line spacing (resolution). Ideally, the period of the line synchronization signal lsync is a common period for YMCK, but it may change from page to page. It is required that the magnification in the sub-scanning direction for the first side of sheet P (the i-th page) matches the magnification in the sub-scanning direction for the second side of sheet P (the (i+1)-th page). However, the sheet P temporarily shrinks due to the heating process used to fix the toner image on the first side. A toner image is formed on the second side of this temporarily shrunk sheet P. As the temperature of sheet P decreases, it absorbs moisture and expands, causing the toner image on the second side to enlarge, and the magnification of the toner image on the first side and the toner image on the second side no longer match. Therefore, by intentionally making the magnification of the electrostatic latent image on the second side smaller than the magnification of the electrostatic latent image on the first side, the magnification of the toner image on the first side and the toner image on the second side can be made to match.

[0033] Incidentally, as shown in Figure 1, each toner image of YMCK is transferred to sheet P in sequence. Therefore, while the image-forming unit 101K is forming the latent image on the first surface, the image-forming unit 101Y may start forming the latent image on the second surface. In order to change the magnification of the latent image on the second surface and the latent image on the first surface, it is necessary to independently control the lsyncK signal, which is the line synchronization signal for the image-forming unit 101K, and the lsyncY signal, which is the line synchronization signal for the image-forming unit 101Y. If the period of the lsyncY signal and the period of the lsyncK signal are changed simultaneously, the magnification of the black image on the first surface will change midway, causing color misalignment.

[0034] The communication signal com is a communication signal transmitted or received between the CPU 603 and the printed circuit board 202. The clock signal clk is transmitted from the clock unit 608 to the printed circuit board 202, etc., via the clock signal line 605. The line synchronization signal lsync is transmitted from the synchronization unit 604 to the printed circuit board 202, CPU 603, and conversion unit 602, etc., via the synchronization signal line 606. Image data data_1 to data_m are transmitted to the light-emitting element arrays 300-1 to 300-m, respectively, via the image signal lines 607-1 to 607-m. The communication signal com is transmitted from the CPU 603 to the information storage unit 610 and the light-emitting element arrays 300-1 to 300-m via the communication signal line 609.

[0035] The image data unit 601 applies image processing to image data received from the scanner unit 100 or an external computer of the image forming apparatus 1 via the higher-level controller 690, and outputs the image data to the conversion unit 602. The image processing includes, for example, dithering processing at a resolution instructed by the CPU 603. For example, dithering processing is performed at a resolution of 2400 dpi in the sub-scanning direction and 1200 dpi in the main scanning direction. The image data is 8-bit wide data and represents, for example, the amount of light emitted.

[0036] The clock unit 608 is an oscillator circuit that generates a clock signal clk with a fixed period. The clock signal clk is supplied to the CPU 603, the synchronization unit 604, the conversion unit 602, and the printed circuit board 202. The CPU 603 performs the following processing according to the control program stored in the ROM area of ​​the memory 650. Note that the memory 650 also includes a RAM area that holds variables, etc.

[0037] The CPU 603 determines the generation period for the line synchronization signal lsync. The generation period is calculated, for example, based on the rotational speed of the photoreceptor drum 102 (speed information of the surface of the photoreceptor drum 102 moving in the rotational direction) and the scaling factor of the sub-scanning direction of the image. The CPU 603 sets the generation period for the line synchronization signal lsync to the synchronization unit 604. The CPU 603 also receives the line synchronization signal lsync from the synchronization unit 604 and recognizes the timing when the generation of the line synchronization signal lsync is complete.

[0038] The conversion unit 602 divides the image data for one line output from the image data unit 601 to generate image data data_1 to data_m. The conversion unit 602 transmits the image data data_1 to data_m to the printed circuit board 202 in synchronization with the line synchronization signal lsync and the clock signal clk.

[0039] The synchronization unit 604 generates line synchronization signals lsyncY, lsyncM, lsyncC, and lsyncK with generation cycles instructed by the CPU 603. Line synchronization signal lsyncY is supplied to the printed circuit board 202Y, the conversion unit 602Y, and the CPU 603. Line synchronization signal lsyncM is supplied to the printed circuit board 202M, the conversion unit 602M, and the CPU 603. Line synchronization signal lsyncC is supplied to the printed circuit board 202C, the conversion unit 602C, and the CPU 603. Line synchronization signal lsyncK is supplied to the printed circuit board 202K, the conversion unit 602K, and the CPU 603.

[0040] The synchronization unit 604 generates an itop signal for each YMCK color based on the top signal supplied from the upper controller 690 and supplies it to the corresponding conversion unit 602. The top signal indicates the leading edge of the toner image formed on the sheet P. The itopY signal indicates the writing timing of the yellow electrostatic latent image. The itopM signal indicates the writing timing of the magenta electrostatic latent image. The itopC signal indicates the writing timing of the cyan electrostatic latent image. The itopK signal indicates the writing timing of the black electrostatic latent image. As shown in Figure 1, the timing at which each YMCK toner image is transferred to the sheet P is staggered. This stagger time is called the inter-drum delay time and is determined according to the transport distance between the image formation units 101Y, 101M, 101C, and 101K and the transport speed of the sheet P. The conversion units 602Y, 602M, 602C, and 602K begin outputting image data when they receive the corresponding itopY, itopM, itopC, and itopK signals, respectively.

[0041] As shown in Figure 7B, on the printed circuit board 202, the light-emitting element array 300-i operates by being supplied with a line synchronization signal lsync, a clock signal clk, image data data_i, and a communication signal com. The information storage unit 610 is a memory circuit that stores head information. The head information includes the amount of light emitted by each light-emitting element array 300-1 to 300-m and position information indicating the mounting position. The CPU 603 accesses the information storage unit 610 via the communication signal line 609 to read head information or write setting information. The information storage unit 610 may also store the set value of the drive current adjusted during the assembly process of the exposure head 106.

[0042] As shown in Figure 7B, the clock signal line 605, communication signal line 609, and synchronization signal line 606 are connected to all light-emitting element arrays 300. The image signal line 607 is connected one-to-one with each light-emitting element array 300. In other words, one image signal line 607 is connected to each light-emitting element array 300.

[0043] <Circuit section configuration> Figure 8 is a block diagram of the circuit section 406 within the i-th light-emitting element array 300-i (where i is an integer from 1 to m). The circuit section 406 has a digital section 700 and an analog section 750. The digital section 700 generates a lighting signal to illuminate the light-emitting element 350 based on a preset value set by the communication signal com, a line synchronization signal lsync, and image data, synchronized with the clock signal clk. The digital section 700 outputs the lighting signal to the analog section 750 via the lighting signal line 708.

[0044] The communication IF 701 controls the writing and reading of setting values ​​to register 702 based on the communication signal com from CPU 603. Register 702 holds the setting values ​​necessary for the operation of the light-emitting element 350. These setting values ​​include a value indicating the drive current set for the analog section 750.

[0045] The timing unit 704 generates a timing signal based on the line synchronization signal lsync and supplies the timing signal to the lighting control unit 705-1 via the signal line 707-1. The lighting control unit 705-1 acquires image data from the image signal line 607 according to the timing signal. The number of lighting control units 705 n is the same as the number of light-emitting elements 350 n. In other words, one lighting control unit 705 is provided for each light-emitting element 350. The lighting control unit 705-j outputs a lighting signal to the analog unit 750 via the lighting signal line 708-j (where j is an integer from 1 to n). The lighting control unit 705-j generates a timing signal for the lighting control unit 705-j+1 based on the input timing signal and supplies the timing signal to the lighting control unit 705-j+1 via the signal line 707-j+1. Thus, the lighting control unit 705-1 is supplied with a timing signal directly from the timing unit 704, while the lighting control units 705-2 to 705-n are supplied with timing signals from the preceding lighting control units 705-1 to 705-n-1, respectively.

[0046] The analog unit 750 drives the light-emitting elements 350-1 to 350-n based on the pulsed lighting signals generated by the digital unit 700.

[0047] <Details of the timing section> Figure 9(A) is a circuit diagram of the timing unit 704. Here, the line synchronization signal lsync is assumed to be a negative logic signal, but it may also be a positive logic signal. we[1] is the timing signal. The timing unit 704 is a logic circuit that outputs the timing signal we[0] only when the line synchronization signal lsync changes from Low to High.

[0048] The delay circuit 801 connects the synchronization signal line 606 and the clock signal line 605, and delays the line synchronization signal lsync transmitted by the synchronization signal line 606 by one cycle before outputting it to the logic gate 802. The delay circuit 801 can be implemented, for example, by a flip-flop circuit.

[0049] Logic gate 802 performs a logical AND operation on the line synchronization signal lsync and the output signal of the delay circuit 801, which is inverted by the inverting element 803, to generate the timing signal we[0]. The timing signal we[0] is output to signal line 707-1.

[0050] Figure 9(B) is a timing chart of the timing unit 704. The timing signal we[0] becomes high when the line synchronization signal lsync changes from low to high. The timing signal we[0] remains high for a time equivalent to one cycle of the clock signal clk, and then returns to low.

[0051] <Details of the lighting control unit> Figure 10(A) is a circuit diagram of the j-th lighting control unit 705-j in the i-th light-emitting element array 300-i (where j is an integer from 1 to n). The delay circuit 901 is connected to the signal line 707-j and the clock signal line 605. The delay circuit 901 delays the timing signal we[j] transmitted by the signal line 707-j by one cycle, generates the timing signal we[j+1] for the subsequent lighting control unit 705-j+1, and outputs it to the signal line 707-j+1. The delay circuit 901 can be any circuit that can delay the input signal by a time equivalent to one cycle of the clock signal clk before outputting it. For example, a flip-flop circuit can be used as the delay circuit 901.

[0052] The latch circuit 902 is connected to the signal line 707-j and the image signal line 607-i. The latch circuit 902 captures the image data_i during the period when the timing signal we[j] is high and outputs it as a lighting signal el[j] to the lighting signal line 708-j. In this embodiment, the latch circuit 902 is used as the circuit to capture the image data_i, but this is just one example. Any circuit that can hold the image data_i from when the timing signal we[j] becomes high until the timing signal we[j] becomes high again will suffice. For example, a flip-flop circuit may be used instead of the latch circuit 902.

[0053] Figure 10(B) is the timing chart for the delay circuit 901. The timing signal we[j+1] is generated by delaying the clock signal clk by one cycle from the timing signal we[j].

[0054] Figure 10(C) is a timing chart of the latch circuit 902. During the period when the timing signal we[j] is high, the image data data_i (in this example, "000") is acquired and the lighting signal el[j] is generated.

[0055] <Details of the analog section> Figure 11 is a block diagram of the analog section 750. For simplicity of explanation, two light-emitting elements 350-1 and 350-n and two drive circuits 1001-1 and 1001-n are shown. In reality, there are n light-emitting elements 350-1 to 350-n and n drive circuits 1001-1 to 1001-n. Here, for generalization, we will describe the j-th light-emitting element 350-j and the j-th drive circuit 1001-j (where j is an integer from 1 to n).

[0056] The drive circuit 1001-j is a circuit that drives the i-th light-emitting element 350-j. The drive circuit 1001-j is supplied with a lighting signal el[j] via the lighting signal line 708-j.

[0057] The DAC1002 converts the drive current data set in register 702 into an analog voltage and supplies the analog voltage to the drive circuits 1001-1 to 1001-n via signal line 1003. DAC is an abbreviation for digital-to-analog converter. Here, the drive current data indicates the set value of the drive current supplied to the light-emitting elements 350-1 to 350-n.

[0058] The selection circuit 1007 generates a select signal to select the drive circuit 1001 based on the data set in register 702. The selection circuit 1007 supplies the select signal to the drive circuits 1001-1 to 1001-n via signal lines 1004-1 to 1004-n. The select signal is such that only the signal connected to the selected drive circuit 1001 out of the n drive circuits 1001-1 to 1001-n becomes High. When drive circuit 1001-1 is selected, only signal line 1004-1 is controlled to a High level. Signal lines 1004-2 (not shown) to 1001-n are controlled to a Low level. Each of the drive circuits 1001-1 to 1001-n has its analog voltage set via signal line 1003 at the timing selected by the selection circuit 1007 (the timing when the select signal becomes High). The CPU 603 selects the drive circuits 1001-1 to 1001-n one by one via the register 702 and sets the analog voltage corresponding to the selected drive circuit 1001. This makes it possible to set individual analog voltages for n drive circuits 1001-1 to 1001-n using a single DAC 1002. In this way, each drive circuit 1001-1 to 1001-n receives an analog voltage that determines the drive current and a lighting signal, causing the corresponding light-emitting elements 350-1 to 350-n to light up.

[0059] <Details of the drive circuit> Figure 12 is the circuit diagram of the j-th drive circuit 1001-j (where j is an integer from 1 to n). Drive circuits 1001-1 to 1001-n all have the same circuit configuration.

[0060] MOSFET Q1 supplies a drive current to the light-emitting element 350-j according to the gate voltage applied to its gate. When the gate voltage is low, the drive current decreases and the light-emitting element 350-j turns off. The gate of MOSFET Q2 is connected to the illumination signal line 708-j. MOSFET Q2 turns on when the illumination signal el[j] is high and transfers the voltage charged to capacitor C1 to MOSFET Q1. The gate of MOSFET Q3 is connected to the signal line 1004-j. MOSFET Q3 turns on and off according to the select signal from the selection circuit 1007. That is, MOSFET Q3 turns on when the select signal is high and applies the analog voltage output from DAC 1002 to capacitor C1, charging capacitor C1. In this embodiment, before image formation, DAC 1002 sets the analog voltage to capacitor C1. During the image formation period, MOSFET Q3 is off and capacitor C1 continuously maintains its voltage level. As a result, MOSFET Q1 supplies or stops supplying a drive current corresponding to the set analog voltage to the light-emitting element 350-1 in response to the lighting signal.

[0061] If the input capacitance of the light-emitting element 350-j is too large, the response speed for switching the light-emitting element 350-j from on to off will be slow. Therefore, to improve the response speed, a MOSFET Q4 and an inverter 1101 may be added. The gate of MOSFET Q4 is input to a signal obtained by the inverter 1101 by inverting the logic of the on signal el[j]. When the on signal el[j] is at a low level, the gate of MOSFET Q4 becomes high. Thus, MOSFET Q4 turns on, making it possible to forcibly discharge the charge stored in the input capacitance of the light-emitting element 350-j.

[0062] <Details of the Class of Alumni> Figure 13 shows the configuration of the synchronization unit 604. The REF generation circuit 1201 generates the lsync_REF signal, which is a periodic signal common to YMCK. The CPU 603 stores lsync_REF_period, which indicates the period of the lsync_REF signal, in register 1204. The REF generation circuit 1201 generates the lsync_REF signal at a period according to lsync_REF_period held in register 1204. For example, if lsync_REF_period is 1000 cycles, the REF generation circuit 1201 asserts the lsync_REF signal every 1000 cycles of the clock signal clk. In other words, the REF generation circuit 1201 may also be a counter circuit that counts up each time the clock signal clk is input and outputs the lsync_REF signal when the count value matches lsync_REF_period.

[0063] The itop generation circuit 1202 generates the itop signal, which serves as the reference timing for generating the lsync signal. Register 1205 holds topMargin. topMargin is written by CPU 603 and indicates the margin (delay time) relative to the top signal. When the top signal is asserted, the itop generation circuit 1202 counts the lsync_REF signal a number of times corresponding to topMargin. In other words, the itop generation circuit 1202 may also be a counter circuit that outputs the itop signal when the count value of the lsync_REF signal reaches topMargin. For example, suppose topMarginY held in register 1205Y is 10 and topMarginM held in register 1205M is 1000. After the top signal is asserted, if the lsync_REF signal is asserted 10 times, the itopY signal is output. After the top signal is asserted, if the lsync_REF signal is asserted 1000 times, the itopM signal is output. The same applies to cyan and black.

[0064] Incidentally, before the i-th itop signal is asserted, the (i + 1)-th top signal may be asserted. In this case, the itop generation circuit 1202 is configured to assert the i-th itop signal when the count value matches the topMargin set when the i-th top signal is asserted.

[0065] The lsync generation circuit 1203 receives the itop signal and the lsync_REF signal. The lsync generation circuit 1203 generates and outputs the lsync signal based on the assertion of the itop signal.

[0066] <lsync generation circuit> FIG. 14(A) is a diagram showing the configuration of the lsync generation circuit 1203. The generation circuit 1300 generates and outputs the lsync signal based on the itop signal. The generation circuit 1300 has two registers 1301 and 1302 into which information is written by the CPU 603. The register 1301 holds the lsync_period, which is the period of the lsync signal. That is, the lsync_period is a parameter indicating the line period (interval) corresponding to the resolution in the vertical blanking direction. The register 1302 holds the magnification mag.

[0067] When the generation circuit 1300 detects the assertion of the itop signal, it continues to assert the lsync signal at a period obtained by multiplying the lsync_period by the magnification mag. For example, assume a case where the lsync_period is 1000 cycles and the mag is 100%. In this case, the lsync signal is asserted every 1000 cycles of the clock signal.

[0068] Assume that 1000 cycles are set for the lsync_period and 99% is set for the mag. In this case, the lsync signal is asserted once every 990 cycles of the clock signal. As a result, the size of the image in the vertical blanking direction is slightly reduced.

[0069] Let's assume that lsync_period is set to 1000 cycles and mag is set to 99.99%. In this case, the lsync signal will be asserted 9 times every 1000 cycles of the clock signal, and then the lsync signal will be asserted once at 999 cycles of the clock signal.

[0070] In this way, it becomes possible to perform 10 LSync signal assertions over 10,000 cycles of the clock signal clk, or to perform 10 LSync signal assertions over 9,999 cycles of the clock signal clk. In the latter case, it becomes possible to generate an LSync signal that can achieve a sub-scanning ratio of 99.99%.

[0071] Figure 14(B) shows another example configuration of the lsync generation circuit 1203. In this example, the lsync generation circuit 1203 includes a first generation circuit 1300 that generates the lsync_1 signal, a second generation circuit 1303 that generates the lsync_2 signal, and a selector 1304. The operation and configuration of the generation circuit 1300 are as described in relation to Figure 14(A). The selector 1304 selects and outputs either the lsync_1 signal or the lsync_2 signal.

[0072] The second generation circuit 1303 may have a register that holds mag. Furthermore, the second generation circuit 1303 generates the lsync_2 signal independently of lsync_period. Specifically, the second generation circuit 1303 generates the lsync_2 signal based on the lsync_REF signal. The selector 1304 outputs either the lsync_1 signal or the lsync_2 signal as the lsync signal according to instructions from the CPU 603.

[0073] The first generation circuit 1300 can easily achieve a large multiplier, but it requires two parameters. The second generation circuit 1303 can achieve multiplier by setting only one parameter (multiplier). Alternatively, the first generation circuit 1300 may be removed, and only the second generation circuit 1303 may be implemented.

[0074] <How to read the timing chart> Figure 15 is a timing chart of the top signal, lsync_REF signal, image data data, and itop signal. The delay time d between drums is denoted as d[n][color], where [n] indicates the nth page and [color] indicates one of the YMCK colors. For example, d1Y indicates the delay time for the first page of yellow. t[n]Top indicates the timing at which the top signal on the nth page is asserted. For example, t1Top indicates the assertion timing of the top signal on the first page, and t2Top indicates the assertion timing of the top signal on the second page.

[0075] t[n][color]_S indicates the timing for writing out each color image on page n. Note that t[n][color]_S corresponds to the timing when the itop signal for each color is asserted. For example, t1Y_S indicates the timing for writing out the yellow image on page 1. t2K_S indicates the timing for writing out the black image on page 2.

[0076] t[n][color]_E indicates the completion timing of image formation for each color on page n. For example, t1Y_E indicates the completion timing of image formation for yellow on page 1. t2K_E indicates the completion timing of image formation for black on page 2.

[0077] Figure 15 shows the input and output of the itop generation circuit 1202, but for the sake of simplicity, only the Y and K colors will be explained. However, this explanation also applies to the M and C colors.

[0078] CPU 603 sets the topMargin for each of YMCK from timing t[n]Y_E to timing t[n+1]Top. First, the Y color is explained. The itop generation circuit 1202 detects the assertion of the top signal on the first page at timing t1Top. The itop generation circuit 1202 asserts the itopY signal at timing t1Y_S. This is because the topMargin for yellow on the first page is set to "1". In other words, the delay time d1Y from timing t1Top to timing t1Y_S corresponds to one period of the lsync_REF signal.

[0079] Between t1Y_E and t2Top, topMargin is updated from "1" to "2". The itop generation circuit 1202 detects the assertion of the top signal on the second page at timing t2Top. The itop generation circuit 1202 asserts the itopY signal at timing t2Y_S. This is because the topMargin of the yellow on the second page is set to "2". In other words, the delay time d2Y from timing t2Top to timing t2Y_S corresponds to two cycles of the lsync_REF signal.

[0080] Next, the K color will be explained. The mechanism of the K color is exactly the same as that of the Y color. However, at timing t2Top, before the itopK signal on the first page is asserted at timing t1K_S, the top signal on the second page is asserted.

[0081] In other words, the CPU 603 sets the topMargin for each of the four colors from timing t[n]Y_E to timing t[n+1]Top. The itop generation circuit 1202 stores the topMargin for all colors when the top signal is asserted and generates the itop signal for each color using the topMargin for each color.

[0082] Figure 16 shows the input / output timing chart for the synchronization unit 604. While the Y and C colors are explained as an example, this explanation also applies to the M and K colors. In Figure 16, the period of the lsync signal for each color is changed between pages 1, 2, and 3.

[0083] CPU603 sets the lsync_period and mag for that color between timing t[n][color]_E and timing t[n+1][color]_S. In other words, the parameters involved in the scaling factor are set at different timings for each color.

[0084] First, the Y color will be explained. The top signal and itop signal are explained in Figure 15, so their explanation will be omitted. The itop generation circuit 1202 detects the assertion of the top signal on the first page at timing t1Top and asserts the itopY signal at timing t1Y_S. When the lsync generation circuit 1203 detects the assertion of the itopY signal, it determines the period of the lsyncY signal according to lsync_period and mag, and outputs the lsyncY signal according to that period.

[0085] During the period from t1Y_E to t2Y_S, the lsync_period and mag for the second page of yellow are updated. The itop generation circuit 1202 detects the assertion of the top signal on the second page at timing t2Top. The itop generation circuit 1202 asserts the itopY signal at timing t2Y_S. When the lsync generation circuit 1203 detects the assertion of the itopY signal, it determines the assertion period of the lsyncY signal according to the lsync_period and mag, and outputs the lsyncY signal according to that period. Thus, in this embodiment, the lsync_period and mag for the Y color are updated from timing t1Y_E to timing t2Y_S. As a result, an lsyncY signal with a shorter period than the period of the first page is generated on the second page.

[0086] For the C color, the CPU 603 sets the lsync_period and mag for the second page of cyan during the setting period from timing t1C_E to timing t2C_S. The itop generation circuit 1202 detects the assertion of the top signal on the second page at timing t2Top. The itop generation circuit 1202 asserts the itopC signal at timing t2C_S. When the lsync generation circuit 1203 detects the assertion of the itopC signal, it determines the assertion period of the lsyncC signal according to the lsync_period and mag, and outputs the lsyncC signal according to that period. In this embodiment, the lsync_period and mag for the C color are updated from timing t1C_E to timing t2C_S. As a result, an lsyncC signal with a shorter period than the period of the first page is generated on the second page.

[0087] As shown in Figure 16, the assertion timing of the itopC signal is different from that of the itopY signal. Therefore, the timing of the period (multiplier) switching between the first and second pages of the lsyncC signal is different from that of the lsyncY signal. In any case, the period (multiplier) will no longer change in the middle of a page.

[0088] Thus, the delay time from the top signal to the itop signal is counted based on the lsync_REF signal, which has a fixed period. Therefore, the timing of writing each color image can be controlled according to the physical installation position of the image creation units 101Y to 101K.

[0089] Furthermore, the period of the line synchronization signal in the sub-scan direction for YMCK is changed in accordance with the image export timing for YMCK. In other words, the period of the line synchronization signal in the sub-scan direction is changed at the appropriate timing for each color. As a result, the magnification will not change in the middle of a page. This means that even when printing multiple pages continuously, variable magnification control in the sub-scan direction is possible.

[0090] [Example 2] As described above, the period of the lsync signal is determined by the resolution in the subscan direction. For example, if the resolution is 2400 dpi, it is not possible to correct the position of the image in the subscan direction at intervals smaller than that. Therefore, in Embodiment 2, a mechanism is disclosed in which the itop signal and lsync signal for each color are shifted at intervals shorter than the period of the lsync signal. As a result, it becomes possible to correct the positional misalignment of the image in the subscan direction with finer precision.

[0091] <Classmates> Figure 17 shows the configuration of the synchronization unit 604 in Example 2. The same reference numerals are used for components in Figure 17 that have already been described in Example 1, and their descriptions are omitted. The letters YMCK at the end of the reference numerals may be omitted when describing matters common to all four colors.

[0092] As can be seen in Figure 17, a delay circuit 1601 is added to each of the YMCK components. The itop signal output from the itop generation circuit 1202 is denoted as the pre_itop signal. The lsync signal output from the lsync generation circuit 1203 is denoted as the pre_lsync signal. The pre_itop signal and the pre_lsync signal are input to the delay circuit 1601.

[0093] The delay circuit 1601 has a register 1602 that holds the delay amount `delay` set by the CPU 603. The delay circuit 1601 outputs the `itop` signal and the `lsync` signal by delaying them by the delay amount `delay` held in register 1602. The delay amount `delay` held in register 1602 is defined by the number of cycles of the clock signal `clk`.

[0094] For example, let's assume that the periods of pre_lsyncY and pre_lsyncM correspond to 1000 cycles of the clock signal clk. Also, register 1602Y is set to 0 cycles as the delay amount delayY. Register 1602M is set to 500 cycles as the delay amount delayM. In this case, the itopM and lsyncM signals are output with a time delay equivalent to half a cycle of the lsync signal, relative to the itopY and lsyncY signals.

[0095] When the resolution in the sub-scanning direction is 2400 dpi, it becomes possible to shift the position of the Y image and the M image in the sub-scanning direction to the equivalent of 4800 dpi.

[0096] [Technical concepts derived from examples] (Perspective 1) Image formation unit 101Y is an example of a first image forming means that forms a first-color image by exposing one line at a time using a first exposure head. Image formation unit 101M is an example of a second image forming means that forms a second-color image by exposing one line at a time using a second exposure head. Image formation unit 101C is an example of a third image forming means that forms a third-color image by exposing one line at a time using a third exposure head. Image formation unit 101K is an example of a fourth image forming means that forms a fourth-color image by exposing one line at a time using a fourth exposure head. Transfer belt 111 is an example of a transfer means that forms a full-color image by sequentially transferring the first-color image, second-color image, third-color image, and fourth-color image to a sheet. Synchronization unit 604 is an example of a first generation means that generates a line period signal for each color at a period corresponding to the resolution of the image in the sub-scanning direction. CPU 603 is an example of a control means that controls the period of the line period signal according to the magnification in the sub-scanning direction for each page, and also controls the writing timing of individual images for each color. The CPU 603 and synchronization unit 604 switch the period of the line period signal for each page, based on the writing timing of individual images for each color. This makes it possible to change the magnification for each page in an image forming apparatus that forms color images. In other words, the magnification is not changed in the middle of a page. Furthermore, image distortion that occurs when changing the magnification in the sub-scanning direction of the image to be formed on the recording medium for each page is suppressed.

[0097] (Perspective 2) The lsync generation circuit 1203Y is an example of a first generation means that generates a line period signal for the first color image. The lsync generation circuit 1203M is an example of a second generation means that generates a line period signal for the second color image. The lsync generation circuit 1203C is an example of a third generation means that generates a line period signal for the third color image. The lsync generation circuit 1203K is an example of a fourth generation means that generates a line period signal for the fourth color image. The first, second, third, and fourth generation means switch the period of the line period signal based on the writing timing of the individual images for each color.

[0098] (Perspective 3) The upper controller 690 is an example of a second generation means that generates a common tip signal (e.g., the top signal) which serves as a reference for the tip in the sub-scanning direction of each page. Registers 1025Y to 1025K are an example of a holding means that holds the delay time from the output timing of the common tip signal to the image writing timing for each color. The itop generation circuit 1202 is an example of a third generation means that generates individual tip signals indicating individual writing timings for each color by applying individual delay times for each color to the output timing of the common tip signal. The first, second, third, and fourth generation means switch the period of the line period signal based on the individual tip signals for each color (e.g., itopY to itopK).

[0099] (Perspective 4) The REF generation circuit 1201 is an example of a fourth generation means that generates a reference period signal common to the first, second, third, and fourth colors. The third generation means (e.g., itop generation circuit 1202) generates individual tip signals for each color according to the delay time for each color based on the reference period signal.

[0100] (Perspective 5) CPU 603 and registers 1205Y~1205K are an example of a first setting means for setting the delay time for each color. As shown in Figure 15, the first setting means sets the delay time for each color to the third generation means after the formation of the first color image on the i-th page is complete and before the common leading edge signal of the (i+1)-th page is output.

[0101] (Perspective 6) As shown in Figure 15, the image of the first color (e.g., yellow) is formed before the images of the second color (e.g., magenta), the third color (e.g., cyan), and the fourth color (e.g., black).

[0102] (Perspectives 7, 8) The clock unit 608 is an example of a clock means for generating a clock signal (e.g., clk). The first, second, third, and fourth generating means output line period signals for each color each time the count value of the clock signal reaches a predetermined value. The first, second, third, and fourth generating means may be implemented by counter circuits. Here, the predetermined value may be a value obtained by multiplying the reference count value of the clock signal by a multiplier.

[0103] (Perspective 9) The first generating means, second generating means, third generating means, and fourth generating means may each have a first holding means (e.g., register 1301) for holding a reference count value and a second holding means (e.g., register 1302) for holding a multiplier. The CPU 603 is an example of a second setting means for setting the reference count value and the multiplier.

[0104] (Perspective 10) The predetermined value may be increased or decreased in units of the clock signal. In other words, the multiplier may be increased or decreased with each clock cycle.

[0105] (Perspective 11) The CPU 603 sets a reference count value in the first holding means of the first generating means and a magnification factor in the second holding means of the first generating means between the completion of the formation of the first color image on the i-th page and the start of the formation of the first color image on the (i+1)-th page. The CPU 603 sets a reference count value in the first holding means of the second generating means and a magnification factor in the second holding means of the second generating means between the completion of the formation of the second color image on the i-th page and the start of the formation of the second color image on the (i+1)-th page. The CPU 603 sets a reference count value in the first holding means of the third generating means and a magnification factor in the second holding means of the third generating means between the completion of the formation of the third color image on the i-th page and the start of the formation of the third color image on the (i+1)-th page. The CPU 603 sets a reference count value in the first holding means of the fourth generating means and a magnification factor in the second holding means of the fourth generating means between the completion of the formation of the fourth color image on the i-th page and the start of the formation of the fourth color image on the (i+1)-th page.

[0106] (Perspectives 12, 13) The delay circuit 1601 is an example of a first delay means that delays the individual tip signals for each color. The first delay means delays the individual tip signals for each color by a time shorter than the period of the line period signal. This makes it possible to finely adjust the tip position of the image in the sub-scanning direction.

[0107] (Perspectives 14, 15) The delay circuit 1601 is an example of a second delay means that delays the line period signal for each color. The second delay means delays the line period signal for each color by a time shorter than the period of the line period signal. This makes it possible to finely adjust the image formation position in the sub-scan direction.

[0108] (Perspective 16) For each page, the period of the line period signal is switched based on the export timing of the individual images for each color, so that the magnification of the four colors on each page matches. The magnification of the four colors are the magnification in the subscan direction of the first color image, the magnification in the subscan direction of the second color image, the magnification in the subscan direction of the third color image, and the magnification in the subscan direction of the fourth color image.

[0109] (Perspective 17) Selector 1304 is an example of a selection circuit that selects either a line period signal generated by the first generation circuit or a line period signal generated by the second generation circuit. The generation circuit 1303 is configured to generate the line period signal based on a common reference period signal. The selection circuit (e.g., selector 1304) selects the line period signal specified by the control means from among the line period signals generated by the first generation circuit or the line period signals generated by the second generation circuit.

[0110] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0111] 101Y~101K: Image creation unit, 111: Transfer belt, 603: CPU, 604: Synchronization unit

Claims

1. A first image forming means that forms a first-color image by exposing one line at a time using a first exposure head, A second image forming means that forms a second-color image by exposing one line at a time using a second exposure head, A third image forming means that forms a third-color image by exposing one line at a time using a third exposure head, A fourth image forming means that forms a fourth-color image by exposing one line at a time using a fourth exposure head, A transfer means for forming a full-color image by sequentially transferring the first color image, the second color image, the third color image, and the fourth color image onto a sheet, A first generation means generates a line period signal for each color with a period corresponding to the resolution of the image in the sub-scanning direction, It includes control means that controls the period of the line period signal according to the magnification in the sub-scanning direction for each page, and also controls the writing timing of individual images for each color, The control means is characterized by switching the period of the line period signal for each page, based on the writing timing of individual images for each color.

2. The first generating means is A first generating means for generating the line period signal for the first color image, A second generating means for generating the line period signal for the second color image, A third generating means for generating the line period signal for the third color image, The system comprises a fourth generating means for generating the line period signal for the fourth color image, The image forming apparatus according to claim 1, characterized in that the first generating means, the second generating means, the third generating means, and the fourth generating means switch the period of the line period signal based on the writing timing of individual images for each color.

3. A second generation means for generating a common leading-edge signal that serves as a reference for the leading-edge in the sub-scanning direction of each page, A holding means for holding the delay time from the output timing of the common leading edge signal to the image writing timing for each color, The system further includes a third generation means that applies the individual delay times for each color to the output timing of the common tip signal to generate individual tip signals indicating individual write timings for each color, The image forming apparatus according to claim 2, characterized in that the first generating means, the second generating means, the third generating means, and the fourth generating means switch the period of the line period signal with reference to the individual tip signals for each color.

4. The system includes a fourth generation means for generating a reference period signal common to the first color, the second color, the third color, and the fourth color, The image forming apparatus according to claim 3, wherein the third generation means generates the individual tip signals for each color according to the delay time for each color based on the reference period signal.

5. The system further includes a first setting means for setting the aforementioned delay time for each color, The image forming apparatus according to claim 3 or 4, characterized in that the first setting means sets the delay time for each color to the third generating means after the formation of the first color image on the i-th page is completed and before the common leading edge signal on the (i+1)-th page is output.

6. The image forming apparatus according to claim 5, characterized in that the first color image is formed before the second color image, the third color image, and the fourth color image.

7. The system further comprises a clock means for generating a clock signal, The image forming apparatus according to any one of claims 2 to 6, characterized in that the first generating means, the second generating means, the third generating means, and the fourth generating means output the line period signal for each color each time the count value of the clock signal reaches a predetermined value.

8. The image forming apparatus according to claim 7, characterized in that the predetermined value is a value obtained by multiplying the reference count value of the clock signal by the magnification factor.

9. The first generating means, the second generating means, the third generating means, and the fourth generating means are, A first holding means for holding the aforementioned reference count value, It has a second holding means for holding the magnification, The image forming apparatus further, The image forming apparatus according to claim 8, characterized in that it has a second setting means for setting the reference count value and the magnification.

10. The image forming apparatus according to any one of claims 7 to 9, characterized in that the predetermined value is increased or decreased in units of the clock signal.

11. The second setting means is, Between the completion of the formation of the first color image on the i-th page and the start of the formation of the first color image on the (i+1)th page, the reference count value is set in the first holding means of the first generating means, and the magnification is set in the second holding means of the first generating means. Between the completion of the formation of the second-color image on the i-th page and the start of the formation of the second-color image on the (i+1)-th page, the reference count value is set in the first holding means of the second generating means, and the magnification is set in the second holding means of the second generating means. Between the completion of the formation of the third-color image on the i-th page and the start of the formation of the third-color image on the (i+1)-th page, the reference count value is set in the first holding means of the third generating means, and the magnification is set in the second holding means of the third generating means. The image forming apparatus according to claim 9, characterized in that, between the completion of the formation of the fourth-color image on the i-th page and the start of the formation of the fourth-color image on the (i+1)-th page, the reference count value is set in the first holding means of the fourth generating means and the magnification is set in the second holding means of the fourth generating means.

12. The image forming apparatus according to any one of claims 3 to 6, further comprising a first delay means for delaying the individual tip signals for each color.

13. The image forming apparatus according to claim 12, characterized in that the first delay means delays the individual tip signals for each color by a time shorter than the period of the line period signal.

14. The image forming apparatus according to any one of claims 1 to 13, further comprising a second delay means for delaying the line period signals for each color.

15. The image forming apparatus according to claim 14, characterized in that the second delay means delays the line period signal for each color by a time shorter than the period of the line period signal.

16. The image forming apparatus according to any one of claims 1 to 5, characterized in that the control means switches the period of the line period signal for each page, based on the writing timing of the individual images for each color, so that the magnification in the sub-scanning direction of the first color image, the magnification in the sub-scanning direction of the second color image, the magnification in the sub-scanning direction of the third color image, and the magnification in the sub-scanning direction of the fourth color image match for each page.

17. The first generating means, the second generating means, the third generating means, and the fourth generating means are, It comprises a first generation circuit, a second generation circuit, and a selection circuit that selects either the line period signal generated by the first generation circuit or the line period signal generated by the second generation circuit, The first generation circuit is, A first holding means for holding the aforementioned reference count value, It has a second holding means for holding the magnification, The second generation circuit is configured to generate the line period signal based on a common reference period signal. The image forming apparatus according to claim 8, characterized in that the selection circuit selects the line period signal specified by the control means from among the line period signal generated by the first generation circuit or the line period signal generated by the second generation circuit.

Images