Semiconductor equipment

Abstract

This improves the trade-off between reverse breakdown voltage and current in semiconductor devices. [Solution] The semiconductor device 10 includes a channel layer 14, an electron supply layer 16, a first cap layer 18 provided in a first region W1 and a second region W2 on the electron supply layer 16 and made of an n-type nitride semiconductor with a larger band gap than the channel layer 14, a second cap layer 20 provided on the first cap layer 18 and made of an n-type nitride semiconductor with a smaller band gap than the first cap layer 18, a first ohmic electrode 22 provided on the second cap layer 20 in the first region W1, a second ohmic electrode 24 provided on the second cap layer 20 in the second region W2, and a Schottky electrode 26 provided in a recess 36 carved out from the upper surface of the electron supply layer 16 at a position between the first region W1 and the second region W2, and at a position away from the first region W1 and the second region W2, respectively.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device including a nitride semiconductor. [Background technology]

[0002] High electron-mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) are known as field-effect transistors capable of processing microwave signals. By connecting the gate electrode of a HEMT to one of its ohmic electrodes, it can be operated as a rectifier diode, also known as a gated anode diode (GAD). HEMTs used as rectifier diodes are required to operate normally off. To realize a normally-off HEMT, the thickness of the electron supply layer located directly beneath the gate electrode must be reduced. [Prior art documents] [Non-patent literature]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-129202 [Overview of the project] [Problems that the invention aims to solve]

[0004] In normally-off HEMTs, the trade-off between reverse breakdown voltage and current is severe, making high-voltage and high-current operation difficult.

[0005] This disclosure has been made in view of these challenges, and one of its exemplary objectives is to provide a technology that improves the trade-off between reverse breakdown voltage and current. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure includes: a channel layer made of a nitride semiconductor; an electron supply layer provided on the channel layer and made of a nitride semiconductor having a band gap larger than that of the channel layer; a first cap layer provided in a first region and a second region on the electron supply layer and made of an n-type nitride semiconductor having a band gap larger than that of the channel layer; a second cap layer provided on the first cap layer and made of an n-type nitride semiconductor having a band gap smaller than that of the first cap layer; a first ohmic electrode provided on the second cap layer in the first region; a second ohmic electrode provided on the second cap layer in the second region; and a Schottky electrode provided in a recess carved out from the upper surface of the electron supply layer at a position between the first region and the second region, and at a position away from each of the first and second regions.

[0007] Furthermore, any combination of the above components, or any substitution of the components or expressions of this disclosure between methods, systems, etc., is also valid as a form of this disclosure. [Effects of the Invention]

[0008] According to this disclosure, the trade-off between reverse breakdown voltage and current can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment. [Figure 2] This graph shows the current-voltage characteristics of the semiconductor device according to the embodiment. [Figure 3] This graph shows the conduction band energy and carrier concentration of the semiconductor device according to the example. [Figure 4] This graph shows the current-voltage characteristics of the semiconductor device in the comparative example. [Figure 5] This graph shows the conduction band energy and carrier concentration of the semiconductor device in the comparative example. [Figure 6] This diagram schematically shows the manufacturing process of a semiconductor device according to an embodiment. [Figure 7] It is a diagram schematically showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 8] It is a diagram schematically showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 9] It is a diagram schematically showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 10] It is a diagram schematically showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 11] It is a cross-sectional view schematically showing the structure of a semiconductor device according to a modified example. [Figure 12] It is a diagram schematically showing the manufacturing process of a semiconductor device according to a modified example. [Figure 13] It is a diagram schematically showing the manufacturing process of a semiconductor device according to a modified example. [Figure 14] It is a diagram schematically showing the manufacturing process of a semiconductor device according to a modified example.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate.

[0011] FIG. 1 is a diagram schematically showing the structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 includes a substrate 12, a channel layer 14, an electron supply layer 16, a first cap layer 18, a second cap layer 20, a first ohmic electrode 22, a second ohmic electrode 24, a Schottky electrode 26, and an insulating layer 28.

[0012] The semiconductor device 10 is, for example, a field effect transistor (FET), and particularly, a high electron mobility transistor (HEMT). In this case, the first ohmic electrode 22 corresponds to the drain of the HEMT, the second ohmic electrode 24 corresponds to the source of the HEMT, and the Schottky electrode 26 corresponds to the gate of the HEMT.

[0013] The semiconductor device 10 is, for example, a rectifying diode based on a HEMT. In this case, the first ohmic electrode 22 corresponds to the cathode, the second ohmic electrode 24 corresponds to the anode, and is short-circuited with the Schottky electrode 26. Such a semiconductor device 10 is also called a gated anode diode (GAD) because the anode is connected to the gate of the HEMT.

[0014] The semiconductor device 10 is a so-called gallium nitride (GaN)-based semiconductor device, and a GaN-based nitride semiconductor is used for the channel layer 14, the electron supply layer 16, the first cap layer 18, and the second cap layer 20. Here, the GaN-based nitride semiconductor is a compound represented by Al x Ga y In 1-x-y N (0 ≦ x < 1, 0 < y ≦ 1, 0 < x + y ≦ 1), and is a compound containing at least GaN.

[0015] A two-dimensional electron gas (2DEG) 30 is generated near the interface between the channel layer 14 and the electron supply layer 16. The semiconductor device 10 controls the concentration of the 2DEG 30 by a control voltage applied to the Schottky electrode 26, and controls the current flowing from the second ohmic electrode 24 toward the first ohmic electrode 22. The semiconductor device 10 is configured to operate in a normally-off state. The semiconductor device 10 is configured such that the current flowing from the second ohmic electrode 24 toward the first ohmic electrode 22 is blocked when the control voltage Vg is 0V.

[0016] The substrate 12 is made of a material suitable for crystal growth of the nitride semiconductor, and is made of silicon carbide (SiC), sapphire (Al2O3), silicon (Si), or gallium nitride (GaN). In one embodiment, the substrate 12 is a semi-insulating SiC substrate.

[0017] The channel layer 14 is a GaN-based nitride semiconductor layer provided on the substrate 12. The channel layer 14 is, for example, an undoped GaN layer or an AlGaN layer. The AlN mole fraction x1 of the channel layer 14 is, for example, 0.1 or less. In one embodiment, the channel layer 14 is a GaN layer. The thickness of the channel layer 14 is 100 nm or more and 10 μm or less. In one embodiment, the thickness of the channel layer 14 is 900 nm. A nucleation layer made of AlN may be inserted between the substrate 12 and the channel layer 14, or a GaN buffer layer doped with carbon (C) or iron (Fe) may be inserted.

[0018] The electron supply layer 16 is a GaN-based nitride semiconductor layer provided on top of the channel layer 14. The electron supply layer 16 is, for example, an undoped AlGaN layer. The AlN mole fraction x2 of the electron supply layer 16 is between 0.1 and 0.4. The electron supply layer 16 has a larger AlN mole fraction and a larger band gap than the channel layer 14. In one embodiment, the AlN mole fraction x2 of the electron supply layer 16 is 0.22.

[0019] The electron supply layer 16 has a first upper surface 32 and a second upper surface 34. The first upper surface 32 of the electron supply layer 16 is provided in the first region W1 and the second region W2. A first cap layer 18 is provided on the first upper surface 32 of the electron supply layer 16. The second upper surface 34 of the electron supply layer 16 is provided in the third region W3. The third region W3 is a different region from the first region W1 and the second region W2, and is located between the first region W1 and the second region W2. The electron supply layer 16 is provided with a recess 36 that is carved out from the second upper surface 34. The recess 36 is provided in the fourth region W4, which is separate from the first region W1 and the second region W2.

[0020] The electron supply layer 16 has a first portion 16a, a second portion 16b, and a third portion 16c. The first portion 16a is provided in the first region W1 and the second region W2 and is a portion having a first upper surface 32. The second portion 16b is provided in the third region W3 excluding the fourth region W4 and is a portion having a second upper surface 34. The third portion 16c is provided in the fourth region W4 and is a portion located under the recess 36. The thickness of each of the first portion 16a and the second portion 16b is 5 nm or more and 100 nm or less. The thickness of the second portion 16b may be the same as the thickness of the first portion 16a or may be slightly smaller than the thickness of the first portion 16a. The thickness of the third portion 16c is 1.5 nm or more and 14 nm or less. In one embodiment, the thickness of the first portion 16a is 18 nm, the thickness of the second portion 16b is 17.5 nm, and the thickness of the third portion 16c is 4.5 nm. By increasing the thicknesses of the first portion 16a and the second portion 16b, the 2DEG 30 can be accumulated in the channel layer 14 at a position different from directly under the Schottky electrode 26.

[0021] The first cap layer 18 is a GaN-based nitride semiconductor layer provided on the first upper surface 32 of the electron supply layer 16. The first cap layer 18 is provided in the first region W1 and the second region W2. The first cap layer 18 has a larger AlN molar fraction and a larger bandgap than the channel layer 14. The AlN molar fraction x3 of the first cap layer 18 is 0.1 or more and 0.4 or less. In one embodiment, the AlN molar fraction x3 of the first cap layer 18 is 0.22 and is the same as the AlN molar fraction x2 of the electron supply layer 16.

[0022] The first cap layer 18 is an n-type nitride semiconductor layer and is doped with, for example, Si as an n-type dopant. The n-type doping concentration of the first cap layer 18 is 1×10 19 / cm 3 or more and 5×10 19 / cm 3 or less, and for example, 2×10 19 / cm 3The thickness of the first cap layer 18 is between 5 nm and 10 nm. The product of the n-type doping concentration of the first cap layer 18 and the thickness of the first cap layer 18 is 5 × 10⁻¹⁰. 12 / cm 2 The above 5 x 10 13 / cm 2 The following is an example: 1.4 × 10 13 / cm 2 That is the case.

[0023] The second cap layer 20 is a GaN-based nitride semiconductor layer provided on top of the first cap layer 18. The second cap layer 20 is provided in the first region W1 and the second region W2. The second cap layer 20 has a smaller AlN mole fraction and a smaller band gap than the first cap layer 18. The AlN mole fraction x4 of the second cap layer 20 is 0.1 or less. In one embodiment, the second cap layer 20 is a GaN layer and has the same band gap as the channel layer 14.

[0024] The second cap layer 20 is an n-type nitride semiconductor layer, and for example, Si is doped as an n-type dopant. The n-type doping concentration of the second cap layer 20 is 2 × 10⁻⁶. 18 / cm 3 The above 2 x 10 19 / cm 3 For example, 5 × 10 18 / cm 3 The n-type doping concentration of the second cap layer 20 is less than that of the first cap layer 18. The thickness of the second cap layer 20 is between 30 nm and 100 nm. The product of the n-type doping concentration of the second cap layer 20 and the thickness of the second cap layer 20 is 6 × 10⁻⁶. 12 / cm 2 The above 2 x 10 14 / cm 2 The following is an example: 3 × 10 13 / cm 2 That is the case.

[0025] The first ohmic electrode 22 and the second ohmic electrode 24 are provided on the second cap layer 20. The first ohmic electrode 22 is provided on the second cap layer 20 within the first region W1. The second ohmic electrode 24 is provided on the second cap layer 20 within the second region W2. The first ohmic electrode 22 and the second ohmic electrode 24 are made of a metallic material that can make ohmic contact with the second cap layer 20. The first ohmic electrode 22 and the second ohmic electrode 24 are formed by depositing a layered structure such as Ti / Al, Ti / Al / Ni / Au, Ti / Al / Nb / Au, Ti / Al / Mo / Au, or Mo / Al / Mo / Au, and then alloying it by high-temperature treatment at 600°C to 900°C.

[0026] The Schottky electrode 26 is provided in the third region W3. The Schottky electrode 26 is provided between the first ohmic electrode 22 and the second ohmic electrode 24. The Schottky electrode 26 is made of a metallic material that makes Schottky contact with the electron supply layer 16, and is composed of a multilayer structure such as Ni / Au, Ni / Pt / Au, or Ni / Pd / Au.

[0027] The Schottky electrode 26 has a field plate structure and comprises a field plate 26a and an embedded portion 26b. The field plate 26a is provided so as to extend from the embedded portion 26b toward the first ohmic electrode 22. The field plate 26a has the function of mitigating electric field concentration between the first ohmic electrode 22 and the Schottky electrode 26 and improving the off-voltage. The field plate 26a also has the function of suppressing current collapse when an AC voltage is applied to the Schottky electrode 26. Note that the field plate 26a is not an essential component, and the Schottky electrode 26 may be configured without the field plate 26a. The embedded portion 26b penetrates the insulating layer 28 and is provided in a recess 36 carved into the electron supply layer 16.

[0028] The distance L1 from the embedded portion 26b (i.e., the recess 36) of the Schottky electrode 26 to the first region W1 affects the reverse breakdown voltage and the magnitude of the forward current of the semiconductor device 10. For example, increasing the distance L1 increases the reverse breakdown voltage, while decreasing the current, creating a trade-off relationship. The distance L1 is between 0.1 μm and 10 μm. In one embodiment, the distance L1 is 0.5 μm.

[0029] The insulating layer 28 is composed of a dielectric material containing nitrogen and silicon, and is mainly composed of silicon nitride (SiNx). The thickness of the insulating layer 28 is between 5 nm and 500 nm, for example, about 60 nm.

[0030] The insulating layer 28 covers the second cap layer 20 and the first ohmic electrode 22 or the second ohmic electrode 24 in the first region W1 and the second region W2. The insulating layer 28 covers the sides of the first cap layer 18 and the second cap layer 20 at the edge of the third region W3. The insulating layer 28 covers the second upper surface 34 of the electron supply layer 16 in the third region W3. The insulating layer 28 is not provided in the fourth region W4.

[0031] The insulating layer 28 is also positioned between the electron supply layer 16 and the field plate 26a of the Schottky electrode 26, and is formed to extend beneath the field plate 26a. The insulating layer 28 is provided so as to overlap at least a portion of the first ohmic electrode 22 and the second ohmic electrode 24. The insulating layer 28 may also be provided so as not to overlap the first ohmic electrode 22 and the second ohmic electrode 24.

[0032] The semiconductor device 10 has a double recess structure that includes a first recess in the third region W3 where the first cap layer 18 and the second cap layer 20 are removed, and a second recess which is a recess 36 provided in the fourth region W4 of the electron supply layer 16. The semiconductor device 10 differs from a wide recess structure which has a first recess but not a second recess, and also differs from a gate recess structure which has a second recess but not a first recess. According to this embodiment, by combining a wide recess structure and a gate recess structure, the trade-off between reverse breakdown voltage and current of the semiconductor device 10 can be improved.

[0033] Figure 2 is a graph showing the current-voltage characteristics of the semiconductor device 10 according to the embodiment. In this embodiment, the distance L1 shown in Figure 1 is set to 0.5 μm. A DC characteristic with a maximum current (drain current Imax or forward current If) of 0.7 A / mm was obtained when the threshold voltage Vth was 0.3 V and the reverse breakdown voltage was 70 V or higher. Furthermore, the cutoff frequency estimated from the on-resistance of 2.5 Ω mm and off-capacitance of 1.0 pF / mm is 64 GHz.

[0034] The electrical characteristics obtained in this embodiment are improved compared to the embodiment having a gate recess structure disclosed in the prior art (Japanese Patent Application Publication No. 2022-129202). In the prior art, the maximum current (drain current Imax or forward current If) is 0.5 A / mm when the threshold voltage Vth is +0.3 V and the reverse breakdown voltage is 70 V or higher, which is lower than the maximum current value obtained in this embodiment. Therefore, according to this embodiment, the trade-off between reverse breakdown voltage and current can be improved compared to the prior art. For example, the maximum current can be improved when the reverse breakdown voltage is kept constant. Also, the reverse breakdown voltage can be improved when the maximum current is kept constant.

[0035] According to this embodiment, by using an n-type nitride semiconductor as the first cap layer 18, good ohmic contact can be obtained in the first region W1 and the second region W2. Furthermore, by appropriately setting the product of the doping concentration and thickness of the first cap layer 18, good ohmic conductivity can be achieved. In one embodiment, good ohmic conductivity was obtained with a contact resistance of 0.14 Ω mm and a sheet resistance of 330 Ω / □.

[0036] Figure 3 is a graph showing the conduction band energy B1 and carrier concentration C1 of the semiconductor device 10 according to the embodiment. In Figure 3, the conduction band energy B1 is shown by a solid line, and the carrier concentration C1 is shown by a dashed line. A high-concentration peak 38, caused by 2DEG30, exists near the interface between the channel layer 14 and the electron supply layer 16.

[0037] As shown in the conduction band energy B1 in Figure 3, an electron barrier 40 exists at the position of the first cap layer 18. Since the width and height of the electron barrier 40 in this embodiment are relatively small, it is thought that the influence on carrier movement between the channel layer 14 and the second cap layer 20 is small, leading to good ohmic conduction characteristics. The width and height of the electron barrier 40 are thought to be small due to band bending caused by making the first cap layer 18 an n-type nitride semiconductor (e.g., an n-type AlGaN layer).

[0038] Furthermore, as shown in the carrier concentration C1 in Figure 3, a region 42 with a high concentration of carriers exists in the central part of the second cap layer 20. This is thought to be because increasing the thickness of the second cap layer 20 (for example, to 50 nm or more) creates a region in the second cap layer 20 where the conduction band energy is near 0 V. The carriers present in the second cap layer 20 form a current path parallel to 2DEG 30, which leads to good sheet resistance.

[0039] On the other hand, in comparative examples where an undoped nitride semiconductor (e.g., an undoped GaN layer) was used as the first capping layer, non-ohmic conductivity characteristics were observed, and good ohmic contact could not be obtained.

[0040] Figure 4 is a graph showing the current-voltage characteristics of the semiconductor device in the comparative example. Normally-off operation was obtained with a threshold voltage Vth of +0.3V and a maximum current (drain current Imax or forward current If) of 0.4A / mm, but it exhibited non-ohmic conduction characteristics.

[0041] Figure 5 is a graph showing the conduction band energy B2 and carrier concentration C2 of the semiconductor device 50 according to the comparative example. The semiconductor device 50 according to the comparative example comprises a channel layer 54 which is an undoped GaN layer, an electron supply layer 56 which is an undoped AlGaN layer, a first cap layer 58 which is an undoped GaN layer, and a second cap layer 60 which is an n-type GaN layer. The comparative example differs from the embodiment described above in that the first cap layer 58 is an undoped GaN layer. The comparative example also differs from the embodiment described above in that the thickness of the second cap layer 60 is thin, at 20 nm or less.

[0042] In Figure 5, the conduction band energy B2 is shown by a solid line, and the carrier concentration C2 is shown by a dashed line. A high-concentration peak 44, attributable to 2DEG, exists near the interface between the channel layer 54 and the electron supply layer 56.

[0043] As shown in the conduction band energy B2 of Figure 5, a peak of the electron barrier 46 exists near the interface between the electron supply layer 56 and the first cap layer 58. The electron barrier 46 is caused by a negative fixed charge generated at the interface between the electron supply layer 56 and the first cap layer 58 due to the piezoelectric effect. In the comparative example, the width and height of the electron barrier 46 are relatively large, which is thought to have a significant effect on carrier movement between the channel layer 54 and the second cap layer 60, leading to non-ohmic conduction characteristics.

[0044] On the other hand, in the embodiment shown in Figure 3, by using an n-type nitride semiconductor as the first cap layer 18, band bending can be induced, significantly reducing the width and height of the electron barrier. This makes it possible to achieve ohmic conductivity.

[0045] Furthermore, as shown in the carrier concentration C2 in Figure 5, there is no region of high carrier concentration in the second cap layer 60. This is thought to be because, due to the small thickness of the second cap layer 60, there is no region in the second cap layer 60 where the conduction band energy is sufficiently reduced. Therefore, it is thought that the comparative example did not yield a good sheet resistance.

[0046] On the other hand, in the embodiment shown in Figure 3, the thickness of the second cap layer 20 is 30 nm or more, so that a carrier-high concentration region 42 can be formed in the second cap layer 20. This makes it possible to form a current path in parallel with 2DEG 30, and good sheet resistance can be achieved.

[0047] Next, the manufacturing method of the semiconductor device 10 will be described. Figures 6 to 10 are schematic diagrams showing the manufacturing process of the semiconductor device 10 according to the embodiment.

[0048] First, as shown in Figure 6, a channel layer 14, an electron supply layer 16, a first cap layer 18, and a second cap layer 20 are sequentially stacked on the substrate 12. Each stacked layer is made of a nitride semiconductor and can be formed using known epitaxial growth methods such as metal-organic chemical vapor deposition (MOVPE).

[0049] Next, as shown in Figure 6, a first ohmic electrode 22 and a second ohmic electrode 24 are formed on the second cap layer 20. The first ohmic electrode 22 and the second ohmic electrode 24 are formed using known techniques such as vapor deposition or sputtering. The first ohmic electrode 22 and the second ohmic electrode 24 can be formed using known patterning techniques such as lift-off. The first ohmic electrode 22 and the second ohmic electrode 24 are brought into ohmic contact with the second cap layer 20 by heat treatment, for example, at 600°C to 900°C.

[0050] Next, as shown in Figure 7, a wide recess structure is formed in which the second upper surface 34 of the electron supply layer 16 is exposed by dry etching the second cap layer 20 and the first cap layer 18 at a position between the first ohmic electrode 22 and the second ohmic electrode 24. For example, a resist is formed that has an opening in the third region W3 and covers the first region W1 and the second region W2, and the wide recess structure can be formed by reactive ion etching (RIE) using a chlorine-based gas such as chlorine gas (Cl2) or boron trichloride (BCl3). The resist is removed after etching.

[0051] Next, as shown in Figure 8, an insulating layer 28 is formed to cover the second upper surface 34 of the electron supply layer 16, the first cap layer 18, the second cap layer 20, the first ohmic electrode 22, and the second ohmic electrode 24. The insulating layer 28 can be formed, for example, by a plasma chemical vapor deposition (PECVD) method using ammonia (NH3) or nitrogen (N2) as the nitrogen source and silane (SiH4) as the silicon source.

[0052] Next, as shown in Figure 9, a recess 36 is formed by dry etching the insulating layer 28 and the electron supply layer 16 in the fourth region W4, which is a part of the third region W3. The etching of the insulating layer 28 can be performed, for example, by forming a resist that has an opening in the fourth region W4 and covers the areas other than the fourth region W4, and using reactive ion etching (RIE) with a fluorine-based gas such as sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4). After etching the insulating layer 28, the resist is removed. Next, the etching of the electron supply layer 16 can be performed by reactive ion etching (RIE) using a chlorine-based gas such as chlorine gas (Cl2) or boron trichloride (BCl3), with the insulating layer 28 as a mask. This forms a gate recess structure.

[0053] Next, as shown in Figure 10, a Schottky electrode 26 is formed having a field plate 26a formed on the insulating layer 28 and an embedded portion 26b that fills the recess 36. The Schottky electrode 26 is formed using known techniques such as vapor deposition or sputtering. The Schottky electrode 26 can be formed using known patterning techniques such as lift-off.

[0054] Subsequently, the semiconductor device 10 shown in Figure 1 can be formed by etching the insulating layer 28 at the locations of the first ohmic electrode 22 and the second ohmic electrode 24 to form openings. The insulating layer 28 covering the first ohmic electrode 22 and the second ohmic electrode 24 can be removed by RIE using a fluorine-based gas such as sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4). When the semiconductor device 10 is a GAD, additional wiring is formed to connect the second ohmic electrode 24 and the Schottky electrode 26.

[0055] According to this embodiment, a semiconductor device 10 with a double recess structure that improves ohmic contact can be realized, and the trade-off between reverse breakdown voltage and current can be improved. This can contribute, for example, to increasing the current and efficiency of microwave rectifier circuits using the semiconductor device 10.

[0056] Figure 11 is a schematic cross-sectional view showing the structure of a modified semiconductor device 70. The semiconductor device 70 differs from the semiconductor device 10 in Figure 1 in that the top portion 76a of the Schottky electrode 76 is configured to be separated from the second upper surface 34 of the electron supply layer 16. The modified device will be described below, focusing on the differences from the above-described embodiment, and the commonalities with the embodiment will be omitted as appropriate.

[0057] The semiconductor device 70 comprises a substrate 12, a channel layer 14, an electron supply layer 16, a first cap layer 18, a second cap layer 20, a first ohmic electrode 22, a second ohmic electrode 24, a Schottky electrode 76, and an insulating layer 78. The substrate 12, channel layer 14, electron supply layer 16, first cap layer 18, second cap layer 20, first ohmic electrode 22, and second ohmic electrode 24 can be configured in the same manner as in the embodiments described above.

[0058] The Schottky electrode 76 has a top portion 76a and an embedded portion 76b. The top portion 76a is located away from the second upper surface 34 of the electron supply layer 16 and does not function as a field plate. The embedded portion 76b is located in a recess 36 carved into the second upper surface 34 of the electron supply layer 16.

[0059] The insulating layer 78 covers the second cap layer 20 and the first ohmic electrode 22 or the second ohmic electrode 24 in the first region W1 and the second region W2. The insulating layer 28 covers the sides of the first cap layer 18 and the second cap layer 20 at the edge of the third region W3. The insulating layer 28 covers the second upper surface 34 of the electron supply layer 16 in the third region W3 and further covers the surface of the Schottky electrode 76.

[0060] According to this modified configuration, since the top portion 76a of the Schottky electrode 76 is provided away from the second upper surface 34 of the electron supply layer 16, the parasitic capacitance can be reduced and the high-frequency gain can be improved compared to the above-described embodiment. For example, in the modified configuration in Figure 11 where the distance L1 is 0.5 μm, a DC characteristic was obtained in which the maximum current (drain current Imax or forward current If) was 0.7 A / mm at a threshold voltage Vth of 0.3 V and a reverse breakdown voltage of 40 V or higher. Furthermore, the cutoff frequency estimated from the on-resistance of 2.5 Ω mm and off-resistance of 0.1 pF / mm is 640 GHz.

[0061] Next, the manufacturing method of the semiconductor device 70 will be described. Figures 12 to 14 are schematic diagrams showing the manufacturing process of the semiconductor device 70 according to a modified example. Note that the steps in Figures 6 to 7 of the above-described embodiment are also common to the modified example.

[0062] Following the process shown in Figure 7, as shown in Figure 12, a recess 36 is formed by dry etching the electron supply layer 16 in the fourth region W4, which is a part of the third region W3. The recess 36 can be formed, for example, by forming a resist that has an opening in the fourth region W4 and covers the area other than the fourth region W4, and then performing reactive ion etching (RIE) using a chlorine-based gas such as chlorine gas (Cl2) or boron trichloride (BCl3). This forms a gate recess structure. After etching, the resist is removed.

[0063] Next, as shown in Figure 13, a Schottky electrode 76 is formed to be embedded in the recess 36. The Schottky electrode 76 is formed using known techniques such as vapor deposition or sputtering. The Schottky electrode 76 can also be formed using known patterning techniques such as lift-off.

[0064] Next, as shown in Figure 14, an insulating layer 78 is formed to cover the second upper surface 34 of the electron supply layer 16, the first cap layer 18, the second cap layer 20, the first ohmic electrode 22, the second ohmic electrode 24, and the Schottky electrode 76. The insulating layer 78 can be formed, for example, by a plasma chemical vapor deposition (PECVD) method using ammonia (NH3) or nitrogen (N2) as the nitrogen source and silane (SiH4) as the silicon source.

[0065] Subsequently, the semiconductor device 70 shown in Figure 11 can be formed by etching the insulating layer 28 at the locations of the first ohmic electrode 22 and the second ohmic electrode 24 to form openings. The insulating layer 28 covering the first ohmic electrode 22 and the second ohmic electrode 24 can be removed by RIE using a fluorine-based gas such as sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4). When the semiconductor device 70 is a GAD, additional wiring is formed to connect the second ohmic electrode 24 and the Schottky electrode 76.

[0066] The present disclosure has been described above based on embodiments. Those skilled in the art will understand that the present disclosure is not limited to the above embodiments, that various design changes are possible, and that various modifications are possible, and that such modifications are also within the scope of the present disclosure. [Explanation of symbols]

[0067] 10, 70... Semiconductor equipment, 12... Substrate, 14... Channel layer, 16... Electron supply layer, 18... First cap layer, 20... Second cap layer, 22... First ohmic electrode, 24... Second ohmic electrode, 26, 76... Schottky electrode, 28, 78... Insulating layer, 32... First top surface, 34... Second top surface.

Claims

1. A channel layer made of nitride semiconductor, An electron supply layer provided on the channel layer and composed of a nitride semiconductor with a band gap larger than that of the channel layer, A first cap layer is provided in the first and second regions on the electron supply layer and is made of an n-type nitride semiconductor with a band gap larger than that of the channel layer, A second cap layer is provided on the first cap layer and is made of an n-type nitride semiconductor having a smaller band gap than the first cap layer, A first ohmic electrode provided on the second cap layer within the first region, A second ohmic electrode provided on the second cap layer within the second region, A semiconductor device comprising: a Schottky electrode provided in a recess carved out from the upper surface of the electron supply layer, at a position between the first region and the second region, and at a position away from each of the first region and the second region.

2. The semiconductor device according to claim 1, wherein the n-type doping concentration of the first cap layer is higher than the n-type doping concentration of the second cap layer.

3. The semiconductor device according to claim 1, wherein the thickness of the first cap layer is 5 nm or more and 10 nm or less.

4. The product of the n-type dope concentration of the first cap layer and the thickness of the first cap layer is 5 × 10 １２ / cm ２ The above 5 x 10 １３ / cm ２ The semiconductor device according to claim 1, wherein the semiconductor device is as follows:

5. The semiconductor device according to claim 1, wherein the thickness of the second cap layer is 30 nm or more and 100 nm or less.

6. The product of the n-type dope concentration of the second cap layer and the thickness of the second cap layer is 6 × 10 １２ / cm ２ The above 2 x 10 １４ / cm ２ The semiconductor device according to claim 1, wherein the semiconductor device is as follows:

7. The semiconductor device according to any one of claims 1 to 6, wherein the thickness between the channel layer and the recess of the electron supply layer is 1.5 nm or more and 14 nm or less.

8. The semiconductor device according to claim 7, wherein the thickness between the channel layer and the upper surface of the electron supply layer is 5 nm or more and 100 nm or less.

9. The semiconductor device according to any one of claims 1 to 6, wherein the distance from the recess to the first cap layer in the first region is 0.1 μm or more and 10 μm or less.

10. The semiconductor device according to any one of claims 1 to 6, further comprising an insulating layer that covers the upper surface of the electron supply layer and covers the side surfaces of the first cap layer and the second cap layer.

11. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a field-effect transistor, the first ohmic electrode is a drain, the second ohmic electrode is a source, and the Schottky electrode is a gate.

12. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a diode, the first ohmic electrode is a cathode, and the second ohmic electrode, which is short-circuited with the Schottky electrode, is an anode.

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