High-frequency component testing apparatus and method thereof

Abstract

The present invention provides a high-frequency component testing apparatus and method that can reduce calibration errors. [Solution] A high-frequency component test apparatus 100 is provided, which includes a test key and a test module. The test key 105 includes a pre-key 110 and a post-key 120 that are symmetrically arranged and have the same electrical length and characteristic impedance. The test module 130 is used to measure the S-parameters of the directly connected pre-key and post-key, and the S-parameters of a structure in which the device under test (DUT) is added between the pre-key and post-key. The test module performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses the matrix root open operation and inverse matrix operation to determine the ABCD parameters of the unembedded DUT.

Description

Detailed description of the invention

[0001] (background) (Technical field) This disclosure relates in general to test equipment, and more particularly to high-frequency component test equipment and test methods thereof.

[0002] (Explanation of related technologies) Traditionally, SOLT or TRL have been primarily used for measuring and calibrating high-frequency components. SOLT requires four calibration kits: short, open, through, and load. TRL requires three sets of test keys, including through, reflect, and line keys. The above calibration techniques typically involve complex calibration procedures because they use different calibration methods depending on the specific measurement requirements (such as broadband frequencies or on-wafer probing).

[0003] Furthermore, calibration methods using SOLT and TRL are susceptible to errors occurring in each measurement, which can easily affect the calibration results. For example, differences in probing depth or misalignment of the probing position can impact the calibration results. Therefore, providing solutions that can avoid inaccurate measurements of the device under test (DUT) caused by calibration errors has become a crucial challenge for the industry.

[0004] U.S. Patent Application Publication No. 20100315115 A1, titled "METHOD OF CHARACTERIZING A SEMICONDUCTOR DEVICE," discloses a method for characterizing a semiconductor device, which includes providing a silicon-on-insulator (SOI) substrate having at least a body-tie (BT) SOI device and a BT dummy device for measurement, and measuring the tunnel current (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, respectively, determining the Igb of the floating-body (FB) SOI device by subtracting the Igb of the BT dummy device from the Igb of the BT SOI device, extracting the S-parameters of the FB SOI device by filtering the characteristics of the BT dummy device, and determining the gate-related capacitance of the FB SOI device by analyzing the S-parameters of the FB SOI device.

[0005] (overview) This disclosure is directed to a high-frequency component testing apparatus and method capable of reducing calibration errors.

[0006] According to one embodiment of the present disclosure, a high-frequency component test apparatus is provided, comprising a first test key and a test module. The first test key includes a first pre-key and a first post-key, which are symmetrically arranged and have the same electrical length and characteristic impedance. The test module is used to measure the S-parameters of the directly connected pre-key and post-key, and the S-parameters of the structure under test, in which a device under test (DUT) is added between the pre-key and post-key. The test module performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses matrix root-open and inverse operations to obtain the ABCD parameters of a non-embedded DUT.

[0007] Another embodiment of the present disclosure provides a method for testing high-frequency components. The method includes the following steps: A test key is provided, comprising a pre-key and a post-key, wherein the pre-key and post-key are symmetrically arranged and have the same electrical length and characteristic impedance. The S-parameters of the directly connected pre-key and post-key are measured, as well as the S-parameters of a structure in which the device under test (DUT) is added between the pre-key and post-key. The S-parameters are calculated in the frequency domain, the S-parameters are converted into an ABCD parameter matrix, and the ABCD parameter matrix of the pre-key and post-key is obtained by root-open operation. The ABCD parameters of a non-embedded DUT are calculated according to the inverse of the ABCD parameter matrix of the pre-key and post-key.

[0008] The above and other aspects of this disclosure will be better understood in relation to the following detailed description of preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

[0009] (Brief explanation of the drawing) Figures 1 and 2 are schematic diagrams of a high-frequency component testing apparatus according to one embodiment of the present disclosure.

[0010] Figure 3 is a flowchart of a high-frequency component testing method according to one embodiment of the present disclosure.

[0011] Figures 4A to 4D are schematic diagrams showing the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure.

[0012] Figures 5 and 6 are schematic diagrams of a high-frequency component testing apparatus according to another embodiment of the present disclosure, respectively.

[0013] Figures 7 and 8 are schematic diagrams of the second and third test keys used in a high-frequency component testing apparatus, respectively.

[0014] Figure 9 shows a flowchart of a high-frequency component testing method according to one embodiment of the present disclosure.

[0015] (Detailed explanation) Technical solutions relating to embodiments of this disclosure are clearly and thoroughly disclosed with reference to the accompanying drawings. Clearly, the embodiments disclosed below are only a selection of, and not all, embodiments of this disclosure. Furthermore, the disclosed features, structures, or properties can be combined in any preferred manner in one or more embodiments. The following disclosure provides many detailed descriptions so that the embodiments of this disclosure may be better and fully understood. However, a person of ordinary skill in the art of this disclosure will understand that the technical solutions of this disclosure may be implemented without using one or more of the specific details disclosed below, or may be implemented using other methods, devices, or steps. In some circumstances, generally known methods, devices, implementations, or operations of the technical solutions that can implement this disclosure are not necessarily illustrated or disclosed in detail, for the sake of avoiding distraction from the aspects of this disclosure.

[0016] In this embodiment, the high-frequency performance of devices such as high-frequency emitters and microwave devices is expressed by scattering parameters (S-parameters). Current S-parameter test equipment suffers from significant parasitic effects, meaning that S-parameters obtained from insufficiently tested high-frequency components cannot accurately represent the component's performance. Therefore, in this embodiment, as shown in Figure 2, a test key is provided to define the non-embedded surface 101 of the high-frequency component, i.e., the surface between the intrinsic component (DUT102) and the parasitic component (test equipment 100). By eliminating the parasitic effects generated by the test equipment in high-frequency operating conditions, accurate intrinsic transmission parameters can be obtained.

[0017] Referring to Figures 1 and 2, schematic diagrams of a high-frequency component test apparatus 100 according to one embodiment of the present disclosure are shown, respectively. In Figure 1, the high-frequency component test apparatus 100 includes a test key 105 and a test module 130. The test key 105 includes a pre-key 110 and a post-key 120. The pre-key 110 and the post-key 120 are arranged symmetrically and have the same electrical length and characteristic impedance. In one embodiment, the pre-key 110 and the post-key 120 have, exemplary, a characteristic impedance of 50 Ω, but the present disclosure is not limited thereto. The pre-key 110 and the post-key 120 can be arranged according to a ground-signal-ground (GSG) configuration. In another embodiment, the pre-key 110 and the post-key 120 can be arranged according to a ground-signal (GS) configuration, a ground-signal-ground-signal-ground (GSGSG) configuration, or other suitable test configuration. The test module 130 can be a network analyzer.

[0018] The front key 110 includes the first transmission line 112. The rear key 120 includes the second transmission line 122. The first transmission line 112 and the second transmission line 122 have the same electrical length and material so that the transmission parameters of the front and rear sides are substantially identical. In Figure 2, the DUT 102 is connected between the two transmission lines 112 and 122. Non-recessed surfaces 101 are formed between the DUT 102 and the first transmission line 112, and between the DUT 102 and the second transmission line 122 (the non-recessed surfaces 101 are perpendicular to the plane of the paper), so that the DUT 102 is connected between the two non-recessed surfaces 101. The left and right structures of the non-recessed surfaces 101 each have their own intrinsic transmission parameters. The intrinsic transmission parameters of the DUT 102 can be estimated according to the intrinsic transmission parameters of the left and right structures and the transmission parameters of the structure under test. In one embodiment, the intrinsic transmission parameters are represented, for example, by ABCD parameters.

[0019] In this embodiment, the parameter conversion module converts S parameters into ABCD parameters. When the front-stage key 110 and the rear-stage key 120 are directly connected, the S parameters can be represented by ABCD parameters such as a parameter matrix.

[0020] [Number]

[0021] For example, when the front-stage key 110 and the rear-stage key 120 are directly connected, the total voltage V1 and the total current I1 are input to one end of the two-port network, and the total voltage V2 and the total current I2 are output from the other end of the two-port network. Here, V1 = AV2 + BI2, I1 = CV2 + DI2.

[0022] [Number]

[0023] That is. Here, the relationship between the input voltage V1, the output voltage V2, the input current I1, and the output current I2 is represented by the parameters A, B, C, and D.

[0024] The test module 130 of this embodiment can obtain the ABCD parameters of the front-stage key 110 and the rear-stage key 120 according to the root open operation of the ABCD parameter matrix, and the calculation formula (1) can be expressed as follows.

[0025] [Dem]=[PAD][PAD] Here, [PAD] is the ABCD parameter matrix of the preceding key 110 and the succeeding key 120, and [Dem] is the ABCD parameter matrix when the preceding key 110 and the succeeding key 120 are directly connected. In this embodiment, since the preceding key 110 and the succeeding key 120 have the same electrical length and characteristic impedance, the preceding key 110 and the succeeding key 120 have the same ABCD parameter matrix. Therefore, the ABCD parameter matrix [PAD] of the preceding key 110 and the succeeding key 120 can be obtained by performing a root-open operation on the ABCD parameter matrices [Dem] of the two directly connected keys 110 and 120 according to the following equation (1).

[0026]

number

[0027] Please also refer to Figure 2. When the device under test (DUT) 102 is added between the pre-key 110 and the post-key 120, the test module 130 measures the S-parameters of the structure under test to which the DUT 102 has been added between the pre-key 110 and the post-key 120. The test module 130 then converts the S-parameters into ABCD parameters and, according to the inverse matrix, determines the ABCD parameters of the non-embedded DUT 102. Formula (2) is expressed as follows.

[0028] [DUT]=[PAD][Golden][PAD], where [Golden] is the ABCD parameter matrix of the unembedded DUT102, and [DUT] is the ABCD parameter matrix when the pre-key 110 and post-key 120 are directly connected to DUT102. Based on equation (2), [Golden]=[PAD] -1 [DUT][PAD] -1 , Here [PAD] -1 This is the inverse of the ABCD parameter matrix of the preceding key 110 and the succeeding key 120. That is,

[0029]

number

[0030] That is the case.

[0031] In this embodiment, with only one set of non-embedded test keys, the high-frequency component test apparatus 100 can eliminate parasitic effects caused by extraneous layout and traces resulting from the measurement, thereby improving the non-embedded test speed and accuracy, as well as reducing probing errors.

[0032] Please refer to Figures 1-3. Figure 3 is a flowchart of a high-frequency component test method according to one embodiment of the present disclosure. First, in step S30, a test key 105 containing a pre-stage key 110 and a post-stage key 120 is provided, and the pre-stage key 110 and the post-stage key 120 are arranged symmetrically and have the same electrical length and characteristic impedance. In step S32, the S-parameters of the state in which the pre-stage key 110 and the post-stage key 120 are directly connected and the S-parameters of the structure in which the device under test (DUT) 102 is added between the pre-stage key 110 and the post-stage key 120 are measured. In step S34, the S-parameters are calculated in the frequency domain, the S-parameters are converted into an ABCD parameter matrix, and the ABCD parameter matrix of the pre-stage key 110 and the post-stage key 120 is obtained by root-open operation. In step S36, the ABCD parameters of the unembedded DUT 102 are calculated according to the inverse matrix of the ABCD parameter matrix of the pre-stage key 110 and the post-stage key 120.

[0033] Referring to Figures 4A to 4D, schematic diagrams illustrating the characteristic verification of the S-parameters of a high-frequency component test apparatus 100 according to one embodiment of the present disclosure are shown. In Figure 4A, the S(1,1) parameter is the input reflection coefficient, i.e., the input return loss. In Figure 4B, the S(1,2) parameter is the reverse transmission coefficient, i.e., the isolation. In Figure 4C, the S(2,1) parameter is the forward transmission coefficient, i.e., the gain. In Figure 4D, the S(2,2) parameter is the output reflection coefficient, i.e., the output return loss. In this embodiment, the feasibility and characteristics of the S-parameters are verified using simulation, and a comparison of the simulation model curve, the DUT model curve, and the unembedded model curve shows that by using the unembedded procedure of this embodiment, intrinsic transmission parameters close to those of the DUT 102 can be obtained. The simulation is performed until the curve fitting error for a 100 GHz small signal is less than 10%. In another embodiment, when verification is performed using a transmit key and a test key, the simulation is performed until the error between the characteristic impedance Z0 and the transmission line length βL of the 67 GHz small signal phase is 8% or less.

[0034] According to the high-frequency component test apparatus and test method disclosed in the above embodiments of this disclosure, only one test key is used as the calibration kit, and the pre- and post-test keys have the same electrical length and characteristic impedance, and the characteristic impedance is the same as the impedance of the probe, 50Ω, thus avoiding inaccurate measurements of the DUT due to calibration errors. Compared to conventional measurement and calibration of high-frequency components that mainly use SOLT or TRL, the method of this embodiment can reduce the calibration step, eliminate parasitic effects caused by high-frequency operating conditions and test devices, and obtain accurate S-parameters.

[0035] Referring to Figures 5 and 6, schematic diagrams of a high-frequency component test apparatus 101 according to another embodiment of the present disclosure are shown, respectively. In Figure 5, the high-frequency component test apparatus 101 includes a first test key 105 and a test module 130. The first test key 105 includes a first pre-key 110 and a first post-key 120. The first pre-key 110 and the first post-key 120 are arranged symmetrically and have the same electrical length and characteristic impedance. In one embodiment, the first pre-key 110 and the first post-key 120 have, exemplary, a characteristic impedance of 50 Ω, but the present disclosure is not limited thereto. The first pre-key 110 and the first post-key 120 can be arranged according to a GSG configuration, a GSGSG configuration, or other suitable test configuration. The test module 130 can be a network analyzer.

[0036] The first pre-stage key 110 may include a first transmission line 112. The first post-stage key 120 may include a second transmission line 122. The first transmission line 112 and the second transmission line 122 have the same electrical length and material such that the transmission parameters on the front and back sides are substantially identical. In Figure 6, the DUT 102 is connected between the first pre-stage key 110 and the first post-stage key 120. The intrinsic transmission parameters of the DUT 102 can be estimated according to the intrinsic transmission parameters of the left and right structures and the transmission parameters of the structure under test. In an embodiment, the intrinsic transmission parameters are represented, for example, by ABCD parameters.

[0037] In this embodiment, the parameter conversion module converts S parameters to ABCD parameters, and when the first pre-key 110 and the first post-key 120 are directly connected, the S parameters can be represented by ABCD parameters as shown in the parameter matrix below.

[0038]

number

[0039] For example, if the first pre-stage key 110 and the first post-stage key 120 are directly connected, the total voltage V1 and total current I1 are input to one end of the 2-port network, and the total voltage V2 and total current I2 are output from the other end of the 2-port network, where V1 = AV2 + BI2, I1 = CV2 + DI2, i.e.,

[0040]

number

[0041] Here, the relationship between the input voltage V1, output voltage V2, input current I1, and output current I2 is expressed by parameters A, B, C, and D.

[0042] The test module 130 of this embodiment can determine the ABCD parameters of the first pre-key 110 and the first post-key 120 according to the root-open operation of the ABCD parameter matrix, and the calculation formula (1') can be expressed as follows.

[0043] [Dem1]=[PAD][PAD] Here, [PAD] is the ABCD parameter matrix of the first pre-key 110 and the first post-key 120, and [Dem1] is the ABCD parameter matrix when the first pre-key 110 and the first post-key 120 are directly connected. In this embodiment, since the first pre-key 110 and the first post-key 120 have the same electrical length and characteristic impedance, the first pre-key 110 and the first post-key 120 have the same ABCD parameter matrix. Therefore, the ABCD parameter matrix [PAD] of the first pre-key 110 and the first post-key 120 can be obtained by performing a root-open operation on the ABCD parameter matrix [Dem1] of the two directly connected keys 110 and 120 according to equation (1'), and is expressed by the following equation.

[0044]

number

[0045] See also Figure 6. When the device under test (DUT) 102 is added between the first pre-key 110 and the first post-key 120, the test module 130 measures the S-parameters of the structure in which the DUT 102 is added between the first pre-key 110 and the first post-key 120. The test module 130 then converts the S-parameters into ABCD parameters and, according to the inverse matrix, determines the ABCD parameters of the unembedded DUT 102. Formula (2) is expressed as follows.

[0046] [DUT]=[PAD][Golden][PAD] [Golden] is the ABCD parameter matrix for the unembedded DUT102, and [DUT] is the ABCD parameter matrix when the first pre-key 110 and the first post-key 120 are directly connected to DUT102. Based on equation (2), [Golden] = [PAD] -1 [DUT][PAD] -1 [PAD] -1 This is the inverse of the ABCD parameter matrix of the first pre-key 110 and the first post-key 120, i.e.,

[0047]

number

[0048] That is the case.

[0049] In one embodiment, the high-frequency component testing apparatus 101, in a non-embedded testing method, uses the first test key 105 to eliminate parasitic effects of extraneous layout and traces caused by the measurement, thereby improving the speed and accuracy of the non-embedded testing as well as reducing probing errors. Furthermore, the high-frequency component testing apparatus 101 verifies whether the inverse matrices of the ABCD parameter matrices of the first pre-key 110 and the first post-key 120 are correct by measuring the ABCD parameter matrices of the second test key 205 and the third test key 305, thereby correctly calculating the ABCD parameters of the non-embedded DUT 102.

[0050] Referring to Figures 7 and 8, schematic diagrams of the second test key 205 and the third test key 305 used in the high-frequency component test apparatus 101 are shown, respectively. The second test key 205 includes a second pre-key 210, a first line segment 212, and a second post-key 220 connected to each other. The second pre-key 210 and the second post-key 220 have the same electrical length and characteristic impedance (e.g., 50 Ω). The second pre-key 210 and the second post-key 220 are arranged according to, for example, a GSG, GGSSG, or other suitable test configuration. Furthermore, the third test key 305 includes a third pre-key 310, a second line segment 312, and a third post-key 320 connected to each other. The third pre-key 310 and the third post-key 320 have the same electrical length and characteristic impedance (e.g., 50 Ω). The third pre-key 310 and the third post-key 320 are arranged, for example, according to a GSG, GGSSG, or other suitable test configuration.

[0051] In one embodiment, the first test key 105, the second test key 205, and the third test key 305 are, for example, coplanar waveguides (CPWs) or microstrip lines, and each transmission line of the first to third test keys has the same characteristic impedance (e.g., 50Ω). Furthermore, the length L2 of the second line segment 312 is, for example, twice the length L1 of the first line segment 212, i.e., L2 = 2 × L1. In one embodiment, the second line segment 312 may be formed by two first line segments 212 connected to each other, or it may consist of a single line segment.

[0052] Please refer to Figures 5 to 9. Figure 9 shows a flowchart of a high-frequency component test method according to one embodiment of the present disclosure. First, in step S91, a first test key 105, a second test key 205, and a third test key 305 are provided. The first test key 105 includes a first pre-key 110 and a first post-key 120 which are directly connected, and the second test key 205 includes a second pre-key 210, a first line segment 212, and a second post-key 220 which are directly connected. The first line segment 212 is electrically connected between the second pre-key 210 and the third post-key 220. The third test key 305 includes a third pre-key 310, a second line segment 312, and a third post-key 320 which are directly connected. The second line segment 312 is electrically connected between the third pre-stage key 310 and the third post-stage key 320, and the length L2 of the second line segment 312 is twice the length L1 of the first line segment 212. In step S92, the S-parameters are measured for the state in which the first pre-stage key 110 and the first post-stage key 120 are directly connected, the S-parameters are measured for the state in which the second pre-stage key 210, the first line segment 212, and the second post-stage key 220 are directly connected, the S-parameters are measured for the state in which the third pre-stage key 310, the second line segment 312, and the third post-stage key 320 are directly connected, and the S-parameters are measured for the structure in which the DUT 102 is added between the first pre-stage key 110 and the first post-stage key 120. In step S93, S-parameter calculations are performed in the frequency domain, and the S-parameters of the first test key 105 are converted into an ABCD parameter matrix. Then, the ABCD parameter matrices of the first pre-key 110 and the first post-key 120 are obtained using the root open operation as described above, and can be obtained from the following equation (1').

[0053]

number

[0054] In step S94, the S parameter of the second test key 205 is converted into an ABCD parameter matrix, the S parameter of the third test key 305 is converted into an ABCD parameter matrix, and it is verified whether the ABCD parameter matrix of the second line segment 312 of the third test key 305 is equal to the product of the two ABCD parameter matrices of the first line segment 212 of the second test key 205. In step S95, the ABCD parameters of the non-embedded DUT 102 are calculated according to the inverse matrices of the ABCD parameter matrices of the first front-stage key 110 and the first rear-stage key 120.

[0055] In step S94, [PAD] is the ABCD parameter matrix of the second front-stage key 210 and the second rear-stage key 220, [Line1] is the ABCD parameter matrix of the first line segment 212, [Dem2] is the ABCD parameter matrix of the directly connected second front-stage key 210, the first line segment 212, and the second rear-stage key 220, and the calculation formula (3) is expressed as follows.

[0056] [Dem2]=[PAD][Line][PAD] Based on this calculation formula (3), [Line1]=[PAD] -1 [Dem2][PAD] -1 is obtained. Here, [PAD] -1 is the inverse matrix of the ABCD parameter matrices of the second front-stage key 210 and the second rear-stage key 220.

[0057] Also, in step S94, [PAD] is the ABCD parameter matrix of the third front-stage key 310 and the third rear-stage key 320, [Line2] is the ABCD parameter matrix of the second line segment 312, [Dem3] is the ABCD parameter matrix directly connecting the third front-stage key 310, the second line segment 312, and the third rear-stage key 320, and the calculation formula (4) is expressed as follows.

[0058] [Dem3]=[PAD][Line2][PAD] Also, based on the calculation formula (4), [Line2]=[PAD] -1 -1[Dem3][PAD] -1 This is required. Here, [PAD] -1 This is the inverse matrix of the ABCD parameter matrix of the third pre-key 310 and the third post-key 320.

[0059] In step S94, when the test module 130 verifies that the ABCD parameter matrix of the second line segment 312 in the third test key 305 is equal to the product of the two ABCD parameter matrices of the first line segment 212, that is, when [Line2]=[Line1][Line1] is satisfied, the inverse matrix [PAD] of the ABCD parameter matrices of the first pre-key 110 and the first post-key 120 is obtained. -1 This indicates that the ABCD parameter matrices of the first pre-key 110 and the first post-key 120 are correct. Conversely, if [Line2]=[Line1][Line1] is not satisfied, then the inverse matrix [PAD] of the ABCD parameter matrices of the first pre-key 110 and the first post-key 120 is correct. -1 The ABCD parameter matrix for the non-embedded DUT102 cannot be correctly calculated, indicating that the result is incorrect.

[0060] In step S95, [Golden] is the ABCD parameter matrix of the unembedded DUT102, and [DUT] is the ABCD parameter matrix of the directly connected first pre-key 110, DUT102, and first post-key 120. Formula (2) is: [DUT]=[PAD][Golden][PAD] It is expressed as follows. Based on formula (2), [Golden] = [PAD] -1 [DUT][PAD] -1 This is required. Here, [PAD] -1 This is the inverse of the ABCD parameter matrix of the first pre-key 110 and the first post-key 120, i.e.,

[0061]

number

[0062] That is the case.

[0063] The inverse matrix [PAD] of the ABCD parameter matrices of the first pre-key 110 and the first post-key 120. -1 Once this is verified to be correct, the ABCD parameter matrix of the unembedded DUT102 can be calculated correctly.

[0064] The high-frequency component testing apparatus 101 of this disclosure can avoid measurement errors in the DUT caused by calibration errors by the verification method described above. For example, during W-band operation (in the range of 75 to 110 GHz, etc.), calibration errors caused by differences in probing depth or deviations in probing position can be prevented, resulting in better measurement results for the DUT.

[0065] While this disclosure has described preferred embodiments (one or more) as examples, it should be understood that this disclosure is not limited thereto. Rather, this disclosure is intended to cover a variety of modifications and similar arrangements and procedures, and therefore the appended claims should be given the broadest possible interpretation to encompass all such modifications and similar arrangements and procedures. [Brief explanation of the drawing]

[0066] [Figure 1] This is a schematic diagram of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 2] This is a schematic diagram of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 3] This is a flowchart of a high-frequency component testing method according to one embodiment of the present disclosure. [Figure 4A] This is a schematic diagram illustrating the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 4B] This is a schematic diagram illustrating the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 4C] This is a schematic diagram illustrating the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 4D]This is a schematic diagram illustrating the characteristics verification of a high-frequency component testing apparatus according to one embodiment of the present disclosure. [Figure 5] This is a schematic diagram of a high-frequency component testing apparatus according to another embodiment of the present disclosure. [Figure 6] This is a schematic diagram of a high-frequency component testing apparatus according to another embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the second and third test keys used in high-frequency component testing equipment. [Figure 8] This is a schematic diagram of the second and third test keys used in high-frequency component testing equipment. [Figure 9] A flowchart of a high-frequency component testing method according to one embodiment of this disclosure is shown.

Claims

1. A first test key includes a first front-level key and a first back-level key, which are symmetrically arranged and have the same electrical length and characteristic impedance. The system comprises a test module used to measure the S-parameters of the directly connected first pre-key and first post-key, and the S-parameters of a structure under test in which a device under test (DUT) is added between the first pre-key and the first post-key, The aforementioned test module is a high-frequency component test apparatus that performs S-parameter calculations in the frequency domain, converts the S-parameters into an ABCD parameter matrix, and uses matrix root open operations and inverse matrix operations to obtain the ABCD parameters of a non-embedded DUT.

2. The second test key is further equipped, The test apparatus according to claim 1, wherein the second test key includes a directly connected second pre-key, a first line segment, and a second post-key, and the first line segment is electrically connected between the second pre-key and the second post-key.

3. The third test key is further equipped, The test apparatus according to claim 2, wherein the third test key includes a directly connected third pre-key, a second line segment, and a third post-key, the second line segment is electrically connected between the third pre-key and the third post-key, and the length of the second line segment is twice the length of the first line segment.

4. [PAD] is the ABCD parameter matrix of the first pre-key and the first post-key, [Dem1] is the ABCD parameter matrix when the first pre-key and the first post-key are directly connected, [Dem1] = [PAD] [PAD], The ABCD parameter matrices of the first pre-key and the first post-key are: [Math 1] The test apparatus according to claim 3, as expressed as follows.

5. [PAD] is the ABCD parameter matrix of the second pre-key and the second post-key, [Line1] is the ABCD parameter matrix of the first line segment, [Dem2] is the ABCD parameter matrix when the second pre-key, the first line segment, and the second post-key are directly connected, The test apparatus according to claim 4, wherein [Dem2] = [PAD] [Line1] [PAD].

6. [PAD] is the ABCD parameter matrix of the third pre-key and the third post-key, [Line2] is the ABCD parameter matrix of the second line segment, [Dem3] is the ABCD parameter matrix when the third pre-key, the second line segment, and the third post-key are directly connected. The test apparatus according to claim 5, wherein [Dem3] = [PAD] [Line2] [PAD].

7. The test module verifies that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment. The ABCD parameter matrix of the second line segment in the third test key is: The test apparatus according to claim 6, wherein [Line2] = [Line1] [Line1].

8. [Golden] is the ABCD parameter matrix of the non-embedded DUT, [DUT] is the ABCD parameter matrix when the first pre-key, the DUT, and the first post-key are directly connected. [DUT] = [PAD] [Golden] [PAD], The ABCD parameter matrix of the non-embedded DUT is calculated according to the inverse of the ABCD parameter matrix of the first pre-key and the first post-key. [Golden] = [PAD] －１ [DUT] [PAD] －１ The test apparatus according to claim 7, as expressed in the following way.

9. A step of supplying a first test key, a second test key, and a third test key, wherein the first test key includes a directly connected first pre-stage key and a first post-stage key, the pre-stage key and the post-stage key are arranged symmetrically and have the same electrical length and characteristic impedance; the second test key includes a directly connected second pre-stage key, a first line segment, and a second post-stage key, the first line segment is electrically connected between the second pre-stage key and the second post-stage key; the third test key includes a directly connected third pre-stage key, a second line segment, and a third post-stage key, the second line segment is electrically connected between the third pre-stage key and the third post-stage key, and the length of the second line segment is twice the length of the first line segment; A step of measuring the S-parameters of the directly connected first pre-key and first post-key, the S-parameters of the directly connected second pre-key, first line segment, and second post-key, the S-parameters of the directly connected third pre-key, second line segment, and third post-key, and the S-parameters of a structure in which a device under test (DUT) is added between the first pre-key and the first post-key, The process involves performing S-parameter calculations in the frequency domain, converting the S-parameters into an ABCD parameter matrix, and obtaining the ABCD parameter matrix of the first pre-key and the first post-key using a root open operation. A step of verifying that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment in the second test key, A step of calculating the ABCD parameters of the unembedded DUT according to the inverse matrix of the ABCD parameter matrices of the first pre-key and the first post-key, A high-frequency component testing method, including the following.

10. The test method according to claim 9, wherein the first test key, the second test key, and the third test key have the same characteristic impedance.

11. [PAD] is the ABCD parameter matrix of the first pre-key and the first post-key, [Dem1] is the ABCD parameter matrix when the first pre-key and the first post-key are directly connected, [Dem1] = [PAD] [PAD], The ABCD parameter matrix of the first pre-key and the first post-key is, [Math 2] The test method according to claim 9, expressed as follows.

12. [PAD] is the ABCD parameter matrix of the second pre-key and the second post-key, [Line1] is the ABCD parameter matrix of the first line segment, [Dem2] is the ABCD parameter matrix when the second pre-key, the first line segment, and the second post-key are directly connected, The test method according to claim 11, wherein [Dem2] = [PAD] [Line1] [PAD].

13. [PAD] is the ABCD parameter matrix of the third pre-key and the third post-key, [Line2] is the ABCD parameter matrix of the second line segment, [Dem3] is the ABCD parameter matrix when the third pre-key, the second line segment, and the third post-key are directly connected, The test method according to claim 12, wherein [Dem3] = [PAD] [Line2] [PAD].

14. It was verified that the ABCD parameter matrix of the second line segment in the third test key is equal to the product of the two ABCD parameter matrices of the first line segment. The ABCD parameter matrix of the second line segment in the third test key is: The test method according to claim 13, wherein [Line2] = [Line1] [Line1].

15. [Golden] is the ABCD parameter matrix of the unembedded DUT, [DUT] is the ABCD parameter matrix when the first pre-key, the DUT, and the first post-key are directly connected. [DUT] = [PAD] [Golden] [PAD], The ABCD parameter matrix of the non-embedded DUT is calculated according to the inverse of the ABCD parameter matrix of the first pre-key and the first post-key. [Golden] = [PAD] －１ [DUT] [PAD] －１ The test method according to claim 14, expressed as follows.

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