Image sensor and imaging device

Abstract

The image sensor comprises a first semiconductor substrate having a first photoelectric conversion unit that converts light into electric charge and a second photoelectric conversion unit that converts light into electric charge; a second semiconductor substrate laminated with the first semiconductor substrate, having a drive unit that outputs a control signal to the first semiconductor substrate to control the storage time for storing the charge converted by the first photoelectric conversion unit and the storage time for storing the charge converted by the second photoelectric conversion unit to be different storage times; and a plurality of junctions that electrically connect the first semiconductor substrate and the second semiconductor substrate, each having conductive members arranged to face each other in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked. [Effect] By configuring the connection section redundantly, the possibility of causing pixel defects due to poor bonding can be reduced. The drive unit can independently control charge accumulation for the photometric pixels.

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] Conventionally, an imaging device is known that controls a circuit connected to a photodiode by a control signal to read out pixel signals. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

Summary of the Invention

[0003] The imaging device according to the first aspect of the present invention includes a first semiconductor substrate having a first photoelectric conversion unit that converts light into charges and a second photoelectric conversion unit that converts light into charges, and a semiconductor substrate laminated on the first semiconductor substrate. A second semiconductor substrate having a driving unit that outputs a control signal for controlling the accumulation time for accumulating the charges converted by the first photoelectric conversion unit and the accumulation time for accumulating the charges converted by the second photoelectric conversion unit to be different accumulation times to the first semiconductor substrate, and a conductive member disposed so as to face each other in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked, and a plurality of joint portions that electrically connect the first semiconductor substrate and the second semiconductor substrate.

[0004] [[ID=z29]]The imaging apparatus according to the second aspect of the present invention includes the above-described imaging device.

[0005] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0006] [Figure 1] It is a cross-sectional view of a back-illuminated MOS type imaging device according to the present embodiment. [Figure 2] It is a diagram for explaining the pixel arrangement and unit group of an imaging chip. [Figure 3] This is a circuit diagram corresponding to a unit group of imaging chips. [Figure 4] This is a block diagram showing the functional configuration of an image sensor. [Figure 5] This is a block diagram showing the configuration of the imaging device according to this embodiment. [Figure 6] This is a diagram illustrating an example scene and its subdivision. [Figure 7] This diagram illustrates the control of charge accumulation in each divided region. [Figure 8] This figure shows the relationship between the number of cumulative operations and the dynamic range. [Figure 9] A flowchart illustrating the processing of the shooting operation. [Figure 10] This block diagram shows a specific configuration as an example of a signal processing chip. [Figure 11] This is an explanatory diagram illustrating the flow of pixel signals transmitted from the imaging chip to the signal processing chip. [Modes for carrying out the invention]

[0007] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] Figure 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. These imaging chip 113, signal processing chip 111, and memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like.

[0009] As shown in the figure, the incident light mainly enters in the Z-axis positive direction, indicated by the white arrow. In this embodiment, the side of the imaging chip 113 that the incident light enters is referred to as the back surface. Also, as shown in the coordinate axes, the direction to the left of the paper perpendicular to the Z-axis is the X-axis positive direction, and the direction towards the front of the paper perpendicular to the Z-axis and X-axis is the Y-axis positive direction. In some of the following figures, the coordinate axes are displayed with the coordinate axes of Figure 1 as the reference point, so that the orientation of each figure can be seen.

[0010] An example of an imaging chip 113 is a back-illuminated MOS image sensor. The PD layer 106 is located on the back side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged in two dimensions, and transistors 105 provided corresponding to the PDs 104.

[0011] A color filter 102 is provided on the incident light side of the PD layer 106 via a passivation film 103. The color filter 102 has multiple types that transmit different wavelength regions and has a specific arrangement corresponding to each PD 104. The arrangement of the color filter 102 will be described later. A set of color filter 102, PD 104, and transistor 105 forms one pixel.

[0012] Microlenses 101 are provided on the incident light side of the color filter 102, corresponding to each pixel. The microlenses 101 focus the incident light toward the corresponding PD 104.

[0013] The wiring layer 108 has wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and may also be provided with passive and active elements.

[0014] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed or the like, so that the aligned bumps 109 are joined to each other and electrically connected.

[0015] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressed or the like, so that the aligned bumps 109 are joined to each other and electrically connected.

[0016] Note that the joining between the bumps 109 is not limited to Cu bump joining by solid-phase diffusion, and micro bump bonding by solder melting may also be employed. Further, one bump 109 may be provided for, for example, one pixel group described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD104. Also, in the peripheral region other than the pixel region where the pixels are arranged, larger bumps than the bumps 109 corresponding to the pixel region may be provided together.

[0017] The signal processing chip 111 has TSVs (through-silicon vias) 110 that connect the circuits provided on the front and back surfaces to each other. The TSVs 110 are preferably provided in the peripheral region. Also, the TSVs 110 may be provided in the peripheral region of the imaging chip 113 and the memory chip 112.

[0018] FIG. 2 is a diagram for explaining the pixel arrangement and the unit group 131 of the imaging chip 113. In particular, it shows a state of observing the imaging chip 113 from the back side. More than 20 million pixels are arranged in a matrix in the pixel region. In the present embodiment, 16 pixels of 4 adjacent pixels × 4 pixels form one group. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form the unit group 131.

[0019] As shown in the partial enlarged view of the pixel region, the unit group 131 includes four pixels of green pixels Gb and Gr, a blue pixel B, and a red pixel R, which are arranged in a so-called Bayer array, and four of them are included in the vertical and horizontal directions. The green pixel is a pixel having a green filter as the color filter 102, and receives light in the green wavelength band of the incident light. Similarly, the blue pixel is a pixel having a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel is a pixel having a red filter as the color filter 102 and receives light in the red wavelength band.

[0020] FIG. 3 is a circuit diagram corresponding to the unit group 131 of the imaging chip 113. In the figure, a rectangle typically surrounded by a dotted line represents a circuit corresponding to one pixel. At least a part of each transistor described below corresponds to the transistor 105 in FIG. 1.

[0021] As described above, the unit group 131 is formed of 16 pixels. The 16 PDs 104 corresponding to each pixel are respectively connected to the transfer transistors 302, and each gate of each transfer transistor 302 is connected to the TX wiring 307 to which a transfer pulse is supplied. In the present embodiment, the TX wiring 307 is commonly connected to the 16 transfer transistors 302.

[0022] The drain of each transfer transistor 302 is connected to the source of the corresponding reset transistor 303, and a so-called floating diffusion FD between the drain of the transfer transistor 302 and the source of the reset transistor 303 is connected to the gate of the amplification transistor 304. The drain of the reset transistor 303 is connected to the Vdd wiring 310 to which a power supply voltage is supplied, and its gate is connected to the reset wiring 306 to which a reset pulse is supplied. In the present embodiment, the reset wiring 306 is commonly connected to the 16 reset transistors 303.

[0023] The drain of each amplification transistor 304 is connected to the Vdd wiring 310 to which the power supply voltage is supplied. The source of each amplification transistor 304 is connected to the drain of the corresponding selection transistor 305. The gate of each selection transistor is connected to the decoder wiring 308 to which the selection pulse is supplied. In this embodiment, the decoder wiring 308 is provided independently for each of the 16 selection transistors 305. The source of each selection transistor 305 is connected to a common output wiring 309. The load current source 311 supplies current to the output wiring 309. That is, the output wiring 309 for the selection transistors 305 is formed by a source follower. The load current source 311 may be provided on the imaging chip 113 side or on the signal processing chip 111 side.

[0024] Here, we will explain the flow from the start of charge accumulation to the pixel output after the accumulation is complete. When a reset pulse is applied to the reset transistor 303 through the reset wiring 306, and at the same time a transfer pulse is applied to the transfer transistor 302 through the TX wiring 307, the potentials of PD104 and floating diffusion FD are reset.

[0025] When the transfer pulse is released, PD104 converts the received incident light into charge and stores it. Subsequently, when a transfer pulse is applied again without a reset pulse being applied, the stored charge is transferred to the floating diffusion FD, and the potential of the floating diffusion FD changes from the reset potential to the signal potential after charge storage. Then, when a selection pulse is applied to the selection transistor 305 through the decoder wiring 308, the fluctuation in the signal potential of the floating diffusion FD is transmitted to the output wiring 309 via the amplification transistor 304 and the selection transistor 305. As a result, the pixel signals corresponding to the reset potential and the signal potential are output from the unit pixel to the output wiring 309.

[0026] As shown in the figure, in this embodiment, the reset wiring 306 and the TX wiring 307 are common to the 16 pixels forming the unit group 131. That is, the reset pulse and the transfer pulse are applied simultaneously to all 16 pixels. Therefore, all pixels forming the unit group 131 start accumulating charge at the same time and end accumulating charge at the same time. However, the pixel signals corresponding to the accumulated charge are sequentially applied by the selection pulses of each selection transistor 305 and selectively output to the output wiring 309.

[0027] By configuring the circuit based on unit group 131 in this way, the charge accumulation time can be controlled for each unit group 131. In other words, adjacent unit groups 131 can output pixel signals with different charge accumulation times. Furthermore, while one unit group 131 is performing one charge accumulation cycle, the other unit group 131 can repeatedly perform charge accumulation cycles, outputting a pixel signal each time. Specific output control will be described later.

[0028] Figure 4 is a block diagram showing the functional configuration of the image sensor 100. The analog multiplexer 411 sequentially selects the 16 PDs 104 that form a unit group 131 and outputs the respective pixel signals to the output wiring 309. The multiplexer 411 is formed on the imaging chip 113 together with the PDs 104.

[0029] The pixel signals output via the multiplexer 411 are subjected to CDS and A / D conversion by a signal processing circuit 412 formed on the signal processing chip 111, which performs correlated double sampling (CDS) and analog-to-digital (A / D) conversion. The A / D converted pixel signals are passed to the demultiplexer 413 and stored in the pixel memory 414 corresponding to each pixel. Each of the pixel memories 414 has a capacity to store pixel signals corresponding to the maximum number of integrations, which will be described later. The demultiplexer 413 and the pixel memories 414 are formed on the memory chip 112.

[0030] The A / D conversion converts the input analog pixel signal into a 12-bit digital pixel signal. Simultaneously, the signal processing circuit 412 concatenates 3-bit exponent digits corresponding to the cumulative number described later, and hands over a total of 15-bit digital pixel signals to the demultiplexer 413. Therefore, the pixel memory 414 stores 15-bit digital pixel signals corresponding to one charge accumulation.

[0031] The arithmetic circuit 415 processes the pixel signals stored in the pixel memory 414 and passes them to the subsequent image processing unit. The arithmetic circuit 415 may be located on the signal processing chip 111 or on the memory chip 112. Although the diagram shows the connection for one group, in reality, these exist for each group and operate in parallel. However, the arithmetic circuit 415 does not necessarily have to exist for each group; for example, a single arithmetic circuit 415 may sequentially process the values ​​in the pixel memory 414 corresponding to each group by referencing them in order.

[0032] Figure 5 is a block diagram showing the configuration of the imaging device according to this embodiment. The imaging device 500 includes an imaging lens 520 as an imaging optical system, which guides the subject light beam incident along the optical axis OA to the image sensor 100. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. The imaging device 500 mainly comprises an image sensor 100, a system control unit 501, a drive unit 502, a photometering unit 503, a work memory 504, a recording unit 505, and a display unit 506.

[0033] The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. In Figure 1, it is represented by a single virtual lens positioned near the pupil. The drive unit 502 is a control circuit that performs charge accumulation control, such as timing control and area control, of the image sensor 100 according to instructions from the system control unit 501. In this sense, the drive unit 502 can be said to perform the function of the image sensor control unit that causes the image sensor 100 to accumulate charge and output a pixel signal. The drive unit 502 is combined with the image sensor 100 to form an imaging unit. The control circuit forming the drive unit 502 may be made into a chip and stacked on the image sensor 100.

[0034] The image sensor 100 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to perform various image processing operations and generate image data. For example, when generating image data in JPEG file format, it performs white balance processing, gamma processing, etc., followed by compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.

[0035] The photometering unit 503 detects the brightness distribution of the scene prior to a series of shooting sequences that generate image data. The photometering unit 503 includes, for example, an AE sensor with approximately 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each region of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. In this embodiment, the calculation unit 512 further determines how many times charge accumulation should be repeated in each pixel group region of the imaging chip 113 until the determined shutter speed is reached. The calculation unit 512 also performs various calculations for operating the imaging device 500.

[0036] Figure 6 illustrates an example of a scene and its region division. Figure 6(a) shows the scene captured by the pixel area of ​​the imaging chip 113. Specifically, it is a scene in which shadow subjects 601 and intermediate subjects 602 included in an indoor environment, and highlight subjects 603 of an outdoor environment observed inside a window frame 604, are simultaneously captured. When photographing such a scene with a large difference in brightness from the highlight area to the shadow area, with conventional image sensors, if charge accumulation is performed based on the highlight area, black crushing occurs in the shadow area, and if charge accumulation is performed based on the shadow area, white blown-out occurs in the highlight area. In other words, the dynamic range of the photodiode is insufficient for scenes with a large difference in brightness to output an image signal with a single charge accumulation uniformly for both the highlight and shadow areas. Therefore, in this embodiment, the scene is divided into partial regions such as the highlight area and the shadow area, and the number of charge accumulation cycles of the photodiode corresponding to each region is made different from each other to substantially expand the dynamic range.

[0037] Figure 6(b) shows the region division in the pixel area of ​​the imaging chip 113. The calculation unit 512 analyzes the scene in Figure 6(a) captured by the photometering unit 503 and divides the pixel area based on brightness. For example, the system control unit 501 causes the photometering unit 503 to perform multiple scene acquisitions while changing the exposure time, and the calculation unit 512 determines the pixel area division lines by referring to the changes in the distribution of blown-out highlights and crushed black areas. In the example in Figure 6(b), the calculation unit 512 divides the area into three regions: the shadow area 611, the intermediate area 612, and the highlight area 613.

[0038] The division lines are defined along the boundaries of the unit group 131. That is, each divided region contains an integer number of groups. The pixels of each group contained within the same region perform the same number of charge accumulations and pixel signal outputs within a period corresponding to the shutter speed determined by the calculation unit 512. Different regions will perform different numbers of charge accumulations and pixel signal outputs.

[0039] Figure 7 illustrates the charge accumulation control for each divided region, as shown in the example in Figure 6. When the calculation unit 512 receives a shooting preparation instruction from the user, it determines the shutter speed T0 from the output of the photometering unit 503. Furthermore, as described above, it divides the area into a shadow region 611, an intermediate region 612, and a highlight region 613, and determines the number of charge accumulations from the brightness information of each region. The number of charge accumulations is determined so that the pixels do not become saturated with each charge accumulation. For example, the number of charge accumulations is determined based on the criterion that 80% to 90% of the charge that can be accumulated is accumulated in one charge accumulation operation.

[0040] Here, the shadow region 611 is considered to have one charge accumulation. That is, the determined shutter speed T0 is matched with the charge accumulation time. Also, the number of charge accumulations in the intermediate region 612 is set to two. That is, the charge accumulation time for one accumulation is set to T0 / 2, and two charge accumulations are repeated during shutter speed T0. Also, the number of charge accumulations in the highlight region 613 is set to four. That is, the charge accumulation time for one accumulation is set to T0 / 4, and four charge accumulations are repeated during shutter speed T0.

[0041] When the camera receives a shooting command from the user at time t=0, the drive unit 502 applies a reset pulse and a transfer pulse to the pixels of any group belonging to any region. This application triggers the start of charge accumulation in each pixel.

[0042] When time t=T0 / 4, the drive unit 502 applies a transfer pulse to the pixels of the group belonging to the highlight region 613. Then, it sequentially applies selection pulses to the pixels within each group, causing the respective pixel signals to be output to the output wiring 309. Once the pixel signals of all pixels in the group have been output, the drive unit 502 again applies a reset pulse and a transfer pulse to the pixels of the group belonging to the highlight region 613 to start the second charge accumulation.

[0043] Note that the selection output of the pixel signal takes time, so there is a time difference between the end of the first charge accumulation and the start of the second charge accumulation. If this time difference is practically negligible, then, as mentioned above, the time for one charge accumulation can be calculated by dividing the shutter speed T0 by the number of charge accumulations. On the other hand, if it cannot be ignored, then the shutter speed T0 should be adjusted to take that time into account, or the time for one charge accumulation should be made shorter than the time obtained by dividing the shutter speed T0 by the number of charge accumulations.

[0044] When time t=T0 / 2, the drive unit 502 applies a transfer pulse to the pixels in the groups belonging to the intermediate region 612 and the highlight region 613. Then, it sequentially applies a selection pulse to the pixels within each group, causing the respective pixel signals to be output to the output wiring 309. Once the pixel signals of all pixels in a group have been output, the drive unit 502 again applies a reset pulse and a transfer pulse to the pixels in the groups belonging to the intermediate region 612 and the highlight region 613, initiating the second charge accumulation for the intermediate region 612 and the third charge accumulation for the highlight region 613.

[0045] When time t=3T0 / 4, the drive unit 502 applies a transfer pulse to the pixels of the group belonging to the highlight region 613. Then, it sequentially applies selection pulses to the pixels within each group, causing the respective pixel signals to be output to the output wiring 309. Once the pixel signals of all pixels in the group have been output, the drive unit 502 again applies a reset pulse and a transfer pulse to the pixels of the group belonging to the highlight region 613 to start the fourth charge accumulation.

[0046] When time t=T0, the drive unit 502 applies a transfer pulse to the pixels in the entire region. Then, it sequentially applies selection pulses to the pixels within each group, causing the respective pixel signals to be output to the output wiring 309. Through this control, one pixel signal is stored in the pixel memory 414 corresponding to the shadow region 611, two pixel signals are stored in the pixel memory 414 corresponding to the intermediate region 612, and four pixel signals are stored in the pixel memory 414 corresponding to the highlight region 613.

[0047] These pixel signals are sequentially transferred to the image processing unit 511. The image processing unit 511 generates high dynamic range image data from these pixel signals. The specific processing will be described later.

[0048] Figure 8 shows the relationship between the number of integration cycles and the dynamic range. Multiple pixel signals corresponding to repeatedly performed charge accumulation are integrated by the image processing unit 511 to form part of high dynamic range image data.

[0049] If we use the dynamic range of the region where the number of integrations is 1, i.e., where charge accumulation is performed once, as the baseline, the expansion of the dynamic range in the region where the number of integrations is 2, i.e., where charge accumulation is performed twice and the output signal is integrated, is equivalent to 1 stage. Similarly, if the number of integrations is 4, it becomes 2 stages, and if it is 128, it becomes 7 stages. In other words, to achieve a dynamic range expansion of n stages, 2 n You just need to integrate the output signals.

[0050] Here, in order for the image processing unit 511 to identify how many charge accumulations have occurred in each divided region, a 3-bit exponent digit indicating the number of accumulations is added to the image signal. As shown in the figure, the exponent digits are assigned sequentially as follows: 000 for 1 accumulation, 001 for 2 accumulations, ... 111 for 128 accumulations.

[0051] The image processing unit 511 refers to the exponent digit of each pixel signal received from the arithmetic circuit 415, and if the result of the reference is two or more integration steps, it performs integration processing of the pixel signals. For example, if the number of integration steps is two (1 step), the upper 11 bits of the 12-bit pixel signals corresponding to charge accumulation are added together for the two pixel signals to generate a single 12-bit pixel signal. Similarly, if the number of integration steps is 128 (7 steps), the upper 5 bits of the 12-bit pixel signals corresponding to charge accumulation are added together for the 128 pixel signals to generate a single 12-bit pixel signal. In other words, the upper bits obtained by subtracting the number of steps corresponding to the number of integration steps from 12 are added together to generate a single 12-bit pixel signal. The lower bits that are not subject to addition are removed.

[0052] By processing in this way, the luminance range to which gradation is applied can be shifted to the higher luminance side in accordance with the number of integration steps. In other words, 12 bits are allocated to a limited range on the higher luminance side. Therefore, gradation can be applied to image areas that were previously overexposed.

[0053] However, since 12 bits are allocated to different brightness ranges for the other divided regions, it is not possible to generate image data by simply stitching the regions together. Therefore, the image processing unit 511 performs requantization processing based on the maximum brightness pixel and the minimum brightness pixel in order to make the entire region into 12-bit image data while maintaining the obtained gradation as much as possible. Specifically, gamma transformation is applied and quantization is performed so that the gradation is maintained more smoothly. By processing in this way, image data with a high dynamic range can be obtained.

[0054] Furthermore, the number of integration steps is not limited to cases where a 3-bit exponent digit is assigned to the pixel signal as described above; it may also be described as supplementary information separate from the pixel signal. Alternatively, the number of integration steps can be obtained during the addition process by omitting the exponent digit from the pixel signal and instead counting the number of pixel signals stored in the pixel memory 414.

[0055] Furthermore, in the image processing described above, a requantization process was performed to fit the entire area into 12-bit image data. However, the number of output bits can be increased in accordance with the upper limit of the number of integration steps relative to the number of bits in the pixel signal. For example, if the upper limit of integration steps is set to 16 (4 stages), then a 12-bit pixel signal can be converted into 16-bit image data for the entire area. Processing in this way allows for the generation of image data without loss of precision.

[0056] Next, the series of shooting operations will be explained. Figure 9 is a flowchart showing the shooting operation process. The flow starts when the power of the imaging device 500 is turned ON.

[0057] In step S101, the system control unit 501 waits until the switch SW1, which is an instruction to prepare for shooting, is pressed down. Once the pressing of switch SW1 is detected, the system proceeds to step S102.

[0058] In step S102, the system control unit 501 performs photometric processing. Specifically, the calculation unit 512 obtains the output from the photometric unit 503 and calculates the brightness distribution of the scene. Then, the process proceeds to step S103, where the shutter speed, area division, number of integrations, etc., are determined as described above.

[0059] Once the shooting preparation operation is complete, proceed to step S104 and wait until the switch SW2, which is the shooting instruction, is pressed down. If the elapsed time exceeds a predetermined time Tw (YES in step S105), return to step S101. If the pressing of switch SW2 is detected before Tw is exceeded (NO in step S105), proceed to step S106.

[0060] In step S106, the drive unit 502, having received instructions from the system control unit 501, executes the charge storage process and signal readout process as described in Figure 7. Once all signal readout is complete, the process proceeds to step S107, where the image processing described in Figure 8 is executed, followed by a recording process to record the generated image data into the recording unit.

[0061] Once the recording process is complete, the process proceeds to step S108 to determine whether the power to the imaging device 500 has been turned off. If the power has not been turned off, the process returns to step S101; if it has been turned off, the series of imaging operations is terminated.

[0062] Next, we will describe an example of the specific configuration of the signal processing chip 111. Figure 10 is a block diagram showing an example of the specific configuration of the signal processing chip 111. In the explanation using Figure 4 above, we showed an example in which the demultiplexer 413 and pixel memory 414 are formed on the memory chip 112, but here we will describe an example in which they are formed on the signal processing chip 111.

[0063] The signal processing chip 111 is responsible for the functions of the drive unit 502. The signal processing chip 111 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, and a signal control unit 444, which are assigned control functions, and a drive control unit 420 that provides overall control of these control units. The drive control unit 420 converts instructions from the system control unit 501 into control signals that can be executed by each control unit and passes them on to each unit.

[0064] The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel, which are sent to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation by sending reset pulses and transfer pulses to the target pixels, and outputs the pixel signal to the output wiring 309 by sending selection pulses to the readout pixels.

[0065] The block control unit 442 sends a specific pulse to the imaging chip 113 to identify the unit group 131 to be controlled. As explained using Figure 6, a divided region may contain multiple adjacent unit groups 131. These unit groups 131 belonging to the same region form a single block. Pixels included in the same block start charge accumulation at the same time and end charge accumulation at the same time. Therefore, the block control unit 442 plays the role of blocking the unit group 131 by sending a specific pulse to the target unit group 131 based on the designation from the drive control unit 420. The transfer pulse and reset pulse that each pixel receives via the TX wiring 307 and reset wiring 306 are the logical AND of each pulse sent by the sensor control unit 441 and the specific pulse sent by the block control unit 442. In this way, by controlling each region as an independent block, the charge accumulation control explained using Figure 7 is realized. The blocking designation from the drive control unit will be described in detail later.

[0066] The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, decimation control, etc., can be realized, which controls only specific pixels of pixels belonging to the same unit group 131.

[0067] The signal control unit 444 is primarily responsible for timing control of the A / D converter 412b. The pixel signal output via the output wiring 309 is input to the A / D converter 412b via the CDS circuit 412a and the multiplexer 411. The A / D converter 412b is controlled by the signal control unit 444 to convert the input pixel signal into a digital signal. The converted pixel signal is then passed to the demultiplexer 413 and stored as the pixel value of the digital data in the pixel memory 414 corresponding to each pixel.

[0068] The signal processing chip 111 has a timing memory 430 as an accumulation control memory that stores block division information, which determines which unit groups 131 are combined to form a block, and accumulation count information, which determines how many times each formed block will repeat charge accumulation. The timing memory 430 is configured, for example, by flash RAM.

[0069] As described above, the system control unit 501 determines which unit groups to combine to form a block based on the detection results of the scene's brightness distribution detection, which is performed prior to the series of shooting sequences. The determined blocks are divided into, for example, the first block, the second block, etc., and each block is defined by which unit group 131 it contains. The drive control unit 420 receives this block division information from the system control unit 501 and stores it in the timing memory 430.

[0070] Furthermore, the system control unit 501 determines how many times each block will repeat charge accumulation based on the detection results of the brightness distribution. The drive control unit 420 receives this accumulation count information from the system control unit 501 and stores it in the timing memory 430 in pairs with the corresponding block division information. By storing the block division information and accumulation count information in the timing memory 430 in this way, the drive control unit 420 can independently execute a series of charge accumulation controls by sequentially referring to the timing memory 430. In other words, once the drive control unit 420 receives a shooting instruction signal from the system control unit 501 in the control of one image, it can then complete the accumulation control without receiving instructions from the system control unit 501 each time for the control of each pixel.

[0071] The drive control unit 420 receives block division information and accumulation count information from the system control unit 501, which are updated based on the photometric results (luminance distribution detection results) performed in synchronization with the shooting preparation instruction, and updates the contents of the timing memory 430 as appropriate. For example, the drive control unit 420 updates the timing memory 430 in synchronization with the shooting preparation instruction or the shooting instruction. This configuration enables faster charge accumulation control, and allows the system control unit 501 to perform other processes in parallel while the drive control unit 420 is performing charge accumulation control.

[0072] The drive control unit 420 not only performs charge accumulation control for the imaging chip 113, but also refers to the timing memory 430 when performing readout control. For example, the drive control unit 420 refers to the accumulation count information for each block and stores the pixel signal output from the demultiplexer 413 at the corresponding address in the pixel memory 414.

[0073] The drive control unit 420 reads the target pixel signal from the pixel memory 414 and hands it over to the image processing unit 511 in accordance with the handover request from the system control unit 501. As described above, the pixel memory 414 has a memory space that can store a pixel signal corresponding to the maximum number of accumulations for each pixel, and stores each pixel signal corresponding to the number of accumulations performed as a pixel value. For example, if charge accumulation is repeated four times in a certain block, the pixels included in that block will output four pixel signals, so four pixel values ​​will be stored in the memory space of each pixel in the pixel memory 414. When the drive control unit 420 receives a handover request from the system control unit 501 requesting the pixel signal of a specific pixel, it specifies the address of that specific pixel in the pixel memory 414, reads all the stored pixel signals, and hands them over to the image processing unit 511. For example, if four pixel values ​​are stored, all four pixel values ​​are handed over sequentially, and if only one pixel value is stored, that pixel value is handed over.

[0074] The drive control unit 420 reads the pixel signals stored in the pixel memory 414 to the arithmetic circuit 415 and causes the arithmetic circuit 415 to perform the integration process described above. The integrated pixel signals are stored in the target pixel address of the pixel memory 414. The target pixel address may be set adjacent to the address space before integration processing, or it may be the same address so as to overwrite the pixel signal before integration processing. Alternatively, a dedicated space may be provided to store the pixel values ​​of each pixel after integration processing. When the drive control unit 420 receives a handover request from the system control unit 501 requesting the pixel signal of a specific pixel, it may hand over the pixel signal after integration processing to the image processing unit 511, depending on the nature of the handover request. Of course, it is also possible to hand over both the pixel signals before and after integration processing.

[0075] The pixel memory 414 is provided with a data transfer interface for transmitting pixel signals in accordance with a handover request. The data transfer interface is connected to a data transfer line that connects to the image processing unit 511. The data transfer line is configured, for example, as a data bus within a bus line. In this case, the handover request from the system control unit 501 to the drive control unit 420 is executed by addressing using the address bus.

[0076] The transmission of pixel signals via a data transfer interface can employ various methods, not limited to address-based methods. For example, a double data rate method can be used, which utilizes both the rising and falling edges of the clock signal used for synchronization of each circuit during data transfer. Alternatively, a burst transfer method can be employed to transfer data all at once by omitting some steps such as addressing, thereby increasing speed. Furthermore, a combination of methods such as a bus system using a line connecting the control unit, memory unit, and input / output unit in parallel, or a serial system that transfers data one bit at a time in series, can also be employed.

[0077] With this configuration, the image processing unit 511 can receive only the necessary pixel signals, allowing for high-speed image processing, especially when forming low-resolution images. Furthermore, when the arithmetic circuit 415 performs integration processing, the image processing unit 511 does not need to perform integration processing itself. Thus, image processing can be accelerated through functional division and parallel processing.

[0078] Figure 11 is an explanatory diagram illustrating the flow of pixel signals transmitted from the imaging chip 113 to the signal processing chip 111. In this example, unit group 131 consists of 2048 pixels, with 32 pixels per row and 64 pixels per column.

[0079] In the configuration shown in Figure 3, one unit group 131 had one output wire 309. However, in the example shown in this figure, one unit group 131 has 16 output wires such that two adjacent rows of pixels share one output wire 309. Each output wire 309 branches into two output wires 309a and 309b near the junction of the imaging chip 113 and the signal processing chip 111.

[0080] On the signal processing chip 111 side, two input wires 409a and 409b are provided, corresponding to the branched output wires 309a and 309b, respectively. Therefore, at the junction, a bump 109a is provided for connecting the output wire 309a and the input wire 409a, and a bump 109b is provided for connecting the output wire 309b and the input wire 409b. By configuring the connection part redundantly in this way, the possibility of causing pixel defects due to connection failures can be reduced. In this sense, the number of branches is not limited to two, but can be multiple. Furthermore, the electrical connection between the output wires and input wires is not limited to bump coupling; when employing an electrical connection that may cause connection failures, it is preferable to configure the connection part redundantly in this way.

[0081] Before inputting input wires 409a and 409b to the CDS circuit 412a, switches 461a and 461b are interposed, respectively. Switches 461a and 461b are controlled by the drive control unit 420 as a mutually linked switch 461. Specifically, the drive control unit 420 normally turns switch 461a ON to enable the transmission of pixel signals from input wire 409a, and turns switch 461b OFF to disable the transmission from input wire 409b. On the other hand, if the drive control unit 420 determines that there is a connection problem with bump 109a, it switches switch 461a OFF to disable the transmission from input wire 409a, and switches switch 461b ON to enable the transmission from input wire 409b. In this way, the linked operation of switch 461, which connects one wire and disconnects the other, is expected to ensure that only normal pixel signals are input to the CDS circuit 412a.

[0082] The determination of a connection failure in bump 109 can be performed by either the drive control unit 420 or the system control unit 501. The connection failure determination is made based on the output result of the pixel signal that has passed through the input wiring 409. Specifically, for example, the system control unit 501 compares the respective pixel signals output from the adjacent output wirings 309 on both sides and determines that a connection failure has occurred if the difference exceeds a predetermined threshold. Whether or not abnormal values ​​are consecutive in the column direction may also be added as a criterion for determination. In this case, the drive control unit 420 receives the determination result from the system control unit 501 and switches the switch 461 of the corresponding input wiring 409. Note that the connection failure determination does not have to be performed sequentially in accordance with the shooting operation; once a determination has been made, the drive control unit 420 can store the determination result in the timing memory 430. In this case, when reading out the pixel signal, the drive control unit 420 controls the switch 461 while referring to the timing memory 430.

[0083] In the embodiments described above, the photometering unit 503 was described as having a configuration that includes an independent AE sensor. However, the photometering process can also be performed using a pre-image output from the image sensor 100 prior to the actual shooting process, which is performed in response to a shooting instruction from the user. Alternatively, one pixel for photometering may be provided in, for example, a unit group 131. For example, in the pixel array of Figure 2, by setting the color filter of the leftmost and topmost pixel of the unit group 131 to a transparent filter or no filter, that pixel can be used as a photometering pixel. Such a pixel can receive visible light in a wide wavelength band, making it suitable for detecting the brightness distribution of a scene. Alternatively, the photometering pixel may be separated from the unit group, and multiple photometering pixels may be grouped together to form a unit group. With this configuration, the drive unit 502 can independently control charge accumulation for the photometering pixel.

[0084] In the embodiments described above, an example was explained in which the determined shutter speed T0 is matched with the charge accumulation time of one charge in the shadow region. However, for example, the system may be controlled to repeat charge accumulation twice in the shadow region during the determined shutter speed T0. In this case, as shown in the example in Figure 7, the brightness range that provides gradation for the pixel signal from the intermediate region, which also repeats charge accumulation twice, is shifted to the higher brightness side in accordance with the number of accumulations. However, no such processing is performed for the pixel signal from the shadow region. That is, the value of the pixel signal due to one charge accumulation (charge accumulation time T0 / 2) in the shadow region is small, and even if two accumulations are added together, the value does not saturate from the 12-bit range, so shift processing is not necessary.

[0085] In this way, by setting the number of charge accumulations for the shadow region to multiple times and adding the output pixel signals, it is possible to expect the effect of canceling out random noise in the dark areas. In this case, unlike the processing of pixel signals in other regions where multiple charge accumulations are performed for the purpose of expanding the dynamic range, a simple addition process is sufficient without performing a shift process. This process may be performed by the arithmetic circuit 415 provided on the signal processing chip 111, as in the embodiment described above, or by the image processing unit 511.

[0086] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0087] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0088] 100 Image sensor, 101 Microlens, 102 Color filter, 103 Passivation film, 104 PD, 105 Transistor, 106 PD layer, 107 Wiring, 108 Wiring layer, 109 Bump, 110 TSV, 111 Signal processing chip, 112 Memory chip, 113 Imaging chip, 131 Unit group, 302 Transfer transistor, 303 Reset transistor, 304 Amplifier transistor, 305 Select transistor, 306 Reset wiring, 307 TX wiring, 308 Decoder wiring, 309 Output wiring, 310 Vdd wiring, 311 Load current source, 409 Input wiring, 411 Multiplexer, 412 Signal processing circuit, 413 Demultiplexer, 414 Pixel memory, 415 Arithmetic circuit, 420 Drive control unit, 430 Timing memory, 441 Sensor control unit, 442 Block control unit, 443 Synchronization control unit, 444 Signal control unit, 461 Switch, 500 Imaging device, 501 System control unit, 502 Drive unit, 503 Photometer unit, 504 Work memory, 505 Recording unit, 506 Display unit, 511 Image processing unit, 512 Calculation unit, 601 Shadow subject, 602 Intermediate subject, 603 Highlight subject, 604 Window frame, 611 Shadow area, 612 Intermediate area, 613 Highlight area

Claims

1. A first semiconductor substrate having a first photoelectric conversion unit that converts light into electric charge and a second photoelectric conversion unit that converts light into electric charge, A semiconductor substrate laminated with the first semiconductor substrate, the second semiconductor substrate having a drive unit that outputs a control signal to the first semiconductor substrate to control the storage time for storing the charge converted by the first photoelectric conversion unit and the storage time for storing the charge converted by the second photoelectric conversion unit to be different storage times, Each of the first semiconductor substrate and the second semiconductor substrate has conductive members arranged to face each other in the stacking direction in which they are stacked, and a plurality of junctions that electrically connect the first semiconductor substrate and the second semiconductor substrate. An image sensor equipped with the following features.

2. In the image sensor according to claim 1, The plurality of junctions include a first junction having a first conductive member that outputs a first signal based on the charge converted by the first photoelectric conversion unit, and a second junction having a second conductive member that outputs a second signal based on the charge converted by the second photoelectric conversion unit. Image sensor.

3. In the image sensor according to claim 2, An image sensor comprising a wiring layer disposed between the first semiconductor substrate and the second semiconductor substrate in the stacking direction, having a first output wiring that is electrically connected to the first conductive member and outputs the first signal, and a second output wiring that is electrically connected to the second conductive member and outputs the second signal.

4. In the image sensor according to claim 2 or claim 3, The second semiconductor substrate includes a first conversion unit that converts the first signal output from the first conductive member into a digital signal, and a second conversion unit that converts the second signal output from the second conductive member into a digital signal. Image sensor.

5. In the image sensor according to claim 4, The second semiconductor substrate has a first storage unit that stores a first digital signal converted from the first signal by the first conversion unit, and a second storage unit that stores a second digital signal converted from the second signal by the second conversion unit. Image sensor.

6. In the image sensor according to claim 5, The second semiconductor substrate has a first arithmetic circuit for reading the first digital signal from the first storage unit and a second arithmetic circuit for reading the second digital signal from the second storage unit. Image sensor.

7. In the image sensor according to claim 4, An image sensor comprising a third semiconductor substrate, which is laminated with the first semiconductor substrate, and has a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, and a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit.

8. In the image sensor according to claim 7, The third semiconductor substrate includes a first arithmetic circuit for reading the first digital signal from the first storage unit and a second arithmetic circuit for reading the second digital signal from the second storage unit. Image sensor.

9. In the image sensor according to claim 4, The second photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit. Image sensor.

10. In the image sensor according to claim 9, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, and a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction. The first conductive member outputs a third signal based on the charge converted by the third photoelectric conversion unit. The second conductive member outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit. The first conversion unit converts the third signal output from the first conductive member into a digital signal. The second conversion unit converts the fourth signal output from the second conductive member into a digital signal. Image sensor.

11. In the image sensor according to claim 9, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, and a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction. The plurality of junctions include a third junction having a third conductive member that outputs a third signal based on the charge converted by the third photoelectric conversion unit, and a fourth junction having a fourth conductive member that outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit. The first conversion unit converts the third signal output from the third conductive member into a digital signal. The second conversion unit converts the fourth signal output from the fourth conductive member into a digital signal. Image sensor.

12. In the image sensor according to claim 10 or claim 11, The second semiconductor substrate includes a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit, a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the first conversion unit, and a fourth storage unit for storing a fourth digital signal converted from the fourth signal to a digital signal by the second conversion unit. Image sensor.

13. In the image sensor according to claim 10 or claim 11, An image sensor comprising a third semiconductor substrate laminated with the first semiconductor substrate, the third semiconductor substrate having a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit, a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the first conversion unit, and a fourth storage unit for storing a fourth digital signal converted from the fourth signal to a digital signal by the second conversion unit.

14. In the image sensor according to claim 4, The second photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit. Image sensor.

15. In the image sensor according to claim 14, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, and a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction, The first conductive member outputs a third signal based on the charge converted by the third photoelectric conversion unit. The second conductive member outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit. The first conversion unit converts the third signal output from the first conductive member into a digital signal. The second conversion unit converts the fourth signal output from the second conductive member into a digital signal. Image sensor.

16. In the image sensor according to claim 14, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, and a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction, The plurality of junctions include a third junction having a third conductive member that outputs a third signal based on the charge converted by the third photoelectric conversion unit, and a fourth junction having a fourth conductive member that outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit. The first conversion unit converts the third signal output from the third conductive member into a digital signal. The second conversion unit converts the fourth signal output from the fourth conductive member into a digital signal. Image sensor.

17. In the image sensor according to claim 15 or claim 16, The second semiconductor substrate includes a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit, a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the first conversion unit, and a fourth storage unit for storing a fourth digital signal converted from the fourth signal to a digital signal by the second conversion unit. Image sensor.

18. In the image sensor according to claim 15 or claim 16, An image sensor comprising a third semiconductor substrate laminated with the first semiconductor substrate, the third semiconductor substrate having a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit, a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the first conversion unit, and a fourth storage unit for storing a fourth digital signal converted from the fourth signal to a digital signal by the second conversion unit.

19. In the image sensor according to any one of claims 1 to 18, The first semiconductor substrate has a first transfer unit for transferring the charge converted by the first photoelectric conversion unit, and a second transfer unit for transferring the charge converted by the second photoelectric conversion unit. The drive unit outputs a transfer control signal to the first semiconductor substrate to control the timing at which charge is transferred from the first photoelectric conversion unit by the first transfer unit and the timing at which charge is transferred from the second photoelectric conversion unit by the second transfer unit to be different. Image sensor.

20. In the image sensor according to claim 19, The first semiconductor substrate has a first reset unit for discharging the charge converted by the first photoelectric conversion unit, and a second reset unit for discharging the charge converted by the second photoelectric conversion unit. The drive unit outputs a reset control signal to the first semiconductor substrate to control the timing at which charge is discharged from the first photoelectric conversion unit by the first reset unit and the timing at which charge is discharged from the second photoelectric conversion unit by the second reset unit to be different. Image sensor.

21. In the image sensor according to any one of claims 1 to 18, The first semiconductor substrate has a first reset unit for discharging the charge converted by the first photoelectric conversion unit, and a second reset unit for discharging the charge converted by the second photoelectric conversion unit. The drive unit outputs a reset control signal to the first semiconductor substrate to control the timing at which charge is discharged from the first photoelectric conversion unit by the first reset unit and the timing at which charge is discharged from the second photoelectric conversion unit by the second reset unit to be different. Image sensor.

22. In the image sensor according to claim 1, The first semiconductor substrate has a third photoelectric conversion unit that converts light into electric charge, The second photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit, The third photoelectric conversion unit is arranged in the row direction alongside the first photoelectric conversion unit. Image sensor.

23. In the image sensor according to claim 22, The plurality of junctions include a first junction having a first conductive member that outputs a first signal based on the charge converted by the first photoelectric conversion unit, a second junction having a second conductive member that outputs a second signal based on the charge converted by the second photoelectric conversion unit, and a third junction having a third conductive member that outputs a third signal based on the charge converted by the third photoelectric conversion unit. Image sensor.

24. In the image sensor according to claim 23, An image sensor comprising a wiring layer disposed between the first semiconductor substrate and the second semiconductor substrate in the stacking direction, having a first output wiring electrically connected to the first conductive member and outputting the first signal, a second output wiring electrically connected to the second conductive member and outputting the second signal, and a third output wiring electrically connected to the third conductive member and outputting the third signal.

25. In the image sensor according to claim 23 or claim 24, The second semiconductor substrate includes a first conversion unit that converts the first signal output from the first conductive member into a digital signal, a second conversion unit that converts the second signal output from the second conductive member into a digital signal, and a third conversion unit that converts the third signal output from the third conductive member into a digital signal. Image sensor.

26. In the image sensor according to claim 25, The second semiconductor substrate includes a first storage unit for storing a first digital signal converted from the first signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal by the second conversion unit, and a third storage unit for storing a third digital signal converted from the third signal by the third conversion unit. Image sensor.

27. In the image sensor according to claim 26, The second semiconductor substrate includes a first arithmetic circuit for reading the first digital signal from the first storage unit, a second arithmetic circuit for reading the second digital signal from the second storage unit, and a third arithmetic circuit for reading the third digital signal from the third storage unit. Image sensor.

28. In the image sensor according to claim 25, An image sensor comprising a third semiconductor substrate, which is laminated with the first semiconductor substrate, and having a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit, and a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the third conversion unit.

29. In the image sensor according to claim 28, The third semiconductor substrate includes a first arithmetic circuit for reading the first digital signal from the first storage unit, a second arithmetic circuit for reading the second digital signal from the second storage unit, and a third arithmetic circuit for reading the third digital signal from the third storage unit. Image sensor.

30. In the image sensor according to claim 25, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction, and a sixth photoelectric conversion unit that converts light into electric charge and is arranged alongside the third photoelectric conversion unit in the row direction. The first conductive member outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit. The second conductive member outputs a fifth signal based on the charge converted by the fifth photoelectric conversion unit. The third conductive member outputs a sixth signal based on the charge converted by the sixth photoelectric conversion unit. The first conversion unit converts the fourth signal output from the first conductive member into a digital signal. The second conversion unit converts the fifth signal output from the second conductive member into a digital signal. The third conversion unit converts the sixth signal output from the third conductive member into a digital signal. Image sensor.

31. In the image sensor according to claim 25, The first semiconductor substrate includes a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction, a fourth photoelectric conversion unit that converts light into electric charge and is arranged alongside the second photoelectric conversion unit in the row direction, and a sixth photoelectric conversion unit that converts light into electric charge and is arranged alongside the third photoelectric conversion unit in the row direction. The plurality of junctions include a fourth junction having a fourth conductive member that outputs a fourth signal based on the charge converted by the fourth photoelectric conversion unit, a fifth junction having a fifth conductive member that outputs a fifth signal based on the charge converted by the fifth photoelectric conversion unit, and a sixth junction having a sixth conductive member that outputs a sixth signal based on the charge converted by the sixth photoelectric conversion unit. The first conversion unit converts the fourth signal output from the fourth conductive member into a digital signal. The second conversion unit converts the fifth signal output from the fifth conductive member into a digital signal. The third conversion unit converts the sixth signal output from the sixth conductive member into a digital signal. Image sensor.

32. In the image sensor according to claim 30 or claim 31, The second semiconductor substrate includes a first storage unit for storing a first digital signal converted from the first signal by the first conversion unit, a second storage unit for storing a second digital signal converted from the second signal by the second conversion unit, a third storage unit for storing a third digital signal converted from the third signal by the third conversion unit, a fourth storage unit for storing a fourth digital signal converted from the fourth signal by the first conversion unit, a fifth storage unit for storing a fifth digital signal converted from the fifth signal by the second conversion unit, and a sixth storage unit for storing a sixth digital signal converted from the sixth signal by the third conversion unit. Image sensor.

33. In the image sensor according to claim 30 or claim 31, An image sensor comprising a third semiconductor substrate laminated with the first semiconductor substrate, the third semiconductor substrate having: a first storage unit for storing a first digital signal converted from the first signal to a digital signal by the first conversion unit; a second storage unit for storing a second digital signal converted from the second signal to a digital signal by the second conversion unit; a third storage unit for storing a third digital signal converted from the third signal to a digital signal by the third conversion unit; a fourth storage unit for storing a fourth digital signal converted from the fourth signal to a digital signal by the first conversion unit; a fifth storage unit for storing a fifth digital signal converted from the fifth signal to a digital signal by the second conversion unit; and a sixth storage unit for storing a sixth digital signal converted from the sixth signal to a digital signal by the third conversion unit.

34. In the image sensor according to any one of claims 1 to 33, The conductive member is a copper member. Image sensor.

35. An imaging device comprising an image sensor according to any one of claims 1 to 34.

36. In the imaging device according to claim 35, An imaging device comprising a control unit that is electrically connected to the image sensor and acquires information about a subject captured by the image sensor.

37. In the imaging device according to claim 36, The control unit controls the drive unit based on the information. Imaging device.

Images