Shift register, display device, method for driving a shift register

Abstract

In the unit circuit of a shift register, a malfunction may occur during reset where the high-potential and low-potential power supplies are short-circuited. [Solution] This shift register comprises a plurality of unit circuits, each unit circuit including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, and a third transistor whose gate terminal is connected to the first node, wherein each unit circuit includes the third circuit, the second node is connected to a first power supply via the third transistor and the third circuit, and a control signal is input to the third circuit.

Description

Technical Field

[0001] This disclosure relates to a shift register and the like.

Background Art

[0002] FIG. 33 is a circuit diagram showing a unit circuit of a conventional shift register. In the unit circuit of FIG. 33, there may be a period during which transistors 103 and 108 are simultaneously ON during reset.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional shift register, there may be a problem that the high - potential power supply and the low - potential power supply are short - circuited during reset.

Means for Solving the Problems

[0005] A shift register according to an aspect of this disclosure includes a plurality of unit circuits. Each unit circuit includes a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, and a third transistor whose gate terminal is connected to the first node. Each unit circuit includes a third circuit, the second node is connected to a first power supply via the third transistor and the third circuit, and a control signal is input to the third circuit.

Effects of the Invention

[0006] The problem of short - circuiting between the low - potential power supply and the high - potential power supply during reset is eliminated. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing the configuration of the unit stage of the shift register according to this embodiment. [Figure 2] This is a block diagram showing the configuration of this shift register. [Figure 3] This is a timing chart showing multiple input signals for this shift register. [Figure 4] This is a timing chart illustrating the operation of this shift register. [Figure 5] This is a cross-sectional view showing an example of the configuration of a liquid crystal panel according to this embodiment. [Figure 6] This is a schematic plan view showing an example of the configuration of this display device. [Figure 7] This is a circuit diagram showing an example of the subpixel configuration of this display device. [Figure 8] This is a schematic plan view showing an example of the configuration of the counter electrodes of this display device. [Figure 9] This is a timing chart showing the operation of this display device. [Figure 10] This is a block diagram showing the configuration of this shift register. [Figure 11] This is a timing chart showing multiple input signals for this shift register. [Figure 12] This is a circuit diagram showing the configuration of the unit stage of the shift register according to this embodiment. [Figure 13] This is a circuit diagram showing the configuration of the unit stage of the shift register according to this embodiment. [Figure 14] This is a circuit diagram showing the configuration of the unit stage of the shift register according to this embodiment. [Figure 15] This is a timing chart illustrating the operation of this shift register. [Figure 16] This is a block diagram showing the configuration of this shift register. [Figure 17] Figure 16 is a circuit diagram showing the configuration of the unit stage. [Figure 18]This is a timing chart showing the operation of this shift register. [Figure 19] This is a block diagram showing the configuration of this shift register. [Figure 20] This is a circuit diagram showing the configuration of the unit stage in FIG. 19. [Figure 21] This is a block diagram showing the configuration of this shift register. [Figure 22] This is a circuit diagram showing the configuration of the unit stage in FIG. 20. [Figure 23] This is a circuit diagram showing the configuration of the unit stage in FIG. 20. [Figure 24] This is a timing chart showing the operation of a display device that performs touch detection. [Figure 25] This is a block diagram showing the configuration of this shift register. [Figure 26] This is a timing chart showing a plurality of input signals for this shift register. [Figure 27] This is a circuit diagram showing the configuration of the unit stage in FIG. 25. [Figure 28] This is a timing chart showing the operation of this shift register. [Figure 29] This is a timing chart showing the operation of this shift register. [Figure 30] This is a block diagram showing the configuration of this shift register. [Figure 31] This is a circuit diagram showing the configuration of the unit stage in FIG. 30. [Figure 32] This is a timing chart showing the operation of this shift register. [Figure 33] This is a circuit diagram showing the unit circuit of a conventional shift register.

Embodiments for Carrying Out the Invention

[0008] Figure 1 is a circuit diagram showing the configuration of the unit stage of the shift register according to this embodiment. Figure 2 is a block diagram showing the configuration of this shift register. Figure 3 is a timing chart showing multiple input signals to this shift register. Figure 4 is a timing chart showing the operation of this shift register. As shown in Figures 1 to 4, the shift register 10 comprises multiple unit circuits (Jn-2, Jn-1, Jn, Jn+1, etc.), and each unit circuit J includes a first circuit 11 to which a set signal SS is input, a second circuit 12 to which a reset signal RS is input, a first transistor T1 and a second transistor T2, a first node N1 connected to the gate terminal of the first transistor T1, a second node N2 connected to the gate terminal of the second transistor T2, and a third transistor T3 whose gate terminal is connected to the first node N1. Each unit circuit J includes a third circuit 13, and the second node N2 is connected to a first power supply VL (e.g., a low-potential power supply) via a third transistor T3 and the third circuit 13, and a control signal ZS is input to the third circuit 13.

[0009] In the shift register 10, the connection state between the second node N2 and the first power supply VL can be controlled by the third circuit 13 to which the control signal ZS is input. Therefore, the problem of the first power supply VL (e.g., low-potential power supply) and the second power supply VH (e.g., high-potential power supply) being short-circuited during reset (e.g., immediately after the reset signal RS is activated) can be eliminated.

[0010] As shown in Figure 1, the third circuit 13 includes the fourth transistor T4, and the second node N2 is connected to the first power supply VL via the third transistor T3 and the fourth transistor T4, and the control signal ZS is input to the gate terminal Y of the fourth transistor T4.

[0011] As shown in Figure 1, the first circuit 11 may include a set transistor TS to which a set signal SS is input at its gate terminal S (hereinafter referred to as terminal S) and which is connected to the first node N1 and the second power supply V2. The second circuit 12 may include a reset transistor TR to which a reset signal RS is input at its gate terminal R (hereinafter referred to as terminal R) and which is connected to the second node N2 and the second power supply V2. The unit circuit J may include a fifth transistor T5 whose gate terminal is connected to the second node N2, and the first node N1 may be connected to the first power supply VL via the fifth transistor T5. The multiple transistors (T1~T5·TS·TR) included in each unit circuit J may be of the same type (e.g., N-channel type).

[0012] As shown in Figure 1, each unit circuit J includes a capacitive element CA, and one conducting terminal (output terminal U) of the first transistor T1 may be connected to the gate terminal of the first transistor T1 via the capacitive element CA. The first circuit 11 and the second circuit 12 may each be connected to a second power supply VH (e.g., a high-potential power supply). For example, the first node N1 may be connected to the second power supply VH via the set transistor TS of the first circuit 11, and the second node N2 may be connected to the second power supply VH via the reset transistor TR of the second circuit 12.

[0013] As shown in Figures 2 and 3, the shift register 10 may be connected to a wiring group 2 through which clock signals (K1~K4·KA~KD) are transmitted. Multiple unit circuits (Jn-2·Jn-1·Jn·Jn+1, etc.) of the shift register 10 may be input to a multi-phase clock signal (K1~K4·KA~KD), one of the multi-phase clock signals may be input to the other conducting terminal X of the first transistor T1 (hereinafter referred to as terminal X), and the other conducting terminal (e.g., source terminal) of the second transistor T2 may be connected to the first power supply VL. Each unit circuit J may include an output terminal U connected to one conducting terminal (e.g., source terminal) of the first transistor T1 and one conducting terminal (e.g., drain terminal) of the second transistor T2. For example, the output terminal U of the nth stage unit circuit Jn outputs an output signal Un (e.g., a scan signal).

[0014] As shown in Figures 3 and 4, clock signal K2 is 1H (horizontal scanning period) behind clock signal K1 in phase, clock signal K3 is 1H behind clock signal K2 in phase, and clock signal K4 is 1H behind clock signal K3 in phase. Clock signal KA has the opposite phase to clock signal K1, clock signal KB has the opposite phase to clock signal K2, clock signal KC has the opposite phase to clock signal K3, and clock signal KD has the opposite phase to clock signal K4.

[0015] For clock signals K1 to K4, the period when it is "High" (the pulse formation period from the rise to the fall of the potential) is sometimes referred to as the active period, and for clock signals KA to KD, the period when it is "Low" (the pulse formation period from the fall to the rise of the potential) is sometimes referred to as the active period. The active period (pulse width) of each clock signal may be 1H or less.

[0016] As shown in Figures 1 to 4, in the (n-1)th stage unit circuit Jn-1, the set signal SS input to terminal S is the output signal Un-2 of the (n-2)th stage, the reset signal RS input to terminal R is the output signal Un of the nth stage, the clock signal K4 is input to terminal X (input terminal), and the clock signal KA is input to terminal Y as the control signal ZS. In the nth stage unit circuit Jn, the set signal SS input to terminal S is the output signal Un-1 of the (n-1)th stage, the reset signal RS input to terminal R is the output signal Un+1 of the (n+1)th stage, the clock signal K1 is input to terminal X (input terminal), and the clock signal KB is input to terminal Y as the control signal ZS. In the (n+1)th stage unit circuit Jn+1, the set signal SS input to terminal S is the output signal Un of the nth stage, the reset signal RS input to terminal R is the output signal Un+2 of the (n+2)th stage, the clock signal K2 is input to terminal X (input terminal), and the clock signal KC is input to terminal Y as the control signal ZS.

[0017] Thus, in the shift register 10, the set signal SS is the output signal of the previous stage, the reset signal RS is the output signal of the next stage, the four-phase clock signals K1 to K4 are input to terminal X of a four-stage unit circuit, and the four-phase clock signals KA to KD may be input to terminal Y of a four-stage unit circuit.

[0018] As shown in Figure 4, during period H1, pulses of clock signals K1, K2, and K3 are output sequentially from the (n-4) to (n-2) stage unit circuits. During period H2, output signal Un-1, which includes the pulse of clock signal K4, is output from unit circuit Jn-1 (previous stage), and the pulse of output signal Un-1, which is the set signal SS, is input to the set transistor TS of unit circuit Jn (current stage). As a result, the set transistor TS turns ON, the potential V1 of the first node N1 rises to "High", the first transistor T1 turns ON, and both the third transistor T3 and the fourth transistor T4 turn ON (during period H2, the clock signal KB is High). Consequently, the potential V2 of the second node N2 falls to "Low", and the second transistor T2 turns OFF. During period H3, the potential of the clock signal K1 input to terminal X (the conductive terminal of the first transistor T1) rises, causing the potential V1 of the first node N1 to be bootstrapped by the capacitive element CA, and an output signal Un containing the pulse of the clock signal K1 is output from the unit circuit Jn (itself).

[0019] During period H4, the output signal Un+1, which includes the pulse of the clock signal K2, is output from the unit circuit Jn+1 (next stage), and the pulse of the output signal Un+1, which is the reset signal RS, is input to the reset transistor TR of the unit circuit Jn (current stage). As a result, the reset transistor TR turns ON, the potential V2 of the second node N2 rises to "High", the second transistor T2 and the fifth transistor T5 turn ON, and the first transistor T1 turns OFF. This connects the output terminal U to the first power supply VL, fixing the output signal Un at a "Low" potential, and the reset is completed. During period H5, the pulses of the clock signals K3 and K4 are output sequentially from the unit circuits of the (n+2)th and (n+3)th stages.

[0020] The clock signal KB, which is the control signal ZS of the current stage (unit circuit Jn), has the opposite phase to the clock signal K2 input to the next stage (unit circuit Jn+1). Therefore, during the period H4 when the reset transistor TR is ON, the fourth transistor T4 is OFF, and the second node N2 is isolated from the first power supply VL. In other words, the problem of the first power supply VL and the second power supply VH being short-circuited via the third transistor T3 and the reset transistor TR during reset (the period when the reset transistor TR is ON) can be avoided.

[0021] In this shift register 10, as shown in period H4, the control signal ZS (clock signal KB) and the reset signal RS may be in opposite phase during the period when the reset signal RS is active. Furthermore, as shown in period H2, during the active period of the set signal SS, the control signal ZS (clock signal KB) may cause the fourth transistor T4 to turn ON (KB is High). This makes it possible to stably set the potential V1 of the first node N1 and the potential V2 of the second node N2 in opposite phase.

[0022] Figure 5 is a cross-sectional view showing an example configuration of a liquid crystal panel according to this embodiment. Figure 6 is a schematic plan view showing an example configuration of the display device. Figure 7 is a circuit diagram showing an example configuration of subpixels of the display device. Figure 8 is a schematic plan view showing an example configuration of counter electrodes of the display device. Figure 9 is a timing chart showing the operation of the display device. As shown in Figure 5, the liquid crystal panel 15 may comprise an active matrix substrate 3, a counter substrate 4, and a liquid crystal layer 5 surrounded by the active matrix substrate 3, the counter substrate 4, and a seal 5.

[0023] As shown in Figure 6, the display device 20 may include a display unit DA, a data driver 8, scan drivers 9F and 9S, and a control circuit 7 that controls each driver. The display unit DA may be provided with multiple data lines DL, multiple scan lines Gn and Gn-1, and multiple sub-pixels SP. The scan drivers 9F and 9S may include a shift register 10. The wiring group 2 in Figure 2 may be connected to the control circuit 7.

[0024] The display device 20 may include a liquid crystal panel 15, and the scanning drivers 9F and 9S may be integrally formed on the active matrix substrate 3, or they may be formed on a driver IC separate from the active matrix substrate 3.

[0025] As shown in Figure 7, a sub-pixel SP may include a pixel transistor TX whose gate terminal is connected to the scan line Gn, and a liquid crystal capacitance CL. The liquid crystal capacitance CL may include a pixel electrode PE and a counter electrode CE. The pixel electrode PE may be connected to the data line DL via the pixel transistor TX. As shown in Figure 8, a plurality of counter electrodes CE may be arranged in the display unit DA, and each counter electrode CE may be connected to the counter electrode driver 17 via wiring W. As shown in Figure 9, the frame period of the display device 20 may include a display period in which the shift register 10 performs a shift operation and a retrace period in which the shift register 10 does not perform a shift operation.

[0026] Figure 10 is a block diagram showing the configuration of this shift register. Figure 11 is a timing chart showing multiple input signals to this shift register. Figures 12 to 14 are circuit diagrams showing the configuration of the unit stage of the shift register according to this embodiment. As shown in Figures 10 to 14, in the shift register 10, the unit circuit J includes a sixth transistor T6 to which an initialization signal IS is input at the gate terminal (terminal I), and the second node N2 may be connected to the second power supply VH via the sixth transistor T6. Since the initialization signal IS is inactive ("Low") during the display period and active ("High") during the retrace period, the second node N2 can be connected to the second power supply VH during the retrace period to keep the second transistor T2 stably ON, and the potential of the output signal Un can be maintained at "Low".

[0027] In the n-th stage unit circuit Jn shown in Figures 12 to 14, the set signal SS input to terminal S is the output signal Un-1 of the (n-1)th stage, the reset signal RS input to terminal R is the output signal Un+1 of the (n+1)th stage, the clock signal K1 is input to terminal X (input terminal), and the clock signal KB is input to terminal Y as the control signal ZS.

[0028] In the shift register 10, as shown in Figures 13 and 14, the first circuit 11 may include a set auxiliary transistor TE to which a set signal SS is input at gate terminal S and connected to the second node N2, and the second circuit 12 may include a reset auxiliary transistor TF to which a reset signal RS is input at gate terminal R and connected to the first node N1. This allows the second node N2 to be quickly charged to a "Low" potential during setting and the first node N1 to be quickly charged to a "Low" potential during reset. The channel width of the reset auxiliary transistor TF may be smaller than the channel width of the reset transistor TR.

[0029] Figure 15 is a timing chart showing the operation of the shift register. As shown in Figures 14 and 15, the unit circuit J of the shift register 10 may include a seventh transistor T7 whose gate terminal is connected to a first node N1, an eighth transistor T8 whose gate terminal is connected to a second node N2, and a third node N3. The third node N3 may be connected to a first power supply VL via a fifth transistor T5, the third node N3 may be connected to a second power supply VH via a seventh transistor T7, and the third node N3 may be connected to a first node N1 via an eighth transistor T8. The fifth transistor and the seventh and eighth transistors T7 and T8 may constitute an active sensing circuit DC.

[0030] As shown in Figure 15, during period H2, the potential V1 of the first node N1 becomes "High," which turns on the seventh transistor T7 and causes the potential V3 of the third node N3 to become "High." During period H4, the potential V2 of the second node N2 becomes "High," which turns on the fifth and eighth transistors T5 and T8, causing the potentials V1 and V3 of the first node N1 and the third node N3 to become "Low." In the active detection circuit DC, the activation of the first node N1 (rise of the potential V1 of N1) and the activation of the third node N3 (rise of the potential V3 of N3) are synchronized, so the activation of the first node N1 can be detected.

[0031] Figure 16 is a block diagram showing the configuration of this shift register. Figure 17 is a circuit diagram showing the configuration of the unit stage in Figure 16. Figure 18 is a timing chart showing the operation of this shift register. As shown in Figures 16 to 18, in the unit stage Jn of the shift register 10, the gate terminal (terminal R) of the reset transistor TR is connected to one of the conductive terminals of the reset transistor TR, the clock signal K2 is input to terminal R as a reset signal, and the output signal Un+1 of the next stage may be input to the gate terminal (terminal Ri) of the reset auxiliary transistor TF as an auxiliary reset signal. The second node N2 is connected to terminal R via the reset transistor TR and may also be connected to the first power supply VL via the auxiliary set transistor TE.

[0032] In the unit circuit Jn of Figure 17, the gate terminal (terminal S) of the set transistor TS is connected to one of the conductive terminals of the set transistor TS, and the output signal Un-1 of the preceding stage may be input to terminal S as a set signal. The first node N1 may be connected to the first power supply VL via the reset auxiliary transistor TF. The clock signal K1 may be input to terminal X (input terminal), the initialization signal IS may be input to terminal I, and the clock signal KB may be input to terminal Y as a control signal ZS.

[0033] As shown in Figures 16 to 18, a clock signal K2 that includes a rise-type pulse synchronized with the pulse of the output signal Un+1 of the next stage can be used as the reset signal input to the gate terminal (terminal R) of the reset transistor TR.

[0034] Figure 19 is a block diagram showing the configuration of this shift register. Figure 20 is a circuit diagram showing the configuration of the unit stage in Figure 19. The operation of this shift register is as shown in Figure 18. As shown in Figures 19 and 20, in the unit stage Jn of the shift register 10, the gate terminal (terminal R) of the reset transistor TR is connected to one of the conductive terminals of the reset transistor TR, the clock signal K2 is input to terminal R as a reset signal, and the output signal Un+1 of the next stage may be input to the gate terminal (terminal Ri) of the reset auxiliary transistor TF as an auxiliary reset signal. The second node N2 is connected to terminal R via the reset transistor TR and may also be connected to the first power supply VL via the auxiliary set transistor TE.

[0035] In the unit circuit Jn shown in Figure 20, the output signal Un-1 from the previous stage is input to the gate terminal (terminal S) of the set transistor TS, and the clock signal K4 may be input to one of the conducting terminals (terminal M) of the set transistor TS. The first node N1 is connected to terminal M via the set transistor TS. The clock signal K1 is input to terminal X (input terminal), the initialization signal IS is input to terminal I, and the clock signal KB may be input to terminal Y as the control signal ZS.

[0036] As shown in Figures 19 and 20, a clock signal K4 containing a rise-type pulse synchronized with the pulse of the output signal Un-1 of the preceding stage can be input to the conductive terminal (terminal M) of the set transistor TS (see Figure 18).

[0037] Figure 21 is a block diagram showing the configuration of this shift register. Figures 22 and 23 are circuit diagrams showing the configuration of the unit stage in Figure 20. The operation of this shift register is as shown in Figure 18. As shown in Figures 21 to 23, in the unit stage Jn of the shift register 10, the gate terminal (terminal R) of the reset transistor TR is connected to the gate terminal of the auxiliary reset transistor TF, and the clock signal K2 may be input to terminal R as a reset signal.

[0038] In the unit circuit Jn shown in Figures 22 and 23, the output signal Un-1 of the previous stage may be input to the gate terminal (terminal S) of the set transistor TS, and the clock signal K4 may be input to one of the conducting terminals (terminal M) of the set transistor TS. The first node N1 is connected to terminal M via the set transistor TS. The clock signal K1 may be input to terminal X (input terminal), the initialization signal IS may be input to terminal I, and the clock signal KB may be input to terminal Y as a control signal ZS.

[0039] The second node N2 is connected to the second power supply VH via the reset transistor TR. Furthermore, the second node N2 may be connected to the first power supply VL via the auxiliary set transistor TE (see Figure 22), or to terminal R via the auxiliary set transistor TE (see Figure 23). This is because the clock signal K2 input to terminal R is at a "low" potential when the set signal (the output signal Un-1 of the previous stage) is active (see Figure 18).

[0040] Figure 24 is a timing chart showing the operation of the display device that performs touch detection. Figure 25 is a block diagram showing the configuration of this shift register. Figure 26 is a timing chart showing multiple input signals to this shift register. Figure 27 is a circuit diagram showing the configuration of the unit stage in Figure 25. Figures 28 and 29 are timing charts showing the operation of this shift register. As shown in Figures 24 to 29, the display device 20 can insert a touch detection period into the display period. In this case, the touch position can be detected by controlling the potential Vc of each of the multiple counter electrodes CE shown in Figure 8.

[0041] The unit circuit Jn shown in Figure 27 includes a fourth circuit (fixed output circuit) 14 connected to the output terminal U, and a switching signal PS that is active (high) for at least a portion of the touch detection period may be input to the fourth circuit 14.

[0042] The fourth circuit 14 may fix the output terminal U to the potential of the first power supply VL during the period when the switching signal PS is active. The fourth circuit 14 may include a ninth transistor T9, to which the switching signal PS is input to the control terminal (terminal P) of the ninth transistor T9, and the output terminal U may be connected to the first power supply VL via the ninth transistor T9.

[0043] As shown in Figure 27, the switching signal PS may be input to the third circuit 13 (for example, the gate terminal of the fourth transistor T4) as a control signal ZS. The control signal ZS may turn the fourth transistor T4 OFF during the shift operation period (for example, the display period) and turn the fourth transistor T4 ON during the shift stop period (for example, the touch detection period).

[0044] As shown in Figures 26 and 28, clock signal K2 is phase-delayed by 1H (horizontal scanning period) compared to clock signal K1, clock signal K3 is phase-delayed by 1H compared to clock signal K2, and clock signal K4 is phase-delayed by 1H compared to clock signal K3. The active period (pulse width) of each clock signal may be 1H or less.

[0045] As shown in Figures 25 and 27, in the (n-1)th stage unit circuit Jn-1, the set signal SS input to terminal S is the output signal Un-2 of the (n-2)th stage, the reset signal RS input to terminal R is the output signal Un of the nth stage, the clock signal K4 is input to terminal X (input terminal), and the switching signal PS is input to terminal Y as the control signal ZS. In the nth stage unit circuit Jn, the set signal SS input to terminal S is the output signal Un-1 of the (n-1)th stage, the reset signal RS input to terminal R is the output signal Un+1 of the (n+1)th stage, the clock signal K1 is input to terminal X (input terminal), and the switching signal PS is input to terminal Y as the control signal ZS. In the (n+1)th stage unit circuit Jn+1, the set signal SS input to terminal S is the output signal Un of the nth stage, the reset signal RS input to terminal R is the output signal Un+2 of the (n+2)th stage, the clock signal K2 is input to terminal X (input terminal), and the switching signal PS is input to terminal Y as the control signal ZS.

[0046] As shown in Figures 28 and 29, the switching signal PS is at a "Low" potential during the indicated period (periods H1, H2, H3, and H4). That is, during period H4 in Figure 28, when the reset signal RS is active High (the reset transistor TR is ON), the switching signal PS is at a "Low" potential, and the second node N2 is isolated from the first power supply VL. In other words, the problem of the first power supply VL and the second power supply VH being short-circuited via the third transistor T3 and the reset transistor TR during reset (the period when the reset transistor TR is ON) can be avoided.

[0047] As shown in Figure 29, during the touch detection period, the switching signal PS is at a "High" potential and the fourth transistor T4 is turned ON, which allows the second node N2 to be stabilized at a "Low" potential. Also, during the period H2 of the display period, when the set signal SS(Un-1) is active High (the set transistor TS is turned ON), the set auxiliary transistor TE is turned ON, which allows the second node N2 to be charged at a "Low" potential.

[0048] Figure 30 is a block diagram showing the configuration of this shift register. Figure 31 is a circuit diagram showing the configuration of the unit stage in Figure 30. Figure 32 is a timing chart showing the operation of this shift register. As shown in Figures 30 to 32, in the unit circuit Jn of the shift register 10, the output signal Un-1 of the previous stage is input to the gate terminal (terminal S) of the set transistor TS, the second power supply VH is connected to one of the conductive terminals of the set transistor TS, the clock signal K1 is input to terminal X (input terminal), the initialization signal IS is input to terminal I, and the switching signal PS may be input to terminal Y as the control signal ZS.

[0049] The first node N1 is connected to the first power supply VL via an auxiliary reset transistor TF and to the second power supply VH via a set transistor TS. The second node N2 is connected to the second power supply VH via a reset transistor TR and to the first power supply VL via an auxiliary set transistor TE. A clock signal K2 is input to the gate terminal (terminal R) of the reset transistor TR, and terminal R is connected to the gate terminal of the auxiliary reset transistor TF. The first and second nodes N1 and N2 may be connected to an active detection circuit DC.

[0050] In Figure 32, during period H4, the reset transistor TR is ON, and the switching signal PS is at a "Low" potential, so the second node N2 is isolated from the first power supply VL. In other words, the problem of the first power supply VL and the second power supply VH being short-circuited via the third transistor T3 and the reset transistor TR during reset (the period when the reset transistor TR is ON) can be avoided.

[0051] Furthermore, during the touch detection period shown in Figure 32, the switching signal PS is at a "High" potential and the fourth transistor T4 is turned ON, which allows the second node N2 to be stabilized at a "Low" potential. Also, during the period H2 of the display period, when the set signal SS(Un-1) is active High (the set transistor TS is turned ON), the set auxiliary transistor TE is turned ON, which allows the second node N2 to be charged at a "Low" potential.

[0052] The embodiments described above are for illustrative and explanatory purposes only, and not for limitation. It will be apparent to those skilled in the art that many variations are possible based on these examples and descriptions.

[0053] 〔summary〕 The shift register of embodiment 1 comprises a plurality of unit circuits, each unit circuit including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, and a third transistor whose gate terminal is connected to the first node, wherein each unit circuit includes the third circuit, the second node is connected to a first power supply via the third transistor and the third circuit, and a control signal is input to the third circuit.

[0054] The shift register of embodiment 2 is the shift register of embodiment 1, wherein the third circuit includes a fourth transistor, the second node is connected to the first power supply via the third and fourth transistors, and the control signal is input to the gate terminal of the fourth transistor.

[0055] In the shift register of embodiment 3, the fourth transistor is turned OFF during the active period of the reset signal by the control signal, as is the case in the shift register of embodiment 1 or 2.

[0056] In the shift register of embodiment 4, the control signal and the reset signal are in opposite phase during the period when the reset signal is active in any one of the shift registers of embodiments 1 to 3.

[0057] In the shift register of embodiment 5, the fourth transistor is turned ON during the active period of the set signal by the control signal, as is the case in the shift register of embodiment 2.

[0058] The shift register of embodiment 6 is a shift register of any one of embodiments 1 to 5 in which each unit circuit includes an output terminal connected to one conductive terminal of the first transistor and one conductive terminal of the second transistor.

[0059] The shift register of embodiment 7 is a shift register of any one of embodiments 1 to 6 in which a plurality of phase clock signals are input to the plurality of unit circuits, one of the plurality of phase clock signals is input to the other conductive terminal of the first transistor, and the other conductive terminal of the second transistor is connected to the first power supply.

[0060] In the shift register of embodiment 8, the control signal is another one of the multi-phase clock signals, in the shift register of embodiment 7.

[0061] The shift register of embodiment 9 is the shift register of claim 1, wherein in any one of the shift registers of embodiments 1 to 8, the reset signal is the output of a unit circuit located after the current stage.

[0062] In the shift register of embodiment 10, the reset signal is one of the other multi-phase clock signals, as in the shift register of embodiment 7.

[0063] The shift register of embodiment 11 is a shift register in any one of embodiments 1 to 10 in which each unit circuit includes a fifth transistor whose gate terminal is connected to the second node, and the first node is connected to the first power supply via the fifth transistor.

[0064] The shift register of embodiment 12 is a shift register in any one of embodiments 1 to 11 in which each unit circuit includes a capacitive element, and one conductive terminal of the first transistor is connected to the gate terminal of the first transistor via the capacitive element.

[0065] The shift register of embodiment 13 is one of the shift registers of embodiments 1 to 12, in which the first circuit and the second circuit are each connected to the second power supply.

[0066] The shift register of embodiment 14 is a shift register of any one of embodiments 1 to 13 in which each unit circuit includes a sixth transistor to which an initialization signal is input at the gate terminal, and the second node is connected to a second power supply via the sixth transistor.

[0067] The shift register of embodiment 15 is a shift register of any one of embodiments 1 to 14, wherein the first circuit includes a set transistor to which the set signal is input and which is connected to a first node, and the second circuit includes a reset transistor to which the reset signal is input and which is connected to a second node.

[0068] The shift register of embodiment 16 is a shift register of any one of embodiments 1 to 15, wherein the first circuit includes a set auxiliary transistor to which the set signal is input and which is connected to a second node, and the second circuit includes a reset auxiliary transistor to which the reset signal is input and which is connected to a first node.

[0069] The shift register of embodiment 17 is a shift register of any one of embodiments 1 to 16 in which each unit circuit includes a seventh transistor whose gate terminal is connected to the first node, an eighth transistor whose gate terminal is connected to the second node, and a third node, wherein the third node is connected to the first power supply via the fifth transistor, the third node is connected to the second power supply via the seventh transistor, and the third node is connected to the first node via the eighth transistor.

[0070] The shift register of embodiment 18 is the shift register of embodiment 6, wherein each unit circuit includes a fourth circuit connected to the output terminal, and the fourth circuit is input to a switching signal that is active for at least a portion of the touch detection period.

[0071] The shift register of embodiment 19 is the same as the shift register of embodiment 18, wherein the fourth circuit fixes the output terminal to the potential of the first power supply during the period when the switching signal is active.

[0072] In the shift register of embodiment 20, the switching signal is input to the third circuit as the control signal in the shift register of embodiment 18.

[0073] The shift register of embodiment 21 is the same as the shift register of embodiment 2, wherein the control signal turns the fourth transistor OFF during the shift operation period and turns the fourth transistor ON during the shift stop period.

[0074] The shift register of embodiment 22 is provided in a display device equipped with a touch sensor, in the shift register of embodiment 17, and the shift stop period is the touch detection period.

[0075] The shift register of embodiment 23 is one of the shift registers of embodiments 1 to 22, wherein the first to third transistors are of the n-channel type, and the first power supply is a low-potential side power supply.

[0076] The display device of embodiment 24 comprises one of the shift registers of embodiments 1 to 23.

[0077] Embodiment 25 comprises a plurality of unit circuits, each unit circuit including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, a third transistor whose gate terminal is connected to the first node, and a fourth transistor, wherein the second node is connected to a shift register via the third and fourth transistors to a first power supply, The active period of the reset signal is the time during which the fourth transistor is turned OFF, which is the method for driving the shift register.

[0078] The shift register driving method of embodiment 26 is the same as the shift register driving method of embodiment 25, wherein the fourth transistor is turned OFF during the shift operation period and the fourth transistor is turned ON during the shift stop period. [Explanation of Symbols]

[0079] T1-T9 Transistors 1-T9 11~14 1st~4th circuit K1~K4 Clock signals KA~KD Clock signal N1~N3 1st~3rd Nodes ZS control signal SS Set Signal RS reset signal TS Set Transistor TR Reset Transistor TE Set Auxiliary Transistor TF Reset Aid Transistor

Claims

1. A shift register comprising multiple unit circuits, each unit circuit including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, and a third transistor whose gate terminal is connected to the first node, Each unit circuit includes a third circuit, The second node is connected to the first power supply via the third transistor and the third circuit. A shift register to which a control signal is input to the third circuit.

2. The third circuit includes a fourth transistor, The second node is connected to the first power supply via the third transistor and the fourth transistor, The shift register according to claim 1, wherein the control signal is input to the gate terminal of the fourth transistor.

3. The shift register according to claim 2, wherein the fourth transistor is turned OFF during the active period of the reset signal by the control signal.

4. The shift register according to claim 2, wherein the control signal and the reset signal are in opposite phase during the period when the reset signal is active.

5. The shift register according to claim 2, wherein the fourth transistor is turned ON during the active period of the set signal by the control signal.

6. The shift register according to claim 1, wherein each unit circuit includes an output terminal connected to one conductive terminal of the first transistor and one conductive terminal of the second transistor.

7. Multiple unit circuits are input to a multi-phase clock signal. One of the multiple-phase clock signals is input to the other conductive terminal of the first transistor. The shift register according to claim 6, wherein the other conductive terminal of the second transistor is connected to the first power supply.

8. The shift register according to claim 7, wherein the control signal is another one of the multi-phase clock signals.

9. The shift register according to claim 1, wherein the reset signal is the output of a unit circuit located after the current stage.

10. The shift register according to claim 7, wherein the reset signal is another one of the multi-phase clock signals.

11. Each unit circuit includes a fifth transistor whose gate terminal is connected to the second node. The shift register according to claim 1, wherein the first node is connected to the first power supply via the fifth transistor.

12. Each unit circuit includes a sixth transistor to which an initialization signal is input at the gate terminal. The shift register according to any one of claims 1 to 11, wherein the second node is connected to the second power supply via the sixth transistor.

13. The first circuit includes a set transistor to which the set signal is input and which is connected to the first node, The shift register according to any one of claims 1 to 11, wherein the second circuit includes a reset transistor to which the reset signal is input and which is connected to the second node.

14. The first circuit includes a set auxiliary transistor to which the set signal is input and which is connected to the second node. The shift register according to claim 13, wherein the second circuit includes a reset assist transistor to which the reset signal is input and which is connected to the first node.

15. Each unit circuit includes a seventh transistor whose gate terminal is connected to the first node, an eighth transistor whose gate terminal is connected to the second node, and a third node. The third node is connected to the first power supply via the fifth transistor, The third node is connected to the second power supply via the seventh transistor, The shift register according to claim 11, wherein the third node is connected to the first node via the eighth transistor.

16. Each unit circuit includes a fourth circuit connected to the output terminal, The fourth circuit receives a switching signal that is active for at least a portion of the touch detection period. The fourth circuit fixes the output terminal to the potential of the first power supply during the period when the switching signal is active. The shift register according to claim 6, wherein the switching signal is input to the third circuit as the control signal.

17. The shift register according to claim 2, wherein the control signal turns the fourth transistor OFF during the shift operation period and turns the fourth transistor ON during the shift stop period.

18. Provided in a display device equipped with a touch sensor, The shift register according to claim 17, wherein the shift stop period is a touch detection period.

19. A display device comprising a shift register according to any one of claims 1 to 11.

20. The shift register comprises multiple unit circuits, each unit circuit including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor and a second transistor, a first node connected to the gate terminal of the first transistor, a second node connected to the gate terminal of the second transistor, a third transistor whose gate terminal is connected to the first node, and a fourth transistor, wherein the second node is connected to a first power supply via the third and fourth transistors, A method for driving a shift register, wherein the fourth transistor is turned OFF during the active period of the reset signal.

Images