Method, apparatus, and medium for performing security verification on data in an integrated circuit.

Abstract

Embodiments of this disclosure disclose a method, apparatus, and medium for performing security verification on data in an integrated circuit. [Solution] A method for performing security verification on data in an integrated circuit includes the steps of: determining a first address segment when a first set of data is written to a first memory located in the integrated circuit, based on an address corresponding to a write pointer; storing the first set of data in the storage space of the first address segment in the first memory; determining target encoded data based on the first set of data; and storing the target encoded data in a second memory located in the integrated circuit, wherein the first memory differs from the second memory in the steps of: performing security verification on a second set of data read from the first memory based on the target encoded data.

Description

Technical Field

[0001] The present disclosure relates to data processing technologies in integrated circuits, and in particular, to a method, apparatus, and medium for performing security verification on data in an integrated circuit.

Background Art

[0002] In in-vehicle applications, high-speed in-vehicle chips (for example, in-vehicle SoC chips, one-chip microcontroller chips, Ethernet chips) have a large amount of data exchange. To temporarily cache data and solve problems such as speed inconsistency, a large number of first-in-first-out (FIFO, First Input First Output) memories are required. The FIFO memory is a buffer stage of the system. Without the FIFO memory, the entire high-speed in-vehicle chip cannot operate normally. When the data in the FIFO memory is used, it needs to be protected by security. How to realize the security protection of the FIFO memory at low cost is a technical problem that needs to be solved urgently.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure is made to solve the above technical problems. Embodiments of the present disclosure provide a method, apparatus, and medium for performing security verification on data in an integrated circuit.

Means for Solving the Problems

[0004] According to one aspect of the embodiments of the present disclosure, determining a first address segment when a first set of data is written into a first memory located in an integrated circuit based on an address corresponding to a write pointer; storing the first set of data in a storage space in the first memory of the first address segment; determining target encoded data based on the first set of data; A step of storing the target encoded data in a second memory located in the integrated circuit, wherein the steps are different from those for the first memory and the second memory. A method is provided for performing security verification on data in an integrated circuit, which includes the step of performing security verification on a second set of data read from the first memory based on the target encoded data.

[0005] According to another embodiment of the embodiments of this disclosure, An address determination module for determining the first address segment when a first set of data is written to a first memory located in an integrated circuit, based on the address corresponding to the write pointer, A data storage module for storing the first set of data in the storage space of the first memory in the first address segment, A data coding module for determining target coded data based on the aforementioned first set of data, A code writing module for storing the target coded data in a second memory located in the integrated circuit, wherein the first memory is a code writing module different from the second memory, A device for performing security verification on data in an integrated circuit is provided, which includes a security verification module for performing security verification on a second set of data read from the first memory based on the target encoded data.

[0006] According to yet another embodiment of the embodiments of the present disclosure, a computer-readable storage medium is provided, which, when executed by a processor, stores a computer program for performing a method for performing security verification on data in the integrated circuit described in any one of the embodiments described above.

[0007] According to yet another embodiment of the embodiments of this disclosure, Processor and The processor includes a memory for storing executable instructions, The provided electronic device is used to implement a method for performing security verification on data in an integrated circuit according to any one of the above embodiments, by reading and executing the executable instructions from the memory. [Effects of the Invention]

[0008] Based on the method, apparatus, and medium for performing security verification of data in the integrated circuit provided in the above embodiments of this disclosure, when a first set of data is stored in the storage space of a first memory, target encoded data corresponding to the first set of data is stored in a second memory, and when the second set of data is read from the first memory, data verification is performed using the independently stored target encoded data. Since the target encoded data used for data verification and the first set of data are stored in different memories, it is avoided that the first set of data and the target encoded data be stored in the same place, thereby reducing the amount of data stored in the first memory, which in turn reduces the bit width of the data during data transmission, lowers the cost of data verification, and enables low-cost data verification.

[0009] The technical solutions of this disclosure will be described in more detail below with reference to drawings and embodiments. [Brief explanation of the drawing]

[0010] The above and other purposes, features and advantages of this disclosure will become more apparent through a more detailed description of the embodiments of this disclosure accompanied by the drawings. The drawings are used to better understand the embodiments of this disclosure, form part of the specification, and are used to illustrate this disclosure together with the embodiments of this disclosure, and do not limit this disclosure. In the drawings, the same reference numerals generally indicate the same component or step. [Figure 1] This is a schematic diagram of a system for performing security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. [Figure 2]This is a flowchart illustrating a method for performing security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. [Figure 3] This is a flowchart of step 206 in the embodiment shown in Figure 2 of this disclosure. [Figure 4] This is a flowchart of step 2062 in the embodiment shown in Figure 3 of this disclosure. [Figure 5] This is a flowchart of step 210 in the embodiment shown in Figure 2 of this disclosure. [Figure 6] This is a flowchart illustrating a method for performing security verification on data in an integrated circuit provided in another exemplary embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the structure of a device that performs security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. [Figure 8a] This is a schematic diagram of the structure of a device for performing security verification on data in an integrated circuit provided in another exemplary embodiment of the present disclosure. [Figure 8b] This is a schematic diagram of the structure of a data encoding module provided in another exemplary embodiment of the present disclosure. [Figure 9a] This is a schematic diagram of the structure of a device for performing security verification on data in an integrated circuit provided in yet another exemplary embodiment of the present disclosure. [Figure 9b] This is a schematic diagram of the structure of a security verification module provided in yet another exemplary embodiment of the present disclosure. [Figure 10] This is a structural diagram of an electronic device provided in one exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] To illustrate this disclosure, exemplary embodiments of this disclosure will be described in detail below with reference to the drawings. It should be understood that the embodiments described are not all embodiments but only a selection of embodiments of this disclosure, and that this disclosure is not limited to the exemplary embodiments described herein.

[0012] It should be noted that the relative arrangements, mathematical formulas, and numerical values of the components and steps described in these embodiments do not limit the scope of the present disclosure unless specifically described otherwise.

[0013] Summary of the Application In the process of implementing the present disclosure, the inventors discovered that integrated circuits (such as high-speed in-vehicle chips, etc.) may have a large number of FIFO memories used for data caching, transfer, and operation speed matching. The functions of the FIFO memory include: 1) caching a continuous data stream and preventing data loss during push and storage operations; 2) performing push and storage of data in batches and processing the data in batches, so that the push and storage that originally required multiple bus operations can be completed in one bus operation, avoiding frequent bus operations, and reducing the burden on the CPU; 3) allowing the system to perform direct memory access (DMA) operations and improving the data transmission speed. Therefore, it is necessary to perform security verification when reading data from the FIFO memory. When the bit width of the FIFO memory is wide and the depth is very deep, in order to perform security verification on the data stored in the FIFO memory by the conventional method, it is necessary to occupy many data bit widths. To solve the above problems, the present disclosure provides a method for performing security verification on data in an integrated circuit, reducing the bit width occupied when performing security verification on the data stored in the FIFO memory, and reducing the chip area and the cost of the integrated circuit.

[0014] Exemplary Method FIG. 1 is a structural schematic diagram of a system for performing security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. As shown in FIG. 1, the system provided in the embodiment of the present disclosure includes a first memory 101 and a second memory 102.

[0015] The first memory 101 is a FIFO memory used to store interactive data. When reading data, it is read in the order in which it was stored; that is, data stored in the FIFO memory first is read first. For example, the diagram shows that the data stream is from top to bottom. In this case, the input data initially entered into the first memory 101 is stored at the bottom (the memory space numbered 1 in the diagram), and subsequent data is stored sequentially according to the order of the memory space in the first memory 101 (to indicate the order, the memory addresses in the first memory 101 are sorted in the diagram according to the numbers 1, 2, 3...n-2, n-1, n). When reading data from the first memory, it is read according to the order of the memory space, and data stored first is read first.

[0016] The second memory 102 stores encoded data corresponding to the input data when data is stored in the first memory 101. When output data is read from the first memory 101, the second memory 102 reads encoded data corresponding to the output data and verifies the integrity of the output data.

[0017] Exemplary Method Figure 2 is a flowchart of a method for performing security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices such as automotive integrated circuits and includes the following steps 202-210, as shown in Figure 2.

[0018] In step 202, the first address segment is determined based on the address corresponding to the write pointer, in which the first set of data is written to the first memory located in the integrated circuit.

[0019] Here, a pointer describes the location of data in memory and indicates the relative distance of the entity occupying the memory space to the starting position of that space, and a write pointer is the pointer corresponding when data is written. In this embodiment, the first address segment is determined by the start address and end address. Optionally, the write pointer indicates the start address of the first address segment of the data to be written in the first memory, and optionally, the size of the first address segment can be determined by the size of the first set of data; that is, the start address of the first address segment is determined by the write pointer, and the end address of the first address segment is obtained by accumulating the size of the first set of data from that start address, thereby determining the first address segment.

[0020] In step 204, the first set of data is stored in the memory space of the first memory in the first address segment.

[0021] In one embodiment, the first memory may be a FIFO memory, and the storage space in the first memory has a correspondence with addresses. For example, a storage space of a certain size can be searched based on the start address and end address corresponding to the first address segment. For example, the amount of bytes that can be stored in the first memory is 256 bytes, and the first address segment is from 00000000 (start address) to 00000110 (end address), corresponding to bytes 0 to 6 in the storage space. At this time, a first set of data is stored based on the storage space from bytes 0 to 6.

[0022] In step 206, the target encoded data is determined based on the first set of data.

[0023] Selectively, the first set of data is subjected to at least one encoding process to obtain the target encoded data, where the encoding method includes, but is not limited to, cyclic redundancy check (CRC), hash encoding, compression encoding, and identifier encoding, and the obtained target encoded data includes, but is not limited to, cyclic redundancy check codes, hash codes, compression codes, identifier codes, etc.

[0024] In step 208, the target encoded data is stored in a second memory located in the integrated circuit.

[0025] Here, the first memory and the second memory are different. The first memory and the second memory are used to store different data, and they are independent of each other, enabling independent storage of the first set of data and the target encoded data. Selectively, the type of memory of the second memory may be the same as or different from that of the first memory; for example, the second memory may be a FIFO memory.

[0026] In step 210, security verification is performed on the second set of data read from the first memory based on the target encoded data.

[0027] In conventional technologies, data can face various interferences and errors during transmission, such as data loss and data tampering. Without effective verification, these data errors can cause system malfunctions and even collapse. Therefore, data verification is particularly important in FIFOs, and the embodiments of this disclosure achieve effective security verification of data by performing security verification on a second set of data based on the target encoded data.

[0028] In this embodiment, data security verification may also be data integrity verification, which is achieved by incrementing a verification code or verification value during data transmission. The sender calculates a verification code when transmitting data, and the receiver recalculates and compares the verification code after receiving the data, thereby checking the integrity of the data.

[0029] In the integrated circuit provided in the embodiment of the present invention, a method for performing security verification on data involves storing target encoded data corresponding to the first set of data in the storage space of the first memory when the first set of data is stored in the storage space of the first memory, and performing data verification using the independently stored target encoded data when the second set of data is read from the first memory. Since the target encoded data used for data verification and the first set of data are stored in different memories, it is avoided that the first set of data and the target encoded data are stored together, thereby reducing the amount of data stored in the first memory, which in turn reduces the data bit width during data transmission, lowers the cost of data verification, and enables low-cost data verification.

[0030] As shown in Figure 3, in the embodiment shown in Figure 2, step 206 may include the following steps 2061 and 2062.

[0031] In step 2061, an encoding operation is performed on the first set of data to obtain the data code corresponding to the first set of data.

[0032] Selectively, the first set of data may contain a predetermined number of data points, and the possible values ​​of this predetermined number can be set according to the specific application scenario, thereby realizing a data encoding process with adjustable granularity. Selectively, encoding is performed on each of the predetermined number of data points contained in the first set of data to obtain the corresponding data code. Here, granularity refers to the size and precision of the data units (corresponding to the first set of data in this embodiment) that are the focus when observing or processing the data. It may be coarse-grained (large data units) or fine-grained (small data units). Coarse-grained data results in a larger amount of encoded data stored at one time, leading to greater spatial compression.

[0033] In step 2062, the target encoded data is determined based on a predetermined number of data codes.

[0034] In this embodiment, the granularity of the data code is adjusted by a preset number, and different preset numbers can be set according to different application scenes, thereby meeting the demands of the corresponding application scenes. For example, when the amount of data is large, the preset number can be increased to increase the amount of data that can be verified in one go, thereby improving the efficiency of data verification. Conversely, when the amount of data is small and the required accuracy is high, the preset number can be decreased to reduce the amount of data that can be verified in one go, thereby quickly positioning error data and improving data verification accuracy.

[0035] As shown in Figure 4, in the embodiment shown in Figure 3, step 2062 may include the following steps 401 to 403.

[0036] In step 401, a numerical value is accumulated for the write pointer, and the number of data codes is determined based on the accumulated amount of the write pointer.

[0037] Selectively, after each write pointer determines an address for the corresponding write data, the write pointer corresponding to the next write data is determined based on the relevant write pointer. That is, the amount of stored data can be determined according to the cumulative amount of the write pointer values, and in a single storage operation, the number of data items in the first set of data can be determined according to the cumulative amount of the write pointers, and furthermore, the number of data codes can be determined.

[0038] In step 402, based on the relationship between the number of data codes and a predetermined number, a predetermined number of data codes are processed to obtain the target encoded data.

[0039] Selectively, the number of data codes can be counted using a counter, and the relationship between the number of data codes and a preset number can be determined based on the counter's count result. Selectively, the determination of target coded data can be determined by calculating whether the remainder when the counter's count result is divided by a preset number is 0 or not. For example, if the remainder is 0, the target coded data can be determined based on a preset number of data codes; if the remainder is not 0, the target coded data can not be determined. Also, for example, if the counter value reaches a preset number, a clear process can be performed once, and the determination of target coded data can be determined depending on whether the counter value is 0 or not. For example, if the counter data is 0, the target coded data can be determined based on a preset number of data codes; if the counter data is not 0, the target coded data can not be determined.

[0040] Selectively, a predetermined number of data codes can be accumulated to obtain target encoded data, or a predetermined number of data codes can be encoded or processed by other data processing methods to obtain target encoded data, for example, at least one of the operations of addition, subtraction, multiplication, or division can be performed on a predetermined number of data codes, or for example, hashing can be performed on a predetermined number of data codes.

[0041] In step 403, the target encoded data is stored in a pre-configured memory space in the second memory.

[0042] Selectively, the determination of a pre-configured memory space in the second memory can be similar to the determination of a memory space in the first memory, for example, by determining the pre-configured memory space based on the corresponding write pointer.

[0043] In this embodiment, each time data is written to the first memory, encoding is performed on the data, and each time data is stored, the write pointer performs a corresponding cumulative operation. Each time the cumulative value of the write pointer reaches a predetermined number, target encoded data is obtained based on a predetermined number of encoded data, and the target encoded data is stored in the second memory. By storing only the target encoded data in the second memory, and by making the number of target encoded data much smaller than the number of encoded data (the number of target encoded data is 1 / m of the encoded data, where m is a predetermined number), the amount of data stored in the second memory is reduced, thereby compressing the storage space of the second memory and reducing the space it occupies within the integrated circuit.

[0044] As shown in Figure 5, in the embodiment shown in Figure 2, step 210 may include the following steps 2101 to 2103.

[0045] In step 2101, the second set of data is read from the first memory.

[0046] Selectively, the first memory is a FIFO memory, and therefore, when data is read, the second set of data read is the data that was stored earliest in the first memory at the current time. For example, the second set of data is the data located in the memory space from memory space number 1 to number m (where m is a predetermined number) in the first memory shown in Figure 1. For example, the second set of data may be the data from the first set.

[0047] Selectively, based on the second address segment corresponding to the read pointer, data is read from the storage space in the first memory of the second address segment, and the numerical value is accumulated against the read pointer.

[0048] In this embodiment, the read pointer can point to the second address segment corresponding to the earliest stored data in the first memory. The data stored in the memory space corresponding to the second address segment is the earliest stored data at the current time. The data in the memory space is read, achieving first-in, first-out data reading. After the second set of data has been read, the memory space corresponding to the second address segment is cleared, and the stored data can continue to be received. Furthermore, the accuracy of the address when the next data is read is guaranteed by accumulating the values ​​of the read pointer.

[0049] Based on the cumulative numerical results, a predetermined number of reading data points are determined, and a second set of data is obtained.

[0050] When selectively reading data, the target encoded data stored in the second memory corresponds to a preset number of input data. To achieve integrity verification of the read data based on the target encoded data, a preset number of read data is read sequentially, the second set of data is used as the verification granularity, and a preset number of read data is verified each time, thereby improving the efficiency of data verification.

[0051] In step 2102, the output encoded data is determined based on the second set of data.

[0052] Selectively, all read data included in the second set of data may be encoded using the same encoding method as the input data, thereby obtaining the output encoded data obtained by encoding the second set of data.

[0053] In step 2103, the integrity of the second set of data is determined based on the relationship between the output encoded data and the target encoded data corresponding to the second set of data.

[0054] Selectively, the target encoded data is the encoded data obtained by encoding the second set of data and storing it in the second memory when the second set of data is input into the first memory.

[0055] In this embodiment, the output encoded data is obtained using the same encoding method as the target encoded data. Therefore, if the data before encoding is the same, the corresponding output encoded data and the target encoded data should be the same. This embodiment matches the output encoded data obtained by encoding when reading the second set of data with the target encoded data obtained by encoding at input. If the output encoded data and the target encoded data are the same, it is determined that the second set of data is complete; otherwise, it is determined that the second set of data is incomplete. In response to the incompleteness of the second set of data, an error report is performed.

[0056] Selectively, step 2102 may include the following:

[0057] Perform at least one encoding operation on the second set of data to obtain at least one operation code, and determine the output encoded data based on at least one operation code.

[0058] In this embodiment, encoding is performed for each output data included in the second set of data, and the encoding method used for the encoding is the same as the encoding method used when storing data in the first memory, ensuring comparability between the output encoded data and the target encoded data. Selectively, each time output data is read, encoding is performed on the read output data to obtain an arithmetic code, and output encoded data is not generated before the number of output data is accumulated to a preset number. Only when the number of output data reaches a preset number, at least one arithmetic code is processed to obtain output encoded data. Selectively, the processing of at least one arithmetic code is the same as the processing of the data code when the data is stored in the first memory. For example, at least one arithmetic code is accumulated to obtain output encoded data, or encoding or processing by another data processing method is performed on at least one arithmetic code to obtain output encoded data.

[0059] In some selectable embodiments, step 2103 may include the following:

[0060] Determine the corresponding target encoded data in the second memory for the second set of data.

[0061] Selectively, if the second memory is a FIFO memory, the earliest stored data from the second memory is retrieved as the target encoded data corresponding to the second set of data. Alternatively, if the second memory is a general-purpose memory, when storing the second set of data in the first memory, an identification code is assigned to the second set of data and its corresponding target encoded data. The second set of data is stored in the first memory with the identification code attached, and the target encoded data is stored in the second memory with the identification code attached. When reading the second set of data, the obtained identification code is used as an index to retrieve the corresponding target encoded data from the second memory.

[0062] The integrity of the second set of data is determined based on the difference between the read-encoded data and the target-encoded data.

[0063] Selectively, in response to the presence of a difference between the read encoded data and the target encoded data, the system determines that the second set of data is incomplete and sends error reporting information. In response to the absence of a difference between the read encoded data and the target encoded data, the system determines that the second set of data is complete and continues reading data from the first memory, reading the data from the next memory space in the first memory, and continuing to perform integrity verification on the read data. This embodiment determines whether the data read from the first memory is complete in the storage process by comparing the read encoded data with the target encoded data, thereby protecting data integrity. Furthermore, the target encoded data is stored in the second memory, thus reducing the occupancy of memory space in the first memory and lowering the cost of data integrity verification.

[0064] In several selectable embodiments, the comparison between the read encoded data and the target encoded data can be performed using a comparator. For example, the code of each bit in the read encoded data and the target encoded data can be compared using a comparator, and if the code of any bit is different, it can be determined that a difference exists between the read encoded data and the target encoded data. Selectively, the codes of multiple bits in the read encoded data and the target encoded data may be compared simultaneously using a multi-bit comparator, or the codes in the read encoded data and the target encoded data may be compared sequentially using a single-bit comparator.

[0065] Figure 6 is a flowchart of a method for performing security verification on data in an integrated circuit provided in another exemplary embodiment of the present disclosure. This embodiment is applied to an automotive application, in which high-speed automotive chips have a large amount of data exchange and require a large amount of FIFO memory to temporarily cache data and solve problems such as speed inconsistencies. As shown in Figure 6, it includes the following steps 601 to 610.

[0066] In step 601, a coding granularity threshold m is set in advance, and it is decided that one target coded data is obtained for every m input data stored according to the coding granularity threshold.

[0067] In step 602, the input data to be exchanged between chips is stored in the first memory according to the memory address corresponding to the write pointer.

[0068] In step 603, each time input data is stored, 1 is added to the write pointer count, and an encoding operation is performed on the corresponding input data to obtain a single data code.

[0069] In step 604, each time a data code (CRC code) is obtained, the value of the first counter is incremented by 1 (the first counter is aligned with the write pointer, and each time 1 is incremented in the write pointer's count, the corresponding value of the first counter is incremented by 1). Based on the cumulative value of the first counter, it is determined whether the number of data codes has reached m. If so, step 605 is performed; otherwise, data writing continues, and step 602 is performed.

[0070] In step 605, the target encoded data is obtained based on m data codes, the target encoded data is stored in the second memory, and the first counter is cleared.

[0071] In step 606, after the input data is stored in the first memory, the system responds to requests for data from other chips by reading data from the first memory according to the memory space corresponding to the read pointer.

[0072] In step 607, each time output data is read, 1 is added to the count of the read pointer, and an encoding operation is performed on the corresponding output data (the encoding method is the same as the encoding method used in step 603) to obtain the operation code.

[0073] In step 608, each time an arithmetic code is obtained, the value of the second counter is incremented by 1 (the second counter is aligned with the read pointer, and each time 1 is incremented in the count of the read pointer, the value of the corresponding second counter is incremented by 1), and based on the cumulative value of the second counter, it is determined whether the number of arithmetic codes has reached m. If so, step 609 is performed; otherwise, data reading continues and step 606 is performed.

[0074] In step 609, output encoded data is obtained based on m arithmetic codes, and the second counter is cleared.

[0075] In step 610, the first data stored in the second memory is read, the obtained target coded data is compared with the output coded data, and it is determined whether the target coded data and the output coded data match. If they do, it is indicated that the m output data corresponding to the output coded data are normal; otherwise, error reporting information is sent to indicate that errors exist in the m output data corresponding to the output coded data.

[0076] Any of the methods for performing security verification on data in an integrated circuit provided in the embodiments of this disclosure can be performed by any device having appropriate data processing capabilities, including but not limited to terminal devices and servers. Alternatively, any of the methods for performing security verification on data in an integrated circuit provided in the embodiments of this disclosure can be performed by a processor, for example, by calling a corresponding instruction stored in memory, thereby performing any of the methods for performing security verification on data in an integrated circuit referred to in the embodiments of this disclosure. Repetitive explanations are omitted below.

[0077] Exemplary device Figure 7 is a schematic diagram of the structure of a device for performing security verification on data in an integrated circuit provided in one exemplary embodiment of the present disclosure. As shown in Figure 7, the device provided in this embodiment includes an address determination module 71, a data storage module 72, a data encoding module 73, a code writing module 74, and a security verification module 75.

[0078] The address determination module 71 is used to determine the first address segment when the first set of data is written to the first memory located in the integrated circuit, based on the address corresponding to the write pointer.

[0079] The data storage module 72 is used to store the first set of data in the storage space of the first memory in the first address segment.

[0080] The data coding module 73 is used to determine the target coded data based on the first set of data.

[0081] The code writing module 74 is used to store the target encoded data in a second memory located in the integrated circuit.

[0082] Here, the first memory and the second memory are different.

[0083] The security verification module 75 is used to perform security verification on the second set of data read from the first memory, based on the target encoded data.

[0084] In the integrated circuit provided in the embodiments of this disclosure, the device for performing security verification on data stores target encoded data corresponding to the first set of data in a second memory when storing the first set of data in the storage space of a first memory, and performs data verification using the independently stored target encoded data when reading the second set of data from the first memory. Since the target encoded data used for data verification and the first set of data are stored in different memories, it avoids storing the first set of data and the target encoded data in the same place, thereby reducing the amount of data stored in the first memory, which in turn reduces the bit width of the data during data transmission, lowers the cost of data verification, and enables low-cost data verification.

[0085] Figure 8a is a schematic diagram of the structure of a device for performing security verification on data in an integrated circuit provided in another exemplary embodiment of the present disclosure. As shown in Figure 8a, the data encoding module 73 in the device provided in this embodiment includes a first encoding unit 731 and a data determination unit 732.

[0086] The first encoding unit 731 is used to perform encoding operations on the first set of data and to obtain data codes corresponding to the first set of data.

[0087] The data determination unit 732 is used to determine the target encoded data based on a predetermined number of data codes.

[0088] Figure 8b is a schematic diagram of the structure of a data coding module provided in another exemplary embodiment of the present disclosure. As shown in Figure 8b, the data determination unit 732 in the data coding module provided in this embodiment includes a first counter 81, a number comparison unit 82, and a code storage unit 83.

[0089] The first counter 81 is used to accumulate a numerical value for the write pointer and to determine the number of data codes based on the accumulated amount for the write pointer.

[0090] The number comparison unit 82 is used to process a predetermined number of data codes based on the relationship between the number of data codes and a predetermined number, in order to obtain the target encoded data.

[0091] The code storage unit 83 is used to store the target coded data in a pre-configured storage space in the second memory.

[0092] Figure 9a is a schematic diagram of the structure of a device for performing security verification on data in an integrated circuit provided in yet another exemplary embodiment of the present disclosure. As shown in Figure 9a, the security verification module 75 in the device provided in this embodiment may include a data reading unit 751, an output encoding unit 752, and a data verification unit 753.

[0093] The data reading unit 751 is used to read the second set of data from the first memory.

[0094] The output coding unit 752 is used to determine the output coded data based on the second set of data.

[0095] The data validation unit 753 is used to determine the integrity of the second set of data based on the relationship between the output encoded data and the target encoded data corresponding to the second set of data.

[0096] Figure 9b is a schematic diagram of the structure of a security verification module provided in yet another exemplary embodiment of the present disclosure. As shown in Figure 9b, the data reading unit 751 in the security verification module provided in this embodiment may include a second counter 91 and a data count determination unit 92.

[0097] The second counter 91 is used to read data from the storage space in the first memory of the second address segment based on the second address segment corresponding to the read pointer, and to accumulate the numerical value with respect to the read pointer.

[0098] The data count determination unit 92 is used to determine a predetermined number of read data based on the cumulative result of the numerical values, and to obtain a second set of data.

[0099] Selectively, in the embodiment shown in Figure 9b, the output encoding unit 752 in the security verification module may include a second encoding unit 93 and an encoded data output unit 94.

[0100] The second coding unit 93 is used to perform at least one coding operation on the second set of data to obtain at least one operation code.

[0101] The encoded data output unit 94 is used to determine the output encoded data based on at least one arithmetic code.

[0102] Selectively, in the embodiment shown in Figure 9b, the data verification unit 753 in the security verification module may include a storage code determination unit 95 and a difference identification unit 96.

[0103] The memory code determination unit 95 is used to determine the corresponding target coded data in the second memory for the second set of data.

[0104] The difference identification unit 96 is used to determine the integrity of the second set of data based on the difference between the read encoded data and the target encoded data.

[0105] Beneficial technical effects corresponding to exemplary embodiments of this apparatus can be found by referring to the corresponding beneficial technical effects of the exemplary method described above, and redundant explanations are omitted here.

[0106] Exemplary electronic device Figure 10 is a structural diagram of an electronic device provided in an embodiment of the present disclosure, the electronic device 10 shown in Figure 10 includes at least one processor 11 and memory 12.

[0107] The processor 11 may be a central processing unit (CPU) or another form of processing unit having data processing and / or instruction execution functions, and can control other components in the electronic device 10 to perform desired functions.

[0108] Memory 12 may include one or more computer program products, which may include computer-readable storage media of various types, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored in the computer-readable storage media, and the processor 11 can execute one or more computer program instructions to implement a method for performing security verification on data and / or other desired functions in the integrated circuits of each embodiment of the present disclosure described above.

[0109] In one example, the electronic device 10 may further include an input device 13 and an output device 14, and these components are connected to each other via a bus system and / or other forms of connection mechanisms (not shown).

[0110] The input device 13 may further include, for example, a keyboard, a mouse, and the like.

[0111] The output device 14 can output various types of information to the outside, and may include, for example, a display, speaker, printer, communication network, and remote output devices connected thereto.

[0112] Naturally, for the sake of simplification, Figure 10 shows only some of the components of the electronic device 10 relevant to this disclosure, omitting components such as buses and input / output interfaces. Beyond this, the electronic device 10 may further include any other appropriate components depending on the specific application.

[0113] Exemplary computer program products and computer-readable storage media Embodiments of the present disclosure may further provide computer program products, including computer program instructions, which, when executed by a processor, cause the processor to perform steps in a method for performing security verification on data in an integrated circuit of various embodiments of the present disclosure as described in the “Exemplary Methods” section above.

[0114] Computer program products can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and general procedural programming languages ​​such as the C language or similar programming languages, to create program code for performing the operations of the embodiments of this disclosure. The program code can run entirely on a user computing device, partially on a user computing device, as a standalone software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0115] Furthermore, embodiments of the present disclosure may be computer-readable storage media on which computer program instructions are stored, and when the computer program instructions are executed by the processor, the processor is instructed to perform steps in the method of performing security verification on data in the integrated circuit of the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0116] Computer-readable storage media can employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0117] The basic principles of this disclosure have been explained above with reference to specific examples; however, the advantages, superiority, and effects mentioned in this disclosure are merely illustrative and not limiting, and are not considered to be necessary for each example of this disclosure. Furthermore, the specific details disclosed above are merely illustrative and for the purpose of facilitating understanding, and are not limiting, and do not imply that this disclosure must be implemented in the specific details described above.

[0118] Those skilled in the art can make various modifications and variations to this disclosure without departing from the spirit and scope of the application. In this manner, the disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and the equivalent art.

Claims

1. The steps include determining the first address segment when the first set of data is written to the first memory located in the integrated circuit, based on the address corresponding to the write pointer, The steps include storing the first set of data in the storage space of the first memory in the first address segment, The steps include determining the target encoded data based on the aforementioned first set of data, The step of storing the target encoded data in a second memory located in the integrated circuit, wherein the first memory performs a different step from the second memory. The step includes performing a security verification on a second set of data read from the first memory based on the target encoded data, A method for performing security verification on data in an integrated circuit, which is executed by a device that performs security verification on data in an integrated circuit.

2. The step of determining the target encoded data based on the first set of data is: The steps include: performing an encoding operation on the first set of data to obtain a data code corresponding to the first set of data; A method for performing security verification on data in an integrated circuit according to claim 1, comprising the step of determining the target encoded data based on a predetermined number of data codes.

3. The step of determining the target encoded data based on a predetermined number of data codes is: The steps include: accumulating numerical values ​​for the write pointer and determining the number of data codes based on the accumulated amount of the write pointer; A method for performing security verification on data in an integrated circuit according to claim 2, comprising the steps of processing the predetermined number of data codes based on the relationship between the number of data codes and a predetermined number, and obtaining the target encoded data.

4. The step of performing security verification on the second set of data read from the first memory based on the target encoded data is: The steps include reading the second set of data from the first memory, The steps include determining the output encoded data based on the second set of data, A method for performing security verification on data in an integrated circuit according to any one of claims 1 to 3, comprising the step of determining the integrity of the second set of data based on the relationship between the output encoded data and the target encoded data corresponding to the second set of data.

5. The step of reading the second set of data from the first memory is: The steps include reading data from the storage space in the first memory of the second address segment based on the second address segment corresponding to the read pointer, and performing a numerical summation with respect to the read pointer, A method for performing security verification on data in an integrated circuit according to claim 4, comprising the steps of determining a predetermined number of read data based on the cumulative result of the aforementioned numerical values, and obtaining the second set of data.

6. The step of determining the output encoded data based on the second set of data is: The steps include performing at least one encoding operation on the second set of data to obtain at least one operation code, A method for performing security verification on data in an integrated circuit according to claim 5, comprising the step of determining the output encoded data based on the at least one arithmetic code.

7. The step of determining the integrity of the second set of data based on the relationship between the output encoded data and the target encoded data corresponding to the second set of data is: The steps include determining the corresponding target encoded data in the second memory for the second set of data, A method for performing security verification on data in an integrated circuit according to claim 5, comprising the step of determining the integrity of the second set of data based on the difference between the read encoded data and the target encoded data.

8. An address determination module for determining the first address segment when a first set of data is written to a first memory located in an integrated circuit, based on the address corresponding to the write pointer, A data storage module for storing the first set of data in the storage space of the first memory in the first address segment, A data coding module for determining target coded data based on the aforementioned first set of data, A code writing module for storing the target coded data in a second memory located in the integrated circuit, wherein the first memory is a code writing module different from the second memory, A device for performing security verification on data in an integrated circuit, comprising: a security verification module for performing security verification on a second set of data read from the first memory based on the target encoded data; and

9. A computer-readable storage medium storing a computer program that, when executed by a processor, performs a method for performing security verification on data in an integrated circuit according to any one of claims 1 to 3.

10. Processor and The processor includes a memory for storing executable instructions, The processor reads and executes the executable instructions from the memory and is used to realize a method for performing security verification on data in an integrated circuit according to any one of claims 1 to 3. electronic equipment.

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