Nitride semiconductor device, method for manufacturing a nitride semiconductor device

Abstract

To reduce the contact resistance between the source electrode, drain electrode, and 2DEG. [Solution] In the nitride semiconductor device 10, the first side wall 52 of the first source opening 36A includes a first source contact region 56 that contacts the side surface 43B of the source contact portion 40A. The first side wall 52 of the first drain opening 38A includes a first drain contact region 56 that contacts the side surface 43B of the drain contact portion 42A. The first source contact region 56 and the first drain contact region 56 contain donor-type impurities and are continuously provided in the electron transport layer 24 and the electron supply layer 26 in the Z-axis direction. The bottom portions 50 of the first source opening and the first drain opening 38A include bottom contact regions 60, 60 that contact the bottom surfaces 43A, 43A of the source contact portion 40A and the drain contact portion 42A. The impurity concentration of donor-type impurities in the bottom contact regions 60, 60 is lower than that in the first drain contact region 56 and the first source contact region 56.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices and methods for manufacturing nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductor devices using a two-dimensional electron gas (2DEG) as a channel are known. Patent Document 1 discloses a nitride semiconductor device having a source electrode and a drain electrode in contact with an electron supply layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-73506

[0004] [overview] Incidentally, it is desirable to reduce the contact resistance between the source electrode, drain electrode, and 2DEG.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes: an electron transport layer; an electron supply layer provided on the electron transport layer and having a band gap larger than that of the electron transport layer; a gate electrode provided on the electron transport layer; a first source opening and a first drain opening arranged so as to sandwich the gate electrode when viewed from the thickness direction of the electron transport layer, penetrating the electron supply layer and reaching the interior of the electron transport layer; a source electrode disposed in the first source opening; and a drain electrode disposed in the first drain opening, wherein the source electrode includes a source contact portion that contacts the electron transport layer within the first source opening, and the drain electrode includes a drain contact portion that contacts the electron transport layer within the first drain opening. The first source opening includes a contact portion, the first side wall of the first source opening includes a first source contact region in contact with the side surface of the source contact portion, the first side wall of the first drain opening includes a first drain contact region in contact with the side surface of the drain contact portion, the first source contact region and the first drain contact region contain donor-type impurities, and are continuously provided in the thickness direction between the electron transport layer and the electron supply layer, the bottom portions of the first source opening and the first drain opening include a bottom contact region in contact with the bottom surfaces of the source contact portion and the drain contact portion, and the impurity concentration of the donor-type impurities in the bottom contact region is lower than that in the first drain contact region and the first source contact region. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view of an exemplary nitride semiconductor device according to one embodiment. [Figure 2] Figure 2 is a schematic plan view showing a magnified portion of the internal structure of the nitride semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a schematic cross-sectional view of a nitride semiconductor device along the line F3-F3 in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device shown in Figure 3. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a nitride semiconductor device of a comparative example. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device of FIG. 3. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 16. [Figure 18] FIG. 18 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a nitride semiconductor device of a modified example. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a nitride semiconductor device of a modified example.

[0007] [Detailed Description] Hereinafter, several embodiments of the nitride semiconductor devices of this disclosure will be described with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for the sake of ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered limiting. Terms such as "first," "second," and "third" in this disclosure are used simply to distinguish between objects and do not rank them.

[0008] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] <Embodiment> An embodiment of the nitride semiconductor device 10 will be described with reference to Figures 1 to 5. Figure 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. Figure 2 is a schematic plan view showing an enlarged portion of the internal structure of the nitride semiconductor device 10 of Figure 1. Figure 3 is a schematic cross-sectional view of the nitride semiconductor device 10 along the line F3-F3 in Figure 2. Figure 4 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device 10 of Figure 3. Figure 5 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device 10 of Figure 3.

[0010] [Overall Outline of Nitride Semiconductor Device Configuration] As shown in Figure 1, the nitride semiconductor device 10 includes a chip body 12. The chip body 12 is, for example, a rectangular flat plate. The chip body 12 includes a first surface 12A and a second surface 12B opposite to the first surface 12A. The first surface 12A and the second surface 12B can be called the main surfaces of the chip body 12. The Z-axis direction of the mutually orthogonal XYZ axes shown in Figure 1 and other drawings is the direction perpendicular to the first surface 12A of the chip body 12. The term "plan view" as used in this disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction, unless explicitly stated otherwise.

[0011] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. In the example shown in Figure 1, the nitride semiconductor device 10 includes one gate pad 14, multiple source pads 16, and multiple drain pads 18. The gate pad 14, multiple source pads 16, and multiple drain pads 18 are located on the first surface 12A of the chip body 12. These pads 14, 16, and 18 can be used as external connection terminals for the nitride semiconductor device 10.

[0012] Each of the gate pads 14, source pad 16, and drain pad 18 is, for example, rectangular in plan view. The gate pad 14 may be positioned, for example, at one corner of the first surface 12A. Each of the source pads 16 and drain pad 18 extends in the Y-axis direction in plan view. The source pads 16 and drain pads 18 are arranged alternately, one by one, in the X-axis direction perpendicular to the Y-axis direction. Thus, each of the source pads 16 and drain pads 18 can be said to extend in the Y-axis direction perpendicular to the X-axis direction in which these pads 16 and 18 are arranged in plan view. Note that the shapes of each of the gate pads 14, source pad 16, and drain pad 18 in plan view can be arbitrarily changed. Also, the arrangement of the gate pads 14, source pad 16, and drain pad 18 can be arbitrarily changed.

[0013] [Schematic structure of nitride semiconductor device] As shown in Figure 3, the nitride semiconductor device 10 is configured as a high-electron-mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a semiconductor substrate 20, a buffer layer 22 provided on the semiconductor substrate 20, an electron transport layer 24 provided on the buffer layer 22, and an electron supply layer 26 provided on the electron transport layer 24. The buffer layer 22, the electron transport layer 24, and the electron supply layer 26 constitute the nitride semiconductor layer 21. In other words, the nitride semiconductor device 10 includes a semiconductor substrate 20 and a nitride semiconductor layer 21 provided on the semiconductor substrate 20.

[0014] The semiconductor substrate 20 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 20 is a Si substrate. The thickness of the semiconductor substrate 20 can be, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 20 is 200 μm. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20.

[0015] The semiconductor substrate 20 includes a first surface 20A and a second surface 20B opposite to the first surface 20A. The second surface 20B of the semiconductor substrate 20 constitutes the second surface 12B of the chip body 12. The nitride semiconductor device 10 may include a back electrode 46. The back electrode 46 is provided on the second surface 20B of the semiconductor substrate 20. In one example, the back electrode 46 may cover the entire second surface 20B of the semiconductor substrate 20, that is, the entire second surface 12B of the chip body 12. The back electrode 46 is electrically connected to the source pad 16. In one example, the back electrode 46 is electrically connected to the source pad 16 by a connecting wire 48 shown in Figure 1. The back electrode 46 can also be called a back source electrode. Note that the connecting wire 48 shown in Figure 1 is an example for setting the back electrode 46 as the source potential. Therefore, the connecting wire 48 may be configured to connect the source pad 16 and the semiconductor substrate 20, and the back electrode 46 is electrically connected to the source pad 16 through the semiconductor substrate 20 and the connecting wire 48. Furthermore, the connection wiring 48 may be configured to electrically connect the semiconductor substrate 20 and the source wiring 104 shown in Figure 2, or it may be configured to electrically connect the back electrode 46 and the source wiring 104 shown in Figure 2. The back electrode 46 may be omitted.

[0016] The buffer layer 22 is in contact with the first surface 20A of the semiconductor substrate 20. The buffer layer 22 may be made of any material that can suppress the occurrence of wafer warping and cracking due to mismatch in thermal expansion coefficients between the semiconductor substrate 20 and the electron transport layer 24. The buffer layer 22 may include one or more nitride semiconductor layers. For example, the buffer layer 22 may include at least one of aluminum nitride (AlN) layers, aluminum gallium nitride (AlGaN) layers, and graded AlGaN layers having different aluminum (Al) compositions. For example, the buffer layer 22 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0017] In one example, the buffer layer 22 may include a first buffer layer provided on the semiconductor substrate 20 and a second buffer layer provided on the first buffer layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm. The second buffer layer may include a plurality of AlGaN layers with different compositions, each having a thickness of 50 nm to 500 nm. The second buffer layer may be a grated AlGaN layer configured such that the Al composition ratio of the plurality of AlGaN layers decreases sequentially from the side closer to the first buffer layer. In addition, to suppress leakage current in the buffer layer 22, impurities may be introduced into a part of the buffer layer 22 to make the buffer layer 22 semi-insulating. In that case, the impurities may be, for example, carbon (C) or iron (Fe), and the concentration of the impurities may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0018] The electron transport layer 24 is made of a nitride semiconductor. The electron transport layer 24 may be, for example, a GaN layer. The electron transport layer 24 includes an upper surface 24A and a lower surface 24B opposite to the upper surface 24A. The lower surface 24B of the electron transport layer 24 is in contact with the buffer layer 22. The thickness of the electron transport layer 24 can be, for example, 0.5 μm or more and 1 μm or less. The electron transport layer 24 may include one or more nitride semiconductor layers. Furthermore, in order to suppress leakage current in the electron transport layer 24, an impurity may be introduced into a part of the electron transport layer 24 to make the area other than the surface region of the electron transport layer 24 semi-insulating. In this case, the impurity is, for example, carbon. The concentration of the carbon impurity is, for example, 4 × 10⁻¹⁶ at the peak concentration. 16 cm -3 That's all.

[0019] The electron supply layer 26 is composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 24. The electron supply layer 26 may be, for example, an AlGaN layer. The electron supply layer 26 includes an upper surface 26A and a lower surface 26B opposite to the upper surface 26A. The lower surface 26B of the electron supply layer 26 is in contact with the electron traveling layer 24. The lower surface 26B of the electron supply layer 26 and the upper surface 24A of the electron traveling layer 24 constitute an interface between the electron traveling layer 24 and the electron supply layer 26. Since the bandgap becomes larger as the Al composition increases, the electron supply layer 26 which is an AlGaN layer has a larger bandgap than the electron traveling layer 24 which is a GaN layer. In one example, the electron supply layer 26 is Al x Ga 1-x composed of N. In this case, the Al composition ratio x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. In one example, the thickness of the electron supply layer 26 is, for example, 10 nm. The thickness T11 of the electron supply layer 26 can be, for example, 8 nm or more and 30 nm or less.

[0020] The electron traveling layer 24 and the electron supply layer 26 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron traveling layer 24 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 26 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron traveling layer 24 and the electron supply layer 26 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the electron traveling layer 24, the energy level of the conduction band of the electron traveling layer 24 near the hetero-junction interface between the electron traveling layer 24 and the electron supply layer 26 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 28 spreads in the electron traveling layer 24 at a position close to the hetero-junction interface between the electron traveling layer 24 and the electron supply layer 26 (e.g., at a distance of about several nm from the interface).

[0021] The nitride semiconductor device 10 includes a gate layer 30 provided on a part of the electron supply layer 26 and a gate electrode 32 provided on the gate layer 30. The gate layer 30 is composed of a nitride semiconductor. In one example, the gate layer 30 has a smaller bandgap than the electron supply layer 26 and is composed of a nitride semiconductor containing acceptor-type impurities. In one example, the gate layer 30 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0022] The gate electrode 32 includes one or more metal layers. In one example, the gate electrode 32 may be a titanium nitride (TiN) layer. In another example, the gate electrode 32 may be composed of a first metal layer made of Ti and a second metal layer provided on the first metal layer and made of TiN. The gate electrode 32 can be composed of a material having, for example, the property of forming a Schottky junction with the gate layer 30. An example of such a material is TiN. The thickness of the gate electrode 32 can be, for example, 50 nm or more and 200 nm or less.

[0023] The nitride semiconductor device 10 includes a passivation layer 34. The passivation layer 34 covers the electron supply layer 26, the gate layer 30, and the gate electrode 32. The passivation layer 34 includes an upper surface 34A and a lower surface 34B opposite to the upper surface 34A. The lower surface 34B of the passivation layer 34 is in contact with the electron supply layer 26, the gate layer 30, and the gate electrode 32. The passivation layer 34 can be composed of, for example, one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 34 can be, for example, 50 nm or more and 200 nm or less, preferably 80 nm or more and 150 nm or less.

[0024] The nitride semiconductor device 10 includes a source aperture 36 and a drain aperture 38 arranged to sandwich the gate electrode 32 in a plan view. The source aperture 36 and the drain aperture 38 penetrate the passivation layer 34 and the electron supply layer 26 and reach the interior of the electron transport layer 24.

[0025] The source opening 36 includes a first source opening 36A and a second source opening 36B. The first source opening 36A is provided in the electron transport layer 24 and electron supply layer 26, which are nitride semiconductor layers 21. The first source opening 36A penetrates the electron supply layer 26 from the upper surface 26A of the electron supply layer 26 and reaches the interior of the electron transport layer 24. The second source opening 36B is provided in the passivation layer 34. The second source opening 36B penetrates the passivation layer 34 and communicates with the first source opening 36A.

[0026] The drain opening 38 includes a first drain opening 38A and a second drain opening 38B. The first drain opening 38A is provided in the electron transport layer 24 and electron supply layer 26, which are nitride semiconductor layers 21. The first drain opening 38A penetrates the electron supply layer 26 from the upper surface 26A of the electron supply layer 26 and reaches the interior of the electron transport layer 24. The second drain opening 38B is provided in the passivation layer 34. The second drain opening 38B penetrates the passivation layer 34 and communicates with the first drain opening 38A.

[0027] The nitride semiconductor device 10 includes a source electrode 40 disposed in a source opening 36. The source electrode 40 includes a source contact portion 40A disposed within the source opening 36. The source contact portion 40A of the source electrode 40 is filled within the source opening 36. The source contact portion 40A can be said to span across a first source opening 36A and a second source opening 36B communicating with the first source opening 36A. The source contact portion 40A is in contact with the electron transport layer 24. The source contact portion 40A is in contact with both the electron transport layer 24 and the electron supply layer 26. The source electrode 40 includes a source extension portion 40B. The source extension portion 40B is located on the periphery of the second source opening 36B in the passivation layer 34. The source extension portion 40B extends from the source contact portion 40A onto the passivation layer 34.

[0028] The nitride semiconductor device 10 includes a drain electrode 42 positioned in a drain opening 38. The drain electrode 42 includes a drain contact portion 42A positioned within the drain opening 38. The drain contact portion 42A of the drain electrode 42 is filled within the drain opening 38. The drain contact portion 42A can be said to span across a first drain opening 38A and a second drain opening 38B communicating with the first drain opening 38A. The drain contact portion 42A is in contact with the electron transport layer 24. The drain contact portion 42A is in contact with both the electron transport layer 24 and the electron supply layer 26. The drain electrode 42 includes a drain extension portion 42B. The drain extension portion 42B is positioned on the periphery of the second drain opening 38B in the passivation layer 34. The drain extension portion 42B extends from the drain contact portion 42A onto the passivation layer 34.

[0029] In a structure where the gate layer 30 is composed of a nitride semiconductor containing acceptor-type impurities, the conductive path (channel) is blocked when 2DEG28 in the region directly beneath the gate layer 30 is depleted under zero bias conditions where no voltage is applied to the gate electrode 32. This enables a normally-off HEMT with a positive gate threshold voltage.

[0030] The nitride semiconductor device 10 may include a field plate electrode 44. The field plate electrode 44 may be provided on a passivation layer 34. The field plate electrode 44 may be in contact with the upper surface 34A of the passivation layer 34. The field plate electrode 44 is electrically connected to the source electrode 40. In one example, the field plate electrode 44 is integrally configured with the source electrode 40. In one example, the field plate electrode 44 extends from the source extension 40B of the source electrode 40 toward the drain electrode 42. A voltage of the same potential as that of the source electrode 40 is applied to the field plate electrode 44. The field plate electrode 44 is also called a source field plate. In a plan view, the field plate electrode 44 may cover the entire gate layer 30.

[0031] The field plate electrode 44 is separated from the drain electrode 42. The field plate electrode 44 includes an end portion 44A located between the gate layer 30 and the drain electrode 42 in a plan view. The field plate electrode 44 plays a role in mitigating electric field concentration near the ends of the gate electrode 32 and the gate layer 30 when a drain voltage is applied to the drain electrode 42 in a zero-bias state where no voltage is applied to the gate electrode 32.

[0032] [Exemplary Planar Layout of Nitride Semiconductor Device] Next, an exemplary planar layout of the HEMT structure in the nitride semiconductor device 10 will be described with reference to Figure 2. In Figure 2, the gate layer 30 and gate electrode 32 are shown with solid lines for clarity.

[0033] As shown in Figure 2, the nitride semiconductor device 10 includes a plurality of transistor elements, each having a HEMT structure, within the device region. Note that Figure 2 only shows a plurality of transistor elements arranged in the X-axis direction. Transistor elements can be arranged in both the X-axis and Y-axis directions.

[0034] A drain electrode 42 is provided for each transistor element. The drain electrode 42 extends in the Y-axis direction in a plan view. The source electrode 40 is provided, for example, so as to surround each drain electrode 42 in a plan view. As explained with reference to Figure 3, the field plate electrode 44, which is integrally configured with the source electrode 40, extends toward the adjacent drain electrode 42 in a plan view. In the example shown in Figure 2, the source electrode 40 is provided continuously in the X-axis direction across multiple adjacent transistor elements in the X-axis direction, but it may be separated into multiple parts in the X-axis direction.

[0035] A gate layer 30 and a gate electrode 32 are provided for each transistor element. Each gate layer 30 and each gate electrode 32 are arranged in a ring shape so as to surround one of the drain electrodes 42 in a plan view.

[0036] The nitride semiconductor device 10 includes a gate wiring 102, a source wiring 104, and a drain wiring 106. The gate wiring 102, source wiring 104, and drain wiring 106 are provided on a first interlayer insulating layer (not shown) that covers the source electrode 40 and the drain electrode 42. In the example shown in Figure 2, each of the gate wiring 102, source wiring 104, and drain wiring 106 extends in the X-axis direction. The gate wiring 102, source wiring 104, and drain wiring 106 are spaced apart from each other in the Y-axis direction. The gate wiring 102 is located in a different position from the drain electrode 42, source opening 36, and drain opening 38 in the Y-axis direction. The source wiring 104 and drain wiring 106 are located in a position that overlaps the drain electrode 42, source opening 36, and drain opening 38 in a plan view in the Y-axis direction.

[0037] For example, gate wiring 102 is connected to gate electrode 32 by gate connection conductor 112 which penetrates the first interlayer insulating layer and extends to gate electrode 32. Source wiring 104 is connected to source electrode 40 by source connection conductor 114 which penetrates the first interlayer insulating layer. Drain wiring 106 is connected to drain electrode 42 by drain connection conductor 116 which penetrates the first interlayer insulating layer. Each of the gate connection conductor 112, source connection conductor 114, and drain connection conductor 116 is, for example, a via that penetrates the first interlayer insulating layer. The number of each of the gate connection conductor 112, source connection conductor 114, and drain connection conductor 116 can be arbitrarily changed.

[0038] For example, the gate wiring 102, source wiring 104, and drain wiring 106 are covered by a second interlayer insulating layer (not shown). In one example, the gate pad 14, source pad 16, and drain pad 18 shown in Figure 1 are located on the second interlayer insulating layer. For example, the gate wiring 102 is electrically connected to the gate pad 14 by a gate connection conductor (not shown) that penetrates the second interlayer insulating layer and extends to the gate pad 14. The source wiring 104 is electrically connected to the source pad 16 by a source connection conductor (not shown) that penetrates the second interlayer insulating layer. The drain wiring 106 is electrically connected to the drain pad 18 by a drain connection conductor (not shown) that penetrates the second interlayer insulating layer.

[0039] [Drain opening configuration, drain electrode junction structure] Next, with reference to Figures 3 and 4, the details of the configuration of the drain opening 38 and the configuration related to the ohmic contact of the drain electrode 42 in the drain opening 38 will be described.

[0040] As shown in Figures 3 and 4, the drain opening 38 includes a first drain opening 38A and a second drain opening 38B. The first drain opening 38A is provided in the electron transport layer 24 and electron supply layer 26, which are nitride semiconductor layers 21. The first drain opening 38A penetrates the electron supply layer 26 from the upper surface 26A of the electron supply layer 26 and reaches the interior of the electron transport layer 24.

[0041] As shown in Figure 4, the first drain opening 38A is demarcated by a bottom 50 and a first side wall 52 that surrounds the bottom 50 in a plan view. The upper surface 50A of the bottom 50 can be said to be the bottom surface constituting the first drain opening 38A. The side surface 52A of the first side wall 52 can be said to be the side surface constituting the first drain opening 38A. The bottom 50 is provided in the electron transport layer 24. The first side wall 52 is provided spanning the electron supply layer 26 and the electron transport layer 24 in the Z-axis direction. The electron transport layer 24 can be said to include the bottom 50 of the first drain opening 38A. The electron transport layer 24 and the electron supply layer 26 can be said to include the first side wall 52 of the first drain opening 38A.

[0042] The side surface 52A of the first side wall 52 of the first drain opening 38A can be said to be composed of the first portion 53A of the electron transport layer 24 and the second portion 53B of the electron supply layer 26. The first portion 53A of the electron transport layer 24 and the second portion 53B of the electron supply layer 26 may be provided continuously. In one example, the side surface 52A of the first side wall 52 extends along the Z-axis direction. In one example, the side surface 52A of the first side wall 52 may be at 0° with respect to the Z-axis direction. In the electron transport layer 24, the space between the first portion 53A and the upper surface 50A of the bottom portion 50 may be a curved surface 54 that curves inward toward the interior of the electron transport layer 24.

[0043] The width W11 of the first drain opening 38A may be expressed as the distance between the sides 52A of the first sidewalls 52 that face each other in the X-axis direction at the position of the upper surface 26A of the electron supply layer 26. In one example, the width W11 of the first drain opening 38A may be 0.9 μm. The depth D11 of the first drain opening 38A may be expressed as the depth in the electron transport layer 24 in the Z-axis direction. The depth D11 of the first drain opening 38A in the electron transport layer 24 may be expressed as the distance from the upper surface 24A of the electron transport layer 24 to the upper surface 50A of the bottom 50 of the first drain opening 38A in the Z-axis direction. In one example, the depth D11 of the first drain opening 38A may be greater than or equal to the thickness T11 of the electron supply layer 26. In another example, the depth D11 of the first drain opening 38A may be 50 nm or less.

[0044] The drain electrode 42 includes a drain contact portion 42A positioned in the drain opening 38. The drain contact portion 42A spans the first drain opening 38A and the second drain opening 38B. The drain contact portion 42A includes a lower surface 43A facing in the Z-axis direction and a side surface 43B intersecting the lower surface 43A. The lower surface 43A of the drain contact portion 42A is in contact with the electron transport layer 24. The side surface 43B of the drain contact portion 42A is in contact with the electron transport layer 24 and the electron supply layer 26. The first drain opening 38A is partitioned by a first side wall 52 and a bottom portion 50. The first side wall 52 extends in the Z-axis direction. The side surface 52A of the first side wall 52 can be said to be in contact with the side surface 43B of the drain contact portion 42A. The upper surface 50A of the bottom portion 50 can be said to be in contact with the lower surface 43A of the drain contact portion 42A.

[0045] The upper surface 50A of the bottom portion 50 is preferably closer to the lower surface 24B of the electron transport layer 24 than the 2DEG28 generated in the electron transport layer 24. The depth D11 of the first drain opening 38A is preferably greater than the distance from the upper surface 24A of the electron transport layer 24 to the location of the 2DEG28 generated in the electron transport layer 24. In this case, the drain contact portion 42A of the drain electrode 42 can be said to be in direct contact with the 2DEG28 generated in the electron transport layer 24.

[0046] The first side wall 52 of the first drain opening 38A includes a first drain contact region 56 that contacts the side surface 43B of the drain contact portion 42A of the drain electrode 42. The first drain contact region 56 contains donor-type (n-type) impurities. One example of a donor-type impurity is Si. The impurity concentration in the first drain contact region 56 is 2 × 10⁻⁶. 19 cm -3 The above 6 x 10 19 cm -3 The following is acceptable:

[0047] The first drain contact region 56 is partially provided on the side surface 52A of the first side wall 52 in the Z-axis direction. The first drain contact region 56 extends from the upper surface 24A of the electron transport layer 24 toward the bottom 50 in the Z-axis direction. The lower end 56A of the first drain contact region 56 is located closer to the upper surface 24A of the electron transport layer 24 than to the upper surface 50A of the bottom 50. The first side wall 52 has a region 58 that does not contain donor-type impurities between the first drain contact region 56 and the bottom 50. In this disclosure, "does not contain impurities" means that impurities have not been intentionally doped into the material.

[0048] The bottom portion 50 may include a bottom contact region 60 that contacts the lower surface 43A of the drain contact portion 42A. The bottom contact region 60 extends across the entire upper surface 50A of the bottom portion 50. The bottom contact region 60 does not contain donor-type impurities. The lower surface 43A of the drain contact portion 42A is in contact with the bottom portion 50, which does not contain donor-type impurities. The impurity concentration of donor-type impurities in the bottom contact region 60 is lower than that in the first drain contact region 56.

[0049] The second drain opening 38B penetrates the passivation layer 34. The second drain opening 38B communicates with the first drain opening 38A. The passivation layer 34 can be said to include the second drain opening 38B that communicates with the first drain opening 38A. The passivation layer 34 includes a second side wall 62 that demarcates the second drain opening 38B. The side surface 62A of the second side wall 62 may be continuous with the side surface 52A of the first side wall 52 in the electron transport layer 24 and the electron supply layer 26.

[0050] The second side wall 62 of the second drain opening 38B includes a second drain contact region 64 that contacts the side surface 43B of the drain contact portion 42A of the drain electrode 42. The second drain contact region 64 contains donor-type (n-type) impurities. In one example, the donor-type impurity is Si. The impurity concentration in the second drain contact region 64 is 2 × 10⁻⁶. 19 cm -3 The above 6 x 10 19 cm -3 The following is acceptable:

[0051] The second drain contact region 64 is partially provided on the side surface 62A of the second side wall 62 in the Z-axis direction. The second drain contact region 64 extends from the lower surface 34B of the passivation layer 34 toward the upper surface 34A of the passivation layer 34 in the Z-axis direction. The upper end 64A of the second drain contact region 64 is located closer to the upper surface 24A of the electron transport layer 24 than the upper surface 34A of the passivation layer 34. The second side wall 62 has a region 66 that does not contain donor-type impurities between the second drain contact region 64 and the upper surface 34A of the passivation layer 34. The second drain contact region 64 is continuous with the first drain contact region 56.

[0052] The drain electrode 42 includes one or more metal layers. In one example, the drain electrode 42 may be made of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the drain electrode 42 is made of a first metal layer 71 in contact with the electron transport layer 24 and the electron supply layer 26, a second metal layer 72 laminated on the first metal layer 71, a third metal layer 73 laminated on the second metal layer 72, and a fourth metal layer 74 laminated on the third metal layer 73. The first metal layer 71 is, for example, a Ti layer, the second metal layer 72 is, for example, an Al layer, the third metal layer 73 is, for example, a Ti layer, and the fourth metal layer 74 is, for example, a TiN layer.

[0053] The first metal layer 71, which is a Ti layer, is in contact with the first side wall 52 and bottom 50 that define the first drain opening 38A. The drain electrode 42 is in contact with the first side wall 52 and bottom 50. The drain contact portion 42A of the drain electrode 42 is in ohmic contact with the electron transport layer 24 and the electron supply layer 26. The upper surface 50A of the bottom 50 that constitutes the first drain opening 38A is located closer to the lower surface 24B of the electron transport layer 24 than the 2DEG generated in the electron transport layer 24. Therefore, the side surface 43B of the first metal layer 71, that is, the drain contact portion 42A of the drain electrode 42, is in ohmic contact with the 2DEG 28. Furthermore, the first metal layer 71 of the drain electrode 42 is in contact with the first drain contact region 56 of the first side wall 52.

[0054] The drain electrode 42 may include a drain contact portion 42A positioned in the drain opening 38 and a drain extension portion 42B positioned on the periphery of the second drain opening 38B in the passivation layer 34. The drain extension portion 42B extends from the drain contact portion 42A onto the passivation layer 34.

[0055] The drain extension 42B includes a drain end 42C on the opposite side of the drain contact 42A. The drain end 42C is the end closer to the gate electrode 32 relative to the drain contact 42A. The drain extension 42B has a second width W31 from the drain contact 42A to the drain end 42C of the drain extension 42B. The second width W31 of the drain extension 42B may be indicated by the length of the drain extension 42B in the X-axis direction. The second width W31 of the drain extension 42B may be indicated by the length from the drain contact 42A to the drain end 42C. In one example, the second width W31 of the drain extension 42B may be 200 nm or less. In one example, the second width W31 of the drain extension 42B is 150 nm.

[0056] The drain extension portion 42B is provided so as to overlap with the first drain contact region 56 of the first side wall 52 in a plan view. The first width W21 of the first drain contact region 56 may be indicated by the length of the first drain contact region 56 in the X-axis direction. The first width W21 of the first drain contact region 56 is smaller than the second width W31 of the drain extension 42B. The length of the first drain contact region 56 may be indicated by the distance in the X-axis direction from the side surface 52A of the first side wall 52 to the position of the first drain contact region 56 closest to the drain end 42C. The first width W21 of the first drain contact region 56 may be 150 nm or less in one example. The first width W21 of the first drain contact region 56 is 100 nm in one example.

[0057] [Source aperture configuration, source electrode bonding structure] Next, with reference to Figures 3 and 5, the configuration of the source opening 36 and the configuration related to the ohmic contact of the source electrode 40 in the source opening 36 will be described. Note that the configuration related to the ohmic contact of the source electrode 40 and the configuration related to the ohmic contact of the drain electrode 42 are the same. In Figures 3 and 5, the same reference numerals are used for the same components as those used for the drain opening 38 and drain electrode 42 in the configuration of the source opening 36 and source electrode 40. Details of the source opening 36 and source electrode 40 can be easily understood by replacing "drain" with "source" in the explanation of the drain opening 38 and drain electrode 42.

[0058] As shown in Figure 5, the first source opening 36A is demarcated by a bottom 50 and a first side wall 52. The upper surface 50A of the bottom 50 can be said to be the bottom surface constituting the first source opening 36A. The side surface 52A of the first side wall 52 can be said to be the side surface constituting the first source opening 36A. The electron transport layer 24 can be said to include the bottom 50 of the first source opening 36A. The electron transport layer 24 and the electron supply layer 26 can be said to include the first side wall 52 of the first source opening 36A.

[0059] The width W12 of the first source aperture 36A may be expressed as the distance between the sides 52A of the first sidewall 52 that face each other in the X-axis direction at the position of the upper surface 26A of the electron supply layer 26. The width W12 of the first source aperture 36A may be equal to or different from the width W11 of the first drain aperture 38A shown in Figure 4. The depth D12 of the first source aperture 36A may be equal to or different from the depth D11 of the first drain aperture 38A shown in Figure 4. In one example, the depth D12 of the first source aperture 36A may be greater than or equal to the thickness T11 of the electron supply layer 26. In one example, the depth D12 of the first source aperture 36A may be 50 nm or less.

[0060] The lower surface 43A of the source contact portion 40A of the source electrode 40 is in contact with the electron transport layer 24. The side surface 43B of the source contact portion 40A is in contact with the electron transport layer 24 and the electron supply layer 26. The first source opening 36A is partitioned by a first side wall 52 and a bottom portion 50. The first side wall 52 extends in the Z-axis direction. The side surface 52A of the first side wall 52 can be said to be in contact with the side surface 43B of the source contact portion 40A. The upper surface 50A of the bottom portion 50 can be said to be in contact with the lower surface 43A of the source contact portion 40A.

[0061] The depth D12 of the first source opening 36A is preferably greater than the distance from the upper surface 24A of the electron transport layer 24 to the position of 2DEG28 generated in the electron transport layer 24. In this case, the source contact portion 40A of the source electrode 40 can be said to be in direct contact with 2DEG28 generated in the electron transport layer 24.

[0062] The first side wall 52 of the first source opening 36A includes a first source contact region 56 that contacts the side surface 43B of the source contact portion 40A of the source electrode 40. The first source contact region 56 contains a donor-type (n-type) impurity. In one example, the donor-type impurity is Si. The impurity concentration in the first source contact region 56 is 2 × 10⁻⁶. 19 cm -3 The above 6 x 10 19 cm -3 The following may apply: The first width W21 of the first source contact region 56 may be 150 nm or less in one example. The first width W21 of the first source contact region 56 is 100 nm in one example.

[0063] The first source contact region 56 is partially provided on the side surface 52A of the first side wall 52 in the Z-axis direction. The first source contact region 56 extends from the upper surface 24A of the electron transport layer 24 toward the bottom 50 in the Z-axis direction. The lower end 56A of the first source contact region 56 is located closer to the upper surface 24A of the electron transport layer 24 than to the upper surface 50A of the bottom 50. The first side wall 52 has a region 58 that does not contain donor-type impurities between the first source contact region 56 and the bottom 50.

[0064] The second side wall 62 of the second source opening 36B includes a second source contact region 64 that contacts the side surface 43B of the source contact portion 40A of the source electrode 40. The second source contact region 64 contains donor-type (n-type) impurities. In one example, the donor-type impurity is Si. The impurity concentration in the second source contact region 64 is 2 × 10⁻⁶. 19 cm -3 The above 6 x 10 19 cm -3 The following is acceptable:

[0065] The second source contact region 64 is partially provided on the side surface 62A of the second side wall 62 in the Z-axis direction. The second source contact region 64 extends from the lower surface 34B of the passivation layer 34 toward the upper surface 34A of the passivation layer 34 in the Z-axis direction. The upper end 64A of the second source contact region 64 is located closer to the upper surface 24A of the electron transport layer 24 than the upper surface 34A of the passivation layer 34. The second side wall 62 has a region 66 that does not contain donor-type impurities between the second source contact region 64 and the upper surface 34A of the passivation layer 34. The second source contact region 64 is continuous with the first source contact region 56.

[0066] The source electrode 40 includes one or more metal layers. In one example, the source electrode 40 is configured similarly to the drain electrode 42. The source electrode 40 is composed of a first metal layer 71 in contact with the electron transport layer 24 and the electron supply layer 26, a second metal layer 72 laminated on the first metal layer 71, a third metal layer 73 laminated on the second metal layer 72, and a fourth metal layer 74 laminated on the third metal layer 73.

[0067] The nitride semiconductor device 10 of the embodiment includes a field plate electrode 44. In one example, the field plate electrode 44 is configured integrally with the source electrode 40. Thus, in one example, the field plate electrode 44 is composed of a first metal layer 71, a second metal layer 72, a third metal layer 73, and a fourth metal layer 74.

[0068] (Effect of the embodiment) Here, a comparative example of the nitride semiconductor device 10 of the embodiment and the operation of the embodiment relative to the comparative example will be described.

[0069] (Comparative example) Figure 6 is a cross-sectional view of a nitride semiconductor device 10X according to a comparative example. Figure 6 corresponds to the cross-sectional view of the nitride semiconductor device 10X shown in Figure 3. For the nitride semiconductor device 10X of the comparative example shown in Figure 6, the same names and reference numerals are used for the components corresponding to the nitride semiconductor device 10X of the embodiment shown in Figure 3.

[0070] The comparative nitride semiconductor device 10X includes a source aperture 36X and a drain aperture 38X arranged to sandwich the gate electrode 32 in a plan view. The source aperture 36X and the drain aperture 38X penetrate the passivation layer 34 and expose a portion of the upper surface 26A of the electron supply layer 26, respectively. In other words, in the comparative nitride semiconductor device 10X, the source aperture 36X is formed by a second source aperture 36B of the passivation layer 34, and the drain aperture 38X is formed by a second drain aperture 38B of the passivation layer 34.

[0071] The source electrode 40X is positioned in the source aperture 36X. The source electrode 40X includes a source contact portion 40AX positioned within the source aperture 36X. The source contact portion 40AX is in contact with the upper surface 26A of the electron supply layer 26 exposed by the source aperture 36X. In the comparative example, the source electrode 40X is in ohmic contact with the 2DEG 28 directly below the source electrode 40X. A portion of the electron transport layer 24 and the electron supply layer 26 are interposed between the source electrode 40X and the 2DEG.

[0072] The drain electrode 42X is positioned in the drain opening 38X. The drain electrode 42X includes a drain contact portion 42AX positioned within the drain opening 38X. The drain contact portion 42AX is in contact with the upper surface 26A of the electron supply layer 26 exposed by the drain opening 38X. In the comparative example, the drain electrode 42X is in ohmic contact with the 2DEG 28 directly below the drain electrode 42X. A portion of the electron transport layer 24 and the electron supply layer 26 are interposed between the drain electrode 42X and the 2DEG.

[0073] As shown in Figures 3 to 5, the nitride semiconductor device 10 of the embodiment includes an electron transport layer 24, an electron supply layer 26 provided on the electron transport layer 24 and having a larger band gap than the electron transport layer 24, a gate electrode 32 provided on the electron transport layer 24, a first source opening 36A and a first drain opening 38A arranged to sandwich the gate electrode 32 when viewed from the Z-axis direction, penetrating the electron supply layer 26 and reaching the interior of the electron transport layer 24, a source electrode 40 located in the first source opening 36A, and a drain electrode 42 located in the first drain opening 38A. The source electrode 40 includes a source contact portion 40A that contacts the electron transport layer 24 within the first source opening 36A. The drain electrode 42 includes a drain contact portion 42A that contacts the electron transport layer 24 within the first drain opening 38A.

[0074] The first side wall 52 of the first source opening 36A includes a first source contact region 56 that contacts the side surface 43B of the source contact portion 40A. The first side wall 52 of the first drain opening 38A includes a first drain contact region 56 that contacts the side surface 43B of the drain contact portion 42A. The first source contact region 56 and the first drain contact region 56 contain donor-type impurities and are continuously provided in the electron transport layer 24 and the electron supply layer 26 in the Z-axis direction. The bottom portions 50 of the first source opening and the first drain opening 38A include bottom contact regions 60, 60 that contact the bottom surfaces 43A, 43A of the source contact portion 40A and the drain contact portion 42A. The impurity concentration of donor-type impurities in the bottom contact regions 60, 60 is lower than that in the first drain contact region 56 and the first source contact region 56.

[0075] The first drain opening 38A penetrates the electron supply layer 26 and reaches the interior of the electron transport layer 24. The drain contact portion 42A of the drain electrode 42 positioned in the first drain opening 38A is in direct contact with the electron transport layer 24. Therefore, the nitride semiconductor device 10 of this embodiment has lower contact resistance between the drain contact portion 42A and the 2DEG28 compared to one in which the drain contact portion 42A is in contact with the upper surface 26A of the electron supply layer 26X. This reduces the on-resistance, which is the drain-source resistance when the nitride semiconductor device 10 is turned on.

[0076] (Method for manufacturing nitride semiconductor equipment) An exemplary manufacturing method of the nitride semiconductor device 10 will be described with reference to Figures 7 to 19. In Figures 7 to 19, components similar to those in Figure 3 are denoted by the same reference numerals.

[0077] As shown in Figure 7, the manufacturing method of the nitride semiconductor device 10 includes sequentially forming a buffer layer 22, an electron transport layer 24, an electron supply layer 26, and a nitride semiconductor layer 802 on a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a Si substrate. The nitride semiconductor layer 802 is, for example, a GaN layer. The buffer layer 22, electron transport layer 24, electron supply layer 26, and nitride semiconductor layer 802 can be epitaxially grown, for example, using a metal-organic chemical vapor deposition (MOCVD) method.

[0078] The buffer layer 22 may be a multilayer buffer layer. In the multilayer buffer layer, an AlN layer (first buffer layer) is formed on the semiconductor substrate 20, and then a grated AlGaN layer (second buffer layer) is formed on the AlN layer. The grated AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0079] The electron transport layer 24 formed on the buffer layer 22 may be a GaN layer. The electron supply layer 26 formed on the electron transport layer 24 may be an AlGaN layer. Therefore, the electron supply layer 26 is made of a nitride semiconductor having a larger band gap than the electron transport layer 24.

[0080] The nitride semiconductor layer 802 formed on the electron supply layer 26 may contain magnesium as an acceptor-type impurity. By doping the nitride semiconductor layer 802 with magnesium while growing it on the electron supply layer 26, a nitride semiconductor layer 802 containing acceptor-type impurities can be formed.

[0081] As shown in Figure 8, the manufacturing method of the nitride semiconductor device 10 includes forming a metal layer 804. In one example, the metal layer 804 can be formed on the nitride semiconductor layer 802 by sputtering. In one example, the metal layer 804 may be a TiN layer.

[0082] A method for manufacturing a nitride semiconductor device 10 includes forming a first mask layer 806. In one example, the first mask layer 806 may be a SiN layer formed by low-pressure chemical vapor deposition (LPCVD). In one example, the first mask layer 806 is formed to cover a metal layer 804.

[0083] As shown in Figure 9, the method for manufacturing the nitride semiconductor device 10 includes forming a gate electrode 32. In one example, a resist film 808 is formed on the first mask layer 806, for example by lithography, and the gate electrode 32 is formed by selectively removing the first mask layer 806 and the metal layer 804 shown in Figure 8 by etching using this resist film 808. Subsequently, the resist film 808 is removed, for example, by a stripping solution.

[0084] As shown in Figures 10 to 12, the manufacturing method of the nitride semiconductor device 10 includes forming a gate layer 30. In one example, as shown in Figure 10, a second mask layer 810 is formed covering the first mask layer 806, the gate electrode 32, and the nitride semiconductor layer 802. The second mask layer 810 is formed, for example, by the LPCVD method. The second mask layer 810 may be composed of at least one of the following materials: SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the second mask layer 810 is composed of SiN.

[0085] Next, as shown in Figure 11, the entire surface of the second mask layer 810 is etched using reactive ion etching (RIE). This removes the second mask layer 810 formed on the upper surface of the nitride semiconductor layer 802 and the upper surface of the first mask layer 806. On the other hand, the second mask layer 810 formed on the side surface of the gate electrode 32 and the side surface of the first mask layer 806 is not removed.

[0086] Next, as shown in Figure 12, the nitride semiconductor layer 802 is etched, for example, by plasma etching. A chlorine-based (Cl2-based) gas can be used for plasma etching. This forms a gate layer 30 directly beneath the gate electrode 32 and directly beneath the second mask layer 810 on the nitride semiconductor layer 802. After this, the first mask layer 806 and the second mask layer 810 are removed.

[0087] As shown in Figure 13, the method for manufacturing the nitride semiconductor device 10 includes forming a passivation layer 34. In one example, the passivation layer 34 may be a SiN layer formed by the LPCVD method. The passivation layer 34 is formed to cover the electron supply layer 26, the gate layer 30, and the gate electrode 32.

[0088] As shown in Figure 14, the method for manufacturing the nitride semiconductor device 10 includes forming a second source opening 36B and a second drain opening 38B in the passivation layer 34. In one example, a resist film 812 is formed on the passivation layer 34, for example, by lithography. This resist film 812 includes openings 812A and 812B located at positions corresponding to the second source opening 36B and the second drain opening 38B. The second source opening 36B and the second drain opening 38B are formed by etching away the passivation layer 34 exposed through these openings 812A and 812B.

[0089] As shown in Figure 15, the manufacturing method of the nitride semiconductor device 10 includes forming a source-doped region 814 and a drain-doped region 816 containing donor-type impurities in the electron supply layer 26 and the electron transport layer 24. The donor-type impurity is, in one example, Si.

[0090] In one example, the source-doped region 814 is formed by ion implanting donor-type impurities into the electron supply layer 26 and the electron transport layer 24 through the opening 812A of the resist film 812 and the second source opening 36B of the passivation layer 34. The source-doped region 814 is formed deeper than the position where 2DEG28 can occur in the electron transport layer 24. Furthermore, the source-doped region 814 is formed so as to overlap with the periphery of the opening 812A of the resist film 812 in a plan view. Donor-type impurities passing through the opening 812A of the resist film 812 can also be implanted into the second sidewall 62 that constitutes the second source opening 36B of the passivation layer 34. In other words, in the passivation layer 34 as well, a region containing donor-type impurities is formed so as to overlap with the periphery of the opening 812A of the resist film 812 in a plan view. This forms the second source contact region 64 in the passivation layer 34.

[0091] Similarly, the drain-doped region 816 is formed by ion implanting donor-type impurities into the electron supply layer 26 and the electron transport layer 24 through the opening 812B of the resist film 812 and the second drain opening 38B of the passivation layer 34. The drain-doped region 816 is formed deeper than the location where 2DEG28 can occur in the electron transport layer 24. Donor-type impurities passing through the opening 812B of the resist film 812 can also be implanted into the second sidewall 62 that constitutes the second drain opening 38B of the passivation layer 34. This forms a second drain contact region 64 in the passivation layer 34.

[0092] As shown in Figure 16, the method for manufacturing the nitride semiconductor device 10 includes forming a first source opening 36A and a first drain opening 38A. The first source opening 36A is formed so as to penetrate the source doped region 814. In one example, the first source opening 36A penetrating the source doped region 814 is formed by dry etching using a resist film 812. This first source opening 36A penetrates the electron supply layer 26 and reaches the interior of the electron transport layer 24. By forming the first source opening 36A, a first source contact region 56 containing donor-type impurities is formed on the first side wall 52 that demarcates the first source opening 36A. Furthermore, by forming the first source opening 36A so as to penetrate the source doped region 814, the bottom portion 50 that demarcates the first source opening 36A can be made free of donor-type impurities.

[0093] The first drain opening 38A is formed so as to penetrate the drain-doped region 816. In one example, the first drain opening 38A penetrating the drain-doped region 816 is formed by dry etching using the resist film 812. This first drain opening 38A penetrates the electron supply layer 26 and reaches the interior of the electron transport layer 24. By forming the first drain opening 38A, a first drain contact region 56 containing donor-type impurities is formed on the first side wall 52 that partitions the first drain opening 38A. Then, by forming the first drain opening 38A so as to penetrate the drain-doped region 816, the bottom portion 50 that partitions the first drain opening 38A can be made free of donor-type impurities. After this, the resist film 812 is removed, for example, with a stripping solution.

[0094] As shown in Figure 17, the method for manufacturing the nitride semiconductor device 10 includes forming a metal layer 818. In one example, the metal layer 818 can be formed on the passivation layer 34 by sputtering. The metal layer 818 is formed to fill the first source opening 36A, the second source opening 36B, the first drain opening 38A, and the second drain opening 38B. The metal layer 818 includes a first metal layer 71, a second metal layer 72, a third metal layer 73, and a fourth metal layer 74, as shown in Figures 4 and 5.

[0095] As shown in Figure 18, the manufacturing method of the nitride semiconductor device 10 includes forming a source electrode 40 and a drain electrode 42. In one example, a resist film 820 is formed which includes an opening 820A that exposes a portion of the metal layer 818 shown in Figure 17, and the source electrode 40 and drain electrode 42 are formed by etching away a portion of the metal layer 818 shown in Figure 17 from the opening 820A of the resist film 820.

[0096] As shown in Figure 19, the manufacturing method of the nitride semiconductor device 10 includes forming a back electrode 46. The back electrode 46 is formed, for example, by sputtering, so as to cover the second surface 20B of the semiconductor substrate 20. The second surface 20B of the semiconductor substrate 20 may be a surface obtained by thinning a wafer for forming a plurality of semiconductor substrates 20. The nitride semiconductor device 10 may also be formed by framing the wafer. Through the above steps, the nitride semiconductor device 10 shown in Figure 3 is obtained.

[0097] (Effects of the embodiment) As described above, the nitride semiconductor device 10 of this embodiment provides the following effects.

[0098] (1) In the nitride semiconductor device 10, the first side wall 52 of the first source opening 36A includes a first source contact region 56 that is in contact with the side surface 43B of the source contact portion 40A. The first side wall 52 of the first drain opening 38A includes a first drain contact region 56 that is in contact with the side surface 43B of the drain contact portion 42A. The first source contact region 56 and the first drain contact region 56 contain donor-type impurities and are continuously provided in the electron transport layer 24 and the electron supply layer 26 in the Z-axis direction. The bottom portions 50 of the first source opening and the first drain opening 38A include bottom contact regions 60, 60 that are in contact with the bottom surfaces 43A, 43A of the source contact portion 40A and the drain contact portion 42A. The impurity concentration of donor-type impurities in the bottom contact regions 60, 60 is lower than that in the first drain contact region 56 and the first source contact region 56.

[0099] The first drain opening 38A penetrates the electron supply layer 26 and reaches the interior of the electron transport layer 24. The drain contact portion 42A of the drain electrode 42 positioned in the first drain opening 38A is in direct contact with the electron transport layer 24. Therefore, the nitride semiconductor device 10 of this embodiment has low contact resistance between the drain contact portion 42A and 2DEG28. This reduces the on-resistance, which is the drain-source resistance when the nitride semiconductor device 10 is turned on.

[0100] (2) The first source opening 36A and the first drain opening 38A penetrate the electron supply layer 26 and reach the interior of the electron transport layer 24. The source contact portion 40A of the source electrode 40 located in the first source opening 36A is in direct contact with the electron transport layer 24. Therefore, the nitride semiconductor device 10 of the embodiment has low contact resistance between the source contact portion 40A and 2DEG28. This reduces the on-resistance, which is the drain-source resistance when the nitride semiconductor device 10 is turned on.

[0101] (3) The side surface 43B of the drain contact portion 42A is in contact with the first drain contact region 56 containing donor-type impurities. Therefore, the contact resistance is reduced in the ohmic contact between the drain contact portion 42A and the electron transport layer 24. This makes it possible to further reduce the on-resistance, which is the drain-source resistance when the nitride semiconductor device 10 is turned on.

[0102] (4) The side surface 43B of the source contact portion 40A is in contact with the first source contact region 56 containing donor-type impurities. Therefore, the contact resistance is reduced in the ohmic contact between the source contact portion 40A and the electron transport layer 24. This further reduces the on-resistance, which is the drain-source resistance when the nitride semiconductor device 10 is turned on.

[0103] (5) The drain electrode 42 includes a first metal layer 71 that is in contact with the electron transport layer 24. The first metal layer 71 is a Ti layer. Ti is a metal that has a reducing effect. The first metal layer 71 reduces the oxide formed between the first metal layer 71 and the electron transport layer 24. Therefore, the oxide formed in the first drain opening 38A disappears or decreases. This reduces the contact resistance between the drain electrode 42 and the electron transport layer 24.

[0104] (6) The source electrode 40 includes a first metal layer 71 which is a Ti layer. Therefore, similar to the drain electrode 42, the contact resistance between the source electrode 40 and the electron transport layer 24 can be reduced. (7) In a zero-bias state, where a voltage equal to the voltage of the source electrode 40 is applied to the gate electrode, a voltage drop occurs between the drain contact portion 42A of the drain electrode 42 and the gate layer 30 in a plan view. The field plate electrode 44 extends a depletion layer in the region directly beneath the field plate electrode 44, and plays a role in mitigating electric field concentration near the ends of the gate electrode 32 and the gate layer 30. This suppresses current collapse.

[0105] (8) The drain electrode 42 includes a drain extension 42B provided on the periphery of the second drain opening 38B of the passivation layer 34. The drain extension 42B has a second width W31 from the drain contact portion 42A to the drain end portion 42C of the drain extension 42B. If the second width W31 from the drain contact portion 42A to the drain end portion 42C of the drain extension 42B is large, electron trapping near the drain electrode 42 may increase. This electron trapping can be a cause of current collapse. Therefore, current collapse can be suppressed by making the second width W31 of the drain extension 42B 200 nm or less.

[0106] (9) The first width W21 of the first drain contact region 56 in the X-axis direction is smaller than the second width W31 of the drain extension portion 42B. If the first width W21 of the first drain contact region 56 is larger than the second width W31 of the drain extension portion 42B, the breakdown voltage between the drain and gate, i.e., between the drain and source, in the zero-bias state is reduced. The distance L11 between the drain contact portion 42A of the drain electrode 42 and the gate layer 30 in the X direction is, for example, 2 μm. Therefore, in the nitride semiconductor device 10 of the embodiment, the reduction in breakdown voltage between the drain and source can be suppressed.

[0107] (10) In the Z-axis direction, a portion of the electron transport layer 24 and the buffer layer 22 between the lower surface 43A of the drain contact portion 42A and the first surface 20A of the semiconductor substrate 20 are an insulating layer 21A interposed between the drain contact portion 42A and the semiconductor substrate 20. The thickness T21 of the insulating layer 21A in the Z-axis direction may be called the vertical insulating layer thickness. The vertical insulating layer thickness T21 may be set according to the dielectric breakdown voltage of the nitride semiconductor device 10. For example, in the case of a 100V withstand voltage product, the vertical insulating layer thickness T21 is 600 nm to 1.3 μm in one example.

[0108] If n-type impurities are present between the drain contact portion 42A and the semiconductor substrate 20 in the Z-axis direction, the longitudinal insulating layer thickness T21 will be substantially reduced. This substantial reduction in the longitudinal insulating layer thickness T21 leads to a decrease in the dielectric breakdown voltage between the drain electrode 42 and the semiconductor substrate 20.

[0109] In the nitride semiconductor device 10 of this embodiment, the bottom portion 50 includes a bottom contact region 60 that contacts the lower surface 43A of the drain contact portion 42A. The bottom contact region 60 extends over the entire upper surface 50A of the bottom portion 50. The bottom contact region 60 does not contain donor-type impurities. The lower surface 43A of the drain contact portion 42A is in contact with the bottom portion 50, which does not contain donor-type impurities. Therefore, in the nitride semiconductor device 10 of this embodiment, a decrease in dielectric breakdown voltage in the vertical direction can be suppressed.

[0110] <Example of changes> The above embodiment can be modified as follows, for example. The above embodiment and the following modifications can be combined with each other as long as no technical inconsistencies arise. In the following modifications, parts common to the above embodiment are denoted by the same reference numerals as in the above embodiment, and their descriptions are omitted.

[0111] Figure 20 shows a modified example of a nitride semiconductor device 210. This nitride semiconductor device 210 includes a first source aperture 36A and a first drain aperture 38A. The side surface 52A of the first side wall 52 of the first source aperture 36A is in contact with the side surface 43B of the source contact portion 40A of the source electrode 40. The side surface 52A of the first side wall 52 may be inclined with respect to the Z-axis direction. The inclination angle θ2 of the side surface 52A of the first side wall 52 with respect to the Z-axis direction may be greater than 0° and 15° or less. The side surface 52A of the first side wall 52 is inclined such that the aperture width W12 in the X-axis direction decreases from the upper surface 26A of the electron supply layer 26 toward the bottom 50 of the first source aperture 36A. The inner wall surface of the first source aperture 36A can be said to be inclined such that the aperture width W12 in the X-axis direction decreases from the upper surface 26A of the electron supply layer 26 toward the bottom 50 of the first source aperture 36A.

[0112] The first side wall 52 spans from the electron transport layer 24 to the electron supply layer 26. Therefore, the inclination angle of the side surface 52A near the interface, which is the boundary between the electron transport layer 24 and the electron supply layer 26, is greater than 0° and 15° or less with respect to the Z-axis direction. 2DEG28 spreads within the electron transport layer 24 at a position close to the interface between the electron transport layer 24 and the electron supply layer 26. Therefore, by making the inclination angle of the side surface 52A near the interface 15° or less with respect to the Z-axis direction, the source contact portion 40A of the source electrode 40 can be brought closer to 2DEG28, thereby reducing the contact resistance between the source contact portion 40A and 2DEG28.

[0113] The passivation layer 34 includes a second source opening 36B that communicates with the first source opening 36A. The passivation layer 34 includes a second side wall 62 that partitions the second source opening 36B. The side surface 62A of the second side wall 62 may have the same inclination angle as the side surface 52A of the first side wall 52, or it may have a different inclination angle than the side surface 52A of the first side wall 52.

[0114] The side surface 52A of the first side wall 52 of the first drain opening 38A is in contact with the side surface 43B of the drain contact portion 42A of the drain electrode 42. The side surface 52A of the first side wall 52 may be inclined with respect to the Z-axis direction. The inclination angle θ1 of the side surface 52A of the first side wall 52 with respect to the Z-axis direction may be greater than 0° and 15° or less. The side surface 52A of the first side wall 52 is inclined such that the opening width W11 in the X-axis direction decreases from the upper surface 26A of the electron supply layer 26 toward the bottom 50 of the first drain opening 38A. The inner wall surface of the first drain opening 38A can be said to be inclined such that the opening width W11 in the X-axis direction decreases from the upper surface 26A of the electron supply layer 26 toward the bottom 50 of the first drain opening 38A.

[0115] The first side wall 52 spans from the electron transport layer 24 to the electron supply layer 26. Therefore, the inclination angle of the side surface 52A near the interface between the electron transport layer 24 and the electron supply layer 26 is greater than 0° and 15° or less with respect to the Z-axis direction. 2DEG28 spreads within the electron transport layer 24 at a position close to the interface between the electron transport layer 24 and the electron supply layer 26. Therefore, by making the inclination angle of the side surface 52A near the interface 15° or less with respect to the Z-axis direction, the drain contact portion 42A of the drain electrode 42 can be brought closer to 2DEG28. This reduces the contact resistance between the drain contact portion 42A and 2DEG28.

[0116] The passivation layer 34 includes a second drain opening 38B that communicates with the first drain opening 38A. The passivation layer 34 includes a second side wall 62 that partitions the second drain opening 38B. The side surface 62A of the second side wall 62 may have the same inclination angle as the side surface 52A of the first side wall 52, or it may have a different inclination angle than the side surface 52A of the first side wall 52.

[0117] Figure 21 shows a modified example of a nitride semiconductor device 310. In this nitride semiconductor device 310, the gate layer 330 may include extended portions 341 and 342. More specifically, the gate layer 330 includes a ridge portion 331 and first extended portions 341 and second extended portions 342 extending in opposite directions from both ends of the ridge portion 331. These ridge portion 331, first extended portion 341, and second extended portion 342 constitute a stepped structure of the gate layer 330. The first extended portion 341 extends from the side of the ridge portion 331 closer to the source electrode 40 toward the source opening 36. The second extended portion 342 extends from the side of the ridge portion 331 closer to the drain electrode 42 toward the drain opening 38. The ridge portion 331 corresponds to the relatively thick portion of the gate layer 330. The second extension portion 342 extends longer from the ridge portion 331 than the first extension portion 341. However, the first extension portion 341 and the second extension portion 342 may be of the same length.

[0118] In this modified example, the nitride semiconductor device 310 can reduce the hole density accumulated at the interface between the gate layer 330 and the electron supply layer 26 due to the first extension portion 341 and the second extension portion 342. Therefore, band bending of the electron supply layer 26 caused by hole accumulation can be suppressed, and the increase in gate leakage current can be suppressed. The field plate electrode 44 covers the end portion 342A of the second extension portion 342 near the drain electrode 42. Therefore, electric field concentration near the end portion 342A of the gate layer 330 can be suppressed.

[0119] The nitride semiconductor device 10 is not limited to the structure of the embodiment described above with reference to Figure 3. For example, although the nitride semiconductor device 10 in the above embodiment is configured as a normally-off HEMT, the configuration of this disclosure is not limited to a normally-off HEMT and is also applicable to a normally-on HEMT. For example, the nitride semiconductor device 10 can be configured as a normally-on HEMT by omitting the gate layer 30 from the nitride semiconductor device 10, or by configuring the gate layer 30 as a nitride semiconductor layer that does not contain acceptor-type impurities.

[0120] The second width W31 of the drain extension portion 42B may be less than or equal to the first width W21 of the first drain contact region 56. For example, if the first width W21 of the first drain contact region 56 is 100 nm, the second width W31 of the drain extension portion 42B may be 100 nm or less.

[0121] As used in this disclosure, the term “on” includes both the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0122] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0123] [Note 1] Electronic transport layer (24), An electron supply layer (26) is provided on the electron transport layer (24) and has a larger band gap than the electron transport layer (24), A gate electrode (32) provided on the electron transport layer (24), A first source opening (36A) and a first drain opening (38A) are arranged to sandwich the gate electrode (32) when viewed from the thickness direction (Z) of the electron transport layer (24), and penetrate the electron supply layer (26) and reach the interior of the electron transport layer (24), The source electrode (40) is positioned in the first source opening (36A), The drain electrode (42) positioned in the first drain opening (38A), Includes, The source electrode (40) includes a source contact portion (40A) that is in contact with the electron transport layer (24) within the first source opening (36A). The drain electrode (42) includes a drain contact portion (42A) that contacts the electron transport layer (24) within the first drain opening (38A). The first side wall of the first source opening (36A) includes a first source contact region (56) that is in contact with the side surface (43B) of the source contact portion (40A). The first side wall of the first drain opening (38A) includes a first drain contact region (56) that is in contact with the side surface (43B) of the drain contact portion (42A). The first source contact region (56) and the first drain contact region (56) contain donor-type impurities and are continuously provided in the electron transport layer (24) and the electron supply layer (26) in the thickness direction (Z). The bottom portion (50) of the first source opening (36A) and the first drain opening (38A) includes a bottom contact region (60) that contacts the bottom surface of the source contact portion (40A) and the drain contact portion (42A). The lower contact region (60) has a lower impurity concentration of the donor-type impurity than the first drain contact region (56) and the first source contact region (56). Nitride semiconductor equipment.

[0124] [Note 2] The aforementioned donor-type impurity is Si, as described in Appendix 1, for the nitride semiconductor device. [Note 3] The lower contact region (60) is free of the donor-type impurities. Nitride semiconductor device as described in Appendix 1 or Appendix 2.

[0125] [Note 4] The electron supply layer (26) and the passivation layer (34) covering the gate electrode (32) are included. The passivation layer (34) includes a second source opening (36B) communicating with the first source opening (36A) and a second drain opening (38B) communicating with the first drain opening (38A), The source contact portion (40A) is located within the first source opening (36A) and the second source opening (36B), and is in contact with the second side wall (62) of the second source opening (36B). The drain contact portion (42A) is located within the first drain opening (38A) and the second drain opening (38B), and is in contact with the second side wall (62) of the second drain opening (38B). Nitride semiconductor device as described in any one of the appendices 1 to 3.

[0126] [Note 5] The second side wall (62) of the second source opening (36B) includes a second source contact region (64) that is in contact with the side surface (43B) of the source contact portion (40A). The second side wall (62) of the second drain opening (38B) includes a second drain contact region (64) that is in contact with the side surface (43B) of the drain contact portion (42A). The second source contact region (64) and the second drain contact region (64) contain the donor-type impurities, Nitride semiconductor device as described in Appendix 4.

[0127] [Note 6] The drain electrode (42) includes a drain extension (42B) provided on the periphery of the second drain opening (38B) of the passivation layer (34), The direction in which the source electrode (40) and the drain electrode (42) are arranged is defined as the first direction (X). In the first direction (X), the first width (W21) of the first drain contact region (56) is smaller than the second width (W31) of the drain extension (42B). Nitride semiconductor device as described in Appendix 4 or Appendix 5.

[0128] [Note 7] The second width (W31) of the drain extension (42B) is 200 nm or less, and the first width (W21) of the first drain contact region (56) is 150 nm or less. Nitride semiconductor device as described in Appendix 6.

[0129] [Note 8] The field plate electrode (44) is provided on the passivation layer (34), extends at least partially into the region between the gate electrode (32) and the drain electrode (42) in a plan view, and is electrically connected to the source electrode (40), Nitride semiconductor device as described in any one of the appendices 4 to 7.

[0130] [Note 9] The passivation layer (34) is made of a material containing SiN. A nitride semiconductor device as described in any one of the appendices 4 through 8.

[0131] [Note 10] The first depth (D12) from the upper surface of the electron transport layer (24) to the bottom (50) of the first source aperture (36A) is 50 nm or less. The second depth (D11) from the upper surface of the electron transport layer (24) to the bottom (50) of the first drain opening (38A) is 50 nm or less. A nitride semiconductor device as described in any one of the appendices 1 through 9.

[0132] [Note 11] The first depth (D12) and the second depth (D11) are greater than or equal to the thickness (T11) of the electron supply layer (26). Nitride semiconductor device as described in Appendix 10.

[0133] [Note 12] The inclination angle (θ1, θ2) of the first side wall (52) with respect to the thickness direction (Z) is 0° or more and 15° or less. A nitride semiconductor device as described in any one of the appendices 1 through 11.

[0134] [Note 13] The first side wall (52) is inclined such that the opening width (W11) in the direction in which the source electrode (40) and the drain electrode (42) are arranged to sandwich the gate electrode (32) decreases from the top surface to the bottom of the electron supply layer (26). A nitride semiconductor device as described in any one of the appendices 1 through 11.

[0135] [Note 14] A semiconductor substrate (20) including a first surface (20A) and a second surface (20B) opposite to the first surface (20A), A buffer layer (22) provided on the first surface (20A), Includes, The electron transport layer (24) is provided on top of the buffer layer (22). A nitride semiconductor device as described in any one of the appendices 1 through 13.

[0136] [Note 15] The thickness (T21) of the longitudinal insulating layer from the bottom surface of the first drain opening (38A) to the first surface (20A) of the semiconductor substrate (20) is 600 nm or more and 1.3 μm or less. Nitride semiconductor device as described in Appendix 14.

[0137] [Note 16] Provided on the electron supply layer (26), and including a gate layer (30) containing acceptor-type impurities, The gate electrode (32) is provided on the gate layer (30). A nitride semiconductor device as described in any one of the appendices 1 through 15.

[0138] [Note 17] The aforementioned gate electrode (32) is made of a material containing TiN. A nitride semiconductor device as described in any one of the appendices 1 through 16.

[0139] [Note 18] The source electrode (40) and the drain electrode (42) are in contact with the electron transport layer (24) and the electron supply layer (26), and include a first metal layer (71) made of a material containing Ti. A nitride semiconductor device as described in any one of the appendices 1 through 17.

[0140] [Note 19] Forming an electron transport layer (24), An electron supply layer (26) having a larger band gap than the electron transport layer (24) is formed on the electron transport layer (24). Forming a gate electrode (32) on the electron transport layer (24), In the electron supply layer (26) and the electron transport layer (24), donor-type impurities are injected so as to sandwich the gate electrode (32) when viewed from the thickness direction (Z) of the electron transport layer (24) to form a source-doped region (814) and a drain-doped region (816). A first source opening (36A) is formed that penetrates the source doped region, and a first drain opening (38A) is formed that penetrates the drain doped region. A source electrode (40) including a source contact portion (40A) disposed within the first source opening (36A), and a drain electrode (42) including a drain contact portion (42A) disposed within the first drain opening (38A), Includes, The first source opening (36A) and the first drain opening (38A) extend from the upper surface of the electron supply layer (26) through the electron supply layer (26) into the electron transport layer (24). The source doped region (814) constitutes a first source contact region (56) that contacts the side surface (43B) of the source contact portion (40A). The drain-doped region (816) constitutes a first drain contact region (56) that contacts the side surface (43B) of the drain contact portion (42A). A method for manufacturing nitride semiconductor devices.

[0141] [Note 20] To form a passivation layer (34) covering the gate electrode (32) and the electron supply layer (26), A second source opening (36B) and a second drain opening (38B) are formed in the passivation layer (34) such that, when viewed from the thickness direction (Z), the gate electrode (32) is sandwiched between them, and a portion of the upper surface of the electron supply layer (26) is exposed. Includes, The donor-type impurity is injected into the electron supply layer (26) and the electron transport layer (24) through the second source opening (36B) to form the source-doped region (814), The donor-type impurity is injected into the electron supply layer (26) and the electron transport layer (24) through the second drain opening (38B) to form the drain-doped region (816). The method for manufacturing a nitride semiconductor device as described in Appendix 19.

[0142] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0143] 10 Nitride semiconductor devices 12 chip body 12A 1st page 12B 2nd side 14 Gate Pads 16 Sourcepad 18 Drain Pads 20 Semiconductor substrates 20A, 20B 1st side, 2nd side 21 Nitride semiconductor layer 21A Insulating layer 22 Buffer Layers 24 Electron Transport Layer 24A, 24B top, bottom 26 Electron supply layer 26A, 26B top, bottom 28. Two-dimensional electron gas (2DEG) 30 gate layers 32 gates 34 Passivation Layer 34A, 34B Top surface, Bottom surface 36 Source opening 36A First Source Aperture 36B Second Source Opening 38 Drain opening 38A First drain opening 38B Second drain opening 40 Source electrodes 40A Source Contact Section 40B Source extension 42 Drain electrode 42A Drain Contact Section 42B Drain extension 42C Drain end 43A, 43B bottom, side 44 Field plate electrodes 44A End 46 Backside electrode 48 Connection Wiring 50 bottom 50A top 52 First side wall 52A Side view 53A, 53B 1st part, 2nd part 54 Curved surface 56 First source contact region, first drain contact region 56A bottom end 58 areas 60 Bottom contact area 62 Second side wall 62A Side view 64 Second source contact region, second drain contact region 64A top end 66 areas 71~74 1st~4th metal layer θ1,θ2 Tilt angle D11, D12 Depth L11 distance T11 Thickness T21 Thickness, Longitudinal Insulation Layer Thickness W11 Opening width W12 opening width W21 1st width W31 2nd width

Claims

1. Electronic transport layer, An electron supply layer provided on the electron transport layer and having a band gap larger than that of the electron transport layer, A gate electrode provided on the electron transport layer, A first source opening and a first drain opening are arranged so as to sandwich the gate electrode when viewed from the thickness direction of the electron transport layer, and penetrate the electron supply layer and reach the interior of the electron transport layer, The source electrode positioned in the first source opening, The drain electrode arranged in the first drain opening, Includes, The source electrode includes a source contact portion that contacts the electron transport layer within the first source opening. The drain electrode includes a drain contact portion that contacts the electron transport layer within the first drain opening. The first side wall of the first source opening includes a first source contact region that is in contact with the side surface of the source contact portion. The first side wall of the first drain opening includes a first drain contact region that is in contact with the side surface of the drain contact portion. The first source contact region and the first drain contact region contain donor-type impurities and are continuously provided in the electron transport layer and the electron supply layer in the thickness direction. The bottoms of the first source opening and the first drain opening include a bottom contact region that contacts the bottom surface of the source contact portion and the drain contact portion. The lower contact region has a lower impurity concentration of the donor-type impurity than the first drain contact region and the first source contact region. Nitride semiconductor equipment.

2. The nitride semiconductor device according to claim 1, wherein the donor-type impurity is Si.

3. The lower contact area does not contain the donor-type impurities. The nitride semiconductor device according to claim 1.

4. The electron supply layer and the passivation layer covering the gate electrode are included. The passivation layer includes a second source opening communicating with the first source opening and a second drain opening communicating with the first drain opening. The source contact portion is located within the first source opening and the second source opening, and is in contact with the second side wall of the second source opening. The drain contact portion is located within the first drain opening and the second drain opening, and is in contact with the second side wall of the second drain opening. A nitride semiconductor device according to any one of claims 1 to 3.

5. The second side wall of the second source opening includes a second source contact region that is in contact with the side surface of the source contact portion. The second side wall of the second drain opening includes a second drain contact region that is in contact with the side surface of the drain contact portion. The second source contact region and the second drain contact region contain the donor-type impurity, The nitride semiconductor device according to claim 4.

6. The drain electrode includes a drain extension provided on the peripheral edge of the second drain opening of the passivation layer, The direction in which the source electrode and the drain electrode are arranged is defined as the first direction. In the first direction, the first width of the first drain contact region is smaller than the second width of the drain extension. The nitride semiconductor device according to claim 4.

7. The second width of the drain extension is 200 nm or less, and the first width of the first drain contact region is 150 nm or less. The nitride semiconductor device according to claim 6.

8. A field plate electrode is provided on the passivation layer, extends at least partially into the region between the gate electrode and the drain electrode in a plan view, and is electrically connected to the source electrode, The nitride semiconductor device according to claim 4.

9. The passivation layer is made of a material containing SiN. The nitride semiconductor device according to claim 4.

10. The first depth from the upper surface of the electron transport layer to the bottom of the first source opening is 50 nm or less. The second depth from the upper surface of the electron transport layer to the bottom of the first drain opening is 50 nm or less. The nitride semiconductor device according to claim 1.

11. The first depth and the second depth are greater than or equal to the thickness of the electron supply layer. The nitride semiconductor device according to claim 10.

12. The inclination angle of the first side wall with respect to the thickness direction is 0° or more and 15° or less. The nitride semiconductor device according to claim 1.

13. The first side wall is inclined such that the opening width in the direction in which the source electrode and the drain electrode are arranged to sandwich the gate electrode decreases from the top surface to the bottom of the electron supply layer. The nitride semiconductor device according to claim 1.

14. A semiconductor substrate including a first surface and a second surface opposite to the first surface, A buffer layer provided on the first surface, Includes, The electron transport layer is provided on the buffer layer, The nitride semiconductor device according to claim 1.

15. The thickness of the longitudinal insulating layer from the bottom surface of the first drain opening to the first surface of the semiconductor substrate is 600 nm or more and 1.3 μm or less. The nitride semiconductor device according to claim 14.

16. Provided on the aforementioned electron supply layer, and including a gate layer containing acceptor-type impurities, The gate electrode is provided on the gate layer, The nitride semiconductor device according to claim 1.

17. The aforementioned gate electrode is made of a material containing TiN. The nitride semiconductor device according to claim 1.

18. The source electrode and the drain electrode are in contact with the electron transport layer and the electron supply layer and include a first metal layer made of a material containing Ti. The nitride semiconductor device according to claim 1.

19. Forming an electron transport layer, Form an electron supply layer having a band gap larger than that of the electron transport layer on the electron transport layer. Forming a gate electrode on the electron transport layer, In the electron supply layer and the electron transport layer, a donor-type impurity is injected so as to sandwich the gate electrode when viewed from the thickness direction of the electron transport layer, thereby forming a source-doped region and a drain-doped region. A first source opening is formed that penetrates the source doped region, and a first drain opening is formed that penetrates the drain doped region. To form a source electrode including a source contact portion disposed within the first source opening, and a drain electrode including a drain contact portion disposed within the first drain opening, Includes, The first source opening and the first drain opening extend from the upper surface of the electron supply layer, through the electron supply layer, into the electron transport layer. The source-doped region constitutes a first source contact region that contacts the side surface of the source contact portion. The drain-doped region constitutes a first drain contact region that contacts the side surface of the drain contact portion. A method for manufacturing nitride semiconductor devices.

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