Semiconductor equipment

Abstract

Reduce the effect of inductance. [Solution] The semiconductor device comprises first switching elements 11U, 11V, 11W, second switching elements, first, second, and third inverter circuits, a first conductive layer 31 on which the first switching elements 11U, 11V, 11W of each inverter circuit are mounted, second, third, and fourth conductive layers on which the second switching elements of each inverter circuit are mounted, and a first integrated circuit element 25H on which a control circuit for controlling the first switching elements 11U, 11V, 11W of each inverter circuit is mounted. The second switching elements of each inverter circuit are mounted on the second, third, and fourth conductive layers respectively in the same orientation in a plan view. At least one of the first switching elements 11U, 11V, 11W of each inverter circuit is mounted on the first conductive layer 31 in a different orientation from the other first switching elements in a plan view.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device has been developed that integrates an inverter circuit having a first switching element to which a power supply voltage is supplied and a second switching element connected in series with the first switching element, and a control circuit that controls the on / off state of each switching element, into a single package by mounting these components on a lead frame (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2016-82281

[0004] [overview] In the semiconductor device described above, the control terminal of the first switching element and the control circuit are electrically connected by a bonding wire. As the length of this bonding wire increases, the influence of the inductance caused by the bonding wire becomes greater.

[0005] A semiconductor device according to one aspect of the present disclosure includes: a first switching element and a second switching element formed in a rectangular shape in plan view, each having a first electrode, a second electrode, and a control electrode; a first inverter circuit, a second inverter circuit, and a third inverter circuit, each including the first switching element and the second switching element, the first electrode of the first switching element being connected to a power supply, the second electrode of the first switching element being connected to the first electrode of the second switching element, and the second electrode of the second switching element being connected to ground; a first conductive layer on which the first switching element included in each of the first inverter circuit, and the third inverter circuit is mounted; a second conductive layer spaced apart from the first conductive layer on which the second switching element of the first inverter circuit is mounted; a third conductive layer spaced apart from the first conductive layer on which the second switching element of the second inverter circuit is mounted; a fourth conductive layer spaced apart from the first conductive layer on which the second switching element of the third inverter circuit is mounted; and the first inverter circuit The first integrated circuit element is provided spaced apart from the second and third inverter circuits and is equipped with a control circuit for controlling the first switching elements of each of the first inverter circuits, the second inverter circuit and the third inverter circuit; and the first wire electrically connects the control electrode of each of the first switching elements of the first inverter circuit and the first integrated circuit element, wherein the second conductive layer, the third conductive layer and the fourth conductive layer are insulated from each other and provided spaced apart in a first direction perpendicular to the thickness direction of each of the switching elements; the second switching elements of the first inverter circuit, the second inverter circuit and the third inverter circuit are mounted on the second conductive layer, the third conductive layer and the fourth conductive layer respectively in the same orientation in a plan view; and at least one of the first switching elements of the first inverter circuit, the second inverter circuit and the third inverter circuit is mounted on the first conductive layer in a different orientation from the other first switching elements in a plan view.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a block diagram showing the electrical configuration of the semiconductor device of the first embodiment. [Figure 2] FIG. 2 is a plan view showing the internal layout configuration of the semiconductor device. [Figure 3] FIG. 3 is a perspective view of the semiconductor device. [Figure 4] FIG. 4 is a bottom view of the semiconductor device. [Figure 5] FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 2. [Figure 6] FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. 2. [Figure 7] FIG. 7 is a partially enlarged view of FIG. 2. [Figure 8] FIG. 8 is a cross-sectional view taken along line 8-8 of FIG. 7. [Figure 9] FIG. 9 is a partially enlarged view of FIG. 2. [Figure 10] FIG. 10 is a cross-sectional view taken along line 10-10 of FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view showing the structure of the MOSFET. [Figure 12] FIG. 12 is a circuit diagram showing a partial detailed electrical configuration of the semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing a partial detailed electrical configuration of the semiconductor device of the second embodiment. [Figure 14] FIG. 14 is a schematic plan view showing the element arrangement of a part of the integrated circuit element of the semiconductor device. [Figure 15] FIG. 15 is a plan view showing a partially enlarged internal layout configuration of the semiconductor device of the third embodiment. [Figure 16] FIG. 16 is a block diagram showing the electrical configuration of the semiconductor device of the fourth embodiment. [Figure 17] FIG. 17 is a plan view showing the internal layout configuration of the semiconductor device. [Figure 18A] FIG. 18A is a cross-sectional perspective view showing the structure of the diode. [Figure 18B] Figure 18B is a cross-sectional view showing the structure of a diode. [Figure 19] Figure 19 is a diagram illustrating the operation of the fourth embodiment and is a circuit diagram showing the electrical connection configuration of the drive unit. [Figure 20] Figure 20 is a block diagram showing the electrical configuration of the semiconductor device according to the fifth embodiment. [Figure 21] Figure 21 is a plan view showing the internal layout of a semiconductor device. [Figure 22] Figure 22 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 23] Figure 23 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 24] Figure 24 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 25] Figure 25 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 26] Figure 26 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 27] Figure 27 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 28] Figure 28 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 29] Figure 29 is a plan view showing the internal layout of a modified semiconductor device. [Figure 30] Figure 30 is a plan view showing the internal layout of a modified semiconductor device. [Figure 31] Figure 31 is a plan view showing the internal layout of a modified semiconductor device. [Figure 32] Figure 32 is an enlarged plan view of a portion of the internal layout of a modified semiconductor device. [Figure 33] Figure 33 is a plan view showing the internal layout of a modified semiconductor device. [Figure 34]Figure 34 is a cross-sectional view showing the structure of a modified MOSFET. [Figure 35] Figure 35 is a cross-sectional view showing the structure of a modified MOSFET. [Figure 36] Figure 36 is a cross-sectional view showing the structure of a modified diode. [Figure 37] Figure 37 is a block diagram showing the electrical configuration of a modified semiconductor device. [Figure 38] Figure 38 is a plan view showing the internal layout of the semiconductor device shown in Figure 37. [Figure 39] Figure 39 is a plan view showing the internal layout of a modified semiconductor device.

[0007] [Detailed explanation] The following describes various embodiments of the semiconductor device with reference to the drawings. The embodiments shown below illustrate configurations and methods for realizing the technical concept, and do not limit the materials, shapes, structures, arrangements, dimensions, etc., of each component to those described below. Various modifications can be made to the embodiments described below.

[0008] In this specification, "member A connected to member B" includes cases where member A and member B are physically and directly connected, as well as cases where member A and member B are indirectly connected via other members that do not affect the electrical connection state.

[0009] Similarly, "the state in which member C is provided between member A and member B" includes cases where member A and member C, or member B and member C are directly connected, as well as cases where member A and member C, or member B and member C are indirectly connected via other members that do not affect the electrical connection state.

[0010] (First Embodiment) As shown in Figure 1, the semiconductor device 1 constitutes an inverter circuit for driving the motor 2 and includes a drive unit 10 having three inverter circuits: a first inverter circuit 10U, a second inverter circuit 10V, and a third inverter circuit 10W, and a control circuit 20 for controlling the drive unit 10. Each inverter circuit 10U, 10V, and 10W is connected in parallel with each other. An example of the motor 2 is a three-phase brushless motor.

[0011] Each inverter circuit 10U, 10V, and 10W includes a first switching element 11 and a second switching element 12. The first switching element 11 and the second switching element 12 are connected in series. The first switching element 11 has a first terminal to which the power supply voltage is supplied, a second terminal connected to the second switching element 12, and a control terminal. The second switching element 12 has a first terminal connected to the second terminal of the first switching element 11, a second terminal connected to ground, and a control terminal. An example of the first switching element 11 and the second switching element 12 is a MOSFET (metal-oxide-semiconductor field-effect transistor). Hereafter, the first switching element 11 of the first inverter circuit 10U will be referred to as MOSFET 11U, the first switching element 11 of the second inverter circuit 10V as MOSFET 11V, and the first switching element 11 of the third inverter circuit 10W as MOSFET 11W. Furthermore, the second switching element 12 of the first inverter circuit 10U will be described as MOSFET 12U, the second switching element 12 of the second inverter circuit 10V will be described as MOSFET 12V, and the second switching element 12 of the third inverter circuit 10W will be described as MOSFET 12W. In this embodiment, N-channel MOSFETs are used for MOSFETs 11U~11W and 12U~12W. The drains of MOSFETs 11U~11W are examples of the first terminals of the first switching element 11, the sources of MOSFETs 11U~11W are examples of the second terminals of the first switching element 11, and the gates of MOSFETs 11U~11W are examples of the control terminals of the first switching element 11. The drains of MOSFETs 12U~12W are examples of the first terminals of the second switching element 12, the sources of MOSFETs 12U~12W are examples of the second terminals of the second switching element 12, and the gates of MOSFETs 12U~12W are examples of the control terminals of the second switching element 12.

[0012] MOSFET11U and MOSFET12U are connected in series. That is, the source of MOSFET11U and the drain of MOSFET12U are connected to each other. Node N between the source of MOSFET11U and the drain of MOSFET12U is electrically connected to the U-phase coil (not shown) of motor 2.

[0013] MOSFET11V and MOSFET12V are connected in series. That is, the source of MOSFET11V and the drain of MOSFET12V are connected to each other. Node N between the source of MOSFET11V and the drain of MOSFET12V is electrically connected to the V-phase coil (not shown) of motor 2.

[0014] MOSFET11W and MOSFET12W are connected in series. That is, the source of MOSFET11W and the drain of MOSFET12W are connected to each other. Node N between the source of MOSFET11W and the drain of MOSFET12W is electrically connected to the W-phase coil (not shown) of motor 2.

[0015] The drains of MOSFETs 11U to 11W are connected to each other. The drains of MOSFETs 11U to 11W are electrically connected to an external power supply. The sources of MOSFETs 12U to 12W are connected to each other. The sources of MOSFETs 12U to 12W are connected to ground (GND). The gates of MOSFETs 11U to 11W and MOSFETs 12U to 12W are electrically connected to the control circuit 20, respectively.

[0016] The current flowing through each of the MOSFETs 11U~11W and MOSFETs 12U~12W is preferably less than 30A. In this embodiment, the current flowing through each of the MOSFETs 11U~11W and MOSFETs 12U~12W is approximately 15A.

[0017] The control circuit 20 includes a drive circuit 21, which is an example of a drive signal output circuit that outputs drive signals to the gates of MOSFETs 11U to 11W and MOSFETs 12U to 12W, respectively; a logic circuit 22 that controls the drive circuit 21; and a bootstrap circuit 23 that generates a drive power supply for the high-potential blocks of the drive circuit 21 and the logic circuit 22. The control circuit 20 has drive circuits 21, logic circuits 22, and bootstrap circuits 23 corresponding to MOSFETs 11U to 11W and MOSFETs 12U to 12W, respectively.

[0018] The drive circuit 21 includes drive circuits 21UU, 21VU, and 21WU that control the gates of MOSFETs 11U to 11W on the high-potential side, and drive circuits 21UL, 21VL, and 21WL that control the gates of MOSFETs 12U to 12W on the low-potential side.

[0019] The drive circuit 21UU is electrically connected to the gate of MOSFET 11U and outputs a drive signal to its gate. The drive circuit 21VU is electrically connected to the gate of MOSFET 11V and outputs a drive signal to its gate. The drive circuit 21WU is electrically connected to the gate of MOSFET 11W and outputs a drive signal to its gate.

[0020] The drive circuit 21UL is electrically connected to the gate of MOSFET 12U and outputs a drive signal to its gate. The drive circuit 21VL is electrically connected to the gate of MOSFET 12V and outputs a drive signal to its gate. The drive circuit 21WL is electrically connected to the gate of MOSFET 12W and outputs a drive signal to its gate.

[0021] The logic circuit 22 includes logic circuits 22UU, 22VU, and 22WU that control drive circuits 21UU, 21VU, and 21WU that control the gates of MOSFETs 11U to 11W on the high-potential side, and logic circuits 22UL, 22VL, and 22WL that control drive circuits 21UL, 21VL, and 21WL that control the gates of MOSFETs 12U to 12W on the low-potential side.

[0022] Logic circuit 22UU is electrically connected to drive circuit 21UU and outputs a signal to drive circuit 21UU for generating the drive signal that drive circuit 21UU outputs to the gate of MOSFET 11U. Logic circuit 22VU is electrically connected to drive circuit 21VU and outputs a signal to drive circuit 21VU for generating the drive signal that drive circuit 21VU outputs to the gate of MOSFET 11V. Logic circuit 22WU is electrically connected to drive circuit 21WU and outputs a signal to drive circuit 21WU for generating the drive signal that drive circuit 21WU outputs to the gate of MOSFET 11W.

[0023] Logic circuit 22UL is electrically connected to drive circuit 21UL and outputs a signal to drive circuit 21UL for generating the drive signal that drive circuit 21UL outputs to the gate of MOSFET 12U. Logic circuit 22VL is electrically connected to drive circuit 21VL and outputs a signal to drive circuit 21VL for generating the drive signal that drive circuit 21VL outputs to the gate of MOSFET 12V. Logic circuit 22WL is electrically connected to drive circuit 21WL and outputs a signal to drive circuit 21WL for generating the drive signal that drive circuit 21WL outputs to the gate of MOSFET 12W.

[0024] The bootstrap circuit 23 includes a first bootstrap circuit 23U, a second bootstrap circuit 23V, and a third bootstrap circuit 23W. Each of the bootstrap circuits 23U, 23V, and 23W has a common configuration and includes a boot diode and a boot capacitor connected in series.

[0025] The first bootstrap circuit 23U is electrically connected to the source of the MOSFET 11U and to the drive circuit 21UU and the logic circuit 22UU. The first bootstrap circuit 23U generates the drive voltage for the drive circuit 21UU and the logic circuit 22UU.

[0026] The second bootstrap circuit 23V is electrically connected to the source of MOSFET 11V and to the drive circuit 21VU and logic circuit 22VU. The second bootstrap circuit 23V generates the drive voltage for the drive circuit 21VU and logic circuit 22VU.

[0027] The third bootstrap circuit 23W is electrically connected to the source of MOSFET 11W and to the drive circuit 21WU and logic circuit 22WU. The third bootstrap circuit 23W generates the drive voltage for the drive circuit 21WU and logic circuit 22WU.

[0028] In this embodiment, the drive circuits 21UU, 21VU, 21WU and the logic circuits 22UU, 22VU, 22WU are examples of first control circuits that control the first switching element 11. The drive circuits 21UL, 21VL, 21WL and the logic circuits 22UL, 22VL, 22WL are examples of second control circuits that control the second switching element 12. The drive circuit 21UL and the logic circuit 22UL are examples of third control circuits that control the second switching element 12 (MOSFET 12U) of the first inverter circuit. The drive circuit 21VL and the logic circuit 22VL are examples of fourth control circuits that control the second switching element 12 (MOSFET 12V) of the second inverter circuit. The drive circuit 21WL and the logic circuit 22WL are examples of fifth control circuits that control the second switching element 12 (MOSFET 12W) of the third inverter circuit.

[0029] An example of the configuration of the semiconductor device 1 will be described with reference to Figures 2 to 6. The semiconductor device 1 further comprises a lead 30, a heat dissipation member 40, and a sealing resin 50 (shown as a dashed line in Figure 2). The semiconductor device 1 is packaged together by the sealing resin 50 sealing the drive unit 10 and the control circuit 20 (both seen in Figure 1). The semiconductor device 1 is formed in a rectangular shape in plan view. In the following description, the longitudinal direction of the semiconductor device 1 is defined as the first direction X, the direction perpendicular to the first direction X in a plan view of the semiconductor device 1 is defined as the second direction Y, and the direction perpendicular to both the first direction X and the second direction Y is defined as the third direction Z. The third direction Z can also be said to be the thickness direction of the semiconductor device 1.

[0030] As shown in Figure 3, the dimension DX in the first direction X of the semiconductor device 1 (encapsulating resin 50) is preferably 60 mm or less. The dimension DY in the second direction Y of the semiconductor device 1 (encapsulating resin 50) is preferably 35 mm or less. The dimension DZ in the third direction Z of the semiconductor device 1 (encapsulating resin 50) is preferably 6 mm or less. In the semiconductor device 1 of this embodiment, the dimension DX in the first direction X is approximately 57 mm, the dimension DY in the second direction Y is approximately 30 mm, and the dimension DZ in the third direction Z is approximately 5 mm.

[0031] As shown in Figure 3, the sealing resin 50 is formed in a flattened rectangular shape. The sealing resin 50 is made of, for example, black epoxy resin. The sealing resin 50 has a surface 50A, a back surface 50B, a first side surface 50C, a second side surface 50D, a third side surface 50E, and a fourth side surface 50F. The surface 50A and the back surface 50B are planes along the first direction X and the second direction Y, and are substantially rectangular with the first direction X as the longitudinal direction. The first side surface 50C is one side surface of the sealing resin 50 in the first direction X, and the second side surface 50D is the other side surface of the sealing resin 50 in the first direction X. The first side surface 50C and the second side surface 50D are planes along the second direction Y and the third direction Z, and are substantially rectangular with the second direction Y as the longitudinal direction. The third side surface 50E is one side surface of the sealing resin 50 in the second direction Y, and the fourth side surface 50F is the other side surface of the sealing resin 50. The third side surface 50E and the fourth side surface 50F are planes aligned with the first direction X and the third direction Z, and are approximately rectangular with the first direction X being the longitudinal direction. The sealing resin 50 is provided with four first recesses 51 and two second recesses 52. The four first recesses 51 are recessed in the second direction Y from the third side surface 50E and penetrate the sealing resin 50 in the third direction Z. The four first recesses 51 are spaced apart in the first direction X in the portion of the third side surface 50E closer to the first side surface 50C. The second recesses 52 are provided at the center of the first side surface 50C of the sealing resin 50 in the second direction Y and at the center of the second side surface 50D of the sealing resin 50 in the second direction Y. The second recesses 52 are recessed in the first direction X and penetrate the sealing resin 50 in the third direction Z.

[0032] As shown in Figure 4, the heat dissipation member 40 is exposed on the back surface 50B of the sealing resin 50. The heat dissipation member 40 is made of, for example, ceramics. The shape of the exposed surface 40A of the heat dissipation member 40 is a rectangle with the first direction X as the longitudinal direction.

[0033] As shown in Figure 2, the lead 30 is a conductive support member that supports the MOSFETs 11U~11W and MOSFETs 12U~12W and the control circuit 20 (see Figure 1), and constitutes the conductive path for these MOSFETs. The lead 30 is formed, for example, from a metal plate material by cutting and bending processes such as punching. An example of the material for the lead 30 is copper (Cu). The thickness of the lead 30 is, for example, about 0.42 mm.

[0034] The lead 30 has a frame 31, each frame 32U, 32V, 32W, a plurality of control frames 33, a plurality of control frames 34, a frame 35U which is an example of a first ground frame, a frame 35V which is an example of a second ground frame, and a frame 35W which is an example of a third ground frame. In addition, the lead 30 of this embodiment has an auxiliary frame 36 which is not electrically connected to MOSFET 11U and MOSFET 12L, and is a so-called non-connected frame. Frame 31 and each frame 32U, 32V, 32W are arranged side by side with spacing in the first direction X. The plurality of control frames 33 and the plurality of control frames 34 are arranged side by side with spacing in the first direction X. The plurality of control frames 33 and the plurality of control frames 34 are arranged side by side with spacing in the second direction Y from frame 31 and each frame 32U, 32V, 32W. In other words, the plurality of control frames 33 and the plurality of control frames 34 are arranged closer to the third side surface 50E of the sealing resin 50 in the second direction Y. Frames 35U, 35V, and 35W are positioned in the first direction X on the opposite side from frame 31 to each of frames 32U, 32V, and 32W. In the second direction Y, frames 35U, 35V, and 35W are positioned closer to the fourth side 50F of the sealing resin 50. The auxiliary frame 36 is positioned at the end of the first side 50C and on the fourth side 50F of the sealing resin 50. The auxiliary frame 36 has terminal portions protruding from the fourth side 50F.

[0035] Frame 31 is a lead frame for electrically connecting the drains of MOSFETs 11U to 11W to an external power supply, and has an island portion 31a, a terminal portion 31b, and a connecting portion 31c. The island portion 31a, terminal portion 31b, and connecting portion 31c are integrally formed. Island portion 31a is formed in a rectangular shape with the first direction X as the longitudinal direction. MOSFETs 11U to 11W are mounted on island portion 31a. Terminal portion 31b protrudes from the fourth side surface 50F of the sealing resin 50. Connecting portion 31c connects island portion 31a and terminal portion 31b. Connecting portion 31c extends from the end of island portion 31a on the terminal portion 31b side in the second direction Y toward terminal portion 31b. Terminal portion 31b protrudes from the sealing resin 50. The terminal portion 31b is formed in an L-shape, extending from the sealing resin 50 in a second direction Y and then in a third direction Z (see Figure 3). Alternatively, the island portion 31a, the terminal portion 31b, and the connecting portion 31c may be formed individually and joined together to form the frame 31.

[0036] The first frame 32U is a lead frame for electrically connecting the drain of MOSFET 12U to an electrical device (e.g., motor 2) driven by the semiconductor device 1. In this embodiment, the first frame 32U is electrically connected to the U-phase coil (not shown) of the motor 2. The second frame 32V is a lead frame for electrically connecting the drain of MOSFET 12V to an electrical device (e.g., motor 2) driven by the semiconductor device 1. In this embodiment, the second frame 32V is electrically connected to the V-phase coil (not shown) of the motor 2. The third frame 32W is a lead frame for electrically connecting the drain of MOSFET 12W to an electrical device (e.g., motor 2) driven by the semiconductor device 1. In this embodiment, the third frame 32W is electrically connected to the W-phase coil (not shown) of the motor 2. Each frame 32U, 32V, and 32W is formed to have a generally identical shape and has an island portion 32a, a terminal portion 32b, and a connection portion 32c. The island portion 32a, terminal portion 32b, and connection portion 32c are integrally formed. The island portion 32a is formed in a rectangular shape with the second direction Y being the longitudinal direction. The size (width dimension) of the island portion 32a of each frame 32U, 32V, and 32W in the first direction X is about 1 / 3 of the size (width dimension) of the island portion 31a of frame 31 in the first direction X. A MOSFET 12U is mounted on the island portion 32a of the first frame 32U. A MOSFET 12V is mounted on the island portion 32a of the second frame 32V. A MOSFET 12W is mounted on the island portion 32a of the third frame 32W.

[0037] The terminal portions 32b of each frame 32U, 32V, and 32W protrude from the fourth side surface 50F of the sealing resin 50. Each terminal portion 32b is formed in an L-shape, extending from the sealing resin 50 in a second direction Y and then in a third direction Z (see Figure 3).

[0038] The connection portion 32c of the first frame 32U extends from the end of the fourth side surface 50F of the sealing resin 50 in the second direction Y and the end of the frame 31 in the first direction X toward the terminal portion 32b in the island portion 32a of the first frame 32U. A rectangular wire joint portion 32f in plan view is provided on the portion of the connection portion 32c on the fourth side surface 50F of the sealing resin 50, extending in the first direction X. As shown in Figure 2, the connection portions 32c of the second frame 32V and the third frame 32W are similar in shape to the connection portion 32c of the first frame 32U. Alternatively, the island portion 32a, the terminal portion 32b, and the connection portion 32c may be formed individually and joined together to form each of the frames 32U, 32V, and 32W.

[0039] The control frame 33 includes frames 33BU, 33BV, 33BW, frames 33U, 33V, 33W, frame 33C, and frame 33S. Frame 33S is a lead frame for supporting the integrated circuit element 25H. In one example of the integrated circuit element 25H, the high-potential block circuit of the control circuit 20 is integrated into a chip. In this embodiment, the high-potential block circuit of the control circuit 20 includes a first control circuit. That is, the high-potential block circuit includes drive circuits 21UU, 21VU, 21WU and logic circuits 22UU, 22VU, 22WU (see Figure 1 for both). Frame 33S has an island portion 33a, a first arm portion 33b extending from the island portion 33a toward the first side surface 50C of the sealing resin 50 along a first direction X, a second arm portion 33c extending from the end of the first arm portion 33b toward the first side surface 50C of the sealing resin 50 in a second direction Y, and a terminal portion 33d extending from the second arm portion 33c. The island portion 33a, the first arm portion 33b, the second arm portion 33c, and the terminal portion 33d are integrally formed.

[0040] Island portion 33a is formed in the shape of a rectangle with the first direction X being the longitudinal direction. The size of island portion 33a in the second direction Y is larger than the size of the first arm portion 33b in the second direction Y. The size of island portion 33a in the first direction X is smaller than the size of island portion 31a of frame 31 in the first direction X. Island portion 33a is positioned with a gap between it and island portion 31a of frame 31 in the second direction Y. Island portion 33a is located approximately in the center of island portion 31a of frame 31 in the first direction X. More specifically, island portion 33a is positioned such that its center is slightly opposite to the first frame 32U from the center of island portion 31a in the first direction X in the first direction X. Integrated circuit elements 25H are mounted on island portion 33a.

[0041] The first arm portion 33b extends beyond the frame 33BU to the first side surface 50C of the sealing resin 50. The first arm portion 33b is provided with a plurality of recesses 33e along the first direction X. The plurality of recesses 33e in this embodiment are circular in plan view and have a curved bottom in cross-sectional view. The second arm portion 33c is located near the first side surface 50C of the sealing resin 50. More specifically, the second arm portion 33c is located between the second recess 52 closest to the first side surface 50C and the first side surface 50C. The size (width dimension) of the second arm portion 33c in the first direction X is smaller than the size (width dimension) of the first arm portion 33b in the second direction Y. The terminal portion 33d protrudes from the sealing resin 50 in the second direction Y. The size (width dimension) of the terminal portion 33d in the first direction X is equal to the width dimension of the second arm portion 33c. The island portion 33a, the first arm portion 33b, and the second arm portion 33c may be formed individually and joined together to form the frame 33S.

[0042] Frames 33BU, 33BV, 33BW, 33U, 33V, 33W, and 33C are arranged to surround the island portion 33a of frame 33S. Frames 33BU, 33BV, and 33BW are lead frames for electrically connecting the control power supply (not shown) and the bootstrap circuit 23 (see Figure 1). Frames 33U, 33V, and 33W are lead frames for connecting to a gate drive circuit (not shown) located outside the semiconductor device 1. The gate drive device applies a gate signal voltage to frames 33U, 33V, and 33W to generate a drive signal. Frame 33C is a lead frame for supplying power to the integrated circuit element 25H.

[0043] The first boot frame 33BU faces the island portion 33a of frame 33S with a gap in the first direction X, and faces the first arm portion 33b of frame 33S with a gap in the second direction Y. Frame 33BU is positioned on the first side surface 50C of the sealing resin 50 than frames 33BV and 33BW.

[0044] Frames 33BV and 33BW are located on the third side surface 50E of the sealing resin 50, rather than on the island portion 33a of frame 33S. Frame 33BV is positioned opposite the island portion 33a of frame 33S with a gap in the second direction Y, and adjacent to frame 33BU with a gap in the second direction Y. Frame 33BW is positioned opposite the island portion 33a of frame 33S with a gap in the second direction Y, and adjacent to frame 33BV with a gap in the second direction Y. Frame 33BV is located between frame 33BU and frame 33BW in the first direction X.

[0045] Frame 33BU has an island portion 33f and a terminal portion 33g. The island portion 33f and the terminal portion 33g are integrally formed. Frames 33BV and 33BW also each have an island portion 33f and a terminal portion 33g, similar to frame 33BU. The area of ​​the island portion 33f of frame 33BU is larger than the area of ​​the island portion 33f of frame 33BV and the island portion 33f of frame 33BW. The island portion 33f of frame 33BU has a portion that extends from the island portion 33f of frame 33BV toward the first arm portion 33b along the second direction Y. The island portion 33f of frame 33BV and the island portion 33f of frame 33BW are each provided with a notch corresponding to the second recess 52.

[0046] The boot diode 24U of the first bootstrap circuit 23U is mounted on the island portion 33f of frame 33BU by soldering or the like. The boot diode 24U is located on the island portion 33f of frame 33BU, closer to the island portion 33f of frame 33BV. The boot diode 24U is formed from a semiconductor chip. The boot diode 24U has a cathode electrode, which is the front electrode, and an anode electrode, which is the back electrode. Frame 33BU is electrically connected to the anode electrode of the boot diode 24U.

[0047] The boot diode 24V of the second bootstrap circuit 23V is mounted on island portion 33f of frame 33BV by soldering or the like. The boot diode 24V is located on island portion 33f of frame 33BV, closer to island portion 33f of frame 33BU. The boot diode 24V is formed from a semiconductor chip. The boot diode 24V has a cathode electrode, which is the surface electrode, and an anode electrode, which is the back electrode. Frame 33BV is electrically connected to the anode electrode of the boot diode 24V.

[0048] The boot diode 24W of the third bootstrap circuit 23W is mounted on the island portion 33f of frame 33BW by soldering or the like. The boot diode 24W is located on the island portion 33f of frame 33BW at the end opposite to the island portion 33f of frame 33BV in the first direction X. The boot diode 24W is formed from a semiconductor chip. The boot diode 24W is provided with a cathode electrode which is the surface electrode and an anode electrode which is the back electrode. Frame 33BW is electrically connected to the anode electrode of the boot diode 24W.

[0049] The terminal portions 33g of frames 33BU, 33BV, and 33BW protrude from the third side surface 50E of the sealing resin 50. The terminal portions 33g of frames 33BU, 33BV, and 33BW are formed in an L-shape, extending in a second direction Y and then in a third direction Z (see Figure 3). A first recess 51 is located between the terminal portion 33g of frame 33BU and the terminal portion 33g of frame 33BV in a first direction X, and a first recess 51 is located between the terminal portion 33g of frame 33BV and the terminal portion 33g of frame 33BW in a first direction X. In other words, the four first recesses 51 and the terminal portions 33g of frames 33BU, 33BV, and 33BW are arranged alternately in the first direction X.

[0050] Frames 33U, 33V, 33W, and 33C are each formed in a substantially L-shape in a plan view. Frames 33U and 33V are located on the third side surface 50E of the sealing resin 50, further than the island portion 33a of frame 33S, in the second direction Y. Frames 33V, 33W, and 33C are located on the second side surface 50D of the sealing resin 50, further than the island portion 33a of frame 33S, in the first direction X. Parts of frames 33W and 33C face the island portion 33a of frame 33S with a gap in the first direction X. Frame 33U faces the island portion 33a of frame 33S with a gap in the second direction Y, and is also positioned facing frame 33BW with a gap in the first direction X. Frame 33V faces frame 33U with a gap in the first direction X and the second direction Y. Frame 33W faces frame 33V with a gap in the first direction X and the second direction Y. Frame 33C faces frame 33W with a gap in the first direction X and the second direction Y. The size of the gap between frame 33U and frame 33V in the first direction X is equal to the size of the gap between frame 33V and frame 33W. In the first direction X, the size of the gap between frame 33W and frame 33C is greater than the size of the gap between frame 33V and frame 33W.

[0051] In frames 33U, 33V, 33W, and 33C, the terminal portion protruding from the third side surface 50E of the sealing resin 50 is formed in an L-shape, extending from the sealing resin 50 in the second direction Y and then in the third direction Z (see Figure 3).

[0052] The control frame 34 includes frames 34U, 34V, 34W, frame 34CV, frame 34S, and frames 34A, 34B, 34C, 34D. Frame 34S is a lead frame that supports the integrated circuit element 25L and grounds the integrated circuit element 25L. In one example of the integrated circuit element 25L, the low-potential block circuit of the control circuit 20 is integrated into a chip. In this embodiment, the low-potential block circuit of the control circuit 20 includes a second control circuit. That is, the low-potential block circuit includes drive circuits 21UL, 21VL, 21WL and logic circuits 22UL, 22VL, 22WL (see Figure 1 for both). Frame 34S is formed in a substantially T-shape in plan view. More specifically, frame 34S has an island portion 34a, a terminal portion 34b, a connection portion 34c, and an extension portion 34d. The island portion 34a, terminal portion 34b, connection portion 34c, and extension portion 34d are integrally formed.

[0053] Island portion 34a is formed in a rectangular shape with the first direction X being the longitudinal direction. In the first direction X, the central position of island portion 34a is equal to the central position of island portion 32a of the second frame 32V. The size of island portion 34a in the first direction X is larger than the size of island portion 32a in the first direction X. The end of the sealing resin 50 on the second side surface 50D side of island portion 34a faces the end of the sealing resin 50 on the first side surface 50C side of island portion 32a of the third frame 32W in the second direction Y. The end of the sealing resin 50 on the first side surface 50C side of island portion 34a faces the end of the sealing resin 50 on the second side surface 50D side of island portion 32a of the first frame 32U in the second direction Y. Also, the size of island portion 34a in the first direction X is larger than the size of island portion 33a in the first direction X of frame 33S. The size of island portion 34a in the second direction Y is smaller than the size of island portion 33a in the second direction Y.

[0054] An integrated circuit element 25L is mounted on the island portion 34a. The integrated circuit element 25L is positioned on the island portion 34a closer to the island portion 32a of the third frame 32W. More specifically, the integrated circuit element 25L is positioned on the island portion 34a such that its edge in the second direction Y is at the same position in the second direction Y as the edge of the island portion 34a of the third frame 32W on the island portion 34a side. In the first direction X, the central position of the integrated circuit element 25L and the central position of the island portion 34a of the third frame 32W are equal to each other. The size of the integrated circuit element 25L in the first direction X is approximately equal to the size of the integrated circuit element 25H in the first direction X. The size of the integrated circuit element 25L in the second direction Y is smaller than the size of the integrated circuit element 25H in the second direction Y. Multiple recesses 34e are provided on both sides of the integrated circuit element 25L in the first direction X on the island portion 34a. The multiple recesses 34e in this embodiment are circular in plan view and have a curved bottom in cross-sectional view.

[0055] The connecting portion 34c connects the island portion 34a and the terminal portion 34b. The connecting portion 34c extends along the second direction Y from the end of the sealing resin 50 on the first side surface 50C and the end on the third side surface 50E of the island portion 34a. The connecting portion 34c is provided so as to face the frame 33C with a gap in the first direction X. The size of the gap in the first direction X between the connecting portion 34c and the frame 33C is approximately equal to the size of the gap in the first direction X between the frame 33C and the frame 33W. The extension portion 34d extends along the first direction X from the end of the sealing resin 50 on the first side surface 50C and the end on the fourth side surface 50F of the island portion 34a. The tip of the extension portion 34d faces the island portion 33a of the frame 33S with a gap in the first direction X. In the second direction Y, the extension 34d faces the island portion 32a of the first frame 32U and the portion of the island portion 31a of the frame 31 near the second side surface 50D of the sealing resin 50, with a gap between them. In the second direction Y, the extension 34d faces the frame 33C of the control frame 33, with a gap between them. The terminal portion 34b protrudes from the third side surface 50E of the sealing resin 50. The terminal portion 34b is formed in an L-shape, extending in the second direction Y and then extending in the third direction Z (see Figure 3).

[0056] Frames 34U, 34V, 34W, 34CV, and 34A, 34B, 34C, 34D are arranged to surround the island portion 34a of frame 34S. Frames 34U, 34V, 34W, 34CV, and 34A are positioned on the third side surface 50E of the sealing resin 50, rather than on the island portion 34a of frame 34S, in the second direction Y. Frames 34B, 34C, and 34D are positioned on the second side surface 50D of the sealing resin 50, rather than on the island portion 34a of frame 34S, in the first direction X.

[0057] Frames 34U, 34V, and 34W are lead frames for connecting to a gate drive circuit (not shown) located outside the semiconductor device 1. The gate drive device applies gate signal voltages to frames 34U, 34V, and 34W to generate drive signals. Frame 34CV is a lead frame for supplying power to the integrated circuit element 25L. Frame 34A is a lead frame for outputting an abnormality signal when an abnormality occurs in the semiconductor device 1. Frame 34B is a lead frame for detecting a short circuit where at least one of the voltages applied to each of frames 32U, 32V, and 32W is short-circuited to a high-voltage application terminal (or a similarly high-potential terminal). Frame 34C is a lead frame for grounding the integrated circuit element 25L. Frame 34D is a non-connected lead frame.

[0058] The portion (connection portion) within the sealing resin 50 in frame 34U extends along the second direction Y, and its size (width dimension) in the first direction X decreases towards its tip. The portions within the sealing resin 50 in frames 34V, 34W, 34CV, and 34A, 34B are inclined toward the second side surface 50D as they approach the third side surface 50E of the sealing resin 50. The portions within the sealing resin 50 in frames 34V, 34W, 34CV, and 34A, 34C each decrease in size (width dimension) in the first direction X as they approach their tip. Frame 34D is formed in an L-shape consisting of a first portion extending in the first direction X and a second portion extending in the second direction Y. The first portion of frame 34D decreases in size (width dimension) in the second direction Y as it approaches its tip. The first portion of frames 34C and 34D is wider than frames 34U, 34V, 34W, frame 34CV, and frames 34A and 34B. Frames 34C and 34D are each provided with a plurality of recesses 34f. The plurality of recesses 34f in this embodiment have the same shape as the plurality of recesses 34e. That is, the plurality of recesses 34f are circular in plan view and have a curved bottom in cross-sectional view.

[0059] Frames 34U, 34V, 34W, 34CV, and 34A, 34B, 34C, 34D each have terminal portions formed in an L-shape that protrude from the third side surface 50E of the sealing resin 50, extend in the second direction Y, and then extend in the third direction Z. The terminal portions of frames 34U, 34V, 34W, 34CV, and 34A, 34B, 34C, 34D are arranged side by side with gaps between them in the first direction X.

[0060] The ground frames 35U, 35V, and 35W are lead frames for grounding the sources of MOSFETs 12U to 12W. Frames 35U and 35V each have an island section 35a and a terminal section 35b. Frame 35W has an island section 35a, a terminal section 35b, and a connection section 35c. In frames 35U and 35V, the island section 35a and the terminal section 35b are integrally formed. In frame 35W, the island section 35a, the terminal section 35b, and the connection section 35c are integrally formed.

[0061] The island portions 35a of frames 35U and 35V are located near the fourth side surface 50F of the sealing resin 50, i.e., in the second direction Y, at the same position as the wire joint portions 32f of each frame 32U, 32V, and 32W. The island portion 35a of frame 35W is located in the same position as the island portion 32a of the third frame 32W in the first direction X. That is, the island portion 35a of frame 35W is located closer to the third side surface 50E of the sealing resin 50 than the island portions 35a of frames 35U and 35V in the second direction Y. When viewed from the fourth side surface 50F of the sealing resin 50, a portion of the island portion 35a of frame 35W is arranged to overlap with the island portion 35a of frame 35V. The island portions 35a of frames 35U and 35V are located closer to the fourth side surface 50F of the sealing resin 50 than the island portion 32a of the third frame 32W. The island portion 35a of frame 35U is formed in a rectangular shape with the first direction X being the longitudinal direction in a plan view. The island portion 35a of frame 35V is formed in a substantially square shape in a plan view. The size of the island portion 35a of frame 35U in the second direction Y is equal to the size of the island portion 35a of frame 35V in the second direction Y. The size of the island portion 35a of frame 35U in the first direction X is larger than the size of the island portion 35a of frame 35V in the first direction X. The island portion 35a of frame 35W is formed in a rectangular shape with the second direction Y being the longitudinal direction. The size of the island portion 35a of frame 35W in the second direction Y is larger than the size of the island portion 35a of frame 35U in the second direction Y. The area of ​​the island portion 35a of frame 35W is larger than the area of ​​the island portion 35a of frame 35U. The connecting portion 35c extends along the second direction Y from the end of the sealing resin 50 of the island portion 35a on the second side surface 50D side and the end on the fourth side surface 50F side in the first direction X.

[0062] The terminal portions 35b of frames 35U, 35V, and 35W protrude from the fourth side surface 50F of the sealing resin 50. The terminal portion 35b of frame 35U is connected to the end of the island portion 35a of frame 35U on the second side surface 50D side of the sealing resin 50. The terminal portion 35b of frame 35V is connected to the center of the island portion 35a of frame 35V in the first direction X. The terminal portion 35b of frame 35W is connected to the connection portion 35c. Each terminal portion 35b is formed in an L-shape, extending in the second direction Y and then in the third direction Z.

[0063] As shown in Figure 5, the island portion 31a of frame 31 is joined to the heat dissipation member 40. The connection portion 31c of frame 31 is positioned spaced apart from the heat dissipation member 40 in the third direction Z. Frames 33S and 33BW are positioned on the surface 50A side of the sealing resin 50 than the island portion 31a of frame 31. Frames 33S and 33BW are positioned spaced apart from the heat dissipation member 40 in the third direction Z. Although not shown in Figure 5, control frames 33 other than frames 33S and 33BW are also positioned on the surface 50A side of the sealing resin 50 than frame 31, that is, spaced apart from the heat dissipation member 40 in the third direction Z.

[0064] As shown in Figure 6, the island portion 32a of the second frame 32V is joined to the heat dissipation member 40. Figure 6 shows the cross-sectional structure of the second frame 32V and the multiple control frames 33. The connection portion 32c of the second frame 32V is spaced apart from the heat dissipation member 40 in the third direction Z. Frames 34S and 34U are located closer to the surface 50A of the sealing resin 50 than the second frame 32V. Frames 34S and 34U are located closer to the surface 50A of the sealing resin 50 than each of the frames 32U, 32V, and 32W. Although not shown in Figure 6, the island portions 32a of the first frame 32U and the third frame 32W are each joined to the heat dissipation member 40. The connection portions 32c of the first frame 32U and the third frame 32W are each spaced apart from the heat dissipation member 40 in the third direction Z. The control frames 34 other than frames 34S and 34U are positioned on the surface 50A side of the sealing resin 50 than each of the frames 32U, 32V, and 32W, that is, they are spaced apart from the heat dissipation member 40 in the third direction Z.

[0065] Next, the detailed configuration of the frame 31 and the arrangement of the MOSFET 11U will be described with reference to Figures 7 and 8. Frame 31 has an element mounting region Rse formed therein, which is an area where integrated circuit elements such as MOSFETs 11U to 11W can be mounted. The element mounting region Rse is a rectangular area with the first direction X as its longitudinal direction, and is separated from the rest of the island portion 31a by a groove portion 31d. The element mounting region Rse is formed so as to be closer to the control frame 33 side of the island portion 31a in the second direction Y. The element mounting region Rse is further divided into six regions Ra1 to Ra6 by a groove portion 31e. The six regions Ra1 to Ra6 are formed by dividing the element mounting region Rse into three in the first direction X and two in the second direction Y. The three regions Ra1 to Ra3 are areas formed on the control frame 33 side of the element mounting region Rse in the second direction Y. The three regions Ra4 to Ra6 are areas formed on the connection portion 31c side of the element mounting region Rse in the second direction Y. As shown in Figure 7, regions Ra1 and Ra4 are aligned along the second direction Y, regions Ra2 and Ra5 are aligned along the second direction Y, and regions Ra3 and Ra6 are aligned along the second direction Y. Region Ra2 is located between regions Ra1 and Ra3 in the first direction X. Region Ra1 is located closer to the first side surface 50C of the sealing resin 50 than region Ra2, and region Ra3 is located closer to the second side surface 50D of the sealing resin 50 than region Ra2. Regions Ra1 to Ra3 are each rectangular regions with the second direction Y as their longitudinal direction. The sizes of regions Ra1 to Ra3 in the first direction X are equal to each other, and the sizes of regions Ra1 to Ra3 in the second direction Y are equal to each other. Regions Ra4 to Ra6 are each rectangular regions with the second direction Y as their longitudinal direction. The sizes of regions Ra4 to Ra6 in the first direction X are equal to each other, and the sizes of regions Ra4 to Ra6 in the second direction Y are equal to each other. The size of the first direction X in regions Ra1 to Ra3 is equal to the size of the first direction X in regions Ra4 to Ra6. The size of the second direction Y in regions Ra1 to Ra3 is larger than the size of the second direction Y in regions Ra4 to Ra6.

[0066] Region Ra1 has a MOSFET 11U mounted on it. This MOSFET 11U is located closer to the control frame 33 in region Ra1 in the second direction Y. Region Ra2 has a MOSFET 11V mounted on it. This MOSFET 11V is located closer to the control frame 33 in region Ra2 in the second direction Y. Region Ra3 has a MOSFET 11W mounted on it. This MOSFET 11W is located closer to the control frame 33 in region Ra3 in the second direction Y. The positions of MOSFET 11U in the second direction Y, MOSFET 11V in the second direction Y, and MOSFET 11W in the second direction Y are equal to each other. Regions Ra4 to Ra6 can be fitted with semiconductor devices different from MOSFETs 11U to 11W. In this embodiment, no semiconductor devices are fitted to regions Ra4 to Ra6.

[0067] As shown in Figure 7, MOSFETs 11U and 11V are positioned so as to overlap with the integrated circuit element 25H when viewed from the second direction Y. On the other hand, MOSFET 11W is positioned on the second side surface 50D side of the integrated circuit element 25H. Furthermore, MOSFET 11U is positioned so that the end of MOSFET 11U on the first side surface 50C side is closer to the first side surface 50C side than the edge of the integrated circuit element 25H on the first side surface 50C side.

[0068] In the island portion 31a, a plurality of recesses 31f are provided in the portion other than the element mounting area Rse, indented in the third direction Z. The plurality of recesses 31f are arranged in a matrix in the first direction X and the second direction Y. The plurality of recesses 31f in this embodiment are circular in plan view and have a curved bottom in cross-sectional view.

[0069] MOSFETs 11U~11W and MOSFETs 12U~12W use the same MOSFET. The MOSFET 11U is formed from a rectangular semiconductor chip in a plan view. The MOSFET 11U is arranged such that the second direction Y is the longitudinal direction. The size of the MOSFET 11U in the first direction X is smaller than the size of the region Ra1 in the first direction X. A source electrode pad 11s and a gate electrode pad 11g are provided on the surface of the MOSFET 11U, and a drain electrode pad 11d (see Figure 8) is provided on the back surface of the MOSFET 11U. As a result, the frame 31 is electrically connected to the drain of the MOSFET 11U. The solder SD (see Figure 8) used to join the MOSFET 11U and the island portion 31a joins the MOSFET 11U and the island portion 31a by hardening after being in a molten state. As can be seen from Figure 7, the solder SD slightly protrudes around the MOSFET 11U. The source electrode pad 11s, drain electrode pad 11d, and gate electrode pad 11g of the MOSFET 11U are made of, for example, aluminum (Al) or an aluminum alloy. Examples of aluminum alloys include Al-Cu and Al-Si-Cu. The shape, size, and structure of MOSFETs 11V and 11W, as well as the connection structure to the island portion 31a, are the same as those of MOSFET 11U.

[0070] The source electrode pad 11s of the MOSFET 11U occupies most of the surface of the MOSFET 11U. The gate electrode pad 11g of the MOSFET 11U is located at one of the four corners of the surface of the MOSFET 11U, on the first side surface 50C side of the sealing resin 50 in the first direction X and on the control frame 33 side in the second direction Y. The source electrode pad 11s of the MOSFET 11U has a notch formed to avoid the gate electrode pad 11g. The gate electrode pad 11g of the MOSFET 11U is formed in a rectangular shape with the second direction Y being the longitudinal direction.

[0071] As shown in Figure 8, the island portion 31a of the frame 31 and the heat dissipation member 40 are joined by adhesive AH. The adhesive AH is applied to the entire surface of the island portion 31a facing the heat dissipation member 40. That is, the entire surface of the island portion 31a facing the heat dissipation member 40 and the heat dissipation member 40 are in contact via the adhesive AH. The adhesive AH is preferably one that appropriately joins the heat dissipation member 40, which is made of ceramics, and the island portion 31a, which is made of copper (Cu), and also has relatively good thermal conductivity. For example, a resin adhesive with excellent thermal conductivity is used.

[0072] Next, with reference to Figures 9 and 10, the detailed configuration of each frame 32U, 32V, and 32W, and the arrangement of MOSFETs 12U to 12W will be described. The island portions 32a of the first frame 32U, the second frame 32V, and the third frame 32W differ in the shape of their ends on the connection portion 32c side in the second direction Y. The island portion 32a of the first frame 32U has a notch 32d to prevent interference with the connection portion 32c of the second frame 32V. The island portion 32a of the second frame 32V has a notch 32e to prevent interference with the connection portion 32c of the third frame 32W. On the other hand, the island portion 32a of the third frame 32W does not have a notch.

[0073] Each frame 32U, 32V, and 32W has an element mounting region Rse formed therein, similar to frame 31. The element mounting regions Rse of each frame 32U, 32V, and 32W are all the same shape. The element mounting region Rse is a rectangular region with the second direction Y as the longitudinal direction. The size of the element mounting region Rse in the second direction Y of each frame 32U, 32V, and 32W is equal to the size of the element mounting region Rse in the second direction Y of frame 31. The size of the element mounting region Rse in the first direction X of each frame 32U, 32V, and 32W is approximately 1 / 3 the size of the element mounting region Rse in the first direction X of frame 31. In other words, the size of the element mounting region Rse in the first direction X of each frame 32U, 32V, and 32W is equal to the size of the element mounting region Rse in the first direction X of frame 31.

[0074] Each frame 32U, 32V, and 32W is separated from the element mounting area Rse and the rest of the island portion 32a by a groove 32g. The element mounting area Rse is further divided into six regions Ra7 and Ra8 by grooves 32h. Regions Ra7 and Ra8 are arranged in a parallel direction Y. Region Ra7 is a region formed on the control frame 34 side of the element mounting area Rse in the second direction Y. Region Ra7 is a rectangular region with the second direction Y as its longitudinal direction. The size of region Ra7 is equal to the size of regions Ra1 to Ra3 of the element mounting area Rse of frame 31. The size of region Ra8 is equal to the size of regions Ra4 to Ra6 of the element mounting area Rse of frame 31. In other words, the area of ​​region Ra7 is larger than the area of ​​region Ra8, and the size of region Ra7 in the second direction Y is larger than the size of region Ra8 in the second direction Y.

[0075] MOSFET12U is mounted in region Ra7 of the first frame 32U. This MOSFET12U is located closer to the control frame 34 in region Ra7 of the first frame 32U in the second direction Y. MOSFET12V is mounted in region Ra7 of the second frame 32V. This MOSFET12V is located closer to the control frame 34 in region Ra7 of the second frame 32V in the second direction Y. MOSFET12W is mounted in region Ra7 of the third frame 32W. This MOSFET12W is located closer to the control frame 34 in region Ra7 of the third frame 32W in the second direction Y. The positions of MOSFET12U in the second direction Y, MOSFET12V in the second direction Y, and MOSFET12W in the second direction Y are equal to each other.

[0076] The Ra8 region of each frame 32U, 32V, and 32W can accommodate semiconductor devices different from those in MOSFETs 12U to 12W. In this embodiment, no semiconductor devices are mounted in the Ra8 region of each frame 32U, 32V, and 32W.

[0077] In the island portion 32a, a plurality of recesses 32i are provided in the portion other than the element mounting area Rse, that is, in the portion of the island portion 32a surrounding the element mounting area Rse. The plurality of recesses 32i in this embodiment have the same shape as the recess 31f, are circular in plan view, and have a curved bottom in cross-sectional view.

[0078] MOSFET12U is formed from a rectangular semiconductor chip in a plan view. MOSFET12U is arranged such that the second direction Y is the longitudinal direction. As mentioned above, since MOSFET12U uses the same semiconductor chip as MOSFET11U, the sizes of the first direction X and second direction Y of MOSFET12U are equal to the sizes of the first direction X and second direction Y of MOSFET11U~11W. In other words, the size of the first direction X of MOSFET12U is smaller than the size of the first direction X of each region Ra7. A source electrode pad 12s and a gate electrode pad 12g are provided on the surface of MOSFET12U, and a drain electrode pad 12d (see Figure 10) is provided on the back surface of MOSFET12U. Thus, the first frame 32U is electrically connected to the drain of the MOSFET12U mounted on the first frame 32U. The solder SD (see Figure 10) used to join the island portion 32a of the first frame 32U to the MOSFET12U joins the MOSFET12U and the island portion 32a by hardening after being in a molten state.

[0079] The second frame 32V is electrically connected to the drain of MOSFET 12V mounted on the second frame 32V. The third frame 32W is electrically connected to the drain of MOSFET 12W mounted on the third frame 32W. The junction structure between MOSFETs 12V and 12W and the island portion 32a of each frame 32V and 32W is the same as the junction structure between MOSFET 12U and the island portion 32a of the first frame 32U.

[0080] The shape of the source electrode pad 12s of MOSFETs 12U to 12W is the same as the shape of the source electrode pad 11s of MOSFET 11U, and the shape of the gate electrode pad 12g of MOSFETs 12U to 12W is the same as the shape of the gate electrode pad 11g of MOSFET 11U. The source electrode pad 12s and gate electrode pad 12g of MOSFETs 12U to 12W are made of, for example, gold (Au). The drain electrode pad 12d of MOSFETs 12U to 12W is made of, for example, gold (Au) or silver (Ag).

[0081] As shown in Figure 10, the island portions 32a of each frame 32U, 32V, and 32W and the heat dissipation member 40 are joined by an adhesive AH. The adhesive AH is applied to the entire surface of the island portion 32a of each frame 32U, 32V, and 32W that faces the heat dissipation member 40. In other words, the entire surface of the island portion 32a of each frame 32U, 32V, and 32W that faces the heat dissipation member 40 and the heat dissipation member 40 are in contact via the adhesive AH. The adhesive AH is preferably one that appropriately joins the heat dissipation member 40, which is made of ceramics, and the island portions 32a of each frame 32U, 32V, and 32W, which are made of copper (Cu), and also has relatively good thermal conductivity. For example, a resin adhesive with excellent thermal conductivity is used.

[0082] As shown in Figure 2, the lead 30, MOSFETs 11U~11W and MOSFETs 12U~12W, and integrated circuit elements 25H and 25L are electrically connected to each other by wire bonding. More specifically, the semiconductor device 1 has high-potential power wires connecting the lead 30 and MOSFETs 11U~11W, respectively. These high-potential power wires include a first wire 60U, an example of a first power wire; a second wire 60V, an example of a second power wire; and a third wire 60W, an example of a third power wire. The semiconductor device 1 also has low-potential power wires connecting the lead 30 and MOSFETs 12U~12W, respectively. These low-potential power wires include a first wire 61U, an example of a fourth power wire; a second wire 61V, an example of a fifth power wire; and a third wire 61W, an example of a sixth power wire. The semiconductor device 1 also has a plurality of wires 62 connecting the integrated circuit element 25H to the MOSFETs 11U to 11W, and a plurality of wires 62 connecting the integrated circuit elements 25H and 25L to a plurality of control frames 33 and 34. In this embodiment, each wire 60U, 60V, and 60W is connected to the lead 30 and the MOSFETs 11U to 11W by wedge bonding. Each wire 61U, 61V, and 61W is connected to the lead 30 and the MOSFETs 12U to 12W by wedge bonding. In this embodiment, a plurality of wires 62 connect the integrated circuit elements 25H and 25L to a plurality of control frames 33 and 34 by ball bonding. The semiconductor device 1 also has a first wire 62U, a second wire 62V, and a third wire 62W, which are examples of control wires connecting the MOSFETs 12U to 12W to the integrated circuit element 25L, and a first wire 63U, a second wire 63V, and a third wire 63W, which are examples of limiting wires. As shown in Figure 9, each wire 63U, 63V, and 63W is provided separately from each wire 62U, 62V, and 62W. In this embodiment, each wire 62U, 62V, and 62W and each wire 63U, 63V, and 63W connect the integrated circuit element 25L and the MOSFETs 12U to 12W by ball bonding.

[0083] Each wire 60U, 60V, 60W, 61U, 61V, and 61W is made of, for example, aluminum (Al), and each wire 62, 62U, 62V, and 62W, and each wire 63U, 63V, and 63W are made of, for example, gold (Au). The wire diameters of each wire 60U, 60V, 60W, 61U, 61V, and 61W are equal to each other. The wire diameters of each wire 62, 62U, 62V, and 62W are equal to each other. The wire diameters of each wire 63U, 63V, and 63W are equal to each other. The wire diameters of each wire 62, 62U, 62V, and 62W, and the wire diameters of each wire 63U, 63V, and 63W are equal to each other. The wire diameters of wires 60U, 60V, 60W, 61U, 61V, and 61W are larger than those of wires 62, 62U, 62V, and 62W, and wires 63U, 63V, and 63W. The wire diameters of wires 60U, 60V, 60W, 61U, 61V, and 61W are approximately 10 times larger than those of wires 62, 62U, 62V, and 62W, and wires 63U, 63V, and 63W. An example of the wire diameter for wires 60U, 60V, 60W, 61U, 61V, and 61W is 400 μm. An example of the wire diameter for wires 62, 62U, 62V, and 62W, and wires 63U, 63V, and 63W, is 38 μm.

[0084] One first wire 60U connects the source electrode pad 11s of MOSFET 11U to the wire junction 32f of the first frame 32U. One second wire 60V connects the source electrode pad 11s of MOSFET 11V to the wire junction 32f of the second frame 32V. One third wire 60W connects the source electrode pad 11s of MOSFET 11W to the wire junction 32f of the third frame 32W. These wires 60U, 60V, and 60W are generally parallel to each other. The first wire 60U passes through region Ra5 of the device mounting region Rse and connects to the wire junction 32f of the first frame 32U. The second wire 60V passes through region Ra6 of the device mounting region Rse and the connection part 32c of the first frame 32U and connects to the wire junction 32f of the second frame 32V. The third wire 60W passes through the connection point 32c between the element mounting area Rse of the first frame 32U and the second frame 32V, and is connected to the wire junction 32f of the third frame 32W.

[0085] Each source electrode pad 11s of MOSFETs 11U to 11W is connected to the integrated circuit element 25H by a single wire 62. Each gate electrode pad 11g of MOSFETs 11U to 11W is connected to the integrated circuit element 25H by a single wire 62.

[0086] As shown in Figure 7, the connection portion of the first wire 60U to the source electrode pad 11s of the MOSFET 11U is thicker than the rest of the first wire 60U. This connection portion is located on the integrated circuit element 25H side of the edge of the gate electrode pad 11g of the MOSFET 11U that is on the source electrode pad 11s side, in the second direction Y. That is, the connection portion of the first wire 60U to the source electrode pad 11s of the MOSFET 11U is located so as to overlap with the gate electrode pad 11g of the MOSFET 11U when viewed from the first direction X, and extends to straddle one edge of the gate electrode pad 11g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of the MOSFET 11U in the first direction X.

[0087] The connection portion of the second wire 60V to the source electrode pad 11s of MOSFET 11V is thicker than the rest of the second wire 60V. This connection portion is located on the integrated circuit element 25H side of the edge of the gate electrode pad 11g of MOSFET 11V on the source electrode pad 11s side in the second direction Y. That is, the connection portion of the second wire 60V to the source electrode pad 11s of MOSFET 11V is located so as to overlap with the gate electrode pad 11g of MOSFET 11V when viewed from the first direction X, and extends to straddle one edge of the gate electrode pad 11g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of MOSFET 11V in the first direction X.

[0088] The connection portion of the third wire 60W to the source electrode pad 11s of MOSFET 11W is thicker than the rest of the third wire 60W. This connection portion is located on the integrated circuit element 25H side of the gate electrode pad 11g of MOSFET 11W on the source electrode pad 11s side in the second direction Y. That is, the connection portion of the third wire 60W to the source electrode pad 11s of MOSFET 11W is located so as to overlap with the gate electrode pad 11g of MOSFET 11W when viewed from the first direction X, and extends across one end edge of the gate electrode pad 11g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of MOSFET 11W in the first direction X.

[0089] The integrated circuit element 25H is connected to frames 33BU, 33BV, and 33BW, and to each of the boot diodes 24U, 24V, and 24W, by wires 62. More specifically, the integrated circuit element 25H is connected to the island portion 33f of frames 33BU, 33BV, and 33BW by two wires 62 each. The integrated circuit element 25H is connected to the cathode electrodes of frames 33BU, 33BV, and 33BW by one wire 62 each.

[0090] The integrated circuit element 25H is connected to frames 33U, 33V, and 33W by one wire 62 each. The integrated circuit element 25H is connected to frame 33C by three wires 62. The integrated circuit element 25H is connected to the extension 34d in frame 34S of the control frame 34 by two wires 62.

[0091] As shown in Figure 2, one first wire 61U connects the source electrode pad 12s of MOSFET 12U to frame 35U. One second wire 61V connects the source electrode pad 12s of MOSFET 12V to frame 35V. One third wire 61W connects the source electrode pad 12s of MOSFET 12W to frame 35W. These wires 61U, 61V, and 61W are generally parallel to each other. The first wire 61U is connected to frame 35U by passing through region Ra8 of the element mounting region Rse of the second frame 32V and the connection part 32c of the third frame 32W. The second wire 61V is connected to frame 35V by passing through region Ra8 of the element mounting region Rse of the third frame 32W to region Ra7. The third wire 61W is connected to frame 35W by passing through region Ra7 of the element mounting region Rse of the third frame 32W, rather than region Ra8.

[0092] As shown in Figure 9, the connection portion of the first wire 61U to the source electrode pad 12s of the MOSFET 12U is thicker than the rest of the first wire 61U. This connection portion is located on the integrated circuit element 25H side of the edge of the gate electrode pad 12g of the MOSFET 12U that is on the source electrode pad 12s side, in the second direction Y. That is, the connection portion of the first wire 61U to the source electrode pad 12s of the MOSFET 12U is located so as to overlap with the gate electrode pad 12g of the MOSFET 12U when viewed from the first direction X, and extends to straddle one edge of the gate electrode pad 12g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of the MOSFET 12U in the first direction X.

[0093] The connection portion of the second wire 61V to the source electrode pad 12s of MOSFET 12V is thicker than the rest of the second wire 60V. This connection portion is located on the integrated circuit element 25H side of the gate electrode pad 12g of MOSFET 12V on the source electrode pad 12s side in the second direction Y. That is, the connection portion of the second wire 61V to the source electrode pad 12s of MOSFET 12V is located so as to overlap with the gate electrode pad 12g of MOSFET 12V when viewed from the first direction X, and extends across one end edge of the gate electrode pad 12g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of MOSFET 12V in the first direction X.

[0094] The connection portion of the third wire 61W to the source electrode pad 12s of MOSFET 12W is thicker than the rest of the third wire 61W. This connection portion is located on the integrated circuit element 25H side of the edge of the gate electrode pad 12g of MOSFET 12W on the source electrode pad 12s side in the second direction Y. That is, the connection portion of the third wire 61W to the source electrode pad 12s of MOSFET 12W is located so as to overlap with the gate electrode pad 12g of MOSFET 12W when viewed from the first direction X, and extends to straddle one edge of the gate electrode pad 12g in the second direction Y. Furthermore, this connection portion is located on the second side surface 50D side of the center line (dotted line) indicating the center of MOSFET 12W in the first direction X.

[0095] One example of a first control wire, wire 62U, connects the gate electrode pad 12g of MOSFET 12U mounted on the first frame 32U to the integrated circuit element 25L. One example of a second control wire, wire 62V, connects the gate electrode pad 12g of MOSFET 12V mounted on the second frame 32V to the integrated circuit element 25L. One example of a third control wire, wire 62W, connects the gate electrode pad 12g of MOSFET 12W mounted on the third frame 32W to the integrated circuit element 25L. One end of each of these wires 62U, 62V, and 62W is connected to the end of the integrated circuit element 25L on the MOSFET 12U~12W side, respectively. Note that the number of each wire 62U, 62V, and 63W is not limited to one, but may be multiple.

[0096] One example of a first limiting wire, wire 63U, connects the source electrode pad 12s of a MOSFET 12U mounted on the first frame 32U to the integrated circuit element 25L. One example of a second limiting wire, wire 63V, connects the source electrode pad 12s of a MOSFET 12V mounted on the second frame 32V to the integrated circuit element 25L. One example of a third limiting wire, wire 63W, connects the source electrode pad 12s of a MOSFET 12W mounted on the third frame 32W to the integrated circuit element 25L. One end of each of these wires 63U, 63V, and 63W is connected to the end of the integrated circuit element 25L on the MOSFET 12U~12W side, respectively. Note that the number of each wire 63U, 63V, and 63W is not limited to one, but may be multiple.

[0097] In the first direction X, the first wire 63U is positioned adjacent to the first wire 62U, the second wire 63V is positioned adjacent to the second wire 62V, and the third wire 63W is positioned adjacent to the third wire 62W. More specifically, the first wire 62U is positioned closer to the second frame 32V than the first wire 63U. The first wire 62U and the first wire 63U are each connected to the corners of the integrated circuit element 25L that are on the first frame 32U side. The second wire 63V is positioned closer to the third frame 32W than the second wire 62V. The second wire 62V and the second wire 63V are each connected to the portion of the integrated circuit element 25L that is closer to the third frame 32W than the center in the first direction X. The third wire 62W is positioned closer to the second frame 32V than the third wire 63W. One end of each of the third wire 62W and the third wire 63W is connected to a portion of the wire 62 connected to the frame 34D in the integrated circuit element 25L that is on the second frame 32V side of the connection point with the integrated circuit element 25L.

[0098] The integrated circuit element 25L is connected to frames 34U, 34V, and 34W by one wire 62 each. The integrated circuit element 25L is connected to frame 34CV by two wires 62 each. The integrated circuit element 25L is connected to frames 34A, 34B, and 34D by one wire 62 each. The integrated circuit element 25L is connected to frame 34C by two wires 62 each. One end of the wire 62 connected to frame 34D is connected to the end of the integrated circuit element 25L on the frame 34D side in the second direction Y.

[0099] [MOSFET structure] Referring to Figure 11, the detailed structures of MOSFETs 11U-11W and MOSFETs 12U-12W will be described. Since MOSFETs 11U-11W and MOSFETs 12U-12W have the same structure, the structure of MOSFET 11U will be described below, and the explanations for MOSFETs 11V, 11W, and MOSFETs 12U-12W will be omitted.

[0100] MOSFET11U comprises a SiC (silicon carbide) substrate 70. The SiC substrate 70 contains a high concentration of N-type impurities (e.g., 1e18~1e21 cm³). -3 It is doped with ). The SiC substrate 70 has a Si surface 70A (top surface) and a C surface 70B (bottom surface).

[0101] The surface 70A of the SiC substrate 70 is made of SiC doped with a lower concentration of N-type impurities than the SiC substrate 70, N - Multiple epitaxial layers 71 are stacked. The epitaxial layers 71 are formed on the SiC substrate 70 by so-called epitaxial growth. The epitaxial layers 71 formed on the Si surface 70A are grown with the Si surface as the main growth surface. Therefore, the surface 71A of the epitaxial layer 71 formed by growth is a Si surface, just like the surface 70A of the SiC substrate 70.

[0102] In the epitaxial layer 71, the portion on the C-side (base layer) opposite to the Si-side portion (surface layer) remains entirely in the same state as after epitaxial growth. - This forms a drain region 72 of type N. The concentration of N-type impurities in the drain region 72 is, for example, 1e15 to 1e17 cm³. -3 That is the case.

[0103] On the other hand, a P-type body region 73 is formed on the surface of the epitaxial layer 71. The body region 73 is in contact with the drain region 72 from the surface 71A side (Si side) of the epitaxial layer 71. The P-type impurity concentration in the body region 73 is, for example, 1e16 to 1e19 cm³. -3 That is the case.

[0104] In the epitaxial layer 71, gate trenches 74 are formed, excavated from the surface 71A. Although not shown in Figure 11, multiple gate trenches 74 are formed at regular intervals, and they run parallel to each other in the same direction (the direction perpendicular to the plane of the paper in Figure 11; hereafter, this direction may be referred to as the "direction along the gate width"), forming, for example, a stripe structure.

[0105] Each gate trench 74 faces each other at a distance from one another and has a pair of side surfaces 74a on a plane perpendicular to the surface 71A, and a bottom surface 74b having a portion parallel to the surface 71A. The gate trench 74 penetrates the body region 73 in the layer thickness direction, and its deepest part (bottom surface 74b) reaches the drain region 72.

[0106] A gate insulating film 75 is formed on the inner surface of the gate trench 74 and the surface 71A of the epitaxial layer 71, covering the entire inner surface (side surface 74a and bottom surface 74b) of the gate trench 74. The gate insulating film 75 consists of an oxide film containing nitrogen (Ni), for example, a silicon nitride oxide film formed by thermal oxidation using a nitrogen-containing gas. The nitrogen content (nitrogen concentration) in the gate insulating film 75 is, for example, 0.1 to 10%.

[0107] The gate insulating film 75 has a thickness T2 on the bottom surface 74b of the gate trench 74 (insulating film bottom portion 75a) that is smaller than the thickness T1 on the side surface 74a (insulating film side portion 75b). Specifically, the ratio of the thickness T2 of the insulating film bottom portion 75a to the thickness T1 of the insulating film side portion 75b (insulating film bottom portion 75a thickness T2 / insulating film side portion 75b thickness T1) is 0.3 to 1.0, preferably 0.5 to 1.0. The thickness T1 of the insulating film side portion 75b is, for example, 300 to 1000 Å, and the thickness T2 of the insulating film bottom portion 75a is, for example, 150 to 500 Å.

[0108] A gate electrode 76 is embedded within the gate insulating film 75. The gate electrode 76 is formed by filling the inside of the gate insulating film 75 with a polysilicon material doped with a high concentration of N-type impurities.

[0109] On the surface layer portion of the body region 73, on both sides in the direction orthogonal to the gate width with respect to the gate trench 74 (the left - right direction in FIG. 11), N + type source regions 77 are formed. The source region 77 is a region with a higher N - type impurity concentration than the N - type impurity concentration of the drain region 72 and is doped with a high concentration of N - type impurities. The N - type impurity concentration of the source region 77 is, for example, 1e18~1e21 cm -3 . The source region 77 extends in the direction along the gate width at a position adjacent to the gate trench 74.

[0110] Also, in the epitaxial layer 71, a P + type body contact region 78 is formed which penetrates the central portion of the source region 77 in the direction orthogonal to the gate width from its surface 71A and is connected to the body region 73. The body contact region 78 is a region with a higher P - type impurity concentration than the P - type impurity concentration of the body region 73 and is doped with a high concentration of P - type impurities. The P - type impurity concentration of the body contact region 78 is, for example, 1e18~1e21 cm -3 .

[0111] That is, the gate trench 74 and the source regions 77 are alternately provided in the direction orthogonal to the gate width and each extends in the direction along the gate width. And on the source region 77, a boundary between adjacent unit cells is set in the direction orthogonal to the gate width along the source region 77. The body contact region 78 is provided with at least one or more across two adjacent unit cells in the direction orthogonal to the gate width. Also, the boundary between adjacent unit cells in the direction along the gate width is set so that the gate electrodes 76 included in each unit cell have a constant gate width.

[0112] On the epitaxial layer 71, an interlayer insulating film 79 made of silicon oxide (SiO2) is laminated. In the interlayer insulating film 79 and the gate insulating film 75, contact holes 80 exposing the surfaces of the source region 77 and the body contact region 78 are formed.

[0113] Source wiring 81 is formed on the interlayer insulating film 79. The source wiring 81 is in contact (electrically connected) with the source region 77 and the body contact region 78 via contact holes 80. The source wiring 81 has a polysilicon layer 82 at the contact portion with the source region 77 and the body contact region 78, and a metal layer 83 is formed on the polysilicon layer 82.

[0114] The polysilicon layer 82 is a doped layer formed using doped polysilicon with impurities, for example, 1e19~1e21 cm². -3 It is preferable that the polysilicon layer is a highly doped layer in which impurities are doped at a high concentration. When forming the polysilicon layer 82 as a doped layer (including a highly doped layer), N-type impurities such as phosphorus (P) and arsenic (As), and P-type impurities such as boron (B) can be used as impurities. Furthermore, the polysilicon layer 82 fills the contact holes 80. The thickness of such a polysilicon layer 82 varies depending on the depth of the contact holes 80, but is for example 5000 to 1000 Å.

[0115] The metal layer 83 is formed using, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), or alloys thereof, or metal materials containing them. The metal layer 83 forms the outermost layer of the source wiring 81, and is bonded to, for example, the first wire 60U. The thickness of the metal layer 83 is, for example, 1 to 5 μm.

[0116] In the source wiring 81, an intermediate layer 84 containing titanium (Ti) is interposed between the polysilicon layer 82 and the metal layer 83. The intermediate layer 84 consists of a single layer of titanium-containing material or multiple layers having such layers. The titanium-containing layer can be formed using titanium, titanium nitride (TiN), or the like. The thickness of the intermediate layer 84 is, for example, 200 to 500 nm.

[0117] The source wiring 81 having such a polysilicon layer 82, an intermediate layer 84, and a metal layer 83 preferably has a laminated structure (Po-Si / Ti / TiN / Al) in which polysilicon (polysilicon layer 82), titanium (intermediate layer 84), titanium nitride (intermediate layer 84), and aluminum (metal layer 83) are stacked in that order.

[0118] A drain wiring 85 is formed on the back surface 70B of the SiC substrate 70. The drain wiring 85 is in contact (electrically connected) with the SiC substrate 70. The drain wiring 85 has a polysilicon layer 86 at the contact portion with the SiC substrate 70, and a metal layer 87 on the polysilicon layer 86.

[0119] The polysilicon layer 86 can be formed using the same material as that which constitutes the polysilicon layer 82. The thickness of the polysilicon layer 86 is, for example, 1000 to 2000 Å.

[0120] The metal layer 87 can be formed using the same material as that used to make up the metal layer 83. The metal layer 87 forms the outermost layer of the drain wiring 85 and is bonded to the island portion 31a, for example, when the SiC substrate 70 is mounted on the island portion 31a of the frame 31. The thickness of the metal layer 87 is, for example, 0.5 to 1 μm.

[0121] In the drain wiring 85, an intermediate layer 88 containing titanium (Ti) is interposed between the polysilicon layer 86 and the metal layer 87. The intermediate layer 88 can be formed using the same material as that which constitutes the intermediate layer 84.

[0122] The gate electrode 76 is in contact (electrically connected) with the gate wiring 89 through a contact hole (not shown) formed in the interlayer insulating film 79. When a predetermined potential difference is generated between the source wiring 81 and the drain wiring 85 (source-drain), a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) is applied to the gate wiring 89, causing a channel to form near the interface between the gate insulating film 75 and the body region 73 due to the electric field from the gate electrode 76. As a result, current flows between the source wiring 81 and the drain wiring 85, and the MOSFET 11U turns on.

[0123] [Configuration of the low-potential block circuit] Referring to Figure 12, the circuit configuration of the low-potential block circuit in the control circuit 20 will be described. Figure 12 is an example of the circuit configuration of the low-potential block circuit.

[0124] As shown in Figure 12, the integrated circuit element 25L has a first output terminal 25au, a second output terminal 25av, a third output terminal 25aw, a first input terminal 25bu, a second input terminal 25bv, and a third input terminal 25bw. The first output terminal 25au and the first input terminal 25bu are electrically connected to the control circuit 20 (specifically, the drive circuit 21UL of the control circuit 20). The second output terminal 25av and the second input terminal 25bv are electrically connected to the control circuit 20 (specifically, the drive circuit 21VL of the control circuit 20). The third output terminal 25aw and the third input terminal 25bw are electrically connected to the control circuit 20 (specifically, the drive circuit 21WL of the control circuit 20).

[0125] The first output terminal 25au is connected to the gate of MOSFET 12U via the first wire 62U. The first input terminal 25bu is connected to the source of MOSFET 12U via the first wire 63U. The second output terminal 25av is connected to the gate of MOSFET 12V via the second wire 62V. The second input terminal 25bv is connected to the source of MOSFET 12V via the second wire 63V. The third output terminal 25aw is connected to the gate of MOSFET 12W via the third wire 62W. The third input terminal 25bw is connected to the source of MOSFET 12W via the third wire 63W.

[0126] The drive circuit 21UL has a common-source circuit 21a which serves as the output stage. The common-source circuit 21a has a first MOSFET 21b which is a P-channel MOSFET and a second MOSFET 21c which is an N-channel MOSFET. The source of the first MOSFET 21b is electrically connected to the power supply voltage terminal (frame 34CV), and the drain of the first MOSFET 21b is connected to the drain of the second MOSFET 21c. The gates of the first MOSFET 21b and the second MOSFET 21c are connected in common. The drive circuit 21UL has an output wire 21d that connects node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to the first output terminal 25au of the integrated circuit element 25L, and a limiting wire 21e that connects the source of the second MOSFET 21c of the common-source circuit 21a to the first input terminal 25bu of the integrated circuit element 25L. The output wire 21d and the limiting wire 21e are each provided within the integrated circuit element 25L. More specifically, the output wiring 21d and limiting wiring 21e are located in the second direction Y, on the side of the first output terminal 25au and first input terminal 25bu relative to the source-grounded circuit 21a. The second MOSFET 21c of the source-grounded circuit 21a in the drive circuit 21UL is electrically connected to the source of MOSFET 12U via the limiting wiring 21e, the first input terminal 25bu, and the first wire 63U.

[0127] The configurations of drive circuits 21VL and 21WL are the same as those of drive circuit 21UL. The output wiring 21d of drive circuit 21VL connects node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to the second output terminal 25av of the integrated circuit element 25L. The limiting wiring 21e of drive circuit 21VL connects the source of the second MOSFET 21c of the source-grounded circuit 21a to the second input terminal 25bv of the integrated circuit element 25L. In drive circuit 21VL, the second MOSFET 21c of the source-grounded circuit 21a is electrically connected to the source of MOSFET 12V via the limiting wiring 21e, the second input terminal 25bv, and the second wire 63V. The output wiring 21d of drive circuit 21WL connects node N1 between the drain of the first MOSFET 21b and the drain of the second MOSFET 21c to the third output terminal 25aw of the integrated circuit element 25L. The limiting wire 21e of the drive circuit 21WL connects the source of the second MOSFET 21c of the source-grounded circuit 21a to the third input terminal 25bw of the integrated circuit element 25L. In the drive circuit 21WL, the second MOSFET 21c of the source-grounded circuit 21a is electrically connected to the source of MOSFET 12V via the limiting wire 21e, the third input terminal 25bw, and the third wire 63W.

[0128] Thus, the semiconductor device 1 has a first control path RC1 that electrically connects the drive circuit 21UL and the gate (control terminal) of MOSFET 12U, a second control path RC2 that electrically connects the drive circuit 21VL and the gate (control terminal) of MOSFET 12V, and a third control path RC3 that electrically connects the drive circuit 21WL and the gate (control terminal) of MOSFET 12W.

[0129] The first control path RC1 transmits the drive signal from the drive circuit 21UL to the gate of the MOSFET 12U. The first control path RC1 includes the output wiring 21d of the drive circuit 21UL and the first wire 62U. In other words, the first wire 62U constitutes a part of the first control path RC1.

[0130] The second control path RC2 transmits the drive signal from the drive circuit 21VL to the gate of the MOSFET 12V. The second control path RC2 has the output wiring 21d of the drive circuit 21VL and the second wire 62V. In other words, the second wire 62V constitutes a part of the second control path RC2.

[0131] The third control path RC3 transmits the drive signal from the drive circuit 21WL to the gate of the MOSFET 12W. The third control path RC3 has the output wiring 21d of the drive circuit 21WL and the third wire 62W. In other words, the third wire 62W constitutes a part of the third control path RC3.

[0132] Furthermore, the semiconductor device 1 includes a first limiting path RS1 that electrically connects the first control path RC1 to the source (second terminal) of MOSFET 12U, a second limiting path RS2 that electrically connects the second control path RC2 to the source (second terminal) of MOSFET 12V, and a third limiting path RS3 that electrically connects the third control path RC3 to the source (second terminal) of MOSFET 12W.

[0133] The first restriction path RS1 has a restriction wiring 21e of the drive circuit 21UL and a first wire 63U. That is, the first wire 63U constitutes part of the first restriction path RS1. The second restriction path RS2 has a restriction wiring 21e of the drive circuit 21VL and a second wire 63V. That is, the second wire 63V constitutes part of the second restriction path RS2. The third restriction path RS3 has a restriction wiring 21e of the drive circuit 21WL and a third wire 63W. That is, the third wire 63W constitutes part of the third restriction path RS3.

[0134] Each of the logic circuits 22UL, 22VL, and 22WL has an RS flip-flop circuit 22a, etc. The RS flip-flop circuit 22a has a set terminal (S terminal) to which a set signal is input, a reset terminal (R terminal) to which a reset signal is input, and an output terminal (Q terminal) to which an output signal is output. The RS flip-flop circuit 22a sets the output signal to a high level triggered by the falling edge of the set signal and sets the output signal to a low level triggered by the falling edge of the reset signal. The RS flip-flop circuit 22a is electrically connected to the gates of each MOSFET 21b and 21c and outputs an output signal to the gate. Each MOSFET 21b and 21c turns on and off complementaryly based on the output signal of the RS flip-flop circuit 22a. This generates a drive signal, which is output to the gate of MOSFET 12L via the output wiring 21d.

[0135] The operation of this embodiment will now be described. The semiconductor device 1 includes a limiting unit that suppresses fluctuations in the source-gate voltage of the MOSFET 12U. More specifically, as shown in Figure 12, the semiconductor device 1 includes a first limiting unit CV1 as a limiting unit. The first limiting unit CV1 is a mechanism that suppresses fluctuations in the source-gate voltage of the MOSFET 12U based on fluctuations in the source voltage of the MOSFET 12U, and has a first limiting path RS1.

[0136] The first limiting unit CV1 (first limiting path RS1) electrically connects the source of the second MOSFET 21c of the source-grounded circuit 21a of the drive circuit 21UL to the source of MOSFET 12U. Therefore, even if the source potential of MOSFET 12U rises due to the current change dI / dt when MOSFET 11U is turned on, and the inductance of the first wire 61U connected to the source of MOSFET 12U, the source potential of the second MOSFET 21c of the source-grounded circuit 21a of the drive circuit 21UL follows suit and rises, thus suppressing the gate-source voltage of MOSFET 12U from becoming negative. As a result, fluctuations in the threshold voltage Vth of MOSFET 12U are suppressed. Consequently, even if the intermittent operation of the first inverter circuit 10U is repeated, the increase in the rate of fluctuation of the threshold voltage Vth of MOSFET 12U is suppressed.

[0137] Furthermore, the semiconductor device 1 includes a second limiting section CV2 and a third limiting section CV3 as limiting sections. The second limiting section CV2 is a mechanism that suppresses fluctuations in the source-gate voltage of MOSFET 12V based on fluctuations in the source voltage of MOSFET 12V, and has a second limiting path RS2. The third limiting section CV3 is a mechanism that suppresses fluctuations in the source-gate voltage of MOSFET 12W based on fluctuations in the source voltage of MOSFET 12W, and has a third limiting path RS3. With this configuration, the increase in the rate of fluctuation of the threshold voltage Vth of MOSFET 12L and MOSFET 12V and 12L is suppressed, similar to MOSFET 12U.

[0138] According to this embodiment, the following effects can be obtained. (1-1) The semiconductor device 1 includes a first limiting section CV1 (first limiting path RS1), a second limiting section CV2 (second limiting path RS2), and a third limiting section CV3 (third limiting path RS3). With this configuration, even if the source potential of MOSFET 12U fluctuates, the gate potential of MOSFET 12U follows suit and fluctuates, thus suppressing fluctuations in the source-gate voltage of MOSFET 12U. Even if the source potential of MOSFET 12V fluctuates, the gate potential of MOSFET 12V follows suit and fluctuates, thus suppressing fluctuations in the source-gate voltage of MOSFET 12V. Even if the source potential of MOSFET 12W fluctuates, the gate potential of MOSFET 12W follows suit and fluctuates, thus suppressing fluctuations in the source-gate voltage of MOSFET 12W. Therefore, fluctuations in the threshold voltage Vth can be suppressed for each of MOSFETs 12U to 12W.

[0139] (1-2) The first wire 63U, which constitutes part of the first limiting path RS1, is connected to the source electrode pad 12s of MOSFET 12U. This allows the potential on the source side of MOSFET 12U to be extracted from the first wire 61U, which is connected to the source electrode pad 12s of MOSFET 12U. This allows MOSFET 12U to be controlled with a gate-source voltage of MOSFET 12U that suppresses the effect of the inductance of the first wire 61U. The second wire 63V, which constitutes part of the second limiting path RS2, is connected to the source electrode pad 12s of MOSFET 12V. The third wire 63W, which constitutes part of the third limiting path RS3, is connected to the source electrode pad 12s of MOSFET 12W. Thus, since the second wire 63V and the third wire 63W have the same configuration as the first wire 63U, the same effect as the first wire 63U can be obtained.

[0140] In addition, since the distance between MOSFETs 12U~12W and integrated circuit element 25L is shorter than the distance between frames 35U, 35V, 35W and integrated circuit element 25L, the lengths of the wires 62U, 62V, 62W and 63U, 63V, 63W connecting the sources of MOSFETs 12U~12W to the integrated circuit element 25L can be shortened. Therefore, the inductance effects of the wires 62U, 62V, 62W and 63U, 63V, 63W can be reduced.

[0141] (1-3) MOSFET 12U is located at the end of region Ra7 of the element mounting region Rse of the first frame 32U on the side of the integrated circuit element 25L in the second direction Y. This shortens the distance between MOSFET 12U and the integrated circuit element 25L, thereby shortening the lengths of the first wire 62U and the first wire 63U that connect MOSFET 12U and the integrated circuit element 25L. Thus, the influence of the inductance of the first wire 62U and the first wire 63U can be reduced. MOSFET 12V is located at the end of region Ra7 of the element mounting region Rse of the second frame 32V on the side of the integrated circuit element 25L in the second direction Y. MOSFET 12W is located at the end of region Ra7 of the element mounting region Rse of the third frame 32W on the side of the integrated circuit element 25L in the second direction Y. With this configuration, the lengths of each wire 62V, 62W and each wire 63V, 63W can be shortened, similar to the first wire 62U and the first wire 63U, thereby reducing the influence of the inductance of each wire 62V, 62W and each wire 63V, 63W.

[0142] (1-4) The first wire 63U is connected to the portion of the source electrode pad 12s of MOSFET 12U that is closer to the integrated circuit element 25L. The second wire 63V is connected to the portion of the source electrode pad 12s of MOSFET 12V that is closer to the integrated circuit element 25L. The third wire 63W is connected to the portion of the source electrode pad 12s of MOSFET 12W that is closer to the integrated circuit element 25L. With this configuration, the length of each wire 63U, 63V, and 63W can be shortened. Therefore, the influence of the inductance of each wire 63U, 63V, and 63W can be reduced.

[0143] (1-5) Each wire 63U, 63V, and 63W is connected to the MOSFET 12U~12W end of the integrated circuit element 25L in the second direction Y. This allows the length of each wire 63U, 63V, and 63W to be shortened. Therefore, the influence of the inductance of each wire 63U, 63V, and 63W can be reduced.

[0144] (1-6) Each frame 32U, 32V, and 32W has grooves 32g and 32h formed to create the element mounting region Rse, respectively. This prevents solder SD from spreading beyond the element mounting region Rse when MOSFETs 12U to 12W are mounted in region Ra7 of the element mounting region Rse. The edges of grooves 32g and 32h are expected to have the effect of keeping the molten solder SD within the grooves 32g and 32h due to the action of surface tension, assuming that molten solder SD is directed toward them. Since grooves 32g and 32h are formed to surround each MOSFET 12U to 12W around its entire circumference, the spreading of solder SD can be further suppressed. Furthermore, since the grooves 31d and 31e of the frame 31 have the same configuration as grooves 32g and 32h, it is possible to suppress the spread of solder SD beyond the element mounting area Rse when MOSFETs 11U to 11W are mounted in the element mounting area Rse.

[0145] (1-7) Frame 31 is provided with a plurality of recesses 31f, and each frame 32U, 32V, and 32W is provided with a plurality of recesses 32i. With this configuration, the sealing resin 50 fills these recesses 31f and 32i, thereby increasing the bonding strength of the sealing resin 50 to frame 31 and each frame 32U, 32V, and 32W. Therefore, it is possible to suppress the peeling of the sealing resin 50 from frame 31 and each frame 32U, 32V, and 32W.

[0146] (1-8) The element mounting region Rse does not have recesses 31f and 32i. This allows for proper bonding of MOSFETs 11U to 11W to frame 31 using solder SD, and bonding of MOSFETs 12U to 12W to their respective frames 32U, 32V, and 32W using solder SD. In addition, the recess 31f of frame 31 is positioned to surround the element mounting region Rse. This ensures that the sealing resin 50 surrounds the MOSFETs 11U to 11W and is firmly bonded to the island portion 31a of frame 31. Furthermore, the recesses 32i of each frame 32U, 32V, and 32W are positioned to surround the element mounting region Rse. This ensures that the sealing resin 50 surrounds the MOSFETs 12U to 12W and is firmly bonded to the island portion 33a of each frame 32U, 32V, and 32W. In this way, it is possible to suppress the formation of gaps in the sealing resin 50 that connect to MOSFETs 11U~11W and MOSFETs 12U~12W due to delamination of the sealing resin 50. Therefore, the insulation state of MOSFETs 11U~11W and MOSFETs 12U~12W can be maintained in good condition.

[0147] (Second Embodiment) The semiconductor device 1 of the second embodiment will be described with reference to Figures 13 and 14. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in the configuration of the drive circuits 21UL, 21VL, and 21WL. In the following description, components common to the configuration of the semiconductor device 1 of the first embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0148] As shown in Figure 13, the first limiting unit CV1 has a diode 13 provided in the first limiting path RS1. The second limiting unit CV2 has a diode 13 provided in the second limiting path RS2. The third limiting unit CV3 has a diode 13 provided in the third limiting path RS3. Each diode 13 is mounted on an integrated circuit element 25L. More specifically, the diode 13 of the first limiting unit CV1 is provided in the limiting wiring 21e of the drive circuit 21UL. The anode of this diode 13 is electrically connected to the first input terminal 25bu, and the cathode is electrically connected to node N2 of the output wiring 21d of the drive circuit 21UL. The diode 13 of the second limiting unit CV2 is provided in the limiting wiring 21e of the drive circuit 21VL. The anode of this diode 13 is electrically connected to the second input terminal 25bv, and the cathode is electrically connected to node N2 of the output wiring 21d of the drive circuit 21VL. The diode 13 of the third limiting section CV3 is provided on the limiting wiring 21e of the drive circuit 21WL. The anode of this diode 13 is electrically connected to the third input terminal 25bw, and the cathode is electrically connected to node N2 of the output wiring 21d of the drive circuit 21WL.

[0149] As shown in Figure 14, in the integrated circuit element 25L, the drive circuits 21UL, 21VL, and 21WL are arranged along the first direction X. That is, the drive circuits 21UL, 21VL, and 21WL are arranged along the longitudinal direction of the integrated circuit element 25L. Here, the direction in which the drive circuits 21UL, 21VL, and 21WL are arranged (first direction X) is an example of the arrangement direction of the third control circuit, the fourth control circuit, and the fifth control circuit.

[0150] The diode 13 of the first limiting section CV1 is positioned around the source-grounded circuit 21a of the drive circuit 21UL. More specifically, the diode 13 of the first limiting section CV1 is positioned in the second direction Y toward the first output terminal 25au and the first input terminal 25bu, i.e., toward the MOSFET 12U, relative to the source-grounded circuit 21a of the drive circuit 21UL.

[0151] The diode 13 of the second limiting section CV2 is positioned around the source-grounded circuit 21a of the drive circuit 21VL. More specifically, the diode 13 of the second limiting section CV2 is positioned in the second direction Y toward the second output terminal 25av and second input terminal 25bv, i.e., toward the MOSFET 12V, compared to the source-grounded circuit 21a of the drive circuit 21VL.

[0152] The diode 13 of the third limiting section CV3 is positioned around the source-grounded circuit 21a of the drive circuit 21WL. More specifically, the diode 13 of the third limiting section CV3 is positioned in the second direction Y toward the third output terminal 25aw and the third input terminal 25bw, i.e., toward the MOSFET 12W, relative to the source-grounded circuit 21a of the drive circuit 21WL.

[0153] The operation of this embodiment will now be described. Since the operation of each inverter circuit 10U, 10V, and 10W is the same, the operation of the first inverter circuit 10U will be described, and the explanations of the operations of the second inverter circuit 10V and the third inverter circuit 10W will be omitted.

[0154] When the MOSFET 11U of the first inverter circuit 10U is turned on, the source potential of MOSFET 12U rises due to the change in current dI / dt flowing through MOSFET 11U and the inductance of the first wire 61U connected to MOSFET 12U. Consequently, the potential of the output wiring 21d of the drive circuit 21UL increases via the first wire 63U connected to the source of MOSFET 12U and the limiting wiring 21e of the integrated circuit element 25L. Therefore, the gate-source voltage of MOSFET 12U is suppressed from becoming negative, and thus the fluctuation of the threshold voltage Vth of MOSFET 12U can be suppressed.

[0155] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) Diodes 13 are provided in the limiting wiring 21e of the drive circuits 21UL, 21VL, and 21WL. This suppresses the increase in the source potential of MOSFETs 12U to 12W due to the output voltages of the drive circuits 21UL, 21VL, and 21WL when MOSFETs 12U to 12W are turned on. Therefore, the current flowing through each of MOSFETs 12U to 12W can be controlled with high precision.

[0156] (2-2) The diode 13 of the first limiting section CV1 is positioned on the side of the first output terminal 25au and the first input terminal 25bu relative to the source-grounded circuit 21a of the drive circuit 21UL. The diode 13 of the second limiting section CV2 is positioned on the side of the second output terminal 25av and the second input terminal 25bv relative to the source-grounded circuit 21a of the drive circuit 21VL. The diode 13 of the third limiting section CV3 is positioned on the side of the third output terminal 25aw and the third input terminal 25bw relative to the source-grounded circuit 21a of the drive circuit 21WL. This makes it possible to shorten the length of the limiting wiring 21e of the drive circuits 21UL, 21VL, and 21WL, and to reduce the effect of the inductance of the limiting wiring 21e.

[0157] (2-3) Each diode 13 is provided within the integrated circuit element 25L. With this configuration, the semiconductor device 1 can be miniaturized compared to a configuration in which each diode 13 is provided as a separate semiconductor chip from the integrated circuit element 25L.

[0158] (Third embodiment) The semiconductor device 1 of the third embodiment will be described with reference to Figures 9 and 15. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in the arrangement of the MOSFET 12U. In the following description, components common to the configuration of the semiconductor device 1 of the first embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0159] As shown in Figure 9, in the first embodiment, the orientation (positioning) of the MOSFETs 12U to 12W mounted on each frame 32U, 32V, and 32W is the same. In Figure 9, the MOSFETs 12U to 12W are mounted on each frame 32U, 32V, and 32W such that the second direction Y is the longitudinal direction. In this case, the length of the first wire 62U and the first wire 63U of the MOSFET 12U of the first frame 32U, which is located closest to frame 31 among the frames 32U, 32V, and 32W, will be longer.

[0160] Therefore, in this embodiment, as shown in Figure 15, the orientation (positioning) of the MOSFET 12U mounted on the first frame 32U is different from the orientation (positioning) of the MOSFET 12V mounted on the second frame 32V and the MOSFET 12W mounted on the third frame 32W. More specifically, the MOSFET 12U on the first frame 32U is mounted on the first frame 32U such that the first direction X is the longitudinal direction. Furthermore, the MOSFET 12U is mounted on the first frame 32U such that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, the MOSFET 12U is mounted on the first frame 32U such that its gate electrode pad 12g is on the MOSFET 12V side in the first direction X and on the frame 34 side in the second direction Y on the surface of the MOSFET 12U.

[0161] Furthermore, in this embodiment, the arrangement of the first wire 63U connecting the source electrode pad 12s of the MOSFET 12U to the integrated circuit element 25L and the arrangement of the first wire 62U connecting the gate electrode pad 12g of the MOSFET 12U to the integrated circuit element 25L are different. Specifically, the first wire 62U is positioned on the second frame 32V side than the first wire 63U. The first wire 62U is adjacent to the gate electrode pad 12g of the source electrode pad 12s in the first direction X and is connected to the region on the frame 33 side.

[0162] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (3-1) The MOSFET 12U mounted on the first frame 32U is positioned on the first frame 32U such that its gate electrode pad 12g is close to the integrated circuit element 25L, thus the length of the first wire 62U connecting the gate electrode pad 12g and the integrated circuit element 25L can be shortened. Therefore, the effect of the inductance of the first wire 62U can be reduced.

[0163] (Fourth Embodiment) The semiconductor device 1 of the fourth embodiment will be described with reference to Figures 16, 17, 18A, and 18B. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in that it is provided with a limiting section that suppresses fluctuations in the source potential of MOSFETs 12U to 12W when MOSFETs 11U to 11W are turned on, instead of the limiting section. In the following description, components common to the semiconductor device 1 of the first embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0164] As shown in Figure 16, the semiconductor device 1 has a first limiting section CP1, a second limiting section CP2, and a third limiting section CP3 as limiting sections, instead of the first limiting section CV1, a second limiting section CV2, and a third limiting section CV3 (see Figure 14) as limiting sections in the first embodiment.

[0165] The first limiting unit CP1 is a mechanism that suppresses fluctuations in the source potential of MOSFET 12U when MOSFET 11U is turned on. The first limiting unit CP1 has a first diode 14U, which is an example of a sixth diode connected to the second switching element of the first inverter circuit 10U. The anode of the first diode 14U is connected to the source of MOSFET 12U, and the cathode of the first diode 14U is connected to the drain of MOSFET 12U.

[0166] The second limiting unit CP2 is a mechanism that suppresses fluctuations in the source potential of MOSFET 12V when MOSFET 11V is turned on. The second limiting unit CP2 has a second diode 14V, which is an example of a seventh diode connected to the second switching element of the second inverter circuit 10V. The anode of the second diode 14V is connected to the source of MOSFET 12V, and the cathode of the second diode 14V is connected to the drain of this MOSFET 12V.

[0167] The third limiting unit CP3 is a mechanism that suppresses fluctuations in the source potential of MOSFET 12W when MOSFET 11W is turned on. The third limiting unit CP3 has a third diode 14W, which is an example of an eighth diode connected to the second switching element of the third inverter circuit 10W. The anode of the third diode 14W is connected to the source of MOSFET 12W, and the cathode of the third diode 14W is connected to the drain of MOSFET 12W.

[0168] An example of each diode 14U, 14V, and 14W is a Schottky barrier diode. In this embodiment, the first diode 14U is configured such that its forward voltage Vf is lower than the forward voltage of the body diode of MOSFET 12U. The second diode 14V is configured such that its forward voltage Vf is lower than the forward voltage of the body diode of MOSFET 12V. The third diode 14W is configured such that its forward voltage is lower than the forward voltage of the body diode of MOSFET 12W. As shown in Figure 17, each diode 14U, 14V, and 14W is formed by a semiconductor chip. The first diode 14U is mounted in region Ra8 of the first frame 32U, the second diode 14V is mounted in region Ra8 of the second frame 32V, and the third diode 14W is mounted in region Ra8 of the third frame 32W. Each diode 14U, 14V, and 14W is located near the fourth side surface 50F of the sealing resin 50 in the second direction Y within region Ra8.

[0169] Each diode 14U, 14V, and 14W has an anode electrode pad 14a, which is a surface electrode, and a cathode electrode, which is a back electrode. The cathode electrode of the first diode 14U is electrically connected to the first frame 32U by solder or the like. The cathode electrode of the second diode 14V is electrically connected to the second frame 32V by solder or the like. The cathode electrode of the third diode 14W is electrically connected to the third frame 32W by solder or the like.

[0170] As shown in Figure 17, the first limiting section CP1 further includes a first wire 61U and a first diode wire 64U, which is an example of a fourth diode wire provided separately from the first wire 61U. The first wire 61U connects the source electrode pad 12s of the MOSFET 12U of the first frame 32U to the island portion 35a of the frame 35U. The first wire 61U is connected to the frame 35U by passing through the connection portion 32c of the second diode 14V of the second frame 32V and the third frame 32W. The first diode wire 64U connects the anode electrode pad 14a of the first diode 14U to the island portion 35a of the frame 35U. The first diode wire 64U is connected to the frame 35U by passing through the connection portion 32c of the frame 32V and the connection portion 32c of the frame 32W. In the island portion 35a of frame 35U, the position where the first wire 61U is connected and the position where the first diode wire 64U is connected are different. More specifically, the position where the first wire 61U is connected to the island portion 35a of frame 35U is located closer to the connection portion 32c of the third frame 32W than the position where the first diode wire 64U is connected to the island portion 35a of frame 35U.

[0171] The second limiting section CP2 further includes a second wire 61V and a second diode wire 64V, which is an example of a fifth diode wire provided separately from the second wire 61V. The second wire 61V connects the source electrode pad 12s of MOSFET 12V of the second frame 32V to the island portion 35a of frame 35V. The second wire 61V is connected to frame 35V by passing through the third diode 14W of the third frame 32W. The second diode wire 64V connects the anode electrode pad 14a of the second diode 14V to the island portion 35a of frame 35V. The second diode wire 64V is connected to frame 35V by passing through the end of the island portion 32a of frame 32W on the connection portion 32c side. In the island portion 35a of frame 35V, the position where the second wire 61V is connected and the position where the second diode wire 64V is connected are different from each other. More specifically, the location where the second wire 61V is connected to the island portion 35a of frame 35V is located closer to the island portion 35a of frame 35U than the location where the wire 64V for the second diode is connected to the island portion 35a of frame 35V.

[0172] The third limiting section CP3 further includes a third wire 61W and a third diode wire 64W, which is an example of a sixth diode wire provided separately from the third wire 61W. The third wire 61W connects the source electrode pad 12s of MOSFET 12W of the third frame 32W to the island portion 35a of frame 35W. The third wire 61W is connected to frame 35W by passing through the portion of frame 32W closer to region Ra7 than the third diode 14W. The third diode wire 64W connects the anode electrode pad 14a of the third diode 14W to the island portion 35a of frame 35W. In the island portion 35a of frame 35W, the position where the third wire 61W is connected and the position where the third diode wire 64W is connected are different from each other. More specifically, the position where the third wire 61W is connected to the island portion 35a of frame 35W is located closer to the island portion 32a of the third frame 32W than the position where the wire 64W for the third diode is connected to the island portion 35a of frame 35W.

[0173] Each diode wire 64U, 64V, and 64W is made of, for example, aluminum (Al). The wire diameters of each diode wire 64U, 64V, and 64W are equal to those of each other. The wire diameter of each diode wire 64U, 64V, and 64W is equal to the wire diameter of each wire 61U, 61V, and 61W.

[0174] [Structure of the 1st to 3rd diodes] Next, with reference to Figures 18A and 18B, an example of the structure of each diode 14U, 14V, and 14W will be described. Since the structures of each diode 14U, 14V, and 14W are the same, the structure of the first diode 14U will be described below, and the descriptions of the structures of the second diode 14V and the third diode 14W will be omitted.

[0175] The first diode 14U is N + Type (for example, N-type impurity concentration of 1e18~1e21 cm³) -3The device comprises a silicon substrate 90. A cathode electrode 91 is formed on the back surface of the silicon substrate 90 so as to cover its entire surface. The cathode electrode 91 is made of a metal that makes ohmic contact with N-type silicon (for example, gold (Au), nickel (Ni), silicide, cobalt (Co) silicide, etc.).

[0176] On the surface of the silicon substrate 90, there is a lower concentration of N than the silicon substrate 90. - Type (for example, N-type impurity concentration of 1e15~1e17cm) -3 Epitaxial layers 92 (semiconductor layers) are stacked. The thickness of the epitaxial layers 92 is, for example, 2 μm to 20 μm.

[0177] A field insulating film 93, made of, for example, silicon oxide (SiO2), is laminated on the surface of the epitaxial layer 92. The thickness of the field insulating film 93 is, for example, 1000 Å or more, preferably 7000 Å to 40000 Å. The field insulating film 93 may also be formed from other insulating materials such as silicon nitride (SiN).

[0178] The field insulating film 93 has an opening 94 that exposes the central part of the epitaxial layer 92. Multiple trenches 95 are formed in the surface of the central part of the epitaxial layer 92 by excavating the epitaxial layer 92 from the surface. Each trench 95 is a longitudinal groove extending in a predetermined direction. The bottom surface of the trench 95 is a plane that is aligned with the surface of the epitaxial layer 92. Therefore, the cross-section of each trench 95 is substantially rectangular. In this embodiment, seven trenches 95 extend parallel to each other at predetermined intervals. That is, the seven trenches 95 are formed in a stripe pattern when viewed from above.

[0179] In the surface portion of the epitaxial layer 92, a mesa portion 96 is formed in the area sandwiched between adjacent trenches 95. If the trenches 95 have a substantially rectangular cross-section, the mesa portion 96 has a substantially rectangular cross-section accordingly. Each mesa portion 96 has a pair of side walls (side walls of the trenches 95) that rise substantially vertically from, for example, one side edge of the bottom surface of an adjacent pair of trenches 95, and a top surface (surface of the epitaxial layer 92) that connects these pair of side walls.

[0180] An anode electrode 97 is formed on the epitaxial layer 92. The anode electrode 97 fills the opening 94 of the field insulating film 93 and extends outward from the opening 94 so as to cover the peripheral edge 98 of the opening 94 in the field insulating film 93. That is, the peripheral edge 98 of the field insulating film 93 is sandwiched from both above and below by the epitaxial layer 92 and the anode electrode 97 around its entire circumference. The amount by which the anode electrode 97 covering the peripheral edge 98 of the field insulating film 93 protrudes from the edge of the opening 94 of the field insulating film 93 is, for example, 10 μm or more, preferably 10 μm to 100 μm.

[0181] The anode electrode 97 has a multilayer structure (a two-layer structure in this embodiment) that includes a Schottky metal 99 bonded to the epitaxial layer 92 within an opening 94 of the field insulating film 93, and a contact metal 100 laminated on the Schottky metal 99.

[0182] The Schottky metal 99 is made of a metal (for example, titanium (Ti), molybdenum (Mo), palladium (Pd), etc.) that forms a Schottky junction by bonding with N-type silicon. In this embodiment, titanium is used for the Schottky metal 99. The Schottky metal 99 is formed to be in contact with the surface of the epitaxial layer 92, including the inner wall surface (bottom surface and a pair of side wall surfaces) of the trench 95. Therefore, the Schottky metal 99 is in contact with the surface of the epitaxial layer 92 both on the inner wall surface of all trenches 95 and outside the trenches 95. Furthermore, the Schottky metal 99 covers the entire inner wall surface of each trench 95 and extends continuously outside the trenches 95. In other words, the Schottky metal 99 is bonded to the surface of the epitaxial layer 92 exposed from the opening 94 of the field insulating film 93 so as to completely cover its entire surface. The Schottky metal 99 of this embodiment includes a bottom portion 99a that contacts the bottom surface of the trench 95, a side portion 99b that contacts the side wall surface of the trench 95 (the side wall surface of the mesa portion 96), and a top portion 99c that contacts the top surface of the mesa portion 96.

[0183] In this case, as shown by the thick line in Figure 18B, the joint surface (Schottky joint surface) S between the Schottky metal 99 and the surface of the epitaxial layer 92 is formed to have an uneven cross-section in the region within the opening 94 of the field insulating film 93. Therefore, the area of ​​the Schottky joint surface S is larger than the apparent area of ​​the epitaxial layer 92 in a plan view along the normal direction of the surface of the epitaxial layer 92 (the portion extending horizontally in Figure 18B). More specifically, the Schottky joint surface S includes a bottom surface portion S1 that contacts the bottom surface of the trench 95, a side surface portion S2 that contacts the side wall surface of the trench 95 (the side wall surface of the mesa portion 96), and a top surface portion S3 that contacts the top surface of the mesa portion 96. When the trench 95 has a substantially rectangular cross-section, the area of ​​the Schottky joint surface S can be increased by the amount of the side surface portion S2 compared to the case where the trench 95 is not formed.

[0184] The Schottky metal 99 bonded to the epitaxial layer 92 forms a Schottky barrier (potential barrier) of, for example, 0.52 eV to 0.9 eV between itself and the silicon semiconductor constituting the epitaxial layer 92. The thickness of the Schottky metal 99 in this embodiment is 0.02 μm to 0.2 μm.

[0185] The contact metal 100 is the part of the anode electrode 97 that is exposed on the outermost surface of the first diode 14U and to which the first diode wire 64U (see Figure 17) and the like are joined. In other words, the contact metal 100 constitutes the anode electrode pad 14a. The contact metal 100 is made of, for example, aluminum (Al). The thickness of the contact metal 100 in this embodiment is, for example, 0.5 μm to 5 μm. The contact metal 100 is embedded in each trench 95 so as to be in contact with the Schottky metal 99 that covers the inner wall surface of each trench 95. That is, the contact metal 100 is in contact with the bottom surface 99a, a pair of side surfaces 99b, and the top surface 99c of the Schottky metal 99. For this reason, the contact metal 100 is formed to have an uneven cross-section on the side of each trench 95 that is in contact with the Schottky metal 99. On the other hand, the surface of the contact metal 100 opposite to the side in contact with the Schottky metal 99 is formed flat along the surface of the epitaxial layer 92 (excluding the inner wall surface of the trench 95).

[0186] When the Schottky metal 99 is made of titanium, it is preferable that a titanium nitride (TiN) layer is interposed between the Schottky metal 99 and the contact metal 100, which is made of aluminum. The titanium nitride layer acts as a barrier layer that bonds the titanium of the Schottky metal 99 to the aluminum of the contact metal 100, ensures conductivity between titanium and aluminum, and further suppresses the mutual diffusion of titanium and aluminum. Such a barrier layer protects the Schottky bonding surface S by suppressing or preventing the diffusion of the material of the contact metal 100 into the Schottky metal 99.

[0187] A surface protective film (not shown) may be formed on the outermost surface of the first diode 14U. In this case, it is preferable that an opening is formed in the center of the surface protective film to expose the contact metal 100. External connecting members such as the first diode wire 64U (see Figure 17) are joined to the contact metal 100 through this opening.

[0188] A guard ring 101 made of a P-type diffusion layer is formed on the surface of the epitaxial layer 92 so as to be in contact with the Schottky metal 99. In a plan view, the guard ring 101 is formed along the contour of the opening 94 of the field insulating film 93 so as to straddle the inside and outside of the opening 94. Therefore, the guard ring 101 has an inner portion 101a that protrudes inward from the opening 94 of the field insulating film 93 and is in contact with the outer edge portion 99d, which is the end portion of the Schottky metal 99 inside the opening 94, and an outer portion 101b that protrudes outward from the opening 94 and is opposite the anode electrode 97 (Schottky metal 99 on the peripheral edge portion 98) with the peripheral edge portion 98 of the field insulating film 93 in between. The depth of the guard ring 101 from the surface of the epitaxial layer 92 is, for example, 0.5 μm to 8 μm.

[0189] The guard ring 101, formed spanning the inside and outside of the opening 94 of the field insulating film 93, covers the boundary between the peripheral edge 98 of the field insulating film 93 and the Schottky metal 99 from the epitaxial layer 92 side. In the absence of the guard ring 101, when a reverse bias is applied to the first diode 14U, the electric field concentrates at the boundary, making leakage more likely. In the first diode 14U of this embodiment, because the boundary is covered by the guard ring 101, the electric field concentration can be mitigated by the depletion layer spreading from the guard ring 101 when a reverse bias is applied, and leakage can be suppressed accordingly. Therefore, the breakdown voltage of the first diode 14U is improved.

[0190] The operation of this embodiment will be explained with reference to Figure 19. Note that the comparative semiconductor device is a semiconductor device that does not have the respective limiting parts CP1, CP2, and CP3 (each diode 14U, 14V, 14W and each diode wire 64U, 64V, 64W).

[0191] In the comparative semiconductor device, for example, when driving motor 2 (see Figure 1), when MOSFET 11U is turned off, a regenerative current flows through the body diode of MOSFET 12U, and when MOSFET 11U is turned on at this time, a recovery current flows through the body diode of MOSFET 12U. At this time, due to the inductance of the first wire 61U, the source potential of MOSFET 12U may rise and become higher than the gate potential of MOSFET 12U, resulting in a so-called negative bias.

[0192] In this regard, the semiconductor device 1 of this embodiment has a configuration in which a first diode wire 64U and a first wire 61U are individually provided as a first limiting section CP1, and the first diode wire 64U is connected to the island section 35a of the frame 35U. For this reason, for example, when the motor 2 (see Figure 1) is driven, the regenerative current generated when the MOSFET 11U is turned on and the MOSFET 12U is turned off flows through the first diode 14U because the forward voltage Vf of the first diode 14U is lower than the forward voltage of the body diode of the MOSFET 12U. That is, this regenerative current does not flow through the body diode of the MOSFET 12U through the first wire 61U. Therefore, the rise in the source potential of the MOSFET 12U caused by the current change dI / dt when the MOSFET 11U is turned on and the inductance of the first wire 61U is suppressed. Therefore, the generation of a negative bias of the MOSFET 12U can be suppressed.

[0193] Furthermore, since the wires 64V and 61V for the second diode and the wires 64W and 61W for the third diode have the same configuration as the wires 64U and 61U for the first diode, they produce the same effects as described above.

[0194] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (4-1) By providing individual wires 61U, 61V, and 61W connected to MOSFETs 12U to 12W, and individual diode wires 64U, 64V, and 64W, the rise in the source potential of MOSFETs 12U to 12W is suppressed. As a result, when MOSFET 11U is turned on, the gate-source voltage of MOSFET 12U is suppressed to become negative. Similarly, when MOSFET 11V is turned on, the gate-source voltage of MOSFET 12V is suppressed to become negative. Similarly, when MOSFET 11W is turned on, the gate-source voltage of MOSFET 12W is suppressed to become negative. Therefore, fluctuations in the threshold voltage Vth can be suppressed for each of MOSFETs 12U to 12W.

[0195] (Fifth embodiment) The semiconductor device 1 of the fifth embodiment will be described with reference to Figures 20 and 21. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the fourth embodiment in that diodes connected in antiparallel to each of the MOSFETs 11U to 11W have been added. In the following description, components common to the configuration of the semiconductor device 1 of the fourth embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0196] As shown in Figure 20, the semiconductor device 1 includes a first diode 15U provided separately from the MOSFET 11U, a second diode 15V provided separately from the MOSFET 11V, and a third diode 15W provided separately from the MOSFET 11W. The anode of the first diode 15U is connected to the source of the MOSFET 11U, and the cathode of the first diode 15U is connected to the drain of the MOSFET 11U. The anode of the second diode 15V is connected to the source of the MOSFET 11V, and the cathode of the second diode 15V is connected to the drain of the MOSFET 11V. The anode of the third diode 15W is connected to the source of the MOSFET 11W, and the cathode of the third diode 15W is connected to the drain of the MOSFET 11W. Note that the first diode 15U is an example of a third diode provided separately from the first switching element of the first inverter circuit 10U and electrically connected to this first switching element. The second diode 15V is an example of a fourth diode provided separately from the first switching element of the second inverter circuit 10V and electrically connected to this first switching element. The third diode 15W is an example of a fifth diode that is provided separately from the first switching element of the third inverter circuit 10W and is electrically connected to this first switching element.

[0197] Examples of each diode 15U, 15V, and 15W are Schottky barrier diodes similar to each diode 14U, 14V, and 14W. As shown in Figure 21, each diode 15U, 15V, and 15W is formed from a semiconductor chip. The first diode 15U is mounted in region Ra4 of frame 31, the second diode 15V is mounted in region Ra5, and the third diode 15W is mounted in region Ra6. The first diode 15U is located near the fourth side surface 50F of the encapsulating resin 50 in the second direction Y in region Ra6, the second diode 15V is located near the fourth side surface 50F of the encapsulating resin 50 in the second direction Y in region Ra7, and the third diode 15W is located near the fourth side surface 50F of the encapsulating resin 50 in the second direction Y in region Ra6.

[0198] Each diode 15U, 15V, and 15W has an anode electrode pad 15a, which is a surface electrode, and a cathode electrode, which is a back electrode. The cathode electrodes of each diode 15U, 15V, and 15W are electrically connected to the frame 31 by solder or the like.

[0199] The anode electrode pad 15a of the first diode 15U and the wire junction 32f of the first frame 32U are connected by the first wire 60U. The anode electrode pad 15a of the second diode 15V and the wire junction 32f of the second frame 32V are connected by the second wire 60V. The anode electrode pad 15a of the third diode 15W and the wire junction 32f of the third frame 32W are connected by the third wire 60W.

[0200] As shown in Figure 21, the semiconductor device 1 has wires 60U, 60V, 60W, a wire 65U for the first diode on the high-potential side, a wire 65V for the second diode on the high-potential side, a wire 65W for the third diode on the high-potential side, wires 61U, 61V, 61W, and wires 64U, 64V, 64W for each diode on the low-potential side. The configuration and connection of each wire 61U, 61V, 61W and each diode wire 64U, 64V, 64W are the same as in the fourth embodiment. Each diode wire 64U, 64V, 64W is provided so as to be generally parallel to each other. Each diode wire 65U, 65V, 65W is provided so as to be generally parallel to each other. Each diode wire 64U, 64V, 64W and each diode wire 65U, 65V, 65W are provided so as to be generally parallel to each other.

[0201] One first wire 60U connects the source electrode pad 11s of MOSFET 11U to the wire junction 32f of the first frame 32U. One second wire 60V connects the source electrode pad 11s of MOSFET 11V to the wire junction 32f of the second frame 32V. One third wire 60W connects the source electrode pad 11s of MOSFET 11W to the wire junction 32f of the third frame 32W. The first wire 60U passes on the side of the first diode 15U beyond the second diode wire 65V of the second diode 15V and connects to the wire junction 32f of the first frame 32U. The second wire 60V passes on the side of the second diode 15V beyond the third diode wire 65W of the third diode 15W and through the connection part 32c of the first frame 32U and connects to the wire junction 32f of the second frame 32V. The third wire 60W is connected to the wire junction 32f of the third frame 32W, passing through the connection point 32c of the second frame 32V and on the third diode 15W side of the first diode wire 64U of the first diode 14U of the first frame 32U.

[0202] The wire 65U for the first diode is provided separately from the first wire 60U. One wire 65U for the first diode connects the anode electrode pad 15a of the first diode 15U to the wire junction 32f of the frame 32U. The position where the first wire 60U is connected to the wire junction 32f of the first frame 32U and the position where the first diode wire 65U is connected to the wire junction 32f of the first frame 32U are different. More specifically, the position where the first wire 60U is connected to the wire junction 32f of the first frame 32U is located on the wire junction 32f side of the second frame 32V than the position where the first diode wire 65U is connected to the wire junction 32f of the first frame 32U. The first diode wire 65U passes through the connection part 31c of the frame 31 and is connected to the wire junction 32f of the first frame 32U. The wire 65V for the second diode passes through the connection point 32c of the first frame 32U and is connected to the wire junction 32f of the second frame 32V. The wire 65W for the third diode passes through the island portion 32a of the first frame 32U and the connection point 32c of the second frame 32V and is connected to the wire junction 32f of the third frame 32W.

[0203] The wire 65V for the second diode is provided separately from the second wire 60V. One wire 65V for the second diode connects the anode electrode pad 15a of the second diode 15V to the wire junction 32f of the second frame 32V. The position where the second wire 60V is connected to the wire junction 32f of the second frame 32V and the position where the wire 65V for the second diode is connected to the wire junction 32f of the second frame 32V are different from each other. More specifically, the position where the wire 65V for the second diode is connected to the wire junction 32f of the second frame 32V is located closer to the wire junction 32f of the first frame 32U than the position where the second wire 60V is connected to the wire junction 32f of the second frame 32V.

[0204] The third diode wire 65W is provided separately from the third wire 60W. One third diode wire 65W connects the anode electrode pad 15a of the third diode 15W to the wire junction 32f of the third frame 32W. The position where the third wire 60W is connected to the wire junction 32f of the third frame 32W and the position where the third diode wire 65W is connected to the wire junction 32f of the third frame 32W are different from each other. More specifically, the position where the third diode wire 65W is connected to the wire junction 32f of the third frame 32W is located closer to the wire junction 32f of the second frame 32V than the position where the third wire 60W is connected to the wire junction 32f of the third frame 32W.

[0205] Each diode wire 65U, 65V, and 65W is made of, for example, aluminum (Al). The wire diameters of each diode wire 65U, 65V, and 65W are equal to each other. The wire diameters of each diode wire 65U, 65V, and 65W are equal to the wire diameters of each wire 60U, 60V, and 60W. According to this embodiment, the same operation and effects as in the fourth embodiment can be obtained.

[0206] (modified version) The above descriptions of the embodiments are illustrative of possible forms of semiconductor devices according to this disclosure and are not intended to limit their forms. In addition to the above embodiments, semiconductor devices according to this disclosure may take the following modifications, for example, and combinations of at least two non-inconsistent modifications.

[0207] • At least two of the second to fifth embodiments can be combined. In each of the above embodiments, the structure of the electrode pads of the MOSFETs 12U to 12W mounted on each frame 32U, 32V, and 32W, and the orientation (positioning) of the MOSFETs 12U to 12W can be arbitrarily changed. For example, the MOSFETs 12U to 12W may be changed as shown in (A1) to (A4) below.

[0208] (A1) As shown in Figure 22, the gate electrode pads 12g of MOSFETs 12U to 12W may be positioned on the second side surface 50D of the sealing resin 50. The source electrode pads 12s of MOSFETs 12U to 12W each have a notch that avoids the gate electrode pad 12g. As shown in Figure 22, MOSFETs 12U and 12V are positioned so that the second direction Y is the longitudinal direction. On the other hand, MOSFET 12W is positioned so that the first direction X is the longitudinal direction. MOSFET 12W is positioned so that its gate electrode pad 12g is located on the frame 34 side. MOSFET 12W is positioned on the second side surface 50D side of the integrated circuit element 25L. Note that in Figure 22, MOSFET 12W is positioned in the center of region Ra7 in the first direction X, but this is not limited to this; for example, MOSFET 12W may be positioned closer to the second frame 32V in the first direction X. Furthermore, while MOSFET12U is positioned in the center of region Ra7 in the first direction X, it is not limited to this arrangement; for example, MOSFET12U may be positioned closer to the second frame 32V in the first direction X.

[0209] The first wire 62U and the first wire 63U are each connected to the end of the MOSFET 12U in the integrated circuit element 25L, near the end on the first frame 32U side. The first wire 62U is located on the second frame 32V side of the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are each connected to the central part of the integrated circuit element 25L in the first direction X. The second wire 62V is located on the third frame 32W side of the second wire 63V in the first direction X. The third wire 62W and the third wire 63W are each connected to the part of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is located on the second frame 32V side of the third wire 62W in the first direction X.

[0210] (A2) As shown in Figure 23, each of MOSFETs 12U to 12W has two gate electrode pads 12g. The structures of MOSFETs 12U to 12W are common to each other. For this reason, the structure of MOSFET 12U will be described as an example, and the descriptions of the structures of MOSFETs 12V and 12W will be omitted. The two gate electrode pads 12g of MOSFET 12U are located at the longitudinal end of MOSFET 12U. The two gate electrode pads 12g of MOSFET 12U are spaced apart in a direction perpendicular to the longitudinal direction in a plan view of MOSFET 12U. The source electrode pad 12s of MOSFET 12U has a portion that extends between the two gate electrode pads 12g and is formed in a convex shape in a plan view.

[0211] As shown in Figure 23, MOSFET 12V is positioned so that the second direction Y is the longitudinal direction. MOSFETs 12U and 12W are positioned so that the first direction X is the longitudinal direction. MOSFET 12U is positioned so that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, MOSFET 12U is positioned so that its gate electrode pad 12g is on the second frame 32V side. MOSFET 12W is positioned so that its gate electrode pad 12g is close to the integrated circuit element 25L. More specifically, MOSFET 12W is positioned so that its gate electrode pad 12g is on the second frame 32V side. Thus, the orientation (positioning) of MOSFET 12U and MOSFET 12W are opposite to each other.

[0212] The first wire 62U is connected to the gate electrode pad 12g on the integrated circuit element 25L side of the two gate electrode pads 12g of the MOSFET 12U. The first wire 63U is connected to the portion between the two gate electrode pads 12g on the source electrode pad 12s. The first wire 63U is located on the second frame 32V side of the first wire 62U in the first direction X. The second wire 62V is connected to the gate electrode pad 12g on the third frame 32W side of the two gate electrode pads 12g. The second wire 63V is connected to the portion between the two gate electrode pads 12g on the source electrode pad 12s. Therefore, the second wire 62V is located on the third frame 32W side of the first direction X. The third wire 62W is connected to the gate electrode pad 12g on the integrated circuit element 25L side of the two gate electrode pads 12g. The third wire 63W is connected to the portion between the two gate electrode pads 12g on the source electrode pad 12s. The third wire 63W is positioned closer to the 32V side of the second frame than the third wire 62W.

[0213] (A3) The orientation (positioning) of each MOSFET 12U~12W mounted on each frame 32U, 32V, and 32W can be arbitrarily changed. In one example, as shown in Figure 24, the orientations (positioning) of MOSFETs 12U~12W are different from each other. More specifically, MOSFET 12U is positioned so that the gate electrode pad 12g is close to the integrated circuit element 25L, and the longitudinal direction of MOSFET 12U is aligned in a direction different from the first direction X and the second direction Y. An example of the angle θ1 between the longitudinal direction of MOSFET 12U and the first direction X is 80°. MOSFET 12V is positioned so that its longitudinal direction is aligned with the first direction X. MOSFET 12W is positioned so that the gate electrode pad 12g is close to the integrated circuit element 25L, and the longitudinal direction of MOSFET 12W is aligned in a direction different from the first direction X and the second direction Y. An example of the angle θ2 between the longitudinal direction of MOSFET 12W and the first direction X is 10°. Note that angles θ1 and θ2 can be arbitrarily changed within the range of 0° or greater and 90° or less. In Figure 24, angles θ1 and θ2 were different, but angles θ1 and θ2 may be equal to each other.

[0214] The first wire 62U and the first wire 63U are each connected to the end of the MOSFET 12U in the integrated circuit element 25L, near the end on the first frame 32U side. The first wire 62U is located on the second frame 32V side of the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are each connected to the central part of the integrated circuit element 25L in the first direction X. The second wire 63V is located on the third frame 32W side of the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are each connected to the part of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is located on the second frame 32V side of the third wire 62W in the first direction X.

[0215] Furthermore, the orientation of MOSFETs 12U and 12W in the modified example shown in Figure 24 may be further changed as shown in Figure 25. That is, as shown in Figure 25, MOSFET 12U is positioned such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25L, and the longitudinal direction of MOSFET 12U is aligned in a direction different from the first direction X and the second direction Y. MOSFET 12W is positioned such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25L, and the longitudinal direction of MOSFET 12W is aligned in a direction different from the first direction X and the second direction Y. An example of angle θ1 is 100°. In this case, angle θ1 can be arbitrarily changed within the range of 90° or more and 180° or less.

[0216] The first wire 62U and the first wire 63U are each connected to the end of the MOSFET 12U in the integrated circuit element 25L, near the end on the first frame 32U side. The first wire 63U is located on the second frame 32V side of the first wire 62U in the first direction X. The third wire 62W and the third wire 63W are each connected to the portion of the integrated circuit element 25L on the third frame 32W side. The third wire 62W is located on the second frame 32V side of the third wire 63W in the first direction X.

[0217] Furthermore, MOSFETs 12U to 12W can be formed by combining the modified versions shown in Figure 24 and Figure 25. In one example, the orientation (positioning) of MOSFET 12U mounted on the first frame 32U is the orientation of MOSFET 12U shown in Figure 24, and the orientation (positioning) of MOSFET 12W mounted on the third frame 32W is the orientation of MOSFET 12W shown in Figure 25.

[0218] Similarly, the orientation of MOSFETs 11U to 11W mounted on frame 31 can also be changed, as shown in the orientations of MOSFETs 12U to 12W in Figures 24 and 25. In one example, as shown in Figure 26, the orientations (positioning) of MOSFETs 11U to 11W are different from each other. More specifically, MOSFET 11U is positioned so that its gate electrode pad 12g is close to the integrated circuit element 25H, and its longitudinal direction aligns with a direction different from the first direction X and the second direction Y. An example of the angle θ1 between the longitudinal direction of MOSFET 11U and the first direction X is 80°. MOSFET 11V is positioned so that its longitudinal direction aligns with the first direction X. MOSFET 11W is positioned so that its gate electrode pad 12g is close to the integrated circuit element 25H, and its longitudinal direction aligns with a direction different from the first direction X and the second direction Y. An example of the angle θ2 between the longitudinal direction of MOSFET 11W and the first direction X is 10°. Note that angles θ1 and θ2 can be arbitrarily changed within the range of 0° or greater and 90° or less. In Figure 26, angles θ1 and θ2 were different, but angles θ1 and θ2 may be equal to each other.

[0219] As shown in Figure 26, the first wire 62U and the first wire 63U are each connected near the MOSFET 11U end of the integrated circuit element 25H. The first wire 62U is located on the first side surface 50C side of the first wire 63U in the first direction X. The second wire 62V and the second wire 63V are each connected near the center of the integrated circuit element 25H in the first direction X. The second wire 63V is located on the second side surface 50D side of the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are each connected to the MOSFET 11W side of the integrated circuit element 25H. The third wire 63W is located on the second side surface 50D side of the third wire 62W in the first direction X.

[0220] As shown in Figure 27, the MOSFET 11U is positioned such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25H, and the longitudinal direction of the MOSFET 11U is aligned in a direction different from the first direction X and the second direction Y. The MOSFET 11W is positioned such that the gate electrode pad 12g is spaced apart from the integrated circuit element 25H, and the longitudinal direction of the MOSFET 11W is aligned in a direction different from the first direction X and the second direction Y. An example of angle θ1 is 100°. In this case, angle θ1 can be arbitrarily changed within the range of 90° or more and 180° or less.

[0221] As shown in Figure 27, the first wire 62U and the first wire 63U are each connected near the end of the MOSFET 11U in the integrated circuit element 25H. The first wire 63U is located on the first side surface 50C side of the first wire 62U in the first direction X. The third wire 62W and the third wire 63W are each connected to the portion of the integrated circuit element 25H on the second side surface 50D side. The third wire 63W is located on the second side surface 50D side of the third wire 62W in the first direction X.

[0222] Furthermore, the orientation of MOSFETs 11U to 11W can also be determined by combining the modified configuration shown in Figure 26 and the modified configuration shown in Figure 27. In one example, the orientation (positioning) of MOSFET 11U is the orientation of MOSFET 11U shown in Figure 26, and the orientation (positioning) of MOSFET 11W is the orientation of MOSFET 11W shown in Figure 27.

[0223] (A4) The shape and position of each gate electrode pad 12g of MOSFETs 12U to 12W can be arbitrarily changed. The shape of the source electrode pad 12s is changed in accordance with the change in the shape and position of the gate electrode pad 12g. In one example, as shown in Figure 28, the gate electrode pad 12g is formed in a rectangular shape with the first direction X as the longitudinal direction. The gate electrode pad 12g is located on the surface of each MOSFET 12U to 12W at the end on the integrated circuit element 25L side in the first direction X and in the center in the second direction Y. A recess is formed at the end on the integrated circuit element 25L side in the first direction X of the source electrode pad 12s to avoid the gate electrode pad 12g. In Figure 28, MOSFETs 12U to 12W are arranged so that their longitudinal direction is aligned with the first direction X. The orientation (positioning) of MOSFETs 12U to 12W can be arbitrarily changed.

[0224] The first wire 62U and the first wire 63U are each connected to the end of the MOSFET 12U in the integrated circuit element 25L, near the end on the first frame 32U side. The first wire 63U is located on the second frame 32V side of the first wire 62U in the first direction X. The second wire 62V and the second wire 63V are each connected to the central part of the integrated circuit element 25L in the first direction X. The second wire 63V is located on the first frame 32U side of the second wire 62V in the first direction X. The third wire 62W and the third wire 63W are each connected to the part of the integrated circuit element 25L on the third frame 32W side. The third wire 63W is located on the second frame 32V side of the third wire 62W in the first direction X.

[0225] The shapes of the gate electrode pads 12g and source electrode pads 12s of MOSFETs 12U to 12W shown in Figure 28 can be applied to the gate electrode pads 11g and source electrode pads 11s of MOSFETs 11U to 11W. In this case, a current of 30A or more can be passed through MOSFETs 11U to 11W and 12U to 12W in semiconductor device 1.

[0226] In the first to third embodiments described above, the shapes of frame 31 and each of frames 32U, 32V, and 32W can be arbitrarily changed. For example, frame 31 and each of frames 32U, 32V, and 32W may be changed to those shown in Figure 29.

[0227] More specifically, the size of the island portion 31a in the second direction Y of the frame 31 in Figure 29 is smaller than the size of the island portion 31a in the second direction Y of the frame 31 in the first to third embodiments described above. The element mounting region Rse of the island portion 31a in Figure 29 has regions Ra1 to Ra3, but does not have regions Ra4 to Ra6.

[0228] The size of the island portion 32a in the second direction Y of each frame 32U, 32V, and 32W in Figure 29 is smaller than the size of the island portion 32a in the second direction Y of each frame 32U, 32V, and 32W in the first to third embodiments described above. The element mounting region Rse of the island portion 32a in Figure 29 has region Ra7 but does not have region Ra8.

[0229] With this configuration, the size of frame 31 and each frame 32U, 32V, and 32W in the second direction Y is reduced, which in turn reduces the size of the sealing resin 50 of the semiconductor device 1 in the second direction Y. Therefore, miniaturization and weight reduction of the semiconductor device 1 can be achieved.

[0230] In the first to third embodiments described above, the number of wires 63U, 63V, and 63W connecting the source electrode pads 12s of the MOSFETs 12U to 12W to the integrated circuit element 25L can be arbitrarily changed. There may be multiple wires 63U, 63V, and 63W. For example, there may be two wires 63U, 63V, and 63W. Also, at least one of the number of first wires 63U, second wires 63V, and third wires 63W may differ from the others.

[0231] In the fifth embodiment described above, the connection configuration in which the MOSFETs 11U to 11W and the diodes 15U, 15V, and 15W of the frame 31 are electrically connected can be arbitrarily changed. For example, the connection configuration between the MOSFETs 11U to 11W and the diodes 15U, 15V, and 15W may be changed as shown in (B1) and (B2) below.

[0232] (B1) As shown in Figure 30, the MOSFET 11U, the first diode 15U, and the first frame 32U are connected by a single first wire 60U. The MOSFET 11V, the second diode 15V, and the second frame 32V are connected by a single second wire 60V. The MOSFET 11W, the third diode 15W, and the third frame 32W are connected by a single third wire 60W. More specifically, the first wire 60U connected to the source electrode pad 11s of the MOSFET 11U has a first portion that extends along the second direction Y to connect to the anode electrode pad 15a of the first diode 15U, and a second portion that extends toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 15a to the wire junction 32f of the first frame 32U. The second wire 60V connected to the source electrode pad 11s of MOSFET 11V has a first portion extending along the second direction Y to connect to the anode electrode pad 15a of the second diode 15V, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 15a to the wire junction 32f of the second frame 32V. The third wire 60W connected to the source electrode pad 11s of MOSFET 11W has a first portion extending along the second direction Y to connect to the anode electrode pad 15a of the third diode 15W, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 15a to the wire junction 32f of the third frame 32W.

[0233] (B2) One or two of the diodes 15U, 15V, and 15W may be omitted. Also, the connection configuration of the wires 60U, 60V, and 60W connected to MOSFETs 11U to 11W can be arbitrarily changed. In one example, as shown in Figure 31, the first diode 15U is omitted from the semiconductor device 1. The first wire 60U connected to the source electrode pad 11s of MOSFET 11U is connected to the wire junction 32f of the first frame 32U. The second wire 60V connected to the source electrode pad 11s of MOSFET 11V has a first portion connected to the anode electrode pad 15a of the second diode 15V and a second portion connecting the anode electrode pad 15a and the wire junction 32f of the second frame 32V, similar to Figure 29. The third wire 60W connected to the source electrode pad 11s of MOSFET 11W is connected to the wire junction 32f of the third frame 32W. The wire 65W for the third diode, which is connected to the anode electrode pad 15a of the third diode 15W, is connected to the wire junction 32f of the third frame 32W.

[0234] In the third embodiment described above, as shown in Figure 32, the wires 63U, 63V, and 63W that connect the source electrode pads 12s of the MOSFETs 12U to 12W of each frame 32U, 32V, and 32W to the integrated circuit element 25L, respectively, may be omitted. The same effects as those of the third embodiment can be obtained with this configuration as well.

[0235] In the fifth embodiment described above, the configuration of the third embodiment, that is, a configuration in which the orientation (positioning) of the MOSFET 12U of the first frame 32U is changed, may be applied. In this case, the connection configuration of each wire 61U, 61V, and 61W can also be changed as shown in Figure 33. More specifically, the MOSFET 12U, the diode 14U, and the frame 35U are connected by one first wire 61U. The MOSFET 12V, the second diode 14V, and the frame 35V are connected by one second wire 61V. The MOSFET 12W, the third diode 14W, and the frame 35W are connected by one third wire 61W. More specifically, the first wire 61U connected to the source electrode pad 12s of MOSFET 12U has a first portion extending along the second direction Y to connect to the anode electrode pad 14a of the first diode 14U, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 14a to the island portion 35a of the frame 35U. The second wire 61V connected to the source electrode pad 12s of MOSFET 12V has a first portion extending along the second direction Y to connect to the anode electrode pad 14a of the second diode 14V, and a second portion extending toward the second side surface 50D as it approaches the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 14a to the island portion 35a of the frame 35V. The third wire 61W connected to the source electrode pad 12s of the MOSFET 12L has a first portion that extends along the second direction Y to connect to the anode electrode pad 14a of the third diode 14W, and a second portion that extends toward the second side surface 50D as it moves toward the fourth side surface 50F of the sealing resin 50 to connect the anode electrode pad 14a to the island portion 35a of the frame 35W.

[0236] In each of the above embodiments, regions Ra7 and Ra8 of the element mounting region Rse of each frame 32U, 32V, and 32W may be formed spaced apart in the second direction Y. In this case, a plurality of recesses 32i may be formed in the portion between region Ra7 and region Ra8 in the second direction Y. Similarly, for frame 31, regions Ra1 to Ra3 and regions Ra4 to Ra6 of the element mounting region Rse may be formed spaced apart in the second direction Y. In this case, a plurality of recesses 31f may be formed in the portion between regions Ra1 to Ra3 and regions Ra4 to Ra6 in the second direction Y.

[0237] In each of the above embodiments, the structures of MOSFETs 11U~11W and 12U~12W can be arbitrarily changed. For example, the structures of MOSFETs 11U~11W and 12U~12W may be changed as shown in (C1) and (C2) below. Since the structures of MOSFETs 11U~11W and 12U~12W are the same, the structure of MOSFET 11U will be described in the explanation of the structures of (C1) and (C2), and the explanation of the structures of MOSFETs 11V, 11W, and 12U~12W will be omitted.

[0238] (C1) As shown in Figure 34, MOSFET11U is N + Type (for example, N-type impurity concentration of 1e18~1e21 cm³) -3 The SiC substrate 110 comprises a SiC substrate 110. The SiC substrate 110 has a Si surface 110A (top surface) and a C surface 110B (bottom surface).

[0239] On the SiC substrate 110, N is present at a lower concentration than that of the SiC substrate 110. - Type (for example, N-type impurity concentration of 1e15~1e17cm) -3 An epitaxial layer 111 made of SiC is stacked on the SiC substrate 110. The epitaxial layer 111, as a semiconductor layer, is formed on the SiC substrate 110 by so-called epitaxial growth. The epitaxial layer 111 formed on the Si surface 110A is grown with the Si surface as the main growth surface. Therefore, the surface 111A of the epitaxial layer 111 formed by growth is a Si surface, just like the surface 110A of the SiC substrate 110.

[0240] On the surface 111A side (Si side) of the epitaxial layer 111, a wide area of ​​P-type body regions 112 is formed in a well-like manner. The concentration of P-type impurities in the body regions 112 is 1e16 to 1e19 cm³. -3 Furthermore, in the epitaxial layer 111, the region on the SiC substrate 110 side (C-plane side) of the body region 112 maintains the same state as after epitaxial growth. - This is the drain region 113 (drift region) of the type.

[0241] Within the body region 112, N is present over almost the entire surface 111A side. + Type (for example, N-type impurity concentration of 1e18~1e21 cm³) -3 ) Source region 114 and P located on the SiC substrate 110 side (downward) from this source region 114 + Type (for example, P-type impurity concentration of 1e18~1e21 cm³) -3 Body contact regions 115 are formed in the epitaxial layer 111. A large number of body contact regions 115 are formed in a matrix. Source trenches 116 are formed in the same number as the body contact regions 115 so as to penetrate each body contact region 115. A grid-like gate trench 117 is formed so as to surround each body contact region 115 where a source trench 116 is formed. As a result, a large number of unit cells 118, each functioning as a field-effect transistor, are formed in the epitaxial layer 111. That is, in a unit cell 118, the body contact region 115 is formed so as to surround the source trench 116, and a body region 112 is formed so as to surround the body contact region 115. The side of the body region 112 opposite to the body contact region 115 is exposed to the side of the gate trench 117. In a unit cell 118, the depth direction of the gate trench 117 is the gate length direction, and the circumferential direction of each unit cell 118, which is perpendicular to the gate length direction, is the gate width direction.

[0242] Both the source trench 116 and the gate trench 117 extend from the surface 111A of the epitaxial layer 111, through the body region 112, and reach the drain region 113. In this embodiment, the depth of the source trench 116 and the depth of the gate trench 117 are equal. The distance D1 between the side surface 116a of the source trench 116 and the side surface 117a of the gate trench 117 is, for example, 0.5 μm to 3 μm. If the distance D1 is within the range of 0.5 μm to 3 μm, the increase in resistance (on-resistance) when each unit cell 118 is turned on can be suppressed, and the electric field applied to the bottom of the gate trench 117 can be mitigated.

[0243] The gate trench 117 has a U-shaped cross-section, with both corners 117b at its bottom curving toward the drain region 113 in a direction perpendicular to the gate width (opposite direction to the adjacent unit cell 118), and its opposing sides 117a and bottom surface 117c being continuous via a curved surface. Furthermore, the source trench 116, similar to the gate trench 117, has a U-shaped cross-section, with its opposing sides 116a and bottom surface 116b being continuous via a curved surface. This allows the electric field applied to both corners 117b at the bottom of the gate trench 117 to be dispersed to the parts other than the corners 117b when the unit cell 118 is turned off. Therefore, dielectric breakdown in the portion of the gate insulating film 120 above the bottom surface 117c (insulating film bottom 120a), which will be described later, can be suppressed.

[0244] In the drain region 113, an impurity-activated layer 119 is formed as an impurity layer formed by the implantation of P-type impurities (e.g., boron (B), aluminum (Al), etc.) from the bottom surface 117c of the gate trench 117 to the middle of its thickness. The impurity-activated layer 119 is formed in a grid shape that overlaps the gate trench 117 in a plan view, and is narrower than the distance between adjacent unit cells 118. The depth of the impurity-activated layer 119 in this embodiment is, for example, 0.1 μm to 0.5 μm.

[0245] The Impreza active layer 119 is a high-resistance layer with a higher resistance value than the surrounding region (e.g., drain region 113) in the epitaxial layer 111. The resistance value of the Impreza active layer 119 is, for example, several tens of kΩ / □ to several hundred kΩ / □. The P-type impurity concentration of the Impreza active layer 119 is, for example, 1e16 to 1e21 cm³. -3 That is the case.

[0246] A gate insulating film 120 is formed on the inner surface of the gate trench 117, covering its entire surface. The gate insulating film 120 consists of a nitrogen-containing oxide film, for example, a silicon nitride oxide film formed by thermal oxidation using a gas containing nitrogen and oxygen. The nitrogen content (nitrogen concentration) in the gate insulating film 120 is, for example, 0.1 to 10%.

[0247] The gate insulating film 120 has a thickness T4 on the bottom surface 117c of the gate trench 117 (insulating film bottom portion 120a) that is smaller than the thickness T3 on the side surface 117a of the gate trench 117 (insulating film side portion 120b). The ratio of thickness T4 to thickness T3 (T4 / T3) is 0.3 to 1.0, preferably 0.5 to 1.0. Thickness T3 is 300 to 1000 Å, and thickness T4 is 150 to 500 Å. The gate electrode 121 is embedded in the gate trench 117 by filling the inside of the gate insulating film 120 with a polysilicon material doped with a high concentration of N-type impurities.

[0248] An interlayer insulating film 122 made of silicon oxide (SiO2) is laminated on the epitaxial layer 111. Contact holes 123 are formed in the interlayer insulating film 122 and the gate insulating film 120, exposing the surface of the source trench 116 and source region 114 of each unit cell 118.

[0249] On the interlayer insulating film 122, a source wiring 124 is formed. The source wiring 124 enters all the source trenches 116 of the unit cells 118 collectively through each contact hole 123, and contacts the drain region 113, the body contact region 115, and the source region 114 in order from the bottom side of the source trench 116 in each unit cell 118. That is, the source wiring 124 is a common wiring for all the unit cells 118. And, an interlayer insulating film (not shown) is formed on this source wiring 124, and the source wiring 124 is electrically connected to the source electrode pad 11s through the interlayer insulating film. On the other hand, the gate electrode pad 11g is electrically connected to the gate electrode 121 through a gate wiring (not shown) routed on the above interlayer insulating film (not shown).

[0250] The source wiring 124 has a polysilicon layer 125, an intermediate layer 126, and a metal layer 127 in order from the contact side with the epitaxial layer 111. The polysilicon layer 125 is a doped layer formed using doped polysilicon doped with an impurity. For example, it is a high-concentration doped layer doped with an impurity at a high concentration of 1e19 to 1e21 cm -3 When forming the polysilicon layer 125 as a doped layer (including a high-concentration doped layer), N-type impurities such as nitrogen (N), phosphorus (P), arsenic (As), and P-type impurities such as aluminum (Al), boron (B), etc. can be used as the impurity. Also, the thickness of the polysilicon layer 125 is, for example, 5000 to 10000 Å.

[0251] The polysilicon layer 125 of the present embodiment is formed so as to cover the entire surface of the unit cell 118 exposed in the contact hole 123, and contacts the drain region 113, the body contact region 115, and the source region 114 in the source trench 116.

[0252] By using polysilicon for the contact layer with the drain region 113, body contact region 115, and source region 114 in the source wiring 124, the source wiring 124 can be ohmically joined to both the body contact region 115 and the source region 114, which are high-concentration impurity regions. On the other hand, for the low-concentration drain region 113, a heterojunction with a smaller junction barrier than the diffusion potential of the body diode 128 (a PN diode formed by the junction of the body region 112 and the drain region 113) inherent in the MOSFET 11U can be formed.

[0253] Incidentally, when a current flows through the body diode 128 inherent in the MOSFET 11U, holes that have moved from the body region 112 to the drain region 113 recombine with electrons in the drain region 113, and due to the binding energy generated at that time, defects in the SiC crystal in the epitaxial layer 111 may spread in the plane. Since this crystal defect has a high resistance value, if the crystal defect expands toward the gate trench 117 side, it may interfere with the normal transistor operation and increase the on-resistance.

[0254] In this regard, as shown in FIG. 34, if a heterojunction is formed by the contact between the polysilicon layer 125 and the drain region 113, even when a reverse voltage is applied between the source and drain and a current flows through the body diode 128, the current can flow preferentially to the heterojunction side rather than the body diode 128 side. As a result, the expansion of the SiC crystal defect can be suppressed, and an increase in the on-resistance can be suppressed.

[0255] The intermediate layer 126 is laminated on the polysilicon layer 125 and is composed of a single layer of a layer containing titanium (Ti) or a plurality of layers having such a layer. The layer containing titanium can be formed using titanium, titanium nitride (TiN), etc. The thickness of the intermediate layer 126 is, for example, 200 to 500 nm.

[0256] The metal layer 127 is laminated on the intermediate layer 126 and is formed using, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), or alloys thereof, or metal materials containing them. The metal layer 127 forms the outermost layer of the source wiring 124. The thickness of the metal layer 127 is 1 to 5 μm.

[0257] As a specific example of the combination of polysilicon layer 125, intermediate layer 126, and metal layer 127 described above, a laminated structure (Poly-Si / Ti / TiN / Al) can be exemplified in which Poly-Si (polysilicon layer 125), Ti (intermediate layer 126), TiN (intermediate layer 126), and Al (metal layer 127) are stacked in that order.

[0258] A drain electrode 129 is formed on the back surface 110B of the SiC substrate 110, covering its entire surface. This drain electrode 129 is a common electrode for all unit cells 118. As an example of the drain electrode 129, a laminated structure (Ti / Al) in which titanium (Ti) and aluminum (Al) are stacked in order from the SiC substrate 110 side can be exemplified.

[0259] When a predetermined potential difference is generated between the source electrode pad 11s (source wiring 124) and the drain electrode 129 (source-drain), a predetermined voltage (a voltage greater than or equal to the gate threshold voltage) is applied to the gate electrode pad 11g. As a result, a channel is formed near the interface between the gate insulating film 120 and the body region 112 due to the electric field from the gate electrode 121. This causes current to flow between the source wiring 124 and the drain electrode 129, and the MOSFET 11U turns on.

[0260] (C2) As shown in Figure 35, MOSFET11U is N + The SiC substrate 130 is provided. The surface 130A of the SiC substrate 130 is made of SiC that is doped with a lower concentration of N-type impurities than the SiC substrate 130. -A series of epitaxial layers 131 are stacked. The surface 131A of the epitaxial layer 131 is composed of, for example, the (0001) plane of SiC.

[0261] The epitaxial layer 131 retains the state it was in after epitaxial growth, N - A drain region 132 of type N is formed. In addition, a P-type body region 133 is formed on the surface of the epitaxial layer 131. Although not shown in Figure 35, multiple body regions 133 are formed at regular intervals, and they are parallel to each other and extend in the same direction (perpendicular to the plane of the paper in Figure 35), arranged, for example, in a stripe or matrix (array) pattern. The drain region 132 is exposed between adjacent body regions 133. In addition, on the surface of the body region 133, N is formed at intervals from its periphery. + A source region 134 of type 134 is formed.

[0262] A gate insulating film 135 is formed on the surface 131A of the epitaxial layer 131, spanning the drain region 132, the body region 133, and the source region 134. The gate insulating film 135 is made of, for example, silicon oxide (SiO2). A gate electrode 136 is formed on the gate insulating film 135, made of polysilicon doped with a high concentration of N-type impurities. The gate electrode 136 faces the drain region 132, the body region 133, and the source region 134 via the gate insulating film 135.

[0263] An interlayer insulating film 137 made of silicon oxide (SiO2) is laminated on the epitaxial layer 131. Source wiring 138 is formed on the interlayer insulating film 137. The source wiring 138 is electrically connected to the body region 133 and the source region 134 via contact holes 139 formed in the interlayer insulating film 137.

[0264] The gate electrode 136 is electrically connected to the gate wiring 140 via a contact hole (not shown) formed in the interlayer insulating film 137. A drain electrode 141 is also formed on the back surface 130B of the SiC substrate 130.

[0265] By applying a positive voltage of an appropriate magnitude to the drain electrode 141 while controlling the potential of the gate electrode 136, a channel can be formed near the interface between the gate insulating film 135 and the body region 133 due to the electric field from the gate electrode 136. This allows current to flow between the source wiring 138 and the drain electrode 141.

[0266] In the fourth and fifth embodiments described above, the structures of each diode 14U, 14V, 14W and each diode 15U, 15V, 15W can be arbitrarily changed. For example, the structures of each diode 14U, 14V, 14W and each diode 15U, 15V, 15W may be changed to a planar type structure as shown in Figure 36. Since the structures of each diode 14U, 14V, 14W and each diode 15U, 15V, 15W are the same, the following description will explain the structure of the first diode 14U, and the explanation of the structures of the other diodes 14V, 14W, 15U, 15V, 15W will be omitted.

[0267] As shown in Figure 36, the first diode 14U is N + Type (for example, N-type impurity concentration of 1e18~1e21 cm³) -3 The semiconductor substrate 150 is made of N-type silicon (Si). A cathode electrode 151 is formed on the back surface 150B of the semiconductor substrate 150 so as to cover its entire surface. The cathode electrode 151 is made of a metal that makes ohmic contact with N-type silicon (for example, gold (Au), nickel (Ni), silicide, cobalt (Co), etc.).

[0268] The surface 150A of the semiconductor substrate 150 has a lower concentration of N than the semiconductor substrate 150. -An epitaxial layer 152 made of silicon of a specific type (for example, with an N-type impurity concentration of 1e15 to 1e17 cm⁻³) is laminated. The thickness of the epitaxial layer 152 is, for example, 2 to 10 μm.

[0269] A field insulating film 153 made of silicon oxide (SiO2) is laminated on the surface 152A of the epitaxial layer 152. The thickness of the field insulating film 153 is, for example, 1000 Å or more, preferably 7000 Å to 40000 Å. The field insulating film 153 may be made of other insulating materials such as silicon nitride (SiN).

[0270] The field insulating film 153 has an opening 153a that exposes the central part of the epitaxial layer 152. An anode electrode 154 is formed on the field insulating film 153. The anode electrode 154 fills the opening 153a of the field insulating film 153 and extends outward in a flange-like manner so as to cover the peripheral edge 153b of the opening 153a from above. In other words, the peripheral edge 153b of the opening 153a of the field insulating film 153 is sandwiched from both above and below on its entire circumference by the epitaxial layer 152 and the anode electrode 154.

[0271] The anode electrode 154 in Figure 36 has a multilayer structure (a two-layer structure in Figure 36) consisting of a Schottky metal 155 bonded to the epitaxial layer 152 within the opening 153a of the field insulating film 153, and an electrode metal 156 laminated on the Schottky metal 155.

[0272] Schottky metal 155 is made of a metal (e.g., titanium (Ti), molybdenum (Mo), palladium (Pd), etc.) that forms a Schottky junction by bonding with N-type silicon. The Schottky metal 155 bonded to the epitaxial layer 152 forms a Schottky barrier (potential barrier) of, for example, 0.52 eV to 0.9 eV between itself and the silicon semiconductor constituting the epitaxial layer 152. The thickness of the Schottky metal 155 is, for example, 0.02 to 0.20 μm.

[0273] The electrode metal 156 is a portion that is exposed on the outermost surface of the first diode 14U in the anode electrode 154 and to which a wire 65U for the first diode or the like is joined. That is, the electrode metal 156 constitutes the anode electrode pad 14a. The electrode metal 156 is made of, for example, aluminum (Al). The thickness of the electrode metal 156 is thicker than that of the Schottky metal 155 and is, for example, 0.5 to 5.0 μm.

[0274] A surface protection film 157 made of silicon nitride (SiN) is formed on the outermost surface of the first diode 14U. An opening 157a for exposing the electrode metal 156 is formed in the central portion of the surface protection film 157. A wire 65U for the first diode or the like is joined to the electrode metal 156 through the opening 157a.

[0275] A region where the Schottky metal 155 makes Schottky contact with the surface 152A of the epitaxial layer 152 in the surface 152A of the epitaxial layer 152 is defined as an active region 158, and a region surrounding the active region 158 is defined as an outer peripheral region 159. An outer peripheral trench 160 dug down from the surface 152A of the epitaxial layer 152 is formed at the boundary between the active region 158 and the outer peripheral region 159 in the surface layer portion of the epitaxial layer 152. The outer peripheral trench 160 is annular in plan view and is formed along the boundary between them so as to straddle the active region 158 and the outer peripheral region 159. The bottom surface of the outer peripheral trench 160 includes a flat surface along the surface 152A of the epitaxial layer 152 and the surface 150A of the semiconductor substrate 150. Therefore, the cross section of the outer peripheral trench 160 is substantially rectangular.

[0276] An insulating layer 161 made of, for example, silicon oxide (SiO2) is formed over the entire inner wall surface (side surface and bottom surface) of the outer peripheral trench 160. The thickness of the insulating layer 161 is, for example, 0.2 to 0.5 μm.

[0277] Within the outer trench 160, a conductor 162 made of polysilicon is provided, connected to the Schottky metal 155 and facing the entire inner wall surface (including the sides and bottom surface) of the outer trench 160 via an insulating layer 161. The conductor 162 may be provided so as to fill the space within the outer trench 160 where the insulating layer 161 is formed, or it may be formed as a film along the inner surface of the insulating layer 161. Thus, the first diode 14U is a planar Schottky barrier diode in which the surface of the epitaxial layer 152, to which the Schottky metal 155 is in Schottky contact, is flat.

[0278] In the second embodiment described above, the position of the diode 13 within the integrated circuit element 25L can be arbitrarily changed. Preferably, the diode 13 is arranged around the common-source circuit 21a of each drive circuit 21UL, 21VL, and 21WL. This makes it possible to shorten the length of the limiting wire 21e connecting the diode 13 and the output wire 21d of the common-source circuit 21a. It is even more preferable that the diode 13 is provided in the second direction Y between the common-source circuit 21a of each drive circuit 21UL, 21VL, and 21WL and the output terminal 25a and input terminal 25b. This makes it possible to further shorten the length of the limiting wire 21e. The diode 13 may also be provided as a semiconductor chip separate from the integrated circuit element 25L.

[0279] In the embodiments described above, a semiconductor device 1 including a first inverter circuit 10U, a second inverter circuit 10V, and MOSFETs 11U~11W, 12U~12W of a third inverter circuit 10W has been described, but the configuration of the semiconductor device 1 is not limited thereto. For example, as shown in Figures 37 and 38, the semiconductor device 1 may include only one inverter circuit.

[0280] More specifically, as shown in Figure 37, the semiconductor device 1 comprises one inverter circuit 10A as a drive unit 10 and one drive circuit 21A and one logic circuit 22A as a control circuit 20. The inverter circuit 10A has MOSFET 11U and MOSFET 12L. The drain of MOSFET 11U is connected to an external power supply, and the source of MOSFET 11U is connected to the drain of MOSFET 12L. The source of MOSFET 12L is grounded. The drive circuit 21A has drive circuit 21AU and drive circuit 21AL, and the logic circuit 22A has logic circuit 22AU and logic circuit 22AL. Drive circuit 21AU is connected to the gate of MOSFET 11U and outputs a gate drive signal to its gate. Drive circuit 21AL is connected to the gate of MOSFET 12L and outputs a gate drive signal to its gate. Logic circuit 22AU is connected to drive circuit 21AU and outputs a signal to drive circuit 21AU for drive circuit 21AU to generate a gate drive signal. The logic circuit 22AL is connected to the drive circuit 21AL and outputs a signal to the drive circuit 21AL for the drive circuit 21AL to generate a gate drive signal.

[0281] As shown in Figure 38, the semiconductor device 1 is provided with a MOSFET 11U, a MOSFET 12L, and an integrated circuit element 25A including a drive circuit 21A and a logic circuit 22A, each as a semiconductor chip. The semiconductor device 1 includes a lead 200 on which the MOSFET 11U, MOSFET 12L, and control circuit 20 are mounted, and a sealing resin 220 that seals the MOSFET 11U, MOSFET 12L, and integrated circuit element 25A. The sealing resin 220 is formed of, for example, a black epoxy resin and is rectangular in shape in a plan view. The sealing resin 220 has a first side surface 221 and a second side surface 222 as sides along its longitudinal direction, and a third side surface 223 and a fourth side surface 224 as sides along a direction perpendicular to the longitudinal direction in a plan view. In the following description, the direction along the longitudinal direction of the sealing resin 220 is defined as the "first direction V," and the direction perpendicular to the first direction V in a plan view is defined as the "second direction W."

[0282] The lead 200 has a frame 201, a frame 205, a control frame 209, and a plurality of terminal frames, namely the first to sixth terminal frames 213 to 218. Frame 201 is positioned on the first side surface 221, which is one end of the sealing resin 220 (the left end in Figure 35) in the first direction V, and frame 205 is positioned on the second side surface 222, which is the other end of the sealing resin 220 (the right end in Figure 35) in the first direction V. Frames 201 and 205 are formed to be symmetrical with respect to a center line CL extending along the first direction V at the center of the sealing resin 220 in the second direction W. The control frame 209 and the first to sixth terminal frames 213 to 218 are positioned on the fourth side surface 224, which is one end of the sealing resin 220 (the lower end in Figure 35) in the first direction V.

[0283] Frame 201 is a lead frame for electrically connecting the drain of MOSFET 11U to an external power supply and constitutes the VDC terminal. Frame 201 has an island portion 202, a terminal portion 203, and a connection portion 204. The island portion 202, terminal portion 203, and connection portion 204 are integrally formed.

[0284] Frame 205 is a lead frame for electrically connecting the drain of MOSFET 12L to equipment or electronic components electrically connected to semiconductor device 1, and constitutes an output terminal (OUT terminal). Frame 205 has an island portion 206, a terminal portion 207, and a connection portion 208. The island portion 206, terminal portion 207, and connection portion 208 are integrally formed.

[0285] Island portion 202 of frame 201 and island portion 206 of frame 205 are positioned closer to the third side surface 223 of the sealing resin 220 in the second direction W, and are arranged side by side in the second direction W. Island portions 202 and 206 are rectangular in shape with the second direction W being the longitudinal direction in a plan view. Island portions 202 and 206 protrude from the third side surface 223 of the sealing resin 220 toward the second direction W. Island portions 202 and 206 are symmetrical with respect to the center line CL.

[0286] The connection portion 204 of frame 201 extends from the end of the sealing resin 220 on the first side surface 221 side and the fourth side surface 224 side of the island portion 202 toward the fourth side surface 224. The terminal portion 203 of frame 201 extends from the connection portion 204 along the second direction W. The terminal portion 203 and the connection portion 204 are positioned on the first side surface 221 side of the sealing resin 220 more than the frame 205, the control frame 209, and the first to sixth terminal frames 213 to 218.

[0287] The connection portion 208 of frame 205 extends from the end of the sealing resin 220 on the second side 222 side and the fourth side 224 side of the island portion 206 toward the fourth side 224. The terminal portion 207 of frame 205 extends from the connection portion 208 along the second direction W. The terminal portion 207 and the connection portion 208 are positioned on the second side 222 side of the sealing resin 220 more than the frame 201, the control frame 209, and the first to sixth terminal frames 213 to 218.

[0288] The control frame 209 and the first to sixth terminal frames 213 to 218 are positioned on the fourth side surface 224 side of the sealing resin 220, further than the island portion 202 of frame 201 and the island portion 206 of frame 205 in the second direction W, and are positioned between the connection portion 204 of frame 201 and the connection portion 208 of frame 205 in the second direction W.

[0289] The control frame 209 is a lead frame for grounding the integrated circuit element 25A and constitutes the GND terminal. The control frame 209 has an island portion 210, a terminal portion 211, and a connection portion 212. The island portion 210, the terminal portion 211, and the connection portion 212 are integrally formed.

[0290] The island portion 210 is formed in a rectangular shape with the first direction V being the longitudinal direction. The island portion 210 is positioned closer to the first side surface 221 of the sealing resin 220 in the first direction V. The island portion 210 is positioned differently from the island portion 202 of frame 201 and the island portion 206 of frame 205 in the second direction W. More specifically, the island portion 210 is positioned closer to the fourth side surface 224 of the sealing resin 220 than the island portions 202 and 206, and is positioned to overlap with the island portions 202 and 206 when viewed from the second direction W. The island portion 210 is positioned closer to the connection portion 204 of frame 201 than to the connection portion 208 of frame 205 in the second direction W.

[0291] The connection portion 212 of the control frame 209 extends from approximately the center of the island portion 210 in the first direction V toward the fourth side surface 224 of the sealing resin 220. The terminal portion 211 of the control frame 209 extends along the second direction W from the end of the connection portion 212 on the fourth side surface 224 side of the sealing resin 220.

[0292] The first terminal frame 213 is a lead frame for grounding the source of MOSFET 12L and constitutes the PGND terminal. The second terminal frame 214 constitutes the VCC terminal, which is the application terminal for the power supply voltage VCC. The third terminal frame 215 constitutes a short-circuit detection terminal (FOB terminal) that detects a state in which the voltage applied to the OUT terminal (frame 205) is short-circuited to a high-voltage application terminal (or a similarly high-potential terminal). The fourth terminal frame 216 constitutes the HIN terminal to which the gate drive signal voltage input to the gate of MOSFET 11U from an external gate drive circuit (not shown) of the semiconductor device 1 is applied. The fifth terminal frame 217 constitutes the LIN terminal to which the gate drive signal voltage input to the gate of MOSFET 12L from the gate drive circuit is applied. The sixth terminal frame 218 constitutes the VB terminal, which is the application terminal for the boost voltage VB, which is the power supply voltage VCC boosted.

[0293] The first terminal frame 213 and the fourth to sixth terminal frames 216 to 218 are positioned between the connection portion 212 of the control frame 209 and the connection portion 208 of the frame 205 in the first direction V. The second terminal frame 214 and the third terminal frame 215 are positioned between the connection portion 212 of the control frame 209 and the connection portion 204 of the frame 201 in the first direction V.

[0294] The first terminal frame 213 has a rectangular island portion 213a whose longitudinal direction is in the second direction W. The island portion 213a is located between the island portion 210 of the control frame 209 and the connection portion 208 of the frame 205 in the first direction V. The island portion 213a is located adjacent to the island portion 206 of the frame 205 in the second direction W. The fourth to sixth terminal frames 216 to 218 are located on the fourth side surface 224 side of the sealing resin 220, closer to the island portion 210 of the control frame 209 and the island portion 213a of the first terminal frame 213, in the second direction W. The second terminal frame 214 and the third terminal frame 215 are located on the fourth side surface 224 side of the sealing resin 220, closer to the island portion 210 of the control frame 209.

[0295] The MOSFET 11U is mounted on the island portion 202 of the frame 201 by soldering or the like, near the fourth side surface 224 of the sealing resin 220. That is, the drain of the MOSFET 11U is electrically connected to the island portion 202 of the frame 201. The MOSFET 11U is positioned such that its gate electrode pad 11g faces both the first side surface 221 and the fourth side surface 224 of the sealing resin 220.

[0296] MOSFET12L is mounted on the island portion 206 of frame 205 near the fourth side surface 224 of the sealing resin 220 by solder or the like. That is, the drain of MOSFET12L is electrically connected to the island portion 206 of frame 205. MOSFET12L is positioned such that its gate electrode pad 12g faces both the MOSFET11U side and the fourth side surface 224 of the sealing resin 220. In other words, in Figure 35, the orientation (positioning) of MOSFET11U and MOSFET12L are the same.

[0297] The integrated circuit element 25A is mounted on the island portion 210 of the control frame 209 by solder or the like. The integrated circuit element 25A is positioned closer to MOSFET 11U than MOSFET 12L in the second direction W.

[0298] The source electrode pad 11s of MOSFET 11U and the frame 205 are electrically connected by wire 60. This electrically connects the source of MOSFET 11U to the drain of MOSFET 12L. Wire 60 is connected to the portion of the island portion 206 of the frame 205 that is on the third side surface 223 side of the sealing resin 220, closer to MOSFET 12L. The source electrode pad 11s of MOSFET 11U and the integrated circuit element 25A are connected by wire 62, and the gate electrode pad 11g of MOSFET 11U and the integrated circuit element 25A are also connected by wire 62. The control wire 62 connected to the gate electrode pad 11g is positioned closer to the first side surface 221 of the sealing resin 220 than wire 63, which is an example of a limiting wire connected to the source electrode pad 11s.

[0299] The source electrode pad 12s of MOSFET 12L and the island portion 213a of the first terminal frame 213 are electrically connected by wire 61. Wire 61 is connected to the island portion 213a of the first terminal frame 213. The gate electrode pad 12g of MOSFET 12L and the integrated circuit element 25A are connected by wire 62, and the source electrode pad 12s of MOSFET 12L and the integrated circuit element 25A are connected by sense wire 63. Wire 62 connected to the gate electrode pad 12g is positioned closer to MOSFET 11U than wire 63 connected to the source electrode pad 12s. Wire 63 is connected to the source of the second MOSFET 21c of the source-grounded circuit 21a in the drive circuit 21AL of the integrated circuit element 25A via a limiting wire 21e (see Figure 37). This makes it possible to obtain effects similar to those of (1-1) of the first embodiment described above.

[0300] Furthermore, the integrated circuit element 25A is connected to the frame 201, the control frame 209, and the first to sixth terminal frames 213 to 218 by wires 62. More specifically, the integrated circuit element 25A is connected to the connection portion 204 of the frame 201 by one wire 62. The integrated circuit element 25A is connected to the connection portion 212 of the control frame 209 by one wire 62. The integrated circuit element 25A is connected to the portion of the sealing resin 220 on the fourth side surface 224 side of the island portion 213a of the first terminal frame 213 by one wire 62. The integrated circuit element 25A is connected to the second terminal frame 214 by two wires 62. The integrated circuit element 25A is connected to the third to sixth terminal frames 215 to 218 by one wire 62 each.

[0301] As shown in Figures 37 and 38, the semiconductor device 1 includes a limiting unit CV that suppresses fluctuations in the source-gate voltage of the MOSFET 12L based on voltage fluctuations at the source of the MOSFET 12L. The limiting unit CV has a limiting path RS that electrically connects the control path RC to the source of the MOSFET 12L. The limiting path RS includes a wire 63 that connects the source electrode pad 12s of the MOSFET 12L to the input terminal 25b of the integrated circuit element 25A, and a limiting wiring 21e of the drive circuit 21AL. That is, the wire 63 constitutes a part of the limiting path RS.

[0302] Furthermore, the semiconductor device 1 is electrically connected to the gate of the drive circuit 21AL and the MOSFET 12L, and includes a control path RC (see Figure 37) through which the drive signal of the drive circuit 21AL is transmitted. The control path RC includes a wire 62 connecting the gate electrode pad 12g of the MOSFET 12L and the output terminal 25a of the integrated circuit element 25A, and the output wiring 21d of the drive circuit 21AL. In other words, the wire 62 connecting the gate electrode pad 12g of the MOSFET 12L and the output terminal 25a constitutes a part of the control path RC.

[0303] In the modified example shown in Figure 38, a diode 13 may be added between the wire 62 connected to the source electrode pad 12s of the MOSFET 12L and the output wiring 21d of the drive circuit 21AL. This allows for effects similar to those of (2-1) in the second embodiment described above. The diode 13 may be provided inside the integrated circuit element 25A, or it may be provided as a separate semiconductor chip from the integrated circuit element 25A.

[0304] In the modified example shown in Figure 38, the orientation of MOSFETs 11U and 12L can be arbitrarily changed. In one example, as shown in Figure 39, the orientation of MOSFET 11U is changed so that the gate electrode pad 11g of MOSFET 11U is closer to the control circuit 20. More specifically, MOSFET 11U is positioned such that the gate electrode pad 11g of MOSFET 11U is located on the surface of MOSFET 11U on both the control circuit 20 side and the MOSFET 12L side. In this case, the wire 62 connecting the control circuit 20 and the gate electrode pad 11g of MOSFET 11U is positioned on the MOSFET 12L side than the wire 62 connecting the control circuit 20 and the source electrode pad 11s of MOSFET 11U. Note that in the modified example shown in Figure 39, the wire 62 connecting the source electrode pad 12s of MOSFET 12L and the control circuit 20 may be omitted.

[0305] In each of the above embodiments, the orientation (positioning) of the frame 31 of MOSFETs 11U to 11W with respect to the island portion 31a can be arbitrarily changed. For example, the orientation (positioning) of MOSFET 11U may be changed so that the gate electrode pad 11g of MOSFET 11U is closer to the integrated circuit element 25H. With this configuration, effects similar to those of the third embodiment can be obtained.

[0306] <Note> [Note A1] An inverter circuit including a first switching element to which a power supply voltage is supplied, and a second switching element having a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal, A first control circuit for controlling the first switching element, A second control circuit for controlling the second switching element, The system includes a limiting unit that suppresses voltage fluctuations between the second terminal and the control terminal based on voltage fluctuations at the second terminal of the second switching element. Semiconductor equipment.

[0307] [Appendix A2] The inverter circuit is spaced apart from the aforementioned inverter circuit, and the second control circuit is mounted on it, and the integrated circuit element has output terminals and input terminals electrically connected to the second control circuit, The semiconductor device includes control wires that electrically connect the control terminal and the output terminal. The limiting section is provided separately from the control wire and includes a limiting wire that electrically connects the input terminal and the second terminal. The semiconductor device described in Appendix A1.

[0308] [Note A3] The second control circuit has a drive signal output circuit that outputs a drive signal, The semiconductor device electrically connects the drive signal output circuit and the control terminal and includes a control path through which the drive signal is transmitted. The limiting unit has a limiting path that electrically connects the control path and the second terminal of the second switching element. The control wire constitutes a part of the control path, The aforementioned limiting wire constitutes a part of the limiting path. Semiconductor equipment as described in Appendix A2.

[0309] [Note A4] The control path is provided within the integrated circuit element and has output wiring that electrically connects the drive signal output circuit and the output terminal. The restriction path is provided within the integrated circuit element and includes a restriction wiring that electrically connects the input terminal and the output wiring of the integrated circuit element. Semiconductor equipment as described in Appendix A3.

[0310] [Note A5] The limiting section has a diode provided in the limiting path, The anode of the diode is electrically connected to the second terminal of the second switching element. The cathode of the diode is electrically connected to the drive signal output circuit. Semiconductor equipment as described in Appendix A3 or A4.

[0311] [Note A6] The diode is mounted on the integrated circuit element and provided on the limiting wiring. The semiconductor device described in Appendix A5, which references Appendix A4.

[0312] [Note A7] The diode is arranged around the drive signal output circuit within the integrated circuit element. The semiconductor device described in Appendix A6.

[0313] [Note A8] The second control circuit further includes a logic circuit that controls the drive signal output circuit, In the aforementioned integrated circuit element, the drive signal output circuit is located on the second switching element side of the logic circuit. The diode is positioned on the second switching element side with respect to the drive signal output circuit. The semiconductor device described in Appendix A7.

[0314] [Note A9] The second switching element includes a ground electrode pad as the second terminal and a control electrode pad as the control terminal, The control wire is connected to the output terminal of the integrated circuit element and the control electrode pad. The limiting wire is connected to the ground electrode pad and the input terminal of the integrated circuit element. A semiconductor device as described in any one of the appendices A2 to A8.

[0315] [Note A10] A power wire is connected to the ground electrode pad for connecting the ground electrode pad to the ground. The diameter of the limiting wire is smaller than the diameter of the power wire. The semiconductor device described in Appendix A9.

[0316] [Note A11] In a plan view, the limiting wire is connected to a location closer to the integrated circuit element than the location on the ground electrode pad where the power wire is connected. The semiconductor device described in Appendix A10.

[0317] [Note A12] The inverter circuit includes a first inverter circuit, a second inverter circuit, and a third inverter circuit connected in parallel with each other. The aforementioned limiting section includes a first limiting section, a second limiting section, and a third limiting section. The first limiting unit suppresses voltage fluctuations between the second terminal of the second switching element in the first inverter circuit and the control terminal, based on voltage fluctuations at the second terminal of the second switching element in the first inverter circuit. The second limiting unit suppresses voltage fluctuations between the second terminal and the control terminal of the second switching element in the second inverter circuit, based on voltage fluctuations at the second terminal of the second switching element in the second inverter circuit. The third limiting unit suppresses voltage fluctuations between the second terminal and the control terminal of the second switching element in the third inverter circuit, which are caused by voltage fluctuations at the second terminal of the second switching element in the third inverter circuit. A semiconductor device as described in any one of the appendices A1 to A11.

[0318] [Note A13] The second control circuit is mounted on an integrated circuit element, The second control circuit includes a third control circuit for controlling the second switching element of the first inverter circuit, a fourth control circuit for controlling the second switching element of the second inverter circuit, and a fifth control circuit for controlling the second switching element of the third inverter circuit. The second switching element of the first inverter circuit, the second switching element of the second inverter circuit, and the second switching element of the third inverter circuit are each formed in a rectangular shape in a plan view and have a ground electrode pad as the second terminal and a control electrode pad as the control terminal. The integrated circuit element has a first input terminal and a first output terminal electrically connected to the third control circuit, a second input terminal and a second output terminal electrically connected to the fourth control circuit, and a third input terminal and a third output terminal electrically connected to the fifth control circuit. The aforementioned semiconductor device is A first frame on which the second switching element of the first inverter circuit is mounted, The second frame on which the second switching element of the second inverter circuit is mounted, The third frame on which the second switching element of the third inverter circuit is mounted, A first control wire connects the control electrode pad of the second switching element of the first inverter circuit to the first output terminal, A first limiting wire connects the ground electrode pad of the second switching element of the first inverter circuit to the first input terminal, A second control wire connects the control electrode pad of the second switching element of the second inverter circuit to the second output terminal, A second limiting wire connects the ground electrode pad of the second switching element of the second inverter circuit to the second input terminal, A third control wire connects the control electrode pad of the second switching element of the third inverter circuit to the third output terminal, A third limiting wire connects the ground electrode pad of the second switching element of the third inverter circuit to the third input terminal, Equipped with, The first frame, the second frame, and the third frame are arranged spaced apart from each other, and the first frame and the third frame are arranged along the direction of the arrangement of the third control circuit, the fourth control circuit, and the fifth control circuit, with the first frame and the third frame flanking the second frame. In a plan view, the second frame is positioned so as to face the integrated circuit elements in a direction perpendicular to the arrangement direction. The semiconductor device described in Appendix A12.

[0319] [Note A14] The control electrode pads of the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are formed at one of the four corners of the second switching element in a plan view. At least one of the second switching element of the first inverter circuit and the second switching element of the third inverter circuit is positioned in a different orientation from that of the second switching element of the second inverter circuit, such that the control electrode pad of the second switching element is closer to the integrated circuit element. The semiconductor device described in Appendix A13.

[0320] [Note A15] An inverter circuit including a first switching element to which a power supply voltage is supplied, and a second switching element having a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal, The system includes a limiting unit that suppresses fluctuations in the potential of the second terminal of the second switching element when the first switching element is turned on. Semiconductor equipment.

[0321] [Note A16] The semiconductor device includes the frame that serves as the ground, The limiting section includes a second diode, a second power wire, and a wire for the second diode. The second diode is provided separately from the second switching element and includes a cathode electrically connected to the first terminal of the second switching element and an anode electrically connected to the frame. The wire for the second diode electrically connects the second terminal of the second switching element to the frame. The wire for the second diode electrically connects the anode of the second diode to the frame. The semiconductor device described in Appendix A15.

[0322] [Note A17] The second diode is a Schottky barrier diode. The semiconductor device described in Appendix A16.

[0323] [Note A18] In the frame, the position where the second power wire is connected and the position where the second diode wire is connected are different from each other. Semiconductor equipment as described in Appendix A16 or A17.

[0324] [Note A19] The first switching element has a first terminal to which a power supply voltage is supplied, and a second terminal connected to the first terminal of the second switching element. The semiconductor device further comprises a first diode, The first diode is provided separately from the first switching element and includes a cathode electrically connected to the first terminal of the first switching element and an anode electrically connected to the second terminal of the first switching element. A semiconductor device as described in any one of the appendices A16 to A18.

[0325] [Note A20] A lead frame on which the second switching element and the second diode are mounted, and on which the first terminal of the second switching element and the cathode of the second diode are electrically connected, A first power wire electrically connects the second terminal of the first switching element to the lead frame, A wire for the first diode electrically connects the anode of the first diode to the lead frame, Equipped with The semiconductor device described in Appendix A19.

[0326] [Note A21] In the lead frame, the position where the first power wire is connected and the position where the first diode wire is connected are different from each other. The semiconductor device described in Appendix A20.

[0327] [Note A22] The inverter circuit includes a first inverter circuit, a second inverter circuit, and a third inverter circuit connected in parallel with each other. The aforementioned limiting section includes a first limiting section, a second limiting section, and a third limiting section. The first limiting unit suppresses fluctuations in the potential of the second terminal of the second switching element of the first inverter circuit when the first switching element of the first inverter circuit is turned on. The second limiting unit suppresses fluctuations in the potential of the second terminal of the second switching element of the second inverter circuit when the first switching element of the second inverter circuit is turned on. The third limiting unit suppresses fluctuations in the potential of the second terminal of the second switching element of the third inverter circuit when the first switching element of the third inverter circuit is turned on. A semiconductor device as described in any one of the appendices A15 to A21.

[0328] [Note A23] A second diode is provided separately from the second switching element, and includes a cathode electrically connected to the first terminal of the second switching element and an anode electrically connected to the frame which becomes the ground. The device comprises a lead frame on which the second switching element and the second diode are mounted, and on which the first terminal of the second switching element and the cathode of the second diode are electrically connected, The lead frame includes a first frame, a second frame, and a third frame. The second diode includes a sixth diode, a seventh diode, and an eighth diode. The sixth diode has a cathode electrically connected to the first terminal of the second switching element of the first inverter circuit, and an anode electrically connected to the second terminal of the second switching element. The seventh diode has a cathode electrically connected to the first terminal of the second switching element of the second inverter circuit, and an anode electrically connected to the second terminal of the second switching element. The eighth diode has a cathode electrically connected to the first terminal of the second switching element of the third inverter circuit, and an anode electrically connected to the second terminal of the second switching element. The first frame is equipped with the second switching element of the first inverter circuit and the sixth diode. The second frame is positioned spaced apart from the first frame. The second frame is equipped with the second switching element of the second inverter circuit and the seventh diode. The third frame is positioned spaced apart from the first and second frames. The third frame is equipped with the second switching element of the third inverter circuit and the eighth diode. The frame includes a first ground frame, a second ground frame, and a third ground frame, which are spaced apart from each other. The first limiting unit is, The sixth diode and, A fourth power wire electrically connects the second terminal of the second switching element of the first inverter circuit to the first ground frame, A wire for the fourth diode electrically connects the anode of the sixth diode to the first ground frame, It has, The second limiting section is, The seventh diode and, A fifth power wire electrically connects the second terminal of the second switching element of the second inverter circuit to the second ground frame, A wire for the fifth diode electrically connects the anode of the seventh diode to the second ground frame, It has, The third limiting section is, The eighth diode and, A sixth power wire electrically connects the second terminal of the second switching element of the third inverter circuit to the third ground frame, A wire for the sixth diode electrically connects the anode of the eighth diode to the third ground frame, has The semiconductor device described in Appendix A22.

[0329] [Note A24] The aforementioned semiconductor device is A third diode is provided separately from the first switching element of the first inverter circuit, and includes a cathode electrically connected to the first terminal of the first switching element and an anode electrically connected to the second terminal of the first switching element. A first power wire electrically connects the second terminal of the first switching element of the first inverter circuit to the first frame, A fourth diode is provided separately from the first switching element of the second inverter circuit, and includes a cathode electrically connected to the first terminal of the first switching element and an anode electrically connected to the second terminal of the first switching element. A second power wire electrically connects the second terminal of the first switching element of the second inverter circuit to the second frame, A fifth diode is provided separately from the second switching element of the third inverter circuit, and includes a cathode electrically connected to the first terminal of the second switching element and an anode electrically connected to the second terminal of the second switching element. A third power wire electrically connects the second terminal of the first switching element of the third inverter circuit to the third frame, Equipped with Semiconductor equipment as described in Appendix A23.

[0330] [Note A25] A wire for the first diode electrically connects the anode of the third diode to the first frame, A wire for the second diode electrically connects the anode of the fourth diode to the second frame, A third diode wire electrically connects the anode of the fifth diode to the third frame, Equipped with The semiconductor device described in Appendix A24.

[0331] [Note A26] The current flowing through the second switching element is less than 30A. A semiconductor device as described in any one of the appendices A1 to A25.

[0332] [Note A27] The second switching element is a SiCMOSFET. A semiconductor device as described in any one of the appendices A1 to A26.

[0333] [Note B1] A first switching element to which a power supply voltage is supplied, A second switching element, which is formed in a rectangular shape in plan view and has a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode, A first inverter circuit, a second inverter circuit, and a third inverter circuit, each including the first switching element and the second switching element, are connected in parallel with each other. A first conductive layer on which the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted, A second conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the first inverter circuit is mounted, A third conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the second inverter circuit is mounted, A fourth conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the third inverter circuit is mounted, An integrated circuit element provided at a distance from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and equipped with a control circuit for controlling the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit, The system comprises a control wire that electrically connects the control electrode of the second switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element, The second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart in the first direction. The first switching elements are mounted on a common first conductive layer in the same orientation as each other in a plan view. The second conductive layer has a first element mounting region on which the second switching element of the first inverter circuit is mounted. The third conductive layer has a second element mounting region on which the second switching element of the second inverter circuit is mounted. The fourth conductive layer has a third element mounting region on which the second switching element of the third inverter circuit is mounted. The first element mounting area, the second element mounting area, and the third element mounting area are identical in shape to each other and are formed in a rectangular shape in plan view. The centers of the second switching elements mounted in the first element mounting area, the centers of the second switching elements mounted in the second element mounting area, and the centers of the second switching elements mounted in the third element mounting area, at least one of these centers of the second switching elements, are mounted spaced apart in a second direction that intersects the first direction in a plan view. At least one of the second switching elements in the first element mounting region, the second switching element in the second element mounting region, and the second switching element in the third element mounting region is tilted relative to the other second switching elements in a plan view. Semiconductor equipment.

[0334] [Note B2] The semiconductor device is formed in a rectangular shape with the first direction being the longitudinal direction when viewed from above. The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a line in the first direction in a plan view, and are positioned so that at least a portion of them overlap each other when viewed from the first direction. The semiconductor device described in Appendix B1.

[0335] [Note B3] The device further comprises a flattened rectangular sealing resin that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire. The sealing resin has a side surface from which a plurality of first terminal portions electrically connected to the control electrode of the first switching element protrude. The plurality of first terminal portions are arranged spaced apart from each other in the direction in which the side surface extends when viewed from above. On the aforementioned side surface, recesses are provided in the portions between adjacent first terminal portions in the direction in which the side surface extends. Semiconductor device as described in Appendix B1 or B2.

[0336] [Note B4] In a plan view, the magnitude of the direction in which the side surface of the recess extends is greater than the magnitude of the direction perpendicular to the direction in which the side surface of the recess extends. Semiconductor equipment as described in Appendix B3.

[0337] [Note B5] Multiple second terminal portions, electrically connected to the integrated circuit element, protrude from the aforementioned side surface. The plurality of second terminal portions are arranged spaced apart from each other in the direction in which the side surface extends when viewed from above. In a plan view, the distance between two first terminal portions located on either side of the recess is greater than the distance between adjacent second terminal portions in the direction in which the side surface extends. Semiconductor equipment as described in Appendix B3 or B4.

[0338] [Note B6] The current flowing through the second switching element is less than 30A. A semiconductor device as described in any one of the appendices B1 to B5.

[0339] [Note B7] The second switching element is a SiCMOSFET. A semiconductor device as described in any one of the appendices B1 to B6.

[0340] [Note C1] A first switching element to which a power supply voltage is supplied, A second switching element, which is formed in a rectangular shape in plan view and has a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode, A first inverter circuit, a second inverter circuit, and a third inverter circuit, each including the first switching element and the second switching element, are connected in parallel with each other. A first conductive layer on which the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted, A second conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the first inverter circuit is mounted, A third conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the second inverter circuit is mounted, A fourth conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the third inverter circuit is mounted, An integrated circuit element provided at a distance from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and equipped with a control circuit for controlling the second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit, The system comprises a control wire that electrically connects the control electrode of the second switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element, The second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart in the first direction. The first switching elements are mounted on a common first conductive layer in the same orientation as each other in a plan view. The second conductive layer has a first element mounting region on which the second switching element of the first inverter circuit is mounted. The third conductive layer has a second element mounting region on which the second switching element of the second inverter circuit is mounted. The fourth conductive layer has a third element mounting region on which the second switching element of the third inverter circuit is mounted. The first element mounting area, the second element mounting area, and the third element mounting area are identical in shape to each other and are formed in a rectangular shape in plan view. The centers of the second switching elements mounted in the first element mounting area, the centers of the second switching elements mounted in the second element mounting area, and the centers of the second switching elements mounted in the third element mounting area, at least one of these centers of the second switching elements, are mounted spaced apart in a second direction that intersects the first direction in a plan view. The device further comprises a flattened rectangular sealing resin that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire. The sealing resin has a third side surface from which a plurality of first terminal portions electrically connected to the control electrode of the first switching element protrude. The plurality of first terminal portions are arranged spaced apart from each other in the direction in which the third side surface extends when viewed from above. On the third side surface, recesses are provided in the portions between adjacent first terminal portions in the direction in which the third side surface extends. In a plan view, the magnitude of the direction in which the third surface of the recess extends is greater than the magnitude of the direction perpendicular to the direction in which the third surface of the recess extends. Semiconductor equipment.

[0341] [Note C2] The semiconductor device is formed in a rectangular shape with the first direction being the longitudinal direction when viewed from above. The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a line in the first direction in a plan view, and are positioned so that at least a portion of them overlap each other when viewed from the first direction. The semiconductor device described in Appendix C1.

[0342] [Note C3] Multiple second terminal portions, electrically connected to the integrated circuit element, protrude from the third side surface. The plurality of second terminal portions are arranged spaced apart from each other in the direction in which the third side surface extends when viewed from above. In a plan view, the distance between two of the plurality of first terminal portions located on either side of the recess is greater than the distance between adjacent second terminal portions in the direction in which the third side surface extends. The semiconductor device described in Appendix C1.

[0343] [Note C4] The sealing resin has a fourth side facing the third side, from which a plurality of third terminal portions protrude. Each of the third terminal portions has an island portion that is electrically connected to the second switching element by a power wire and covered by the sealing resin. At least two of the island portions have ends on the third side that are flush with the surface. The semiconductor device described in Appendix C1.

[0344] [Note C5] The aforementioned integrated circuit element is mounted on a fifth conductive layer separated from the first to fourth conductive layers. The first switching element has a back surface on which a drain electrode pad is provided, and a front surface on which a source electrode pad and a gate electrode pad are provided. The sealing resin has a sealing resin back surface facing the back surface and a sealing resin surface facing the front surface, The connection surface between the integrated circuit element and the fifth conductive layer is located on the sealing resin surface side of the back surface of the first switching element, in a cross-sectional view from the first direction. The semiconductor device described in Appendix C1.

[0345] [Appendix C6] The current flowing through the second switching element is less than 30A. A semiconductor device as described in any one of the appendices C1 to C5.

[0346] [Note C7] The second switching element is a SiCMOSFET. A semiconductor device as described in any one of the appendices C1 to C6.

[0347] [Note D1] A first switching element, which is formed in a rectangular shape in plan view and to which a power supply voltage is supplied, A second switching element, which is formed in a rectangular shape in plan view and has a first electrode connected to the first switching element, a second electrode connected to ground, and a control electrode, A first inverter circuit, a second inverter circuit, and a third inverter circuit, each including the first switching element and the second switching element, are connected in parallel to each other. A common first conductive layer on which the first switching elements included in each of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted, A second conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the first inverter circuit is mounted, A third conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the second inverter circuit is mounted, A fourth conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the third inverter circuit is mounted, An integrated circuit element provided at a distance from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and equipped with a control circuit that controls the second switching element of each of the first inverter circuit, the second inverter circuit, and the third inverter circuit, A control wire that electrically connects the control electrode of the second switching element of each of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the integrated circuit element independently of each other, A flattened rectangular sealing resin that seals the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the integrated circuit element, and the control wire, Equipped with, The second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and spaced apart in the first direction. When a pair of the first and second switching elements, arranged adjacent to each other in the first direction, are defined as the first specific switching element and the second specific switching element, The first specific switching element has a first side surface closer to the second specific switching element and a second side surface opposite to the first side surface. The second specific switching element has a first side surface closer to the first specific switching element and a second side surface opposite to the first side surface. In the first direction, the first side surface of the first specific switching element and the first side surface of the second specific switching element face each other. The control electrode of the first specific switching element is positioned closer to the second side surface of the first specific switching element. The control electrode of the second specific switching element is positioned closer to the second side surface of the second specific switching element. The sealing resin has a third side surface from which a plurality of first terminal portions electrically connected to the control electrode of the first switching element protrude. The plurality of first terminal portions are arranged spaced apart from each other in the direction in which the third side surface extends when viewed from above. On the third side surface, recesses are provided in the portions between adjacent first terminal portions in the direction in which the third side surface extends. In a plan view, the magnitude of the direction in which the third surface of the recess extends is greater than the magnitude of the direction perpendicular to the direction in which the third surface of the recess extends. Semiconductor equipment.

[0348] [Note D2] The semiconductor device is formed in a rectangular shape with the first direction being the longitudinal direction when viewed from above. The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a line in the first direction in a plan view, and are positioned so that at least a portion of them overlap each other when viewed from the first direction. The semiconductor device described in Appendix D1.

[0349] [Note D3] Multiple second terminal portions, electrically connected to the integrated circuit element, protrude from the third side surface. The plurality of second terminal portions are arranged spaced apart from each other in the direction in which the third side surface extends when viewed from above. In a plan view, the distance between two of the plurality of first terminal portions located on either side of the recess is greater than the distance between adjacent second terminal portions in the direction in which the third side surface extends. The semiconductor device described in Appendix D1.

[0350] [Note D4] The sealing resin has a fourth side facing the third side, from which a plurality of third terminal portions protrude. Each of the third terminal portions has an island portion that is electrically connected to the second switching element by a power wire and covered by the sealing resin. At least two of the island portions have ends on the third side that are flush with the surface. The semiconductor device described in Appendix D1.

[0351] [Note D5] The aforementioned integrated circuit element is mounted on a fifth conductive layer separated from the first to fourth conductive layers. The first switching element has a back surface on which a drain electrode pad is provided, and a front surface on which a source electrode pad and a gate electrode pad are provided. The sealing resin has a sealing resin back surface facing the back surface and a sealing resin surface facing the front surface, The connection surface between the integrated circuit element and the fifth conductive layer is located on the sealing resin surface side of the back surface of the first switching element, in a cross-sectional view from the first direction. The semiconductor device described in Appendix D1.

[0352] [Note D6] The current flowing through the second switching element is less than 30A. A semiconductor device as described in any one of the appendices D1 to D5.

[0353] [Note D7] The second switching element is a SiCMOSFET. A semiconductor device described in any one of the appendices D1 to D6. [Explanation of symbols]

[0354] 1…Semiconductor device, 10A…Inverter circuit, 10U…First inverter circuit, 10V…Second inverter circuit, 10W…Third inverter circuit, 11…First switching element, 11U, 11V, 11W…MOSFET (first switching element), 12…Second switching element, 12U, 12V, 12W…MOSFET (second switching element), 12s…Source electrode pad (ground electrode pad), 12g…Gate electrode pad (control electrode pad), 13…Diode, 14U…First diode (second diode, sixth diode), 14V…Second diode (2nd diode, 7th diode), 14W...3rd diode (2nd diode, 8th diode), 15U...1st diode (1st diode, 3rd diode), 15V...2nd diode (1st diode, 4th diode), 15W...3rd diode (1st diode, 5th diode), 21...Drive circuit (drive signal output circuit), 21UU...Drive circuit (1st control circuit), 21VU...Drive circuit (1st control circuit), 21WU...Drive circuit (1st control circuit), 21UL...Drive circuit (2nd control circuit, 3rd control circuit), 21VL...Drive Eve circuit (2nd and 4th control circuits), 21WL…Drive circuit (2nd and 5th control circuits), 21a…Source-grounded circuit, 21d…Output wiring, 21e…Limiting wiring, 22…Logic circuit, 22UU…Logic circuit (1st control circuit), 22VU…Logic circuit (1st control circuit), 22WU…Logic circuit (1st control circuit), 22UL…Logic circuit (2nd and 3rd control circuits), 22VL…Logic circuit (2nd and 4th control circuits), 22WL…Logic circuit (2nd and 5th control circuits), 25L…Integrated circuit element (integrated circuit element of the 2nd control circuit), 25a…Output terminal ,25au…1st output terminal (output terminal),25av…2nd output terminal (output terminal),25aw…3rd output terminal (output terminal),25b…input terminal,25bu…1st input terminal (input terminal),25bv…2nd input terminal (input terminal),25bw…3rd input terminal (input terminal),32U…1st frame,32V…2nd frame,32W…3rd frame,35U…frame (ground frame, 1st ground frame),35V…frame (ground frame, 2nd ground frame),35W…frame (ground frame, 3rd ground frame),60…wire,60U...1st wire (1st power wire), 60V...2nd wire (2nd power wire), 60W...3rd wire (3rd power wire), 61...wire, 61U...1st wire (4th power wire), 61V...2nd wire (5th power wire), 61W...3rd wire (6th power wire), 62...control wire, 62U...1st wire, 62V...2nd wire, 62W...3rd wire, 63...wire (limiting wire), 63U...1st wire (1st limiting wire), 63V...2nd wire (2nd limiting wire), 63W...3rd wire (3rd limiting wire), 64U...1st diode wire (4th diode (Wire for diode), 64V...Wire for the 2nd diode (Wire for the 5th diode), 64W...Wire for the 3rd diode (Wire for the 6th diode), 65U...Wire for the 1st diode, 65V...Wire for the 2nd diode, 65W...Wire for the 3rd diode, RC...Control path, RC1...1st control path, RC2...2nd control path, RC3...3rd control path, RS...Restriction path, RS1...1st restriction path, RS2...2nd restriction path, RS3...3rd restriction path, CV...Restriction section, CV1...1st restriction section, CV2...2nd restriction section, CV3...3rd restriction section, CP1...1st restriction section, CP2...2nd restriction section, CP3...3rd restriction section.

Claims

1. A first switching element and a second switching element, which are formed in a rectangular shape in plan view and each have a first electrode, a second electrode, and a control electrode, respectively. The first electrode of the first switching element is connected to the power supply, the second electrode of the first switching element is connected to the first electrode of the second switching element, and the second electrode of the second switching element is connected to ground. A first inverter circuit, a second inverter circuit, and a third inverter circuit each include the first switching element and the second switching element. A first conductive layer on which the first switching element included in each of the first inverter circuit, the second inverter circuit, and the third inverter circuit is mounted, A second conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the first inverter circuit is mounted, A third conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the second inverter circuit is mounted, A fourth conductive layer is provided spaced apart from the first conductive layer, on which the second switching element of the third inverter circuit is mounted, A first integrated circuit element is provided spaced apart from the first inverter circuit, the second inverter circuit, and the third inverter circuit, and is equipped with a control circuit that controls the first switching element of each of the first inverter circuit, the second inverter circuit, and the third inverter circuit. A first wire electrically connects the control electrode of the first switching element of each of the first inverter circuit, the second inverter circuit, and the third inverter circuit to the first integrated circuit element, Equipped with, The second conductive layer, the third conductive layer, and the fourth conductive layer are insulated from each other and are spaced apart in a first direction perpendicular to the thickness direction of each switching element. The second switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are mounted on the second conductive layer, the third conductive layer, and the fourth conductive layer, respectively, in the same orientation to each other in a plan view. At least one of the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit is mounted on the first conductive layer such that its orientation is different from that of the other first switching elements in a plan view. Semiconductor equipment.

2. The center of at least one of the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit is offset from the centers of the other first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit in a second direction perpendicular to the first direction in a plan view. The semiconductor device according to claim 1.

3. The semiconductor device is formed in a rectangular shape with the first direction being the longitudinal direction in a plan view. The first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a line in the first direction in a plan view, and are positioned so that at least a portion of them overlap each other when viewed from the first direction. The semiconductor device according to claim 1.

4. The invention further comprises a sealing resin for sealing the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first integrated circuit element, and the first wire. The sealing resin has a third side surface from which a plurality of first terminal portions for receiving signals to form a signal to be applied to the control electrode of the first switching element protrude. The plurality of first terminal portions are arranged spaced apart from each other in the direction in which the third side surface of the sealing resin extends when viewed from above. On the third side surface, a recess is provided in the portion between adjacent first terminal portions in the direction in which the third side surface extends. The semiconductor device according to claim 1.

5. In a plan view, the magnitude of the direction in which the third surface of the recess extends is greater than the magnitude of the direction perpendicular to the direction in which the third surface of the recess extends. The semiconductor device according to claim 4.

6. The circuit further comprises a second integrated circuit element provided at a distance from the first inverter circuit, the second inverter circuit, and the third inverter circuit, which controls each of the second switching elements, Multiple second terminal portions, electrically connected to the second integrated circuit element, protrude from the third side surface. The plurality of second terminal portions are arranged spaced apart from each other in the direction in which the third side surface extends when viewed from above. In a plan view, the distance between two first terminal portions arranged on both sides of the recess is greater than the distance between adjacent second terminal portions in the direction in which the third side surface extends. The semiconductor device according to claim 4.

7. The current flowing through the second switching element is less than 30A. The semiconductor device according to claim 1.

8. The aforementioned second switching element is a SiCMOSFET, The first electrode is a drain electrode, the second electrode is a source electrode, and the control electrode is an gate electrode. The semiconductor device according to claim 1.

9. The first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a first direction in a plan view. The first switching element of the first inverter circuit and the first switching element of the third inverter circuit are arranged so as to sandwich the first switching element of the second inverter circuit. In a plan view, the first switching element of the second inverter circuit faces the first integrated circuit element in a direction intersecting the first direction. The semiconductor device according to claim 1.

10. The control electrodes of the first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in one of the four corners of the first switching element in a plan view. At least one of the first switching element of the first inverter circuit and the first switching element of the third inverter circuit is arranged in a different orientation from that of the first switching element of the second inverter circuit, such that the control electrode of the first switching element of at least one of the first inverter circuit and the third inverter circuit is closer to the first integrated circuit element. The semiconductor device according to claim 1.

11. The control electrodes of the first switching elements in each of the first inverter circuit, the second inverter circuit, and the third inverter circuit are positioned in a plan view at the corner of the first switching element closest to the first integrated circuit element among the four corners of the first switching element. The semiconductor device according to claim 10.

12. The first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a first direction in a plan view. The first switching element of the first inverter circuit and the first switching element of the third inverter circuit are arranged so as to sandwich the first switching element of the second inverter circuit. The first switching element of the first inverter circuit is arranged such that the longitudinal direction of the first switching element is aligned along a direction different from the first direction and a second direction perpendicular to the first direction. The first switching element of the second inverter circuit is arranged such that the longitudinal direction of the first switching element is aligned with the first direction or the second direction. The first switching element of the third inverter circuit is arranged such that the longitudinal direction of the first switching element is aligned in a direction different from the first direction and the second direction. The semiconductor device according to claim 1.

13. The first switching elements of the first inverter circuit, the second inverter circuit, and the third inverter circuit are arranged in a first direction in a plan view. The first switching element of the first inverter circuit and the first switching element of the third inverter circuit are arranged so as to sandwich the first switching element of the second inverter circuit. In a plan view, in a direction perpendicular to the first direction, any of the first switching elements among the first inverter circuit, the second inverter circuit, and the third inverter circuit faces the first integrated circuit element. The semiconductor device according to claim 1.

14. The semiconductor device according to claim 1, wherein the second electrode of the first switching element of the first inverter circuit, the second inverter circuit, and the third inverter circuit is electrically connected to the second conductive layer, the third conductive layer, and the fourth conductive layer, respectively, via the second wire, the third wire, and the fourth wire.

15. The semiconductor device according to claim 1, wherein the fifth conductive layer on which the first integrated circuit element is mounted is arranged at a different height from the first conductive layer.

16. The semiconductor device according to claim 4, further comprising a heat dissipation member connected to the surface of the first conductive layer opposite to the mounting surface of the first switching element, and partially exposed from the sealing resin.

17. The invention further comprises a sealing resin for sealing the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first integrated circuit element, and the first wire. The semiconductor device according to claim 1, wherein each conductive layer is part of the lead frame and has a terminal portion protruding from the side surface of the sealing resin.

18. The invention further comprises a sealing resin for sealing the first inverter circuit, the second inverter circuit, the third inverter circuit, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first integrated circuit element, and the first wire. The sealing resin has a third side surface from which a plurality of first terminal portions for receiving signals to form a signal applied to the control electrode of the first switching element protrude, and a fourth side surface facing the third side surface from which a plurality of third terminal portions protrude. Each of the third terminal portions has an island portion that is electrically connected to the second switching element by a fifth wire and covered by the sealing resin. The ends of the third side of at least two of the island portions, which constitute the first island portion, are flush with each other. If the ends that are flush with each other are designated as the first ends, The end on the third side of at least one island portion, which is a second island portion distinct from the first island portion, is positioned differently from the first end in a second direction perpendicular to the first direction. The semiconductor device according to claim 1.

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