Drive circuits, inverters, electronic equipment, and vehicles

Abstract

The drive circuit still needed further consideration regarding the drive control of the switches being driven. [Solution] The drive circuit comprises a high-side driver, a low-side driver, and a bootstrap circuit. The bootstrap circuit includes a capacitive circuit configured to receive a power supply voltage and a reference voltage lower than the power supply voltage, and to be charged according to the power supply voltage and the reference voltage to generate a drive voltage, and a precharge circuit configured to supply the reference voltage to the capacitive circuit when the high-side switch and low-side switch are not driven, and not to supply the reference voltage to the capacitive circuit when the high-side switch and low-side switch are driven, based on an external signal.

Description

[Technical Field]

[0001] The inventions disclosed herein relate to signal transmission devices, electronic devices, and vehicles. [Background technology]

[0002] Conventionally, there are drive circuits that transmit pulse signals while isolating the input and output to drive the object being driven. These drive circuits are used in a variety of applications (such as power supplies or motor drive devices).

[0003] As an example of prior art related to the above, Patent Document 1 can be cited. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-188903

[0005] [overview] The drive circuit disclosed in Patent Document 1 had room for further consideration regarding the drive control of the switch to be driven.

[0006] The drive circuit disclosed in this specification includes a high-side driver, a low-side driver, and a bootstrap circuit. The high-side driver is configured to drive and control the high-side switch among the high-side switch and the low-side switch that are bridge-connected to each other based on an external signal. The low-side driver is configured to drive and control the low-side switch based on an external signal. The bootstrap circuit is configured to boost the power supply voltage and generate a drive voltage for the high-side switch based on an external signal. The bootstrap circuit receives the supply of the power supply voltage and a reference voltage lower than the power supply voltage, and is configured with a capacitive circuit that is charged according to the power supply voltage and the reference voltage to generate a drive voltage, and a precharge circuit that supplies the reference voltage to the capacitive circuit when the high-side switch and the low-side switch are not being driven based on an external signal, and does not supply the reference voltage to the capacitive circuit when the high-side switch and the low-side switch are being driven. The capacitive circuit receives the supply of the reference voltage via the low-side switch when the low-side switch is being driven and the low-side switch is in the on state, and receives the supply of the reference voltage via the precharge circuit when the low-side switch is not being driven.

[0007] The inverter disclosed in this specification includes the drive circuit having the above configuration, and a switch output stage including a high-side switch and a low-side switch that are bridge-connected to each other, and is configured to receive a DC input voltage and output an AC output voltage.

[0008] The electronic device disclosed in this specification includes the inverter having the above configuration.

[0009] The vehicle disclosed in this specification includes the electronic device having the above configuration.

Brief Description of Drawings

[0010] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transchip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel type transchip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. [Figure 5] FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. [Figure 8] FIG. 8 is a diagram showing an enlarged view (separation structure) of region XIII shown in FIG. 7. [Figure 9] FIG. 9 is a diagram schematically showing a layout example of a transchip. [Figure 10] FIG. 10 is a diagram showing the configuration of an inverter 700Y equipped with a drive circuit 500Y of a comparative example. [Figure 11] FIG. 十一は、本開示にかかるインバータ700Xを搭載したモータ装置800の構成を示す図である。 [Figure 12] FIG. 12 is a diagram showing the configuration of an inverter 700X equipped with a drive circuit 500X. [Figure 13] FIG. 13 is a diagram showing a vehicle A including a motor device 800.

BEST MODE FOR CARRYING OUT THE INVENTION

[0011] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 in this example configuration is a semiconductor integrated circuit device (a so-called isolated gate driver IC) that transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) and the secondary circuit system 200s (VCC2-GND2 system), and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 consists of a controller chip 210, a driver chip 220, and a transformer chip 230, all packaged together.

[0012] The controller chip 210 is a semiconductor chip that operates on a power supply voltage VCC1 (for example, up to 7V relative to GND1). The controller chip 210 integrates, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0013] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmission circuit 211 indicates that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it indicates that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmission circuit 211 pulse-drives either the transmission pulse signal S11 or S21 depending on the logic level of the input pulse signal IN.

[0014] The buffer 212 receives the input of the transmitted pulse signal S11 from the pulse transmission circuit 211 and pulses the transformer chip 230 (specifically the transformer 231).

[0015] The buffer 213 receives the input of the transmitted pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically the transformer 232).

[0016] The driver chip 220 is a semiconductor chip that operates on a power supply voltage VCC2 (for example, up to 30V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0017] Buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0018] Buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0019] The pulse receiving circuit 223 generates an output pulse signal OUT by driving a driver 224 in response to received pulse signals S12 and S22 input via buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. For example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0020] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0021] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0022] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0023] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0024] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0025] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0026] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0027] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0028] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0029] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0030] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0031] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0032] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0033] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0034] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0035] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0036] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0037] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0038] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0039] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0040] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0041] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0042] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0043] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0044] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0045] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0046] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0047] Referring to Figures 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0048] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0049] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0050] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0051] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0052] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0053] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0054] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0055] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0056] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0057] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0058] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0059] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0060] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0061] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0062] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0063] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0064] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0065] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0066] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0067] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0068] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0069] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0070] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0071] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0072] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0073] Referring to Figures 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0074] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0075] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0076] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0077] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0078] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0079] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0080] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0081] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0082] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0083] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0084] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0085] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0086] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0087] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0088] Referring to Figures 6 and 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0089] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0090] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In a plan view, the high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0091] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. Each of the multiple pad plug electrodes 82 has a planar area less than the planar area of ​​the high-potential connection wiring 81 in a plan view.

[0092] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0093] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0094] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0095] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0096] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0097] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0098] The dummy pattern 85 includes a floating dummy pattern formed electrically in a floating state within the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0099] In this embodiment, the floating dummy pattern is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern may be formed with ends or without ends.

[0100] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated.

[0101] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. A floating dummy pattern may consist of multiple floating lines.

[0102] Referring to Figure 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 7, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0103] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0104] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0105] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0106] Referring to Figures 5 to 7, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0107] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0108] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0109] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0110] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0111] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0112] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0113] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0114] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0115] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0116] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0117] Referring to Figures 7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, which electrically isolates the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0118] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0119] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0120] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0121] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0122] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0123] Referring to Figure 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0124] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0125] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0126] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0127] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0128] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0129] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0130] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0131] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0132] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0133] Embodiments of the present invention can be implemented in yet other forms. In the embodiments described above, an example was described in which a first functional device 45 and a second functional device 60 are formed. However, an embodiment may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0134] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0135] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0136] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0137] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0138] <Trans arrangement> Figure 9 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0139] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0140] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0141] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is positioned directly below each of the secondary coils L1s to L4s, facing them respectively.

[0142] Specifically, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Similarly, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0143] Furthermore, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Similarly, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0144] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0145] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0146] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0147] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0148] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0149] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0150] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0151] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0152] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0153] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between their respective primary coils. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transformer chip 300.

[0154] Furthermore, as shown in Figure 9, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0155] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0156] <Regarding the 500Y drive circuit> Next, we will describe the signal transmission device 400, which corresponds to the signal transmission device 200 described above. The signal transmission device 400 can be used in both the drive circuit 500Y, which is a comparative example of the present disclosure, and the drive circuit 500X of the present disclosure. First, we will describe the drive circuit 500Y in detail. Next, we will describe the problems of the drive circuit 500Y. After that, we will describe the drive circuit 500X of the present disclosure.

[0157] In the following, the voltages at the ground terminal GND1, the reference potential terminal GND2, and the reference potential terminal GND3 will be referred to as ground voltage GND1, reference voltage GND2, and reference voltage GND3, respectively, using the same symbols. That is, the symbols GND1 to GND3 shown in the diagram represent both the contacts (nodes) and the voltages at each contact.

[0158] Figure 10 shows the configuration of the inverter 700Y equipped with the comparative example drive circuit 500Y. The drive circuit 500Y in this configuration example is usable with the inverter 700Y. The inverter 700Y is a type of motor drive device that converts DC power supplied from an on-board battery (not shown) into AC power to drive a motor M. The motor M is a three-phase motor that is driven to rotate according to the three-phase drive voltages input from each of the three-phase half-bridge output stages. Note that only one phase of the three-phase half-bridge output stage is shown in Figure 10.

[0159] As shown in Figure 10, the inverter 700Y comprises a drive circuit 500Y and a switch output stage 550. The drive circuit 500Y operates by receiving a power supply voltage Vccb. When the drive circuit 500Y is started, the power supply voltage Vccb rises to the operating voltage of the drive circuit 500Y.

[0160] The drive circuit 500Y receives an enable signal ENA and input signals INA and INB from the ECU (Electronic Control Unit) 2. The drive circuit 500Y operates or stops depending on the logic level of the enable signal ENA. The drive circuit 500Y generates drive voltages GH and GL based on the input signals INA and INB (more specifically, combinations of the logic levels of input signals INA and INB). The drive circuit 500Y uses drive voltages GH and GL to drive and control the switch output stage 550.

[0161] ECU2 is a means for comprehensively controlling the electrical operation of the drive circuit 500Y (drive circuit 500X, described later) and vehicle A (see Figure 13, shown later) on which the drive circuit 500Y (drive circuit 500X, described later) is installed. ECU2 generates an enable signal ENA and input signals INA and INB. ECU2 switches the logic levels of the enable signal ENA and input signals INA and INB between high and low levels. ECU2 inputs the enable signal ENA and input signals INA and INB to the drive circuit 500Y.

[0162] Specifically, ECU2 raises the enable signal ENA to a high level when operating the drive circuit 500Y. Conversely, ECU2 lowers the enable signal ENA to a low level when stopping the operation of the drive circuit 500Y.

[0163] The switch output stage 550 is connected between the application terminal of the motor drive voltage VD1 and the ground terminal GND1. The motor drive voltage VD1 is a DC voltage. The switch output stage 550 receives the motor drive voltage VD1 and the ground voltage GND1 and generates an AC output voltage Vout. Specifically, the switch output stage 550 pulses the output voltage Vout between a high level (=equivalent to the motor drive voltage VD1) and a low level (=equivalent to the ground voltage GND1) by the switching operation described later.

[0164] The switch output stage 550 comprises a high-side switch SWH and a low-side switch SWL. Both the high-side switch SWH and the low-side switch SWL are N-channel MOSFETs. The high-side switch SWH and the low-side switch SWL are connected to each other to form a half-bridge output stage. Specifically, this is as follows:

[0165] The drain of the high-side switch SWH is connected to the terminal to which the motor drive voltage VD1 is applied. The source of the high-side switch SWH is connected to the drain of the low-side switch SWL. The source of the low-side switch SWL is connected to the ground terminal GND1. For the sake of explanation, the connection node between the source of the high-side switch SWH and the drain of the low-side switch SWL will be referred to as node n1.

[0166] The gate of the high-side switch SWH is input with the drive voltage GH. The gate of the low-side switch SWL is input with the drive voltage GL. The high-side switch SWH turns on / off according to the logic level of the drive voltage GH. The low-side switch SWL turns on / off according to the logic level of the drive voltage GL. Node n1 outputs an output voltage Vout corresponding to the on / off state of the high-side switch SWH and the low-side switch SWL.

[0167] The high-side switch SWH and the low-side switch SWL are switched on and off complementaryly according to the drive voltages GH and GL (and consequently according to the combination pattern of logic levels of the input signals INA and INB). The term "complementary" includes cases where the on / off states of the high-side switch SWH and the low-side switch SWL are completely reversed. It also includes cases where there is a simultaneous off period (dead time) for the high-side switch SWH and the low-side switch SWL.

[0168] <Detailed configuration of the 500Y drive circuit> The drive circuit 500Y also functions as a gate driver that controls the gate voltages of the high-side switch SWH and the low-side switch SWL. The drive circuit 500Y comprises a signal transmission device 400, a plurality of discrete components (resistors R1 to R4), and a bootstrap circuit 510Y.

[0169] The signal transmission device 400 corresponds to the aforementioned signal transmission device 200. The signal transmission device 400 has an external terminal (as shown in this figure, external terminal T) as a means of communication with the outside world.

[0173] , , ,

[0172] , vcca , OBH ,

[0174] , , , , , OBL , T INA , T INB , T vccb , T OBH , T OBL , T GND1 , T GND2 , T Vcca , T OAH , T OAL , T MC , T GND2 ) has. The signal transmission device 400 generates drive voltages GH and GL according to input signals INA and INB. The detailed configuration of the signal transmission device 400 will be described later.

[0170] The first end of resistor R1 is connected to external terminal T OHA is connected. The first end of resistor R2 is connected to external terminal T OAL is connected. The second end of resistor R2 is connected to the second end of resistor R1 and to the switch output stage 550 (more specifically, the gate of the high-side switch SWH and node n1, which will be described later).

[0171] The first end of resistor R3 is connected to external terminal T OBH is connected. The first end of resistor R4 is connected to external terminal T OBL is connected. The second end of resistor R4 is connected to the second end of resistor R3 and to the switch output stage 550 (more specifically, the gate of the low-side switch SWL and ground terminal GND1, which will be described later).

[0172] The bootstrap circuit 510Y receives the supply of the power supply voltage Vccb, boosts the power supply voltage Vccb, and generates the power supply voltage Vcca. The bootstrap circuit 510Y will be described in detail.

[0173] The bootstrap circuit 510Y includes a diode D1 and a capacitor Cb. The anode of the diode D1 is connected to the applied terminal of the power supply voltage Vccb. The cathode of the diode D1 is connected to the first end of the capacitor Cb together with external terminal T vcca . The second end of the capacitor Cb is connected to node n1.

[0174] The bootstrap circuit 510Y is configured to charge capacitor Cb by switching the low-side switch SWL on and off. Specifically, when the low-side switch SWL is on and the high-side switch SWH is off, the voltage at node n1 is equivalent to the ground voltage GND1. Therefore, at this time, capacitor Cb is charged by the potential difference between the power supply voltage Vccb and the ground voltage GND1.

[0175] As the charge level of capacitor Cb increases, the first terminal of capacitor Cb, and consequently the external terminal T... vcca The voltage of this external terminal T increases. vcca The voltage at the external terminal T is called the power supply voltage Vcca. vcca It is supplied to the high-side chip 420 via this.

[0176] Here, the voltage at node n1 is the midpoint voltage between the high-side switch SWH and the low-side switch SWL (= the source voltage of the high-side switch SWH). When capacitor Cb is charged, the power supply voltage Vcca will rise relative to the voltage at node n1, in proportion to the amount of charge of capacitor Cb.

[0177] In this way, the bootstrap circuit 510Y generates a power supply voltage Vcca that is higher than the midpoint voltage (=voltage at node n1) and supplies it to the signal transmission device 400 (more specifically, the high-side chip 420).

[0178] The high-side chip 420 operates by receiving the power supply voltage Vcca. In other words, the bootstrap circuit 510Y can also be understood as a power supply circuit for operating the high-side chip 420.

[0179] Specifically, the high-side chip 420 uses this power supply voltage Vcca to control the on / off state of the high-side switch SWH. More specifically, the high-side chip 420 pulses the drive voltage GH between a high level (equivalent to the power supply voltage Vcca) and a low level (equivalent to the reference voltage GND1).

[0180] When the drive voltage GH is at a high level (equivalent to the power supply voltage Vcca), the voltage difference between node n1 and the power supply voltage Vcca exceeds the on-threshold voltage of the high-side switch SWH. Therefore, the high-side switch SWH turns on. Conversely, when the drive voltage GH is at a low level (equivalent to the ground voltage GND1), the voltage difference between node n1 and the power supply voltage Vcca falls below the on-threshold voltage of the high-side switch SWH. Therefore, the high-side switch SWH turns off.

[0181] <Detailed configuration of signal transmission device 400> The configuration of the signal transmission device 400 will be described in more detail. The signal transmission device 400 comprises a low-side chip 410, a high-side chip 420, and a transformer chip 430. The signal transmission device 400 is a semiconductor integrated circuit device formed by encapsulating the low-side chip 410, the high-side chip 420, and the transformer chip 430 in a single package.

[0182] The low-side chip 410 has an external terminal T Vccb It operates by receiving the power supply voltage Vccb via the terminal. The low-side chip 410 has an external terminal T ENA The enable signal ENA is input via [this]. The low-side chip 410 also has an external terminal T INA The input signal INA is received via the low-side chip 410. INB It receives the input signal INB via [this method].

[0183] When the input enable signal ENA is at a high level, the low-side chip 410 generates a control signal S1 and a drive voltage GL based on the input signals INA and INB. At this time, the low-side chip 410 transmits the generated control signal S1 to the high-side chip 420 via the transformer chip 430. The low-side chip 410 also inputs the generated drive voltage GL to the gate of the low-side switch SWL to drive and control the low-side switch SWL.

[0184] The details of the low-side chip 410 are as follows: The low-side chip 410 comprises a logic circuit 411, a driver 412, a switch element P1, and a switch element N1.

[0185] When the enable signal ENA is at a high level, logic circuit 411 generates control signals S1 to S3 according to the input signals INA and INB. Logic circuit 411 inputs control signals S1 and S2 to transformer chip 430 (more specifically, transformers 431 and 432, described later). Logic circuit 411 inputs control signal S3 to driver 412.

[0186] The driver 412 generates drive signals G1 and G2 according to the logic level of the control signal S3. The driver 412 inputs the generated drive signal G1 to the gate of the switch element P1 to drive and control the switch element P1. The driver 412 also inputs the generated drive signal G2 to the gate of the switch element N1 to drive and control the switch element N1.

[0187] The switch element P1 is a P-channel MOSFET. The source of the switch element P1 is the external terminal T. Vccb It is connected to the application terminal of the power supply voltage Vccb via [a certain connection]. The drain of the switch element P1 is connected to the external terminal T OBH It is connected to the first terminal of resistor R3 via [this].

[0188] The switch element N1 is an N-channel MOSFET. The source of the switch element N1 is connected to the ground terminal GND1. The drain of the switch element N1 is connected to the external terminal T OBL It is connected to the first end of resistor R4 via [a specific component].

[0189] The second terminal of resistor R4, along with the second terminal of resistor R3, is connected to the gate of the low-side switch SWL and to the ground terminal GND1.

[0190] When switch element P1 is in the ON state, the power supply voltage Vccb is connected to the external terminal T OBHIt is output from there. Also, when the switch element N1 is in the ON state, the ground voltage GND1 is connected to the external terminal T OBL Output from here.

[0191] The driver 412 drives and controls the switch elements P1 and N1 as follows to turn the low-side switch SWL on / off. For example, to turn on the low-side switch SWL, switch element P1 is turned on and switch element N1 is turned off. Then, as described above, the power supply voltage Vccb is connected to the external terminal T OBH Output is generated from there. At this time, since the switch element N1 is off, the ground voltage GND1 is output from the external terminal T OBL No output is produced. This generates a high-level drive voltage GL (= voltage relative to the power supply voltage Vccb) at the connection node between resistors R3 and R4 (i.e., the gate terminal of the low-side switch SWL).

[0192] Conversely, to turn off the low-side switch SWL, switch element P1 is turned off and switch element N1 is turned on. Then, as described above, the ground voltage GND1 is connected to the external terminal T OBL The output is from the external terminal T. Also, since the switch element P1 is off at this time, the power supply voltage Vccb is output from the external terminal T. OBH No output is produced. This generates a low-level drive voltage GL (voltage relative to ground voltage GND1) at the connection node between resistors R3 and R4 (i.e., the gate terminal of the low-side switch SWL).

[0193] The transformer chip 430 has multiple transformers (transformers 431 and 432 as shown in this figure). Each of transformers 431 and 432 has a primary winding and a secondary winding.

[0194] The primary windings of transformers 431 and 432 are connected to the low-side chip 410 (more specifically, the logic circuit 411). The secondary windings of transformers 431 and 432 are connected to the high-side chip 420 (more specifically, the logic circuit 421, which will be described later). Transformers 431 and 432 establish signal transmission and reception between the low-side chip 410 and the high-side chip 420 while providing DC isolation between them via their primary and secondary windings.

[0195] The control signal S1 input to the primary winding of transformer 431 and the control signal S2 input to the primary winding of transformer 432 are transmitted to the secondary windings and input to the high-side chip 420 (more specifically, the logic circuit 421).

[0196] As described above, the high-side chip 420 receives control signals S1 and S2 via the transformer chip 430. Based on the input control signals S1 and S2, the high-side chip 420 generates a drive voltage GH. The high-side chip 420 then inputs the drive voltage GH to the gate of the high-side switch SWH. Details of the high-side chip 420 are as follows.

[0197] The high-side chip 420 includes a logic circuit 421, a driver 422, a switch element P2, and switch elements N2 and N3.

[0198] Logic circuit 421 receives control signals S1 and S2 as inputs. Based on control signals S1 and S2, logic circuit 421 generates control signal S4. Logic circuit 421 inputs control signal S4 to driver 422.

[0199] The driver 422 generates drive signals G3 to G5 based on the input control signal S4. The driver 422 inputs drive signal G3 to the gate of switch element P2 to drive and control switch element P2. The driver 422 also inputs drive signal G4 to the gate of switch element N2 to drive and control switch element N2. The driver 422 also inputs drive signal G5 to the gate of switch element N3 to drive and control switch element N3.

[0200] The switch element P2 is a P-channel MOSFET. The source of the switch element P2 is connected to the terminal to which the power supply voltage Vcca is applied. The drain of the switch element P2 is connected to the external terminal T OAH It is connected to the first terminal of resistor R1 via [a specific component].

[0201] Switch element N2 is an N-channel MOSFET. The source of switch element N2 is connected to the reference potential terminal GND2. The drain of switch element N2 is connected to the external terminal T OAL It is connected to the first end of resistor R2 via [a specific component].

[0202] When switch element P2 is in the ON state, external terminal T OAH The power supply voltage Vcca is output from there. Also, when the switch element N2 is in the ON state, the external terminal T OAL The reference potential terminal GND2 is output from there.

[0203] The driver 422 controls the switching elements P2 and N2 to turn the high-side switch SWH on / off as follows: When the high-side switch SWH is turned on, the switching element P2 is turned on and the switching element N2 is turned off. Then, as described above, the power supply voltage Vcca is at the external terminal T OAH This is output from the resistor R1, supplying a high-level drive voltage GH (= voltage relative to the power supply voltage Vcca) to the gate terminal of the high-side switch SWH.

[0204] As mentioned above, the power supply voltage Vcca is higher than the voltage at node n1 (= the source voltage of the high-side switch SWH). Therefore, at this time, the gate-source voltage (the voltage difference between the voltage at node n1 and the power supply voltage Vcca) exceeds the on-threshold voltage of the high-side switch SWH, and the high-side switch SWH turns on.

[0205] Conversely, to turn off the high-side switch SWH, switch element P2 is turned off and switch element N2 is turned on. Then, as described above, the reference potential terminal GND2 is connected to the external terminal T OAL This is output from the resistor R2, supplying a low-level drive voltage GH (= reference voltage GND2) to the gate terminal of the high-side switch SWH. As a result, the gate-source voltage (the voltage difference between the voltage at node n1 and the power supply voltage Vcca) falls below the on-threshold voltage of the high-side switch SWH, causing the high-side switch SWH to turn off.

[0206] <About the mirror clamp circuit 423> The switch element N3, together with the driver 422, constitutes the Miller clamp circuit 423. The Miller clamp circuit 423 will be described here. The switch element N3 is an N-channel MOSFET. The source of the switch element N3 is the external terminal T MC It is connected to node n1 via [a certain method]. The drain of switch element N3 is connected to the reference potential terminal GND2.

[0207] The Miller clamp circuit 423 prevents the high-side switch SWH from being accidentally turned on. Specifically, to prevent the gate voltage of the high-side switch SWH from rising unintentionally, the Miller clamp circuit 423 forcibly lowers the gate voltage of the high-side switch SWH to an arbitrary value (e.g., 0V) at a predetermined timing.

[0208] The "false turn-on" described above can occur, for example, when the high-side switch SWH and low-side switch SWL are SiC-MOSFETs. SiC-MOSFETs can experience ringing or a rise in gate voltage during on-to-off state transitions (switching). This rise can cause the high-side switch SWH to self-turn on (false turn-on). Furthermore, this rise in gate voltage is not limited to SiC-MOSFETs and can occur in other types of switching elements as well.

[0209] As described above, the Miller clamp circuit 423 forcibly lowers the gate voltage of the high-side switch SWH to an arbitrary value (e.g., 0V) at a predetermined timing. Specifically, the logic circuit 411 raises the drive signal G5 to a high level at the off timing of the high-side switch SWH to turn on the switch element N3. Therefore, at the off timing of the high-side switch SWH, the gate voltage of the high-side switch SWH is forcibly lowered to below the on threshold (specifically, relative to the reference voltage GND2). In this way, the Miller clamp circuit 423 suppresses false on-off of the high-side switch SWH.

[0210] <Considerations regarding the mirror clamp circuit 423> As mentioned above, the high-side chip 420 operates by receiving the power supply voltage Vcca generated by the bootstrap circuit 510Y. However, for a predetermined period from the start-up of the drive circuit 500Y, the charge level of capacitor Cb is not sufficiently high. Therefore, during this period, the power supply voltage Vcca is low, and the high-side chip 420 may not operate properly.

[0211] In other words, the Miller clamp circuit 423 may not function as described above. Specifically, it may not be possible to turn on the switch element N3 at the off timing of the high-side switch SWH. If this occurs, the rise in the gate voltage (= drive voltage GH) of the high-side switch SWH as described above cannot be suppressed during this period. Therefore, during this period, the high-side switch SWH may unintentionally self-turn on (falsely turn on).

[0212] To address these issues, the drive circuit 500X of this disclosure is capable of suppressing the self-turn-on of the high-side switch SWH as described above. The drive circuit 500X according to an embodiment of this disclosure will now be described in detail. Note that the drive circuit 500X according to an embodiment of this disclosure includes components common to the previously described drive circuit 500Y. For this reason, the same reference numerals are used for the common components and their descriptions are omitted.

[0213] <Regarding the drive circuit 500X of the embodiment described herein> Figure 11 shows the configuration of a motor device 800 equipped with the inverter 700X according to this disclosure. The drive circuit 500X in this configuration example is usable with the inverter 700X. The inverter 700X is a type of motor drive device that converts DC power supplied from an on-board battery (not shown) into AC power to drive a motor M.

[0214] As shown in Figure 11, motor M is a three-phase motor that is driven to rotate according to the three-phase drive voltages input from the three-phase half-bridge output stage. Motor M is a three-phase motor that is driven to rotate according to the three-phase drive voltages GU / GV / GW (corresponding to the output voltage Vout in Figure 12, which will be shown later) input from the three-phase half-bridge output stage. Motor M is mounted on motor device 800. Motor device 800 is configured to drive motor M using a three-phase inverter 700X.

[0215] Figure 12 shows the configuration of the inverter 700X equipped with the drive circuit 500X. Note that Figure 12 shows the inverter 700X which is one phase of the three-phase half-bridge output stage.

[0216] As shown in Figure 12, the inverter 700X is equipped with a switch output stage 550 similar to that described above. In addition, the inverter 700X is equipped with a drive circuit 500X. The drive circuit 500X operates by receiving a power supply voltage Vccb. When the drive circuit 500X is started up, the power supply voltage Vccb rises to the operating voltage of the drive circuit 500X.

[0217] The drive circuit 500X receives an enable signal ENA and input signals INA and INB from the ECU (Electronic Control Unit) 2. The drive circuit 500X operates or stops depending on the logic level of the enable signal ENA. The drive circuit 500X generates drive voltages GH and GL based on the input signals INA and INB (more specifically, the combination of the logic levels of input signals INA and INB). The drive circuit 500X uses drive voltages GH and GL to drive and control the switch output stage 550.

[0218] In the case shown in Figure 11, the switch output stage 550 of each inverter 700X becomes a 3-phase (U-phase / V-phase / W-phase) half-bridge output stage. Each switch output stage 550 generates a 3-phase output voltage Vout (drive voltage GU / GV / GW in Figure 11) and outputs it from each node n1. The motor M is driven by receiving the 3-phase drive voltage GU / GV / GW.

[0219] <Detailed configuration of the 500X drive circuit> The drive circuit 500X includes a signal transmission device 400 similar to that described above, and predetermined disk read components (as shown in this figure, resistors R1 to R4). In addition, the drive circuit 500X includes a bootstrap circuit 510X.

[0220] Bootstrap circuit 510X corresponds to bootstrap circuit 510Y described above. That is, bootstrap circuit 510X has the same diode D1 and capacitor Cb as described above. On the other hand, bootstrap circuit 510X differs from bootstrap circuit 510Y in that it includes a precharge circuit 600.

[0221] The pre-charge circuit 600 includes switching elements N4 and N5, resistors R5 to R7, and a Zener diode D2.

[0222] Switch elements N4 and N5 are each N-channel MOSFETs. The drain of switch element N4 is connected to the second terminal of capacitor Cb. The gate of switch element N4 is connected to the cathode of Zener diode D2, along with the first terminal of resistor R5. The source of switch element N4 is connected to the reference potential terminal GND3, along with the cathode of Zener diode D2.

[0223] The drain of switch element N5 is connected to the first terminal of resistor R6. The gate of switch element N5 is connected to the first terminal of resistor R7. The source of switch element N5 is connected to the reference potential terminal GND3.

[0224] The second terminal of resistor R5, along with the second terminal of resistor R6, is connected to the terminal to which the power supply voltage Vccb is applied. The second terminal of resistor R7 is connected to the external terminal T. ENA It is also connected to the output terminal of the enable signal ENA (=ECU2). At the connection node between resistor R5 and Zener diode D2 (=gate of switch element N4), a voltage V1 is generated, which is the power supply voltage Vccb divided by resistor R5 and Zener diode D2.

[0225] <Regarding the charging of capacitor Cb> Next, we will explain the operation of the bootstrap circuit 510X (especially the charging of capacitor Cb). First, when the drive circuit 500X is started, the power supply voltage Vccb rises to a predetermined voltage value (= the operating voltage of the drive circuit 500X). At this time, the ECU2 maintains the enable signal ENA at a low level. Therefore, the signal transmission device 400 does not start operating. Also at this time, the gate voltage of the switch element N5 is below the on threshold voltage of the switch element N5. Therefore, the switch element N5 is off at this time.

[0226] At this time, as the power supply voltage Vccb rises, the voltage V1 also rises. When the voltage V1 rises and exceeds the ON threshold voltage of the switch element N4, the switch element N4 turns on. That is, the source and drain of the switch element N4 become conductive. Then, the capacitor Cb has the power supply voltage Vccb applied to its first terminal and the reference voltage GND3 applied to its second terminal. As a result, the capacitor Cb is charged by the voltage difference between the power supply voltage Vccb and the reference voltage GND3.

[0227] When capacitor Cb is sufficiently charged, ECU2 raises the enable signal ENA to a high level. Note that "capacitor Cb is sufficiently charged" can be interpreted as the power supply voltage Vcca reaching a voltage value that can activate the Miller clamp circuit 423 (specifically, a voltage value that can control the on / off state of the switch element N3).

[0228] When the enable signal ENA rises to a high level, the signal transmission device 400 is activated. At this time, the gate voltage of the switch element N5 (= the enable signal ENA supplied from the ECU2 via resistor R7) exceeds the on threshold voltage of the switch element N5. Then, the switch element N5 turns on.

[0229] When switch element N5 is turned on, the gate of switch element N4 becomes at the same potential as the reference potential terminal GND3 via resistors R5 and R6 and switch element N5. That is, at this time the voltage V1 falls below the on threshold voltage of switch element N4. As a result, switch element N4 is turned off.

[0230] Therefore, while the signal transmission device 400 is running (i.e., while the enable signal ENA is maintained at a high level), the switch element N4 is off, and the capacitor Cb is not charged by the switch element N4. Note that while the signal transmission device 400 is running, the capacitor Cb is charged by the turning on of the low-side switch SWL.

[0231] Regarding the timing of when ECU2 raises the enable signal ENA to a high level, the following may be considered: For example, ECU2 can be configured to monitor the charge level of capacitor Cb (more specifically, the voltage value of the power supply voltage Vcca) and raise the enable signal ENA to a high level depending on the monitoring status.

[0232] As described above, the signal transmission device 400 is not activated during the period from when the drive circuit 500X is started up until the enable signal ENA rises to a high level. Therefore, the switch elements P2 and N2 remain off, and the drive voltage GH is not driven. Consequently, the gate voltage of the high-side switch SWH does not rise unintentionally during this period. On the other hand, the capacitor Cb is charged by the pre-charge circuit 600 during this period as described above. Therefore, even if the signal transmission device 400 is not started and the low-side switch SWL remains off, the capacitor Cb can be charged and the power supply voltage Vcca can be boosted to a sufficient voltage (the voltage at which the Miller clamp circuit 423 can operate). Thus, it is possible to suppress the high-side switch SWH from self-turning (falsely turning on) during the period from when the drive circuit 500X is started up until the high-side chip 420 becomes operational.

[0233] As mentioned above, when capacitor Cb is sufficiently charged, the enable signal ENA rises to a high level, and the signal transmission device 400 starts up. At this time, as mentioned above, the switch element N5 turns on, and capacitor Cb is no longer charged by the precharge circuit 600. Meanwhile, the signal transmission device 400 is running, and the switch elements P1, P2, N1, and N2 turn on / off according to the combination of logic levels of the input signals INA and INB. As a result, the high-side switch SWH and the low-side switch SWL turn on / off. At this time (=while the signal transmission device 400 is running), the low-side switch SWL turns on to charge capacitor Cb and maintain the power supply voltage Vcca at an arbitrary voltage. Therefore, even while the signal transmission device 400 is running, the Miller clamp circuit 423 can suppress the self-turn-on of the high-side switch SWH.

[0234] <Implementation example of the inverter 700X of this disclosure> Figure 13 shows a vehicle A equipped with a motor unit 800. As shown in Figure 13, the drive circuit 500X, inverter 700X, and motor unit 800 can be mounted on vehicle A.

[0235] <Variation> Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. For example, although ECU2 is shown to raise the enable signal ENA to a high level according to the monitoring state of capacitor Cb, it is not limited to this. For example, ECU2 may not monitor the state of capacitor Cb, but instead measure the time from the start of the drive circuit 500X (for example, the rising time of the power supply voltage Vccb) using a timer circuit, and raise the enable signal ENA when the measured time exceeds a predetermined time. This predetermined time is the time required for capacitor Cb to be sufficiently charged, and is an arbitrary set time determined in advance.

[0236] <Note> The drive circuit (500X) described in the specification comprises a high-side driver (420) configured to drive and control the high-side switch (SWH) of a high-side switch (SWL) and a low-side switch (SWL) bridged together based on external signals (ENA, INA, INB); a low-side driver (410) configured to drive and control the low-side switch (SWL) based on external signals (ENA, INA, INB); and a bootstrap circuit (510X) configured to boost the power supply voltage (Vccb) to generate the drive voltage (GH) for the high-side switch (SWH) based on external signals (ENA, INA, INB), wherein the bootstrap circuit (510X) is supplied with the power supply voltage (Vccb) and a reference voltage (GND1, GND3) lower than the power supply voltage (Vccb), and is charged according to the power supply voltage (Vccb) and the reference voltage (GND1, GND3). The system includes a capacitance circuit (Cb) configured to generate a drive voltage (GH), and a precharge circuit (600) configured to supply a reference voltage (GND1, GND3) to the capacitance circuit (Cb) when the high-side switch (SWH) and low-side switch (SWL) are not driven, based on an external signal (ENA), and not supply the reference voltage (GND1, GND3) to the capacitance circuit (Cb) when the high-side switch (SWH) and low-side switch (SWL) are driven, wherein the capacitance circuit (Cb) is configured to receive the reference voltage (GND1, GND3) via the low-side switch (SWL) when the low-side switch (SWL) is driven and the low-side switch (SWL) is ON, and to receive the reference voltage (GND1, GND3) via the precharge circuit (600) when the low-side switch (SWL) is not driven (first configuration).

[0237] The first configuration of the drive circuit (500X) has a capacitance circuit (Cb) in which the first terminal is connected to the terminal to which the power supply voltage (Vccb) is applied and the second terminal is supplied with a reference voltage (GND1, GND3), and the capacitor (Cb) is configured to be charged according to the voltage difference between the power supply voltage (Vccb) and the reference voltage (GND1, GND3). The precharge circuit (600) is configured to conduct through itself to the second terminal and the terminal to which the reference voltage (GND1, GND3) is applied when the high-side switch (SWH) and low-side switch (SWL) are not driven, and to eliminate the conduction between the second terminal and the terminal to which the reference voltage (GND1, GND3) is applied through itself when the high-side switch (SWH) and low-side switch (SWL) are driven (second configuration).

[0238] The drive circuit (500X) according to the second configuration is preferably configured such that the precharge circuit (600) includes a precharge switch element (N4) connected between the second terminal and the terminal to which the reference voltage (GND1, GND3) is applied, and configured to conduct between the second terminal and the terminal to which the reference voltage (GND1, GND3) is applied when it is ON, and a control switch element (N5) connected to the output terminal of the external signal (ENA), the terminal to which the power supply voltage (Vccb) is applied, the terminal to which the reference voltage (GND1, GND3) is applied, and the control terminal of the precharge switch element (N4), and configured to drive and control the precharge switch element (N4) by supplying either the power supply voltage (Vccb) or the reference voltage (GND1, GND3) to the control terminal depending on whether the high-side switch (SWH) or the low-side switch (SWL) is driven based on the external signal (ENA) (third configuration).

[0239] In the third configuration, the drive circuit (500X) is configured such that when the high-side switch (SWH) and low-side switch (SWL) are not driven, the control switch element (N5) supplies a power supply voltage (Vccb) to the control terminal to turn on the pre-charge switch element (N4), and when the high-side switch (SWH) and low-side switch (SWL) are driven, it supplies a reference voltage (GND1, GND3) to the control terminal to turn off the pre-charge switch element (N4) (fourth configuration).

[0240] In any of the first to fourth configurations, the drive circuit (500X) is preferably configured such that the high-side driver (420) is an integrated chip (fifth configuration).

[0241] In any of the first to fifth configurations, the drive circuit (500X) is configured such that the low-side driver (410) is an integrated chip (sixth configuration).

[0242] In the sixth configuration, the drive circuit (500X) is preferably configured such that the pre-charge circuit (600) is integrated within the low-side driver (410) (seventh configuration).

[0243] The drive circuit (500X) according to any of the fifth to seventh configurations may be configured to include an isolation circuit (430) configured to transmit signals between the high-side driver (420) and the low-side driver (410) while insulating the high-side driver (420) from the low-side driver (410) (eighth configuration).

[0244] The inverter (700X) described in the specification is configured to include a drive circuit (500X) in any of the first to eight configurations, and a switch output stage comprising a high-side switch (SWH) and a low-side switch (SWL) bridged together, configured to receive a DC input voltage (VD1) and output an AC output voltage (Vout) (configuration 9).

[0245] In the ninth configuration, the inverter (700X) is configured such that the low-side switch (SWL) is connected between the capacitive circuit (Cb) and the application terminals of the reference voltage (GND1, GND3), and in the ON state, it conducts between the capacitive circuit (Cb) and the application terminals of the reference voltage (GND1, GND3) through itself, and in the OFF state, it eliminates the conduction between the capacitive circuit (Cb) and the application terminals of the reference voltage (GND1, GND3) through itself (tenth configuration).

[0246] The electronic device (800) disclosed in the specification is configured to include an inverter (700X) of the ninth or tenth configuration (eleventh configuration).

[0247] The vehicle (A) disclosed in the specification is configured to include electronic equipment (800) according to the 11th configuration (12th configuration). [Explanation of Symbols]

[0248] 5 Semiconductor Equipment 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformers 22 Low-potential coil (primary coil) 23. High-potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42. First Main Surface 43 Second Main Surface 44A~44D Chip sidewall 45. First Functional Device 51 Insulating layer 52 Insulation main surface Insulating side walls 53A to 53D Lowermost insulating layer 55 Topmost insulating layer 56 Interlayer insulating layer 57 First insulating layer 58 Second insulating layer 59 Second functional device 60 Seal conductor 61 Device region 62 Outer region 63 Seal plug conductor 64 Seal via conductor 65 First inner region 66 Second inner region 67 Through-wiring 71 Low-potential connection wiring 72 Lead-out wiring 73 First connection plug electrode 74 Second connection plug electrode 75 Pad plug electrode 76 Substrate plug electrode 77 First electrode layer 78 Second electrode layer 79 Wiring plug electrode 80 High-potential connection wiring 81 Pad plug electrode 82 Dummy pattern 85 High-potential dummy pattern 86 First high-potential dummy pattern 8​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​141 First Inorganic Insulating Layer 142 Second Inorganic Insulating Layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 buffers 220 Driver chip (second chip) 221, 222 buffers 223 Pulse receiving circuit (RS flip-flop) 224 drivers 230 Transchip (Third Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformers 231p, 232p primary coil 231s, 232s Secondary coil 300 Transchips 301 First Transformer 302 Second Transformer 303 Third Transformer 304 4th Transformer 305 First Guard Ring 306 Second Guard Ring a1~a8 Pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads Primary coils of L1p and L2p Secondary coils of L1s, L2s, L3s, and L4s External terminals of T21, T22, T23, T24, T25, and T26 First direction X Internal terminals of X21, X22, and X23 Second direction Y Wiring of Y21, Y22, and Y23 Normal direction Z Vias of Z21, Z22, and Z23 Signal transmission device 400 Low-side chip 410 Logic circuit 411 Driver 412 High-side chip 420 Logic circuit 421 Driver 422 Mirror clamp circuit 423 Transformer chip 430 Transformers 431 and 432 Drive circuit 500X Drive circuit 500Y Bootstrap circuit 510X Bootstrap circuit 510Y Switch output stage 550 Pretcharge circuit 600 Inverter 700X Inverter 700Y Motor device 800 Vehicle A Capacitor Cb Diode D1 Zener diode D2 Enable signal ENA Drive signals G1 to G5 Drive voltages GH and GL Drive voltages GU, GV, and GW Ground terminal and ground voltage GND1 Reference potential terminal and reference voltage GND2 Reference potential terminal and reference voltage GND3 Input signals INA and INB Motor M N1~N5 Switching elements P1, P2 switching elements R1~R7 resistance S1~S4 Control signals SWH High-Side Switch SWL Low Side Switch T ENA External terminals T INA External terminals T INB External terminals T MC External terminals T OAH External terminals T OAL External terminals T OBH External terminals T OBL External terminals T OHA External terminals T Vccb External terminals T vcca External terminals VD1 Motor drive voltage Vcca (Power supply voltage) Vccb Power supply voltage Vout output voltage n1 node

Claims

1. A high-side driver configured to drive and control the high-side switch among a high-side switch and a low-side switch that are bridged together, based on an external signal, A low-side driver configured to drive and control the low-side switch based on the aforementioned external signal, A bootstrap circuit configured to boost the power supply voltage to generate the drive voltage for the high-side switch based on the aforementioned external signal, Equipped with, The bootstrap circuit described above is A capacitive circuit is configured to receive the aforementioned power supply voltage and a reference voltage lower than the aforementioned power supply voltage, and to be charged according to the aforementioned power supply voltage and the reference voltage to generate the aforementioned drive voltage, A precharge circuit configured to supply the reference voltage to the capacitance circuit when the high-side switch and the low-side switch are not driven, based on the external signal, and not supply the reference voltage to the capacitance circuit when the high-side switch and the low-side switch are driven, It has, The aforementioned capacitance circuit is When the low-side switch is driven and the low-side switch is in the ON state, the reference voltage is supplied via the low-side switch. A drive circuit that receives the reference voltage via the precharge circuit when the low-side switch is not driven.

2. The capacitance circuit has a capacitor configured such that the first terminal is connected to the terminal for applying the power supply voltage, and the second terminal receives the reference voltage and charges according to the voltage difference between the power supply voltage and the reference voltage. The aforementioned pre-charge circuit is When the high-side switch and the low-side switch are not driven, the second terminal and the terminal to which the reference voltage is applied are made conductive through themselves. The drive circuit according to claim 1, which eliminates the conduction state between the second terminal and the terminal to which the reference voltage is applied via itself when the high-side switch and the low-side switch are driven.

3. The aforementioned pre-charge circuit is A precharge switch element is connected between the second terminal and the terminal to which the reference voltage is applied, and is configured to conduct when the ON state, the second terminal and the terminal to which the reference voltage is applied. A control switch element is connected to the output terminal of the external signal, the application terminal of the power supply voltage, the application terminal of the reference voltage, and the control terminal of the precharge switch element, and is configured to drive and control the precharge switch element by supplying either the power supply voltage or the reference voltage to the control terminal based on the external signal, depending on whether the high-side switch and the low-side switch are driven or not. The drive circuit according to claim 2, having the following features.

4. The control switch element is When the high-side switch and the low-side switch are not driven, the power supply voltage is supplied to the control terminal to turn on the pre-charge switch element. The drive circuit according to claim 3, wherein when the high-side switch and the low-side switch are driven, the reference voltage is supplied to the control terminal to turn off the precharge switch element.

5. The drive circuit according to claim 1, wherein the high-side driver is an integrated chip.

6. The drive circuit according to claim 5, wherein the low-side driver is an integrated chip.

7. The drive circuit according to claim 6, wherein the pre-charge circuit is integrated within the low-side driver.

8. The drive circuit according to claim 6, further comprising an isolation circuit configured to transmit signals between the high-side driver and the low-side driver while insulating the high-side driver from the low-side driver.

9. A drive circuit according to any one of claims 1 to 8, A switch output stage includes the high-side switch and the low-side switch, which are bridged together, and is configured to receive a DC input voltage and output an AC output voltage, An inverter equipped with [a specific feature / feature].

10. The inverter according to claim 9, wherein the low-side switch is connected between the capacitive circuit and the terminal to which the reference voltage is applied, and in the ON state, it causes the capacitive circuit and the terminal to which the reference voltage is applied to conduct through itself, and in the OFF state, it resolves the conduction between the capacitive circuit and the terminal to which the reference voltage is applied through itself.

11. An electronic device comprising the inverter described in claim 9.

12. A vehicle equipped with the electronic equipment described in claim 11.

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