Method, apparatus, medium, and device for detecting bus access status in integrated circuits

Abstract

Embodiments of this disclosure disclose methods, apparatus, media, and devices for detecting bus access states in integrated circuits. [Solution] This method includes the steps of: detecting a first instruction transmitted on a first channel in a bus of an integrated circuit; accumulating the number of first instructions using a first counter to obtain a first cumulative value; using a second counter to perform a count representing the timeout duration for the first instructions accumulated by the first counter based on the first cumulative value to obtain a second cumulative value; and determining the access state of the bus based on the relationship between the second cumulative value and a preset threshold.

Description

Technical Field

[0001] The present disclosure relates to the field of data interaction technology, and particularly to a method, apparatus, medium, and device for detecting a bus access state in an integrated circuit.

Background Art

[0002] Chip systems (such as system-on-chip (SoC) and application-specific integrated circuits (ASICs)) have various SoC bus transmission protocols, and these transmission protocols have a common feature of correctly transmitting data using handshake signals between master and slave devices. Most bus transmissions can be divided into two parts: the handshake stage of instruction transmission and the handshake stage of data transmission.

[0003] Once the handshake signal of the slave device is not correctly sent, the bus will hang up. When the bus hangs up, serious problems such as chip system freezing will occur.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure is made to solve the above technical problems. Embodiments of the present disclosure provide a method, apparatus, medium, and device for detecting a bus access state in an integrated circuit.

Means for Solving the Problems

[0005] A method for detecting a bus access state in an integrated circuit according to an aspect of an embodiment of the present disclosure includes: detecting a first instruction transmitted on a first channel in a bus of the integrated circuit; The steps include: accumulating the number of the first instructions using a first counter and obtaining a first cumulative value; Based on the first cumulative value, a second counter performs a count representing the timeout duration for the first instruction accumulated by the first counter, and obtains a second cumulative value. The process includes the step of determining the access state of the bus based on the relationship between the second cumulative value and a preset threshold.

[0006] A bus access state detection device in an integrated circuit according to another embodiment of the embodiments of the present disclosure is: An instruction detection module for detecting a first instruction transmitted on a first channel in an integrated circuit bus, A first counter that accumulates the number of first instructions detected by the instruction detection module and obtains a first cumulative value, A second counter is used to obtain a second cumulative value by performing a count representing the timeout duration for the first instruction accumulated by the first counter, based on the first cumulative value obtained by the first counter, The system includes a state determination module for determining the access state of the bus based on the relationship between a second cumulative value obtained by the second counter and a preset threshold.

[0007] A computer-readable storage medium according to another embodiment of the present disclosure stores a computer program for performing a method for detecting the bus access state in an integrated circuit described in any of the above embodiments.

[0008] Electronic devices relating to further embodiments of the embodiments of this disclosure are: Processor and The processor comprises a memory for storing executable commands, The processor performs the bus access state detection method in the integrated circuit described in any of the above embodiments by reading and executing the executable command from the memory. [Effects of the Invention]

[0009] According to the bus access state detection method, apparatus, medium, and device in the above embodiment of the present disclosure, the number of incomplete first instructions transmitted on the first channel of the bus can be determined by accumulating the number of first instructions transmitted on the first channel of the bus using a first counter. If the first cumulative value is not zero, it indicates that there are incomplete first instructions on the first channel. In this case, a second counter is used to count the timeout duration for these incomplete first instructions, and the second cumulative value obtained from the count represents the duration for which the first instruction is transmitted on the first channel. By comparing the relationship between the second cumulative value and a preset threshold, it is possible to determine whether the duration for which the bus is occupied by the first instruction exceeds the preset threshold, thereby determining the bus access state. Consequently, detection of the situation in which the first channel of the bus is occupied can be achieved, bus occupancy timeout problems can be detected in a timely manner, reducing the occurrence of serious problems such as freezes in the chip system and significantly improving the transmission performance of the chip system.

[0010] The technical proposal of this disclosure will be described in more detail below with reference to the drawings and examples.

[0011] A more detailed description of embodiments of this disclosure with reference to the drawings will make the above and other objectives, features, and advantages of this disclosure clearer. The drawings are used to provide a further understanding of embodiments of this disclosure and constitute part of the specification and are used in conjunction with embodiments of this disclosure to interpret this disclosure and do not limit this disclosure. In the drawings, the same reference numerals usually represent the same member or step. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram of the flow of a method for detecting the bus access state in an integrated circuit according to one exemplary embodiment of the present disclosure. [Figure 2]This is a schematic diagram of the timeout counting flow in a method for detecting the bus access state in an integrated circuit according to another exemplary embodiment of the present disclosure. [Figure 3] This is a schematic diagram of the instruction accumulating flow in a method for detecting the bus access state in an integrated circuit according to another exemplary embodiment of the present disclosure. [Figure 4] This is a schematic diagram of a timeout counting flow in a method for detecting the bus access state in an integrated circuit according to a further exemplary embodiment of the present disclosure. [Figure 5] This is a schematic diagram of a timeout counting flow in a method for detecting the bus access state in an integrated circuit according to a further exemplary embodiment of the present disclosure. [Figure 6] This is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to one exemplary embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to another exemplary embodiment of the present disclosure. [Figure 8] This is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to another exemplary embodiment of the present disclosure. [Figure 9] This is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to further exemplary embodiments of the present disclosure. [Figure 10] This is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to further exemplary embodiments of the present disclosure. [Figure 11] This is a structural diagram of an electronic device relating to one exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0013] Hereinafter, illustrative examples of the Disclosure will be described in detail with reference to the drawings in order to interpret this Disclosure. However, the examples described are only a selection of the Disclosure, not all of the Disclosure, and this Disclosure is not limited to the illustrative examples described herein.

[0014] Note that, unless otherwise specified, the scope of the present disclosure is not limited to the relative arrangements of the members and steps, mathematical formulas, and values described in these embodiments.

[0015] [Summary of the Application] During the implementation of the present disclosure, the inventors have found the following. Bus hang-up refers to a situation where an instruction in a bus cannot release the bus normally due to some reason during communication, resulting in the bus being locked and unable to perform normal data transmission. In such a situation, usually, the entire chip system cannot communicate with another device on the bus, affecting the normal operation of the chip system. In the existing technology, the problem of bus hang-up cannot be discovered in a timely manner, the bus becomes unusable for a long time, and serious problems such as a significant reduction in the performance of the chip system and even crashes occur.

[0016] [Exemplary Method] FIG. 1 is a schematic diagram of the flow of a method for detecting a bus access state in an integrated circuit according to an exemplary embodiment of the present disclosure. This embodiment can be applied to an electronic device and, as shown in FIG. 1, includes steps 102 to 108.

[0017] In step 102, a first instruction transmitted on a first channel in the bus of the integrated circuit is detected.

[0018] Selectively, the first channel can be any channel on the bus, for example, the first channel is a Read Address Channel (AR channel, for transmitting address and control information of read requests), a Write Address Channel (AW channel, for transmitting address and control information of write requests), or a Snoop Address Channel (AC channel, for transmitting snooping transactions between caches in the system, allowing one cache master device to snoop on read and write operations of other cache master devices to a specific memory address). The first instruction corresponds to the first channel, for example, if the first channel is an AR channel, the corresponding first instruction is a read instruction (AR instruction); if the first channel is an AW channel, the corresponding first instruction is a write instruction (AW instruction); and if the first channel is an AC channel, the corresponding first instruction is a snoop instruction (AC instruction).

[0019] In step 104, the number of first instructions is accumulated using the first counter to obtain the first cumulative value.

[0020] In one embodiment, the first cumulative value represents the number of first instructions transmitted on the first channel that are incomplete, and this first cumulative value can represent the situation in which the first channel is occupied.

[0021] In step 106, based on the first cumulative value, the second counter performs a count representing the timeout duration for the first instruction accumulated by the first counter, and obtains the second cumulative value.

[0022] In the embodiments of this disclosure, if the first cumulative value is not zero, the timeout duration is counted for at least one first instruction that has been accumulated in the first counter; if the first cumulative value is zero, it means that there is no first instruction for which the timeout duration needs to be accumulated, and the second cumulative value is zero.

[0023] In one selectable embodiment, the first counter does not distinguish between at least one first instruction, the second cumulative value counts the timeout duration of at least one first instruction in the first counter, and when one of the feedback indicators corresponding to the first instruction is received, the second cumulative value is cleared and the first cumulative value is decremented, and if the first cumulative value is not zero, the counting of the timeout duration is restarted. In another selectable embodiment, each first instruction is distinguished in the first counter, the timeout duration of the first instruction first received in chronological order is counted by a second cumulative value, the second cumulative value is cleared and the first cumulative value is decremented only when a feedback indicator corresponding to this first received first instruction is received, and if the first cumulative value is not zero, the counting of the timeout duration is restarted, and in this embodiment, when a feedback indicator corresponding to another first instruction in the first counter is received, the second cumulative value is not cleared but the first cumulative value is decremented.

[0024] In step 108, the bus access status is determined based on the relationship between the second cumulative value and the preset threshold.

[0025] In this embodiment, the preset threshold can be set according to the specific application scenario, and the set preset threshold can be stored in a register for read-only convenience.

[0026] If the second cumulative value is selected to be greater than or equal to a preset threshold, the bus access status is determined to be hung up, and an access hang-up message is sent.

[0027] In this embodiment, a hang-up state refers to a state in which the first channel on the bus is occupied by at least one first instruction, preventing it from operating normally, and thus preventing other data, instructions, etc. from being transmitted through this first channel, resulting in all devices communicating via this first channel being unable to communicate. Selectively, if the second cumulative value is less than a preset threshold, the bus access state is normal, which indicates that devices communicating via this first channel can communicate normally.

[0028] In this embodiment, access hang-up information can be optionally sent via an interrupt mechanism, and this information can be optionally sent to an interrupt collection module (e.g., the CPU). Interrupt reporting in this embodiment refers to the process by which, when an abnormal situation requiring urgent processing (bus hang-up) or a request from an external device is sent while the computer is executing a program, the execution of the current program is temporarily suspended to process these requests, and once processing is complete, the program returns to its original breakpoint and continues execution. The interrupt mechanism is implemented in hardware and enables the computer to respond to external requests while a program is executing, thereby improving the degree of parallel operation of the system and the operating efficiency of the CPU.

[0029] The bus access state detection method in the integrated circuit according to the above embodiment of this disclosure can determine the number of incomplete first instructions transmitted on the first channel of the bus by accumulating the number of first instructions transmitted on the first channel using a first counter. If the first cumulative value is not zero, it indicates that there are incomplete first instructions on the first channel. In this case, a second counter is used to count the timeout duration for these incomplete first instructions. The second cumulative value obtained from the count represents the duration for which the first instruction is transmitted on the first channel. By comparing the relationship between the second cumulative value and a preset threshold, it is possible to determine whether the duration for which the bus is occupied by the first instruction exceeds the preset threshold, thereby determining the bus access state. Consequently, detection of the situation in which the first channel of the bus is occupied can be achieved, bus occupancy timeout problems can be detected in a timely manner, reducing the occurrence of serious problems such as freezes in the chip system and significantly improving the transmission performance of the chip system.

[0030] In some of the selectable embodiments, step 104 is: The process may include the step of performing a decrement operation on a first cumulative value based on a feedback indicator corresponding to a first instruction received.

[0031] In this embodiment, different types of first instructions correspond to different feedback indicators. In one selectable example, if the first channel transmitting the first instructions is a read-address channel, then in this embodiment, the corresponding feedback indicator is the rlast signal, which indicates the reception of the last read data corresponding to any of the first instructions (read instructions) (the read data represents the data returned based on this first instruction, and each first instruction can correspond to multiple read data). Upon receiving this feedback indicator, a decrement operation is performed on the first cumulative value; that is, upon receiving the feedback indicator corresponding to any of the first instructions, it indicates that one first instruction has already been completed, and 1 is subtracted from the first cumulative value, which represents the number of cumulative first instructions.

[0032] In another selectable example, if the first channel transmitting the first instruction is a write address channel, then in this embodiment, the corresponding feedback indicator is a signal (e.g., a bvalid signal, indicating that the write response is valid) that has received all the data corresponding to any of the first instructions (write instructions), and upon receiving this feedback indicator, a decrement operation is performed on the first cumulative value.

[0033] In yet another selectable example, if the first channel transmitting the first instruction is a snoop address channel, then in this embodiment, the corresponding feedback indicator is a response signal (e.g., a crvalid signal, indicating that the snoop response is valid) returned from a Snoop Response Channel (abbreviated as CR channel), and upon receiving this feedback indicator, a decrement operation is performed on the first cumulative value.

[0034] As shown in Figure 2, in addition to the embodiment shown in Figure 1 above, step 106 may include steps 1061 to 1062.

[0035] In step 1061, based on the first cumulative value, it is determined that there is a first instruction for which the feedback indicator was not received (not received).

[0036] In this embodiment, if the first cumulative value is zero, it indicates that there are no incomplete first instructions in the first channel, that is, the first instruction is not occupying the first channel, so there is no need to count the timeout, and it can be understood that the second cumulative value does not exist or the second cumulative value is zero. If the first cumulative value is not zero, it indicates that at least one first instruction is occupying the first channel, that is, at least one first instruction has not received a feedback indicator.

[0037] In step 1062, the second cumulative value is cleared based on the feedback indicator of the first command received.

[0038] In this embodiment, when one of the first instructions corresponding to the first cumulative value receives a feedback indicator, the first channel is able to receive the feedback indicator, indicating that the first channel is smooth (capable of transmitting information), and the second cumulative value is cleared. After clearing the second cumulative value, it is determined again whether the first cumulative value is zero. If the first cumulative value is not zero, timing is restarted by the second counter, and the second cumulative value accumulated by the timing represents the duration for which the first channel is occupied by at least one first instruction corresponding to the first cumulative value.

[0039] This embodiment clears a second cumulative value based on a feedback indicator, improving the accuracy of the timeout duration represented by the second cumulative value.

[0040] As shown in Figure 3, in addition to the embodiment shown in Figure 1 above, step 104 may include steps 1041 to 1042.

[0041] In step 1041, a first linked list stores at least one type of related information corresponding to at least one first instruction in the order in which the first instruction was received.

[0042] Selectively, at least one type of related information includes address information. Different first instructions can correspond to different related information. For example, related information corresponding to read and write instructions may include, but are not limited to, instruction identifier information (for distinguishing different instructions) and instruction address information (for storing the address of the first instruction). Related information corresponding to snoop instructions may include, but are not limited to, instruction address information (for storing the address of the first instruction) and access type information (for representing the access type corresponding to the snoop instruction). Selectively, each first instruction corresponds to one data in the first linked list. For example, one data corresponding to one first instruction may include instruction identifier: a1, instruction address information: 01011001, etc., and one data corresponding to another first instruction may include instruction identifier: a2, instruction address information: 01011011, etc. This embodiment is merely schematic and is not intended to limit the implementation of the embodiments of this disclosure.

[0043] In some selectable examples, if the first instruction is a read instruction or a write instruction, step 1041 is performed. This may include assigning a corresponding first indicator to a detected first instruction to obtain at least one first indicator, where the relevant information includes the first indicator, each first indicator corresponding to at least one first instruction.

[0044] If a single first indicator (ID) corresponds to multiple first instructions, the multiple first instructions corresponding to the same first indicator are sorted (arranged) in chronological order, and the received feedback indicators are also assigned in chronological order to the multiple first instructions corresponding to this first indicator. This ensures order preservation of the same indicator (ID), and by increasing the number of first indicators and preserving the order of the same indicators, the timeout count is executed independently for each first instruction, improving the accuracy of the count.

[0045] Step 1041 may further include saving at least one first marker by a first link list.

[0046] In this embodiment, by assigning the corresponding first indicator to the first instruction, the problem of the order of feedback indicators being disrupted is solved. When a feedback indicator is received, the first indicator and the feedback indicator are matched to determine which first instruction has been completed. This ensures that a timeout count can be performed for the same instruction using the second cumulative value, thereby improving the accuracy of the second cumulative value.

[0047] In step 1042, the first counter is used to accumulate the number of first instructions corresponding to the related information stored in the first linked list, thereby obtaining a first cumulative value.

[0048] In this embodiment, by increasing the first link list, the received first instructions are sorted in chronological order, and by storing the relevant information corresponding to each first instruction in the first link list, distinction between each first instruction is achieved. A second cumulative value allows for a timeout count to be performed for each first instruction individually, rather than performing a timeout count for all first instructions as a whole. This improves the accuracy of the timeout duration represented by the second cumulative value. Furthermore, in this embodiment, the relevant information is stored in the first link list, and the problematic address can be quickly identified according to the relevant information.

[0049] As shown in Figure 4, in addition to the embodiment shown in Figure 1 above, step 106 includes steps 1063 to 1065.

[0050] In step 1063, based on the first cumulative value, it is determined that there is a first instruction for which no feedback signal was received (not received).

[0051] Selectively, it is determined whether the first cumulative value is zero or not. If the first cumulative value is zero, it indicates that all first instructions have received a feedback indicator. If the first cumulative value is not zero, it indicates that there are first instructions that did not receive a feedback indicator. In other words, in this embodiment, it is determined whether there are first instructions that require a timeout count based on the relationship between the first cumulative value and zero.

[0052] In step 1064, the second counter sorts the first instruction, which is at the top of the first linked list, into the second instruction.

[0053] In some examples, a timeout count can be performed for each first instruction in the first linked list based on a single second cumulative value. In this example, it is necessary to assign a corresponding second counter to each first instruction and perform the timeout count, which improves the accuracy of the timeout count but also leads to increased resource consumption. In some other examples, a timeout count can be performed only on the first sorted second instruction. This improves the accuracy of the timeout count by performing the timeout count on the second instruction alone and reduces resource consumption by performing the timeout count on only one second instruction.

[0054] In step 1065, a count representing the timeout duration is performed for the second instruction to obtain a second cumulative value.

[0055] In this embodiment, resource consumption is reduced and accurate statistics of channel occupancy are achieved by using only one second counter to count the timeout duration for the second instruction in the first link list. Furthermore, when the first sorted second instruction receives a feedback indicator, the data record corresponding to this second instruction is deleted from the first link list, and the second counter is cleared. In this case, the first instruction sorted at the top of the first link list automatically becomes the new second instruction, and the second counter counts the timeout duration for this new second instruction. This process is repeated until there is no first instruction in the first link list.

[0056] As shown in Figure 5, in addition to the embodiment shown in Figure 4 above, step 1065 may include steps 501 to 502.

[0057] In step 501, a feedback marker transmitted on the first channel is detected.

[0058] In this embodiment, different first channels correspond to different feedback indicators. For example, the first indicator corresponding to the AR channel is represented as ARID, and the corresponding feedback indicator is represented as RID. If ARID and RID match, the first command (or second command) corresponding to this first indicator is removed from the first link list. The first indicator corresponding to the AW channel is represented as AWID, and the corresponding feedback indicator is represented as BID. If AWID and BID match, the first command (or second command) corresponding to this first indicator is removed from the first link list. Since no corresponding first indicator is assigned to the AC channel, the system determines whether or not to remove the first command (or second command) corresponding to this feedback indicator from the first link list by matching the feedback indicators in the order they appear in the first link list.

[0059] In step 502, the corresponding process is performed on the second cumulative value based on the first indicator corresponding to the feedback indicator.

[0060] In this embodiment, for the read address channel and the write address channel, a corresponding first indicator can be found from each feedback indicator, and based on this first indicator, it is determined whether to perform a clear operation or a continuing accumulation operation on the second cumulative value, and by matching the first indicator, it is determined whether the feedback indicator corresponds to the second instruction, and for the snoop address channel, although there is no first indicator, the first instruction is sorted in chronological order in the first link list, so in this embodiment, for the AC channel, the feedback indicator is matched with the second instruction sorted at the top of the first link list, and the corresponding operation (clear) is performed on the second cumulative value.

[0061] The relationship between the first signal corresponding to the feedback signal and the first signal corresponding to the second command is determined in a selectable manner.

[0062] Selectively, the above relationships may include matches and mismatches, and different relationships correspond to different processes. For example, if the relationship between the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second instruction matches, it indicates that the second instruction has received the feedback indicator, and the cumulative timeout duration for this instance can be terminated.

[0063] Based on the above relationship, either clear the second cumulative value or continue accumulating it.

[0064] In this embodiment, since the second cumulative value is the sum of only the timeout duration of the second instruction, it is possible to determine whether or not the second cumulative value is cleared simply by comparing the first indicator that has been fed back with the first indicator corresponding to the second instruction, thereby simplifying the indicator comparison process and improving the indicator identification efficiency.

[0065] In this embodiment, by assigning a corresponding sign to an instruction, the matching efficiency between the first instruction and the feedback sign is improved. Furthermore, because the sign is present, it is possible to identify a corresponding first instruction from among multiple first instructions. As a result, it is not necessary to store each first instruction individually, and all first instructions can be stored in just one first link list, improving memory efficiency, saving memory space, and reducing resource usage.

[0066] In some selectable embodiments, the step of clearing or continuing to accumulate for the second cumulative value is: If the above relationship indicates that the first indicator corresponding to the feedback indicator matches the first indicator corresponding to the second instruction, the steps include clearing the second cumulative value, updating the next first instruction in the sort (array) of the first linked list to the second instruction, and restarting the count for the new second instruction.

[0067] For the second cumulative value, the steps to either clear or continue accumulating are: If the above relationship indicates a mismatch between the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second instruction, the further step includes designating the first instruction that is sorted first among the first instructions corresponding to the first indicator in the first linked list as the third instruction, and deleting the third instruction from the first linked list.

[0068] In this embodiment, if the above relationship indicates a mismatch, this feedback indicator indicates that it does not correspond to the second instruction. In this case, the second cumulative value is not cleared, the second counter continues to time out, and because one feedback indicator has been received, the third instruction corresponding to this feedback indicator is removed from the first link list. When confirming the third instruction, based on maintaining the order of the same indicators, if the first indicator corresponding to the feedback indicator corresponds to multiple first instructions in the first link list, the first instruction sorted to the front of the multiple first instructions is designated as the third instruction. This ensures that the first instruction sorted to the front in the first link list is the first instruction received earlier, and the third instruction that received the feedback indicator is correctly removed from the first link list. As a result, all first instructions stored in the first link list are first instructions that have not received a feedback indicator, thereby improving the accuracy of the second cumulative value.

[0069] In some of the selectable embodiments, step 108 is: If the second cumulative value is equal to or greater than a preset threshold, it is determined that the bus access state is in a hung state, and this may include sending access hang-up information and at least one type of related information.

[0070] In this embodiment, by sending access hang-up information and at least one type of related information, the hang-up information is made easier to obtain. Based on the related information, the channel where the hang-up occurred and the address corresponding to the first instruction that caused the hang-up are determined, and processing is performed to address the hang-up problem based on the interrupt reporting status.

[0071] The method for detecting the bus access state in any integrated circuit according to the embodiments of this disclosure may be performed by any suitable device having data processing capabilities, which includes, but is not limited to, terminal devices and servers. Furthermore, the method for detecting the bus access state in any integrated circuit according to the embodiments of this disclosure may be performed by a processor, for example, by calling a corresponding command stored in memory to perform the method for detecting the bus access state in any integrated circuit referred to in the embodiments of this disclosure. Further redundant explanations are omitted below.

[0072] [Example device] Figure 6 is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to one exemplary embodiment of the present disclosure. The device according to this embodiment is integrated into a single module (or chip), which can be designed within a chip system. As shown in Figure 6, the device according to this embodiment is An instruction detection module 61 for detecting a first instruction transmitted on a first channel in the bus of an integrated circuit, A first counter 62 for accumulating the number of first instructions detected by the instruction detection module 61 and obtaining a first cumulative value, Based on the first cumulative value obtained by the first counter 62, a second counter 63 is used to obtain a second cumulative value by performing a count representing the timeout duration for the first instruction accumulated by the first counter 62, The system includes a state determination module 64 for determining the bus access state based on the relationship between a second cumulative value obtained by a second counter 63 and a preset threshold.

[0073] The bus access state detection device in the integrated circuit according to the above embodiment of this disclosure can determine the number of incomplete first instructions transmitted on the first channel of the bus by accumulating the number of first instructions transmitted on the first channel of the bus using a first counter. If the first cumulative value is not zero, it indicates that there are incomplete first instructions on the first channel. In this case, a second counter performs a count representing the timeout duration for this incomplete first instruction, and the second cumulative value obtained from the count represents the duration for which the first instruction is transmitted on the first channel. By comparing the relationship between the second cumulative value and a preset threshold, it is possible to determine whether the duration for which the bus is occupied by the first instruction exceeds the preset threshold, thereby determining the bus access state. Consequently, detection of the situation in which the first channel of the bus is occupied is realized, bus occupancy timeout problems can be detected in a timely manner, reducing the occurrence of serious problems such as freezes in the chip system and significantly improving the transmission performance of the chip system.

[0074] Selectively, the state determination module 64 determines that the bus access state is hang-up when the second cumulative value is greater than or equal to a preset threshold, and sends out access hang-up information.

[0075] When the device according to this embodiment is integrated on an independent chip within a chip system, this state determination module can be an external communication module, and this state determination module transmits access hang-up information to the interrupt collection module.

[0076] Selectively, the first counter 62 performs a decrement operation on a first cumulative value, specifically based on a feedback indicator corresponding to the received first instruction.

[0077] Figure 7 is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to another exemplary embodiment of the present disclosure. In this embodiment, the second counter 63 is A first instruction confirmation unit 631 for determining that there is a first instruction for which no feedback indicator was received, based on a first cumulative value, The system includes an cumulative value clearing unit 632 for clearing a second cumulative value based on a feedback indicator of a received first command.

[0078] Figure 8 is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to another exemplary embodiment of the present disclosure. As shown in Figure 8, the first counter 62 in this embodiment is A first link list 621 for storing at least one type of related information corresponding to at least one first instruction in the order in which the first instruction was received, The system includes an instruction accumulation unit 622 for accumulating the number of first instructions corresponding to related information stored in a first link list and obtaining a first cumulative value.

[0079] Selectively, the first link list 621 obtains at least one first sign by assigning a corresponding first sign to a detected first instruction, the associated information includes the first sign, each first sign corresponds to at least one first instruction, and stores at least one first sign.

[0080] Selectively, at least one type of related information includes address information.

[0081] For example, if the first link list 621 corresponds to a read address channel, then, as shown in Table 1, the first column may be the first identifier (ARID) and the second column may be the address information (ARADDR). In Table 1, only the information storage format is schematically shown, and specific ID and address information is not explicitly entered. Furthermore, the number of rows included in the first link list of this embodiment is not limited.

[0082] [Table 1]

[0083] For example, if the first link list 621 corresponds to a write address channel, then, as shown in Table 2, the first column may be the first indicator (AWID) and the second column may be the address information (AWADDR). In Table 2, only the information storage format is schematically shown, and specific ID and address information are not explicitly entered here. Furthermore, the number of rows included in the first link list of this embodiment is not limited.

[0084] [Table 2]

[0085] For example, if the first link list 621 corresponds to a snoop address channel, as shown in Table 3, the first column may be address information (ACADDR) and the second column may be access type information (ACSNOOP). Table 3 schematically shows only the information storage format, and does not specify the ID and address information. Furthermore, the number of rows included in the first link list in this embodiment is not limited.

[0086] [Table 3]

[0087] Figure 9 is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to a further exemplary embodiment of the present disclosure. As shown in Figure 9, the second counter 63 in this embodiment is An indicator identification unit 633 for determining that there is a first instruction for which no feedback indicator was received, based on the first cumulative value, A linked list sorting unit 634 for making the first instruction, which is sorted to the top of the first linked list, into the second instruction, The system includes a timeout count unit 635 for performing a count representing the timeout duration for a second instruction and obtaining a second cumulative value.

[0088] Figure 10 is a schematic diagram of the structure of a bus access state detection device in an integrated circuit according to a further exemplary embodiment of the present disclosure. As shown in Figure 10, the timeout count unit 635 in the second counter 63 in this embodiment is A sign detection unit 6351 for detecting a feedback sign transmitted on the first channel, The system includes an cumulative value processing unit 6352 for performing a corresponding process on a second cumulative value based on a first indicator corresponding to a feedback indicator.

[0089] Selectively, the cumulative value processing unit 6352 determines the relationship between a first indicator corresponding to a feedback indicator and a first indicator corresponding to a second instruction, and based on this relationship, either clears the second cumulative value or continues to accumulate it.

[0090] If the cumulative value processing unit 6352 is selectable, it will either clear the second cumulative value based on this relationship or continue accumulating. If this relationship indicates that the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second instruction match, it will clear the second cumulative value. If this relationship indicates that the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second instruction do not match, it will determine the first instruction sorted to the top of the first instructions corresponding to the first indicator in the first linked list as the third instruction and delete the third instruction from the first linked list.

[0091] Selectively, the state determination module 64 determines that the bus access state is hang-up when the second cumulative value is greater than or equal to a preset threshold, and sends access hang-up information along with at least one type of related information.

[0092] Beneficial technical effects corresponding to exemplary embodiments of this apparatus can be found by referring to the corresponding beneficial technical effects of the exemplary method portion described above, and redundant explanations are omitted here.

[0093] [Example electronic device] Figure 11 is a structural diagram of an electronic device comprising at least one processor 111 and memory 112 according to an embodiment of the present disclosure.

[0094] The processor 111 can be a central processing unit (CPU) or another type of processing unit having data processing capability and / or command execution capability, and can control other components in the electronic device 11 to perform a desired function.

[0095] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard drives, flash memory, etc. The computer-readable storage media may store one or more computer program commands, and the processor 11 can implement a method for detecting the bus access state in the integrated circuit in each embodiment of the present disclosure and / or other desired functions by executing one or more computer program commands.

[0096] As an example, the electronic device 11 may further include an input device 113 and an output device 114 connected to each other via a bus system and / or other type of connection mechanism (not shown).

[0097] This input device 113 may be further equipped with, for example, a keyboard, a mouse, etc.

[0098] This output device 114 can output various types of information to the outside. This output device 114 may include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0099] For simplification, Figure 11 shows only some of the components of the electronic device 11 relevant to this disclosure, omitting components such as buses and input / output interfaces. The electronic device 11 may further comprise any other suitable components depending on the specific application.

[0100] [Examples of computer program products and computer-readable storage media] Embodiments of the present disclosure may further provide computer program products, including computer program commands, in addition to the methods and devices described above. When the computer program commands are executed by a processor, the processor is caused to perform the steps of the method for detecting the bus access state in an integrated circuit in each embodiment of the present disclosure described in the “Exemplary Methods” portion above.

[0101] A computer program product can be created using any combination of one or more programming languages ​​to produce program code for performing the operations of the embodiments of this disclosure, and such programming languages ​​may include object-oriented programming languages ​​such as Java and C++, and may further include general procedural programming languages ​​such as the C language or similar programming languages. The program code may be executed as follows: it may be executed entirely on a user computing device, partially on a user device, as a standalone software package, partially on a user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0102] Furthermore, embodiments of the present disclosure may also be computer-readable storage media on which computer program commands are stored. When the computer program commands are executed by the processor, the processor is instructed to perform the steps of the method for detecting the bus access state in the integrated circuit in each embodiment of the present disclosure as described in the “Exemplary Methods” portion above.

[0103] Any combination of one or more types of readable media can be used as a computer-readable storage medium. A readable medium can be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples (non-exclusive list) of readable storage media include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0104] While the basic principles of this disclosure have been explained above with reference to specific examples, the advantages, merits, and effects mentioned in this disclosure are illustrative and not limiting, and various examples of this disclosure do not necessarily possess these advantages, merits, and effects. Furthermore, the specific details of the above disclosure are for illustrative and easy-to-understand purposes only and are not limiting, and the above details do not necessarily restrict this disclosure to being realized by the above specific details.

[0105] The above description is provided for illustrative and illustrative purposes only. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. While several exemplary embodiments and examples have been described above, those skilled in the art will be able to recognize certain variations, modifications, changes, additions, and subcombinations thereof.

Claims

1. A method for detecting the bus access state in an integrated circuit, wherein each step is performed by a bus access state detection device in the integrated circuit, A step of detecting a first instruction transmitted on a first channel in the bus of an integrated circuit, The steps include: accumulating the number of the first instructions using a first counter and obtaining a first cumulative value; Based on the first cumulative value, a second counter performs a count representing the timeout duration for the first instruction accumulated by the first counter, and obtains a second cumulative value. The process includes the step of determining the access state of the bus based on the relationship between the second cumulative value and a preset threshold, A method for detecting the bus access state in an integrated circuit, characterized by the features described above.

2. The step of determining the access state of the bus based on the relationship between the second cumulative value and the preset threshold is as follows: The process includes the step of determining that the bus access state is hang-up if the second cumulative value is equal to or greater than the preset threshold, and sending access hang-up information. A method for detecting the bus access state in an integrated circuit according to feature 1.

3. The step of accumulating the number of the first instruction using the first counter and obtaining a first cumulative value is: The process includes the step of performing a decrement operation on the first cumulative value based on a feedback indicator corresponding to the received first command, A method for detecting the bus access state in an integrated circuit according to feature 1.

4. Based on the first cumulative value, the second counter performs a count representing the timeout duration for the first instruction accumulated by the first counter, and obtains a second cumulative value. A step of determining, based on the first cumulative value, that there is a first command for which no feedback signal was received, The process includes the step of clearing the second cumulative value based on the feedback indicator of the received first command, A method for detecting the bus access state in an integrated circuit according to feature 1.

5. The step of accumulating the number of the first instruction using the first counter and obtaining a first cumulative value is: The first link list stores at least one type of related information corresponding to at least one of the first instructions in the time order in which the first instructions are received, The process includes the step of using the first counter to accumulate the number of the first instructions corresponding to the related information stored in the first link list, and obtaining the first cumulative value, A method for detecting the bus access state in an integrated circuit according to feature 1.

6. The step of storing at least one type of related information corresponding to at least one of the first instructions in the first link list in the time order in which the first instructions are received is: A step of assigning a first indicator corresponding to the detected first command to obtain at least one of the first indicators, The first link list includes the step of storing at least one of the first labels, The aforementioned related information includes the first sign, Each of the first indicators corresponds to at least one of the first instructions. A method for detecting the bus access state in an integrated circuit according to feature 5.

7. Based on the first cumulative value, the second counter performs a count indicating the timeout duration for the first instruction accumulated by the first counter, and obtains a second cumulative value. A step of determining, based on the first cumulative value, that there is a first command for which no feedback signal was received, The steps include: using the second counter to sort the first instruction at the top of the first linked list into the second instruction; The process includes the step of performing a count representing the timeout duration for the second instruction and obtaining the second cumulative value, A method for detecting the bus access state in an integrated circuit according to feature 6.

8. The step of performing a count representing the timeout duration for the second instruction and obtaining the second cumulative value is: The steps include detecting the feedback sign transmitted on the first channel, The process includes the step of performing a corresponding process on the second cumulative value based on a first indicator corresponding to the feedback indicator, A method for detecting the bus access state in an integrated circuit according to feature 7.

9. The step of performing a corresponding process on the second cumulative value based on a first indicator corresponding to the feedback indicator is: A step of determining the relationship between a first sign corresponding to the feedback sign and a first sign corresponding to the second command, Based on the aforementioned relationship, the step includes either clearing the second cumulative value or continuing to accumulate it, A method for detecting the bus access state in an integrated circuit according to feature 8.

10. Based on the relationship described above, the step of clearing or continuing to accumulate the second cumulative value is: If the relationship indicates that the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second command are in agreement, then the step of clearing the second cumulative value is performed. If the relationship indicates that the first indicator corresponding to the feedback indicator and the first indicator corresponding to the second instruction are inconsistent, the first instruction sorted to the front of the first instructions corresponding to the first indicator in the first link list is determined to be the third instruction, and the third instruction is removed from the first link list. A method for detecting the bus access state in an integrated circuit according to feature 9.

11. The aforementioned at least one type of related information includes address information. A method for detecting the bus access state in an integrated circuit according to claim 5.

12. The step of determining the access state of the bus based on the relationship between the second cumulative value and the preset threshold is as follows: If the second cumulative value is equal to or greater than the preset threshold, the access state of the bus is determined to be in a hang-up state, and the process includes sending access hang-up information and sending at least one type of related information. A method for detecting the bus access state in an integrated circuit according to feature 5.

13. An instruction detection module for detecting a first instruction transmitted on a first channel in an integrated circuit bus, A first counter that accumulates the number of first instructions detected by the instruction detection module and obtains a first cumulative value, A second counter is used to obtain a second cumulative value by performing a count representing the timeout duration for the first instruction accumulated by the first counter, based on the first cumulative value obtained by the first counter, The system includes a state determination module for determining the access state of the bus based on the relationship between a second cumulative value obtained by the second counter and a preset threshold, A device for detecting the bus access state in an integrated circuit, characterized by the above.

14. A computer-readable storage medium on which computer programs are stored, The computer program executes the method for detecting the bus access state in an integrated circuit according to any one of claims 1 to 12. A computer-readable storage medium characterized by the following features.

15. An electronic device comprising a processor and a memory for storing commands that the processor can execute, The processor performs the bus access state detection method in the integrated circuit according to any one of claims 1 to 12 by reading and executing the executable command from the memory. An electronic device characterized by the following features.

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