Semiconductor memory

Abstract

To provide a semiconductor memory device that can reduce power consumption. [Solution] The semiconductor memory device comprises a semiconductor substrate 200 and a memory cell array layer L arranged in one of the first directions intersecting the semiconductor substrate. MCA The memory cell array comprises a first memory region R aligned in a second direction intersecting the first direction. MH1 and the second memory region R MH2 The conductive layers 110 include a first conductive layer closest to the semiconductor substrate, a second conductive layer furthest from the semiconductor substrate, and a third conductive layer provided between the first and second conductive layers. The first conductive layer is divided in a second direction to form a first divided layer SGD0 located in a first region and a second divided layer SGD1 located in a second region. The second conductive layer is divided in a second direction to form a third divided layer SGS0 located in a first region and a fourth divided layer SGS1 located in a second region. The third conductive layer is continuous across the first and second regions.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (SiN) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent Application Publication No. 2024-046343 [Patent Document 2] U.S. Patent Application Publication No. 2023 / 0395500 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that can reduce power consumption. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a semiconductor substrate and a memory cell array disposed on one side of the semiconductor substrate in a first direction intersecting the semiconductor substrate. The memory cell array includes a plurality of conductive layers extending in a second direction intersecting the first direction and aligned in the first direction, a plurality of semiconductor layers extending in the first direction and aligned in a direction intersecting the first direction and facing the plurality of conductive layers, gate insulating films provided between the plurality of semiconductor layers and the plurality of conductive layers, and a plurality of wirings extending in a third direction intersecting the first and second directions and aligned in the second direction, electrically connected to one end of the semiconductor layer in the first direction. The memory cell array has a first region and a second region aligned in the second direction, and the plurality of conductive layers include a first conductive layer closest to the semiconductor substrate, a second conductive layer furthest from the semiconductor substrate, and a third conductive layer provided between the first and second conductive layers. The first conductive layer is divided in the second direction to constitute a first divided layer located in the first region and a second divided layer located in the second region. The second conductive layer is divided in the second direction to form a third divided layer located in the first region and a fourth divided layer located in the second region. The third conductive layer is continuous across the first and second regions. The plurality of wirings comprises a first wiring located in the first region and a second wiring located in the second region. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic block diagram showing the configuration of the memory die MD. [Figure 2] This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 3] This is a schematic circuit diagram showing the configuration of the low decoder RD. [Figure 4] This is a schematic circuit diagram showing the configuration of the sense amplifier module SAM. [Figure 5] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 6]This is a schematic perspective view showing an example configuration of chip CM and chip CP. [Figure 7] This is a schematic bottom view showing a portion of the chip CM's structure as seen from the direction of arrow A in Figure 6. [Figure 8] This is a schematic cross-sectional view taken along the BB' line in Figure 7, as seen in the direction of the arrow. [Figure 9] This is a schematic cross-sectional view taken along the CC' line in Figure 7, as seen from the direction of the arrow. [Figure 10] This is a schematic cross-sectional view showing an enlarged view of section D in Figure 9. [Figure 11] This diagram shows a schematic representation of the voltages applied to each part of the memory die MD during a read operation according to the first embodiment. [Figure 12] This diagram shows a schematic representation of the voltages applied to each part during other read operations of the memory die MD according to the first embodiment. [Figure 13] This diagram shows a schematic representation of the voltages applied to each part during other read operations of the memory die MD according to the first embodiment. [Figure 14] This diagram shows a schematic representation of the voltages applied to each part during other read operations of the memory die MD according to the first embodiment. [Figure 15] This diagram shows a schematic representation of the voltages applied to each part of the memory die MD during the writing operation according to the first embodiment. [Figure 16] This figure shows a schematic of the voltages applied to each part during the erase operation of the memory die MD according to the first embodiment. [Figure 17] This is a cross-sectional view showing the schematic configuration of a semiconductor memory device according to the second embodiment. [Figure 18] This is a block diagram showing the schematic configuration of the low decoder RD used in the second embodiment. [Figure 19] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the third embodiment. [Figure 20] This is a schematic perspective view showing an example configuration of chips CM1, CM2, and CP. [Figure 21]This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 22] This is a schematic circuit diagram showing the configuration of the low decoder RD. [Figure 23] This is a schematic block diagram showing the configuration of the sense amplifier module SAM. [Figure 24] This is a schematic bottom view showing a portion of the configuration of chips CM1 and CM2 as seen from the direction of arrow E in Figure 20. [Figure 25] This is a schematic cross-sectional view taken along the FF' line in Figure 24, as seen in the direction of the arrow. [Figure 26] This is a schematic cross-sectional view taken along the GG' line in Figure 24, viewed from the direction of the arrow. [Figure 27] This figure shows a schematic representation of the voltages applied to each part of the memory plane MP1 and MP2 during the read operation of the memory die MD according to the third embodiment. [Figure 28] This diagram shows a schematic representation of the voltages applied to various parts of the memory plane MP1 and MP2 during other read operations. [Figure 29] This diagram shows a schematic representation of the voltages applied to various parts of the memory plane MP1 and MP2 during other read operations. [Figure 30] This diagram shows a schematic representation of the voltages applied to various parts of the memory plane MP1 and MP2 during other read operations. [Figure 31] This figure shows a schematic of the voltages applied to each part during the writing operation of the memory die MD according to the third embodiment. [Figure 32] This figure shows a schematic of the voltages applied to each part during the erase operation of the memory die MD according to the third embodiment. [Figure 33] This figure illustrates a semiconductor memory device according to the fourth embodiment, and is a schematic plan view taken from the direction of arrow E in Figure 20. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0015] Furthermore, in this specification, the term "wiring" may include wiring, via contact electrodes, connectors for connecting wiring and via contact electrodes, bonded electrodes, etc.

[0016] [First Embodiment] [Circuit configuration of the memory die MD] Figure 1 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 2 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 3 is a schematic circuit diagram showing the configuration of the raw decoder RD. Figure 4 is a schematic block diagram showing the configuration of the sense amplifier module SAM.

[0017] Figure 1 illustrates multiple control terminals. These control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals). They may also be represented as control terminals corresponding to low-active signals (negative logic signals). Furthermore, they may be represented as control terminals corresponding to both high-active and low-active signals. In Figure 1, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 1 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals.

[0018] As shown in Figure 1, the memory die MD comprises a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC comprises a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also comprises a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuit PC comprises an input / output control circuit I / O and a logic circuit CTR.

[0019] [Circuit configuration of memory cell array MCA] The memory cell array MCA comprises multiple memory blocks BLK, as shown in Figure 2. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. Note that the number of memory blocks BLK, string units SU, and memory strings MS is not limited to the number shown in the figure. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0020] The memory cell array MCA has a first memory region R in the direction in which multiple bit lines BL are aligned. MH1 and the second memory region R MH2 It is divided into two parts. Below, the first memory region R MH1 The memory block BLK, string unit SU, and bit line BL contained within are sometimes referred to as the first partitioned block DBLK1, the first partitioned string unit DSU1, and the first bit line BL1, respectively. Also, the second memory region R MH2 The memory block BLK, string unit SU, and bit line BL contained within are sometimes referred to as the second partitioned block DBLK2, the second partitioned string unit DSU2, and the second bit line BL2, respectively. Here, a reading unit of multiple bit lines BL is referred to as 1 page. This 1 page can be arbitrarily defined. Furthermore, the reading unit of the first bit line BL1 and the second bit line BL2 are referred to as 1 / 2 page, respectively.

[0021] A memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory transistors), and a source-side selection transistor STS. The drain-side selection transistor STD, the multiple memory cells MC, and the source-side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0022] A memory cell MC is a field-effect transistor. A memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0023] A selection transistor (STD, STS) is a field-effect transistor. A selection transistor (STD, STS) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer.

[0024] The gate electrodes of the selection transistors (STD, STS) included in the first divided string unit DSU1 are connected to selection gate lines (SGD0, SGS0), respectively. These selection gate lines (SGD0, SGS0) are sometimes referred to as first selection gate lines. One drain-side first selection gate line SGD0 is commonly connected to the drain-side selection transistor STD of all memory strings MS in one first divided string unit DSU1. One source-side first selection gate line SGS0 is commonly connected to the source-side selection transistor STS of all memory strings MS in one first divided block DBLK1.

[0025] The gate electrodes of the selection transistors (STD, STS) in the second split string unit DSU2 are connected to selection gate lines (SGD1, SGS1), respectively. These selection gate lines (SGD1, SGS1) are sometimes referred to as second selection gate lines. One drain-side second selection gate line SGD1 is commonly connected to the drain-side selection transistor STD of all memory strings MS in one second split string unit DSU2. One source-side second selection gate line SGS1 is commonly connected to the source-side selection transistor STS of all memory strings MS in one second split block DBLK2.

[0026] In addition, drain-side select gate lines SGD0 and SGD1 are sometimes collectively referred to as drain-side select gate line SGD, source-side select gate lines SGS0 and SGS1 are sometimes collectively referred to as source-side select gate line SGS, and drain-side select gate line SGD and source-side select gate line SGS are sometimes collectively referred to as select gate line SG.

[0027] [Circuit Configuration of Voltage Generation Circuit VG] As shown in FIG. 3, the voltage generation circuit VG generates a voltage of a predetermined magnitude in a read operation, a write operation, and an erase operation, and outputs the generated voltage to the voltage selection circuit VSEL. For example, the voltage generation circuit VG includes a read voltage V CGR used in the read operation, and a read path voltage V READ , and a selection gate line voltage V SGD ,V SGS and the like. Further, the voltage generation circuit VG includes a program voltage V PGM used in the write operation, a write path voltage V PASS , and a verify read voltage V CGR and the like. Further, the voltage generation circuit VG includes an erase voltage V ERA and the like used in the erase operation. The voltage generation circuit VG includes, for example, a boosting circuit such as a charge pump circuit, or a bucking circuit such as a regulator. The operation voltage output from the voltage generation circuit VG is appropriately adjusted according to a control signal from the sequencer SQC.

[0028] Further, the voltage generation circuit VG can generate a plurality of operation voltages applied to the bit line BL, the source line SL, and the selection gate lines (SGD, SGS) during a read operation, a write operation, and an erase operation on the memory cell array MCA, and output them to a plurality of voltage supply lines. These operation voltages are appropriately adjusted according to a control signal from the sequencer SQC.

[0029] [Circuit Configuration of Row Decoder RD] The row decoder RD includes, for example, as shown in FIG. 3, a block decoder BLKD, a voltage selection circuit VSEL, and a block selection circuit BLKSW.

[0030] The block decoder BLKD decodes the block address, which is the higher-order address of the low address RA, during read and write operations. During read and write operations, for example, one signal line BLKSEL corresponding to the block address in the address register ADR (Figure 1) becomes "H" and the other signal lines BLKSEL become "L". For example, a predetermined drive voltage with a positive magnitude is supplied to one signal line BLKSEL, and a ground voltage V is supplied to the other signal lines BLKSEL. SS These are supplied. These signal lines BLKSEL turn on one of the block selection circuits BLKSW and turn off the other block selection circuits BLKSW. As a result, all word lines WL and selection gate lines SG in the memory block BLK corresponding to this block address become conductive with all wiring CGI. In addition, all word lines WL and selection gate lines SG in the other memory block BLK become floating.

[0031] The voltage selection circuit VSEL decodes the lower address of the low address RA and the split block selection signal CS1 from the sequencer SQC, selects the required voltage from the various voltages output from the voltage generation circuit VG, and outputs it to the wiring CGI. The wiring CGI receives voltages to supply to the drain-side selection gate lines SGD00, SGD01, SGD10, and SGD11 of the selected memory block BLK, and to the word line WL and source-side selection gate lines SGS0 and SGS1 of the selected string unit SU in the selected memory block BLK. The voltage applied to the word line WL is determined by the lower address of the low address RA. The voltages applied to the drain-side selection gates SGD00, SGD01, SGD10, and SGD11, and the source-side selection gates SGS0 and SGS1, respectively, are determined by the split block selection signal CS1 output from the sequencer SQC.

[0032] A block selection circuit BLKSW is provided for each memory block BLK. The block selection circuit BLKSW comprises, for example, multiple field-effect NMOS transistors. These NMOS transistors connect the drain-side selection gate lines SGD00, SGD01, SGD10, SGD11, word line WL, and source-side selection gate lines SGS0, SGS1 of the memory block BLK selected by the block decoder BLKD, to the wiring CGI.

[0033] [Circuit configuration of the SAM sense amplifier module] The sense amplifier module SAM detects the ON / OFF state of a memory cell MC, for example, as shown in Figure 4, and acquires data indicating the state of this memory cell MC. This type of operation is sometimes called a sense operation. The sense amplifier module SAM comprises multiple sense amplifier units SAU. Each of the multiple sense amplifier units SAU corresponds to multiple bit lines BL. Each of the multiple sense amplifier units comprises a sense amplifier circuit SA and latch circuits SDL, TDL, ADL, BDL, and CDL. Each of the multiple sense amplifier units SAU also comprises a selection circuit SEL. The selection circuit SEL switches the connection configuration of bit lines BL1 and BL2 based on the divided block selection signal SC2 from the sequencer SQC. Specifically, when reading or writing 1 page of data, the selection circuit SEL selects all bit lines BL. When reading or writing 1 / 2 page of data, the selection circuit SEL selects and connects only the first bit line BL1 or the second bit line BL2.

[0034] The sense amplifier module SAM includes a data register DREG. The data register DREG includes, for example, multiple latch circuits XDL provided for each sense amplifier unit SAU. The latch circuits XDL temporarily store read and write data. The latch circuits XDL are used for data input and output between the external controller and the sense amplifier unit SAU. Each latch circuit XDL is connected to the corresponding sense amplifier unit SAU via the bus DBUS. Note that multiple sense amplifier units SAU may be connected to a single latch circuit XDL.

[0035] The sense amplifier circuit SA and latch circuits SDL, ADL, BDL, CDL, and TDL of the sense amplifier unit SAU are commonly connected to the bus LBUS. This connects the latch circuit XDL, sense amplifier circuit SA, and latch circuits SDL, ADL, BDL, CDL, and TDL so that they can send and receive data from each other.

[0036] During a read operation, the sense amplifier circuit SA senses the data read onto the corresponding bit line BL and determines whether the read data is "0" or "1". During a write operation, the sense amplifier circuit SA applies a voltage to the bit line BL based on the data stored in one of the latch circuits SDL, ADL, BDL, CDL, or TDL.

[0037] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store read and write data. For example, during a read operation, data may be transferred from the sense amplifier circuit SA to one of the latch circuits SDL, ADL, BDL, CDL, and TDL. Similarly, during a write operation, data may be transferred from the latch circuit XDL to one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0038] The configuration of the sense amplifier unit SAU is not limited to this and can be modified in various ways. For example, the number of latch circuits in the sense amplifier unit SAU can be designed based on the number of bits of data that one memory cell MC can store.

[0039] [Circuit configuration of cache memory CM] As shown in Figure 1, the cache memory CM comprises multiple latch circuits. These multiple latch circuits are connected to the latch circuits in the sense amplifier module SAM via the bus DBUS. The data DAT contained in these multiple latch circuits is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0040] Furthermore, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to column address CA to the bus BUS (Figure 1) in response to the output signal of the decode circuit.

[0041] [Circuit configuration of the SQC sequencer] As shown in Figure 1, the sequencer SQC stores command data D in the command register CMR. CMD Accordingly, internal control signals are output to the low decoder RD, sense amplifier module SAM, and voltage generation circuit VG. In addition, the sequencer SQC outputs status data D indicating its own status as appropriate. ST Output this to the status register STR.

[0042] The SQC sequencer also generates a ready / busy signal and outputs it to the RY / / BY terminal. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted.

[0043] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O comprises data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. The multiple input circuits, multiple output circuits, shift register, and buffer circuit are each connected to the power supply voltage V CCQ and ground voltage V SS It is connected to the terminal to which the power is supplied.

[0044] Data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or command register CMR, according to an internal control signal from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit, according to an internal control signal from the logic circuit CTR.

[0045] Multiple input circuits include, for example, comparators connected to any of the data signal input / output terminals DQ0 to DQ7, or to both of the toggle signal input / output terminals DQS and DQS. Multiple output circuits include, for example, OCD (Off Chip Driver) circuits connected to any of the data signal input / output terminals DQ0 to DQ7, or to either of the toggle signal input / output terminals DQS and DQS.

[0046] [Circuit configuration of the logic circuit CTR] The logic circuit CTR (Figure 1) receives external control signals from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0047] [Memory die MD structure] Figure 5 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 5, the memory die MD is located on the chip C on the memory cell array MCA side. M And, the peripheral circuit PC side chip C P It is equipped with the following.

[0048] Chip C M On the upper surface are multiple external pad electrodes P (not shown) that can be connected to bonding wires. X A chip C is provided. M On the lower surface, there are multiple bonded electrodes P I1 A chip C is provided. P On the upper surface, there are multiple bonded electrodes P I2 A chip C is provided below. M Regarding this, multiple bonded electrodes P I1 The surface on which the multiple external pad electrodes P are provided is called the surface, and X The side on which this is provided is called the back side. Also, chip C P Regarding this, multiple bonded electrodes P I2 The surface on which the surface is provided is called the front surface, and the surface opposite the front surface is called the back surface.

[0049] Chip C M and chip C P This is chip C M Surface and chip C P Multiple bonded electrodes P are arranged so as to face each other on the surface. I1 This is a plurality of bonded electrodes P I2 Multiple adhesive electrodes P are provided, corresponding to each of them. I2 It is positioned in a location where it can be bonded. Bonding electrode P I1 and bonded electrode P I2 This refers to chip C M and chip C P It functions as a bonding electrode for bonding two materials together and for electrical conductivity.

[0050] Furthermore, in the example in Figure 5, chip C M The corners a1, a2, a3, and a4 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0051] Figure 6 shows chip C M and chip C P This is a schematic perspective view. Figure 6 shows the bonded electrode P I1 Some components, such as those shown, have been omitted. Figure 7 shows chip C as viewed from the direction of arrow A in Figure 6. MThis is a schematic bottom view showing a part of the structure. Figure 8 is a schematic cross-sectional view taken along line BB' of Figure 7 and viewed in the direction of the arrow. Figure 9 is a schematic cross-sectional view taken along line CC' of Figure 7 and viewed in the direction of the arrow. Figure 10 is a schematic cross-sectional view showing an enlarged view of section D in Figure 9.

[0052] [Chip C M [Structure] In the example in Figure 6, chip C M It comprises two memory planes MP1 and MP2 aligned in the Y direction. Note that the two memory planes MP1 and MP2 are sometimes simply referred to as memory plane MP. Furthermore, these two memory planes MP1 and MP2 each comprise multiple memory blocks BLK aligned in the Y direction. In the example in Figure 6, these two memory planes MP1 and MP2 each have a first memory region R provided on both sides in the X direction. MH1 and the second memory region R MH2 And these first memory regions R MH1 and the second memory region R MH2 Hookup region R provided between HU It is equipped with the following. Note that in the example in Figure 6, peripheral circuits provided around the memory cell array MCA are omitted.

[0053] In the illustrated example, the hookup region R HU This is located in the center of the memory plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be changed as appropriate. For example, the hookup region R HU These may be located at both ends of the memory plane MP in the X direction, rather than in the center of the X direction.

[0054] [Chip C M [Structure] Next, chip C M The structure of [the chip] will be explained below. For the sake of explanation, chip C will be used below. P With the side facing upwards, tip C M The side will be described as the lower side. Tip C M For example, as shown in Figure 8, the substrate layer L SB and the base layer LSB Memory cell array layer L located above MCA and memory cell array layer L MCA It comprises a via contact electrode layer CH provided above, a plurality of wiring layers M0, M1 provided above the via contact electrode layer CH, and a chip bonding electrode layer MB provided above the wiring layers M0, M1.

[0055] [Chip C M The base layer L SB [Structure] For example, as shown in Figure 8, the substrate layer L SB The memory cell array layer L MCA A conductive layer 100 is provided on the lower surface of the conductive layer 100, an insulating layer 101 is provided on the lower surface of the conductive layer 100, a back surface wiring layer MA is provided on the insulating layer 101, and an external pad electrode P is connected to the lower surface of the back surface wiring layer MA. X It is equipped with the following.

[0056] The conductive layer 100 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0057] The conductive layer 100 functions as part of the source line SL (Figure 1). Two conductive layers 100 are provided, corresponding to the two memory planes MP1 and MP2 (Figure 6). The insulating layer 101 contains, for example, silicon oxide (SiO2).

[0058] The back wiring layer MA includes multiple wirings ma. These multiple wirings ma may include, for example, aluminum (Al). Some of these multiple wirings ma function as part of the source wire SL (Figure 2).

[0059] [Chip C M Memory cell array layer L MCA Memory region R MH [Structure in] As explained with reference to Figure 6, the memory cell array layer LMCA Multiple memory blocks BLK are provided, arranged in the Y direction. As shown in Figures 7 and 9, an interblock insulating layer ST made of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks BLK in the Y direction. The interblock insulating layer ST may also include a conductive layer containing an insulating film such as silicon oxide (SiO2), a barrier conductive film such as titanium nitride (TiN), and a metal film such as tungsten (W).

[0060] The memory block BLK comprises, for example, a plurality of conductive layers 110 aligned in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction, as shown in Figure 9. Furthermore, as shown in Figure 10, an enlarged view of section D in Figure 9, a gate insulating film 130 is provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

[0061] The conductive layer 110 has a substantially plate-like shape that extends in the X direction. The conductive layer 110 may also contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). Furthermore, the conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between a plurality of conductive layers 110 arranged in the Z direction.

[0062] Of the multiple conductive layers 110, one or more conductive layers 110 (SGS) located at the bottom layer function as the gate electrode and source-side selection gate line SGS of the source-side selection transistor STS (Figure 2). These one or more conductive layers 110 (SGS) are electrically independent for each memory block BLK.

[0063] Furthermore, multiple conductive layers 110(WL) located above this function as gate electrodes and word lines WL of the memory cell MC (Figure 2). Each of these conductive layers 110(WL) is electrically independent for each memory block BLK.

[0064] Furthermore, one or more conductive layers 110(SGD) located above this function as the gate electrode and drain-side selection gate line SGD of the drain-side selection transistor STD. For example, as shown in Figure 9, the width in the Y direction of these multiple conductive layers 110(SGD) is smaller in the Y direction than the width in the Y direction of the conductive layer 110(WL) that functions as a word line WL. In addition, an inter-string unit insulating layer SHE made of silicon oxide (SiO2) or the like is provided between two adjacent conductive layers 110(SGD) in the Y direction.

[0065] The semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 7, for example. Each semiconductor layer 120 functions as a channel region for multiple memory cells MC and selection transistors (STD, STS) contained in one memory string MS (Figure 2). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and as shown in Figure 10, an insulating layer 125 made of silicon oxide or the like is provided in the central portion. The outer surface of the semiconductor layer 120 is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110.

[0066] Furthermore, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100. This impurity region contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0067] Furthermore, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. As shown in Figure 8, this impurity region is connected to the bit line BL via via contact electrodes ch and Vy. This impurity region contains, for example, N-type impurities such as phosphorus (P).

[0068] The gate insulating film 130 has a substantially cylindrical shape, as shown in Figure 10, for example, covering the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon nitride (SiON), etc. The charge storage film 132 includes, for example, a charge-storing film such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0069] Figure 10 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0070] [Chip C M Memory cell array layer L MCA Hookup region R HU [Structure in] As shown in Figure 8, the hookup region R HU Then, the uppermost conductive layer 110 (SGD), which functions as the drain-side selected gate line SGD, is divided in the X direction. That is, the conductive layer 110 (SGD) is divided into the first memory region R MH1 A conductive layer 110 (SGD0) (first division layer) that functions as the drain-side first selected gate line SGD0 of the first division block DBLK1 located at and the second memory area R MH2 It comprises a conductive layer 110 (SGD1) (second division layer) that functions as the drain-side second selected gate line SGD1 of the second division block DBLK2 located at [location].

[0071] Also, the hookup region R HU Then, the bottom conductive layer 110 (SGS), which functions as the source-side selected gate line SGS, is divided in the X direction. That is, the conductive layer 110 (SGS) is divided into the first memory region RMH1 A conductive layer 110(SGS0) (the third divided layer) that functions as a source-side first selection gate line SGS0 of the first divided block DBLK1 located at MH2 and a conductive layer 110(SGS1) (the fourth divided layer) that functions as a source-side second selection gate line SGS1 of the second divided block DBLK2 located at

[0072] Hook-up region R HU has a plurality of via contact electrodes CC WL , CC SGD0 , CC SGD1 , CC SGS0 , CC SGS1 are provided. These plurality of via contact electrodes CC WL , CC SGD0 , CC SGD1 , CC SGS0 , CC SGS1 each extend in the Z direction and are connected to the conductive layers 110(WL), 110(SGD0), 110(SGD1), 110(SGS0), 110(SGS1) at the lower end. Hereinafter, the plurality of via contact electrodes CC WL , CC SGD0 , CC SGD1 , CC SGS0 , CC SGS1 may be collectively referred to as via contact electrodes CC. The via contact electrodes CC are electrically connected to the bonding electrode P of the chip CP through the wirings m0, m1 and the bonding electrode P at the upper end. 11 through the wiring m0, m1 and the bonding electrode P 12 of the chip CP at the upper end.

[0073] The via contact electrode CC includes a columnar conductive layer 111 extending in the Z direction and an insulating layer 102 covering the outer periphery of the conductive layer 111. The insulating layer 102 insulates the conductive layer 111 from the conductive layers 110 other than the conductive layer to be connected. The conductive layer 111 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The insulating layer 102 may include silicon oxide (SiO2) or the like.

[0074] [Structure of via contact electrode layer CH] The plurality of via contact electrodes ch included in the via contact electrode layer CH are electrically connected to at least one of, for example, the configuration in the memory cell array layer L and the configuration in the chip C. MCA and the configuration in the chip C P at least one of which is electrically connected.

[0075] The via contact electrode layer CH includes a plurality of via contact electrodes ch as a plurality of wirings. These plurality of via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to the plurality of semiconductor layers 120 and are connected to the lower ends of the plurality of semiconductor layers 120.

[0076] [Structure of the wiring layers M0 and M1 of the chip C M The plurality of wirings included in the wiring layers M0 and M1 are electrically connected to at least one of, for example, the configuration in the memory cell array layer L and the configuration in the chip C. MCA and the configuration in the chip C P at least one of which is electrically connected.

[0077] The wiring layer M0 includes a plurality of wirings m0. These plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), etc. and a metal film such as copper (Cu). Note that a part of the plurality of wirings m0 functions as bit lines BL. The bit lines BL are arranged in the X direction and extend in the Y direction, for example, as shown in FIG. 7.

[0078] The wiring layer M1 includes a plurality of wirings m1, for example, as shown in FIG. 8. These plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0079] <000,0907>[Structure of the chip C P Chip C P ​As shown in Figure 6, for example, it includes regions MP1' and MP2' that overlap with two memory planes MP1 and MP2 aligned in the Y direction. In the center of these two regions MP1' and MP2' in the X direction is a low control circuit region R RC Each of these is provided. Furthermore, the low control circuit region R RC On both sides in the X direction are two block decoder regions R aligned in the X direction. BD These block decoder regions R are provided. BD Outside of these are the column control circuit regions R. CC A column control circuit region R is provided. CC Outside of this is the peripheral circuit region R. PC A circuit region R is provided. In addition, other regions also have a circuit region R. C A system is in place.

[0080] Low control circuit region R RC This includes multiple block selection circuits BLKSW, as explained with reference to Figure 3. That is, the low control circuit region R RC Multiple NMOS transistors are provided to constitute multiple block selection circuits (BLKSW). Block decoder region R BD A block decoder BLKD, as explained with reference to Figure 3, is provided in the column control circuit region R. CC A sense amplifier module SAM, as explained with reference to Figure 4, is provided in the circuit region R. C An input / output circuit (not shown) is provided. This input / output circuit connects to an external pad electrode P via a via contact electrode CC, etc., as explained with reference to Figure 8. X Connected.

[0081] Also, chip C PAs shown in Figure 8, for example, the device comprises a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 provided above the electrode layer GC, and a chip-bonded electrode layer DB provided above the wiring layers D0, D1, D2, D3, D4. The semiconductor substrate 200 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). On the surface of the semiconductor substrate 200, for example, multiple transistors constituting a peripheral circuit PC, and multiple resistors, capacitors, etc. are formed. The chip-bonded electrode layer DB contains a bonded electrode P 12 A system is in place.

[0082] [Operation] Next, the operation of the memory die MD according to the first embodiment will be described. [Read operation] Figure 11 shows the main parts of Figure 8 and is a schematic diagram of the voltages applied to each part during the read operation of the memory die MD according to the first embodiment. For the sake of simplicity, the details of the voltage application timing are omitted.

[0083] First, the data DA of 1 / 2 page stored in the memory cell MC connected to the word line WL1 of the first partition block DBLK1 MH1 This section explains how to read the data from the first bit line, BL1.

[0084] When the sequencer SGC (Figure 1) receives a command to read data from the memory cell MC connected to the word line WL1 of the first partitioned block DBLK1, it sets the partitioned block selection signals SC1 and SC2 to the signal level that selects the first partitioned block DBLK1. A voltage V is applied to the conductive layer 100, which functions as the source line. SRC A voltage V is applied. SRC The ground voltage V SS It is larger than the ground voltage V SS It is approximately equal to . Also, the first bit line BL1 and the second bit line BL2 are connected via the sense amplifier module SAM, and voltage V DD It will be charged.

[0085] Voltage V is applied to the drain-side first selected gate line SGD0 of the selected first partition block DBLK1. SGD When a voltage is applied, the first selected gate line SGS0 on the source side is given a voltage V SGS A voltage V is applied. SGD V SS This is the gate voltage greater than or equal to the voltage V that turns on the drain-side selection transistor STD. SGS V SS This is the gate voltage greater than that which turns on the source-side selection transistor STS. Voltage V SGD and voltage V SGS They can be the same or different.

[0086] Additionally, the selection word line WL is connected to the memory cell MC from which the data is read. SEL This includes a voltage V between two or more threshold levels. CGR The voltage is applied in stages. Meanwhile, the unselected word line WL is connected to the memory cell MC from which data is not read. NSEL The voltage V READ A voltage V is applied. READ is the voltage V CGR This voltage is greater than the specified voltage and always turns on the memory cell MC, regardless of the value of the data stored in the memory cell MC.

[0087] When the above voltages are applied to the word line WL and the selection gate lines SGD0 and SGS0, the selection transistors STD and STS connected to the selected string unit SU turn ON. NSEL All connected memory cells MC will be turned on. Also, the selected word line WL SEL Among the connected memory cells MC, the threshold level is voltage V CGR Since the selected memory cell MC is larger than this value, the voltage on the first bit line BL1 is V DD Maintain the selected word line WL. SEL Among the connected memory cells MC, the threshold level is voltage V CGR Since the selected memory cell MC is smaller than this value, the voltage of the first bit line BL1 is V DDThe current is discharged to the conductive layer 100 side via the drain-side selection transistor STD, memory cell MC, and source-side selection transistor STS, resulting in a voltage V SS The voltage drops to this level. By detecting the voltage state of these first bit lines BL1 with the sense amplifier module SAM, the latch circuit XDL receives 1 / 2 page of read data DA. MN1 It can be read.

[0088] On the other hand, on the unselected second division block DBLK2 side, the sense amplifier module SAM is not connected to the second bit line BL2. Also, the drain-side second selected gate line SGD1 and the source-side second selected gate line SGS1 of the unselected second division block DBLK2 have a voltage V SS (or V SS Larger than V SS A voltage close to V is applied. SS This is the gate voltage that does not turn on the drain-side selection transistor STD and the source-side selection transistor STS. As a result, the second partitioned block DBLK2 becomes floating. Therefore, the second memory region R MH2 No charging occurs to the conductive layer 110 located at that position.

[0089] Figure 12 is a diagram illustrating another read operation. Here, 1 / 2 page of data DA stored in memory cell MC connected to word line WL1 of the second partition block DBLK2 is read. MH2 This section explains how to read the data from the second bit line, BL2. Note that explanations that overlap with those in Figure 11 will be omitted.

[0090] When the sequencer SGC (Figure 2) receives a command to read data from the memory cell MC connected to the word line WL2 of the second partition block DBLK2, it sets the partition block selection signals SC1 and SC2 to the signal level that selects the second partition block DBLK2. A voltage V is applied to the conductive layer 100, which functions as the source line. SRC A voltage is applied. In addition, the first bit line BL1 and the second bit line BL2 are connected via the sense amplifier module SAM to a voltage VDD It will be charged.

[0091] A voltage V is applied to the drain-side second selected gate line SGD1 of the selected second partition block DBLK2. SGD A voltage V is applied to the source-side second selected gate line SGS1. SGS It is applied.

[0092] Additionally, the selection word line WL is connected to the memory cell MC from which the data is read. SEL This includes a voltage V between two or more threshold levels. CGR The voltage is applied in stages. Meanwhile, the unselected word line WL is connected to the memory cell MC from which data is not read. NSEL The voltage V READ It is applied.

[0093] When the above voltages are applied to the word line WL and the selection gate lines SGD1 and SGS1, the operation of the second partition block DBLK2 is the same as the operation of the first partition block DBLK1 in Figure 11. As a result, the latch circuit XDL receives 1 / 2 page of read data DA. MN2 It can be read.

[0094] On the other hand, on the unselected first partition block DBLK1 side, the sense amplifier module SAM is not connected to the first bit line BL1. Also, the drain-side first selected gate line SGD0 and the source-side first selected gate line SGS0 of the unselected first partition block DBLK1 have a voltage V SS (or V SS Larger than V SS A voltage close to [value] is applied. As a result, the first partitioned block DBLK1 becomes floating. Therefore, the first memory area R MH1 No charging occurs to the conductive layer 110 located at that position.

[0095] FIG. 13 is a diagram for explaining yet another read operation. Here, a diagram is shown for the case of reading 1 page of data DA stored in memory cells MC connected to word line WL1 of first split block DBLK1 and second split block DBLK2 from first bit line BL1 and second bit line BL2. Note that descriptions of parts overlapping with the descriptions in FIGS. 11 and 12 are omitted.

[0096] When sequencer SGC (FIG. 2) inputs a command to read normal 1 page of data, it sets split block selection signals SC1 and SC2 to signal levels for selecting first split block DBLK1 and second split block DBLK2. A voltage V is applied to conductive layer 100 functioning as a source line. SRC Also, voltages V are charged to first bit line BL1 and second bit line BL2 via sense amplifier module SAM. DD

[0097] A voltage V is applied to drain side first selection gate line SGD0 of first split block DBLK1 and drain side second selection gate line SGD1 of second split block DBLK2, and a voltage V is applied to source side first selection gate line SGS0 and source side second selection gate line SGS1. SGD SGS

[0098] Also, a voltage V between binary or more threshold levels is applied stepwise to selection word line WL connected to memory cell MC for reading data. On the other hand, a voltage V is applied to non - selection word line WL connected to memory cell MC for not reading data. SEL CGR NSEL READ

[0099] Thereby, 1 / 2 page of data DA, DA can be read from first split block DBLK1 and second split block DBLK2 respectively. MN1 ,DA MN2

[0100] Figure 14 illustrates another read operation. Here, we show an example of simultaneously reading 1 / 2 page of data DA from two different string units SU0 and SU1 of the same memory block BLK0, for a total of 1 page. Figure 14 corresponds to Figure 7.

[0101] The voltages stored in the word line WL and the source-side selection gate lines SGS0 and SGS1 are the same as the voltages described in Figure 13. In this example, string unit SU0 is selected in the first division block DBLK1, and string unit SU1 is selected in the second division block DBLK2.

[0102] The first selected gate line SGD00 on the drain side, connected to the string unit SU0 of the first divided block DBLK1, has a voltage V SGD When a voltage is applied, the first selected gate line SGD01 on the drain side, which is connected to the string unit SU1, receives the voltage V. SS It is applied.

[0103] On the other hand, the second selected gate line SGD10 on the drain side, which is connected to the string unit SU0 of the second divided block BLK2, has a voltage V SS When a voltage is applied, the drain-side second selected gate line SGD11 connected to the string unit SU1 receives the voltage V SGD It is applied.

[0104] As a result, in the first divided block DBLK1, string unit SU0 is used, and in the second divided block DBLK2, data DA for 1 / 2 page is used from string unit SU1. MH2 The following is read out.

[0105] [Writing operation] Figure 15 shows the main parts of Figure 8 and is a schematic diagram of the voltages applied to each part during the writing operation of the memory die MD according to the first embodiment. For the sake of simplicity, the details of the voltage application timing are omitted.

[0106] Here, 1 / 2 page of data DA is sent to the memory cell MC connected to the word line WL1 of the first partitioned block DBLK1. MH1 This section explains how to write data via the first bit line BL1.

[0107] When the sequencer SGC (Figure 1) receives a command to write data to the memory cell MC connected to the word line WL1 of the first partitioned block DBLK1, it sets the partitioned block selection signals SC1 and SC2 to the signal level that selects the first partitioned block DBLK1. A voltage V is applied to the conductive layer 100, which functions as the source line. SRC A voltage V is applied. Additionally, the sense amplifier module SAM connects to the first bit line BL1, and a voltage V corresponding to the written data is applied to the first bit line BL1 via the sense amplifier module SAM. DD or V SRC A voltage V is applied. That is, a voltage V is applied to the first bit line BL1 connected to the memory cell MC that increases the threshold. SRC A voltage V is applied to the first bit line BL1 connected to the memory cell MC, which does not change the threshold voltage. DD Apply the solution.

[0108] Voltage V is applied to the drain-side first selected gate line SGD0 of the selected first partition block DBLK1. SGDW When a voltage is applied, the first selected gate line SGS0 on the source side is given a voltage V SS A voltage V is applied. SGDW is the voltage V SRC ,V DD Larger than. Voltage V SGDW is the voltage V SRC The drain-side selection transistor STD, connected to the first bit line BL1 to which the voltage V is applied, is turned ON. DD This is the voltage that does not turn on the drain-side selection transistor STD, which is connected to the first bit line BL1 to which the voltage is applied.

[0109] Additionally, the selection word line WL is connected to the memory cell MC where data is written. SEL The program voltage V PGMA voltage is applied, and the unselected word line WL is connected to the memory cell MC that does not write data. NSEL The write path voltage V PASS The following is applied: Program voltage V PGM The write path voltage V PASS Larger than. Write path voltage V PASS This is the voltage that turns on the memory cell MC.

[0110] When the above voltages are applied to the word line WL and the selection gate lines SGD0 and SGS0, the source-side selection transistor STS turns off, and the memory cell MC is disconnected from the conductive layer 100.

[0111] Also, the voltage applied to the first bit line BL1 is voltage V. SRC In this case, the drain-side selection transistor STD connected to the first bit line BL1 turns ON, and a voltage V is applied to the channel formed in the memory string MS. SRC The data is transferred. Meanwhile, the voltage applied to the first bit line BL1 is voltage V. DD In this case, the drain-side selection transistor STD connected to the first bit line BL1 is turned off, and the channel formed in the memory string MS becomes floating.

[0112] In this state, the selected word line WL SEL Program voltage V PGM When applied, voltage V is applied to the channel. SRC In the memory cell MC to which the data has been transferred, electrons move from the channel to the charge storage film 132 (Figure 10) via the tunnel insulating film 131 (Figure 10), and the threshold voltage of the memory cell MC rises. The write-verify operation is the same as the read operation shown in Figure 11, so it will not be explained here. On the other hand, when voltage V is applied to the channel... SRD In memory cells (MC) where data transfer did not occur, the channel is boosted and no electron movement takes place. In this way, 1 / 2 page of data (DA) is stored in the latch circuit (XDL). MN1 This can be written to the memory cell MC of the first partitioned block DBLK1.

[0113] On the other hand, on the unselected second division block DBLK2 side, the drain-side second selected gate line SGD1 and the source-side second selected gate line SGS1 have a voltage V SS (or V SS Larger than V SS A voltage close to [value] is applied. As a result, the second partitioned block DBLK2 enters a floating state, and no writing operation is performed.

[0114] [Erase operation] Figure 16 shows the main parts of Figure 8 and is a schematic diagram of the voltages applied to each part during the erase operation of the memory die MD according to the first embodiment. For the sake of simplicity, the details of the voltage application timing are omitted.

[0115] This section describes the case where the first partitioned block DBLK1 is the memory section ERMH to be erased.

[0116] When the sequencer SGC (Figure 1) receives an erase command for the first division block DBLK1, it sets the division block selection signals SC1 and SC2 to the signal level that selects the first division block DBLK1. The conductive layer 100, which functions as a source line, receives the erase voltage V ERA The following is applied: Erasing voltage V ERA The write path voltage V PASS Larger than. Eradication voltage V ERA The program voltage V PGM It can be about the same size, or the program voltage V PGM It can be larger or smaller. The sense amplifier module SAM connects the first bit line BL1 and the second bit line BL2, and applies an erase voltage V to these first bit line BL1 and second bit line BL2. ERA Apply the solution.

[0117] Voltage V is applied to the drain-side first selected gate line SGD0 of the selected first partition block DBLK1. SGD Apply the voltage V to the first selected gate line SGS0 on the source side. SGSThe erase voltage V is applied. This causes GIDL (Gate Induced Drain Leakage) to occur in the channel region of the drain-side selection transistor STD corresponding to the drain-side first selection gate line SGD0, generating electron-hole pairs. The electrons move to the bit line BL1 side, and the holes move to the memory cell MC side. Additionally, the erase voltage V is applied from the source-side conductive layer 100. ERA It will be forwarded.

[0118] Also, the word line WL has a voltage V SS A charge is applied. This causes holes diffused in the channels of the memory string MS to move through the tunnel insulating film 131 (Figure 10) to the charge storage film 132 (Figure 10), lowering the threshold of the memory cell MC.

[0119] On the other hand, on the unselected second division block DBLK2 side, the drain-side second selected gate line SGD1 and the source-side selected gate line SGS1 are connected with an erase voltage V ERA This is applied. As a result, the second partitioned block DBLK2 enters a floating state and no erase operation is performed.

[0120] [effect] Thus, according to the first embodiment, the drain-side selected gate lines SGD0, SGD1 and the source-side selected gate lines SGS0, SGS1 are divided in the X direction, and different voltages can be applied to each independently. Therefore, by dividing the memory cell array MCA into two and making the non-selected region floating, the amount of charge on the word line can be reduced, and the read performance, write performance, and erase performance can be improved.

[0121] Furthermore, since the read, write, and erase units can be precisely configured, unnecessary power consumption can be reduced when users want to operate in fine read units.

[0122] [Second Embodiment] Figure 17 is a cross-sectional view showing the schematic configuration of a semiconductor memory device according to the second embodiment. Figure 17 shows the memory cell array layer L in Figure 8.MCA It supports this. In the second embodiment, the memory cell array layer L MCA It is divided into four parts in the X direction. More specifically, the memory cell array layer L MCA This is the first memory region R, which is aligned in the X direction. MH1 , second memory area R MH2 , third memory area R MN3 , and the fourth memory area R MH4 It has a memory cell array layer L MCA The first hookup region R is located at both ends in the X direction. HU1 , and the third hookup region R HU3 It has a memory cell array layer L. MCA This is the second memory region R MH2 , and the third memory area R MH3 During this time, the second hookup region R HU2 It holds.

[0123] First hookup area R HU1 , Second hookup area R HU2 , and the third hookup region R HU3 In this case, some of the multiple conductive layers 110 have terrace portions T formed in a stepped shape.

[0124] First memory region R MH1 and the second memory region R MH2 Between these, the second hookup region R HU2 , and the third memory area R MH3 and the fourth memory region R MH4 Between these two points, the uppermost conductive layer 110 (SGD), which functions as a drain-side selected gate line SGD, is divided in the X direction. That is, the conductive layer 110 (SGD) is divided in the first memory region R MH1 A conductive layer 110 (SGD0) that functions as the drain-side first selected gate line SGD0 of the first divided block DBLK1 located at and the second memory area R MH2 A conductive layer 110 (SGD1) that functions as the drain-side second selected gate line SGD1 of the second divided block DBLK2 located in the third memory area R MH3A conductive layer 110 (SGD2) that functions as the drain-side third selected gate line SGD2 of the third divided block DBLK3 located in the fourth memory area R MH4 It comprises a conductive layer 110 (SGD3) which functions as the drain-side fourth selected gate line SGD3 of the fourth divided block DBLK4 located at [location].

[0125] Also, the first memory region R MH1 and the second memory region R MH2 Between these, the second hookup region R HU2 , and the third memory area R MH3 and the fourth memory region R MH4 Between these two points, the bottom conductive layer 110 (SGS), which functions as a source-side selected gate line SGS, is divided in the X direction. That is, the conductive layer 110 (SGS) is divided in the first memory region R MH1 A conductive layer 110 (SGS0) that functions as the first selected gate line SGS0 on the source side of the first divided block DBLK1 located at and the second memory area R MH2 A conductive layer 110 (SGS1) that functions as the source-side second selected gate line SGS1 of the second divided block DBLK2 located in the third memory region R MH3 A conductive layer 110 (SGS2) that functions as the source-side third selected gate line SGS2 of the third divided block DBLK3 located in the fourth memory region R MH4 It comprises a conductive layer 110 (SGS3) which functions as the source-side fourth selected gate line SGS3 of the fourth partitioned block DBLK4 located therein.

[0126] Hookup area R HU1 It has multiple via contact electrodes CC SGD0 CC SGS0 A hookup region R is provided. HU2 It has multiple via contact electrodes CC WL CC SGD1 CC SGD2 CC SGS1 CC SGS2 A hookup region R is provided. HU3 It has multiple via contact electrodes CC SGD3 CC SGS3Multiple via contact electrodes CC are provided. WL CC SGD0 CC SGD1 CC SGD2 CC SGD3 CC SGS0 CC SGS1 CC SGS2 CC SGS3 Each extends in the Z direction and is connected at its lower end to the terrace portions T of the conductive layers 110(WL), 110(SGD0), 110(SGD1), 110(SGD2), 110(SGD3), 110(SGS0), 110(SGS1), 110(SGS2), and 110(SGS3).

[0127] Figure 18 is a block diagram showing the schematic configuration of the low decoder RD used in this embodiment, and corresponds to Figure 3. In the row decoder RD shown in Figure 3, each memory block BLK is connected to the word line WL, as well as the drain-side first selection gate line SGD0, the drain-side second selection gate line SGD2, the source-side first selection gate line SGS0, and the source-side second selection gate line SGS1. In this embodiment, each memory block BLK is further connected to the drain-side third selection gate line SGD2, the drain-side fourth selection gate line SGD3, the source-side third selection gate line SGS2, and the source-side fourth selection gate line SGS3. The wiring CGI is increased by the number of additional selection gate lines SGD and SGS.

[0128] According to the second embodiment, the amount of charge on the word line can be further reduced compared to the first embodiment, and the read performance, write performance, and erase performance can be improved. In addition, since the read unit, write unit, and erase unit can be set more precisely, power consumption can be further reduced.

[0129] [Third Embodiment] Figure 19 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the third embodiment. As shown in Figure 19, the memory die MD is a chip C including a first memory cell array MCA1. M1And chip C, which includes the second memory cell array MCA2. M2 And, the peripheral circuit PC side chip C P The memory die MD shown in Figure 19 has two layers of chips CM1 and CM2, but it also has three or more layers of chips C Mn It's fine if it has that feature.

[0130] Chip C M1 On the upper surface, there are multiple bonded electrodes P I3 A chip C is provided. M1 On the lower surface, there are multiple bonded electrodes P I1 A chip C is provided. M2 On the upper surface are multiple external pad electrodes P (not shown) that can be connected to bonding wires. X A chip C is provided. M2 On the lower surface, there are multiple bonded electrodes P I4 A chip C is provided. P On the upper surface, there are multiple bonded electrodes P I2 A chip C is provided below. M1 ,C M2 Regarding this, multiple bonded electrodes P I1 ,P I4 The surface on which the multiple adhesive electrodes P are provided is called the surface, and I3 and multiple external pad electrodes P X The side on which this is provided is called the back side. Also, chip C P Regarding this, multiple bonded electrodes P I2 The surface on which the surface is provided is called the front surface, and the surface opposite the front surface is called the back surface.

[0131] Chip C M1 and chip C P This is chip C M1 Surface and chip C P Multiple bonded electrodes P are arranged so as to face each other on the surface. I1 This is a plurality of bonded electrodes P I2 Multiple adhesive electrodes P are provided, corresponding to each of them. I2 It is positioned in a location where it can be bonded. Bonding electrode P I1 and bonded electrode P I2 This refers to chip C M1 and chip CP It functions as a bonding electrode for bonding two materials together and for electrical conductivity.

[0132] Chip C M1 and chip C M2 This is chip C M1 The back side and chip C M2 Multiple bonded electrodes P are arranged so as to face each other on the surface. I4 This is a plurality of bonded electrodes P I3 Multiple adhesive electrodes P are provided, corresponding to each of them. I3 It is positioned in a location where it can be bonded. Bonding electrode P I4 and bonded electrode P I3 This refers to chip C M1 and chip C M2 It functions as a bonding electrode for bonding two materials together and for electrical conductivity.

[0133] Furthermore, in the example in Figure 19, chip C M1 The corners a11, a21, a31, and a41 are, respectively, chip C P It corresponds to corners b1, b2, b3, and b4. Also, chip C M2 The corners a12, a22, a32, and a42 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0134] Figure 20 shows chip C M1 , Chip C M2 and chip C P This is a schematic perspective view. Figure 20 shows the bonded electrode P. I1 Some of the components have been omitted.

[0135] [Chip C M1 ,C M2 [Structure] In the example shown in Figure 20, chip C M1 It has two memory planes MP1 and MP2 aligned in the Y direction. Also, chip C M2It comprises two memory planes MP3 and MP4 aligned in the Y direction. Memory planes MP1 and MP3 are stacked in the Z direction and under the same control. Similarly, memory planes MP2 and MP4 are stacked in the Z direction and under the same control. Note that the four memory planes MP1, MP2, MP3, and MP4 are sometimes simply referred to as memory plane MP. Furthermore, these four memory planes MP1, MP2, MP3, and MP4 each comprise multiple memory blocks BLK aligned in the Y direction. In the example in Figure 20, these four memory planes MP1, MP2, MP3, and MP4 each have a first memory region R provided on both sides in the X direction. MH1 and the second memory region R MH2 And these first memory regions R MH1 and the second memory region R MH2 Hookup region R provided between HU It is equipped with the following. Note that in the example in Figure 20, peripheral circuits provided around the memory cell arrays MCA1 and MCA2 are omitted.

[0136] Note that in the illustrated example, the hookup region R HU This is located in the center of the memory plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be adjusted as needed. For example, the hookup region R HU These may be located at both ends of the memory plane MP in the X direction, rather than in the center of the X direction.

[0137] Figure 21 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 22 is a schematic circuit diagram showing the configuration of the row decoder RD. Figure 23 is a schematic block diagram showing the configuration of the sense amplifier module SAM. In Figures 21, 22, and 23, only the memory plane MP1 included in the memory cell array MCA1 and MP3 included in the memory cell array MCA2 are shown as examples, but the memory planes MP2 and MP4 can be configured in the same way. Also, in the following explanation, the explanation of configurations identical to those in Figures 2, 3, and 4 will be omitted.

[0138] As shown in Figure 21, the memory cell arrays MCA1 and MCA2, which are stacked in the Z direction, are configured in the same way as the memory cell array MCA shown in Figure 2.

[0139] Memory planes MP1 and MP3 are arranged in the direction of multiple bit lines BL, and the first memory region R MH1 and the second memory region R MH2 It is divided into two parts. As a result, memory planes MP1 and MP3 each comprise a first partitioned block DBLK1 and a second partitioned block DBLK2, a first partitioned string unit DSU1 and a second partitioned string unit DSU2, and a first bit line BL1 and a second bit line. Memory planes MP1 and MP3 each allow access in 1-page units and read in 1 / 2-page units corresponding to the first partitioned string unit DSU1 and the second partitioned string unit DSU2.

[0140] The difference from the first embodiment is that the word lines WL of the corresponding memory blocks BLK of memory planes MP1 and MP3, which are stacked in the Z direction, are connected in common.

[0141] Furthermore, a difference from the first embodiment is that the drain-side first selected gate line SGD01, the drain-side second selected gate line SGD11, the source-side first selected gate line SGS01, and the source-side second selected gate line SGS11 are connected to the memory plane MP1, and the drain-side first selected gate line SGD03, the drain-side second selected gate line SGD13, the source-side first selected gate line SGS03, and the source-side second selected gate line SGS13 are connected to the memory plane MP3.

[0142] Another difference from the first embodiment is that the bit lines BL from memory plane MP1 and memory plane MP3 are connected to the sense amplifier module SAM.

[0143] As shown in Figure 22, the raw decoder RD supplies predetermined voltages to the drain-side first selected gate line SGD01, the drain-side second selected gate line SGD11, the source-side first selected gate line SGS01, and the source-side second selected gate line SGS11 of the memory plane MP1. In addition, it also supplies predetermined voltages to the drain-side first selected gate line SGD03, the drain-side second selected gate line SGD13, the source-side first selected gate line SGS03, and the source-side second selected gate line SGS13 of the memory plane MP3. The other configurations are the same as in the first embodiment.

[0144] As shown in Figure 23, the sense amplifier module SAM includes a bit line hookup circuit BLHU1 that switches between the first bit line BL1 of memory plane MP1 and the first bit line BL1 of memory plane MP3, and a bit line hookup circuit BLHU2 that switches between the second bit line BL2 of memory plane MP1 and the second bit line BL2 of memory plane MP3, based on the divided block selection signal SC2 output from the sequencer SQC. The bit line hookup circuits BLHU1 and BLHU2 select one of eight possible connection configurations with the bit line BL: four for 1 / 2 page read or write, and four for 1 page read or write.

[0145] Next, the structure of the memory die MD according to this embodiment will be described. Figure 24 shows the chip C as viewed from the direction of arrow E in Figure 20. M1 ,C M2 This is a schematic bottom view showing part of the structure. Figure 25 is a schematic cross-sectional view taken along the FF' line in Figure 24 and viewed in the direction of the arrow. Figure 26 is a schematic cross-sectional view taken along the GG' line in Figure 24 and viewed in the direction of the arrow.

[0146] As shown in Figure 24, memory planes MP1 and MP3 comprise multiple memory blocks BLK aligned in the Y direction. Each memory block BLK comprises multiple (two in this example) string units SU aligned in the Y direction. Hookup region R HUEach memory block BLK is equipped with multiple via contact electrodes CC. Hook-up region R HU It is equipped with two rows of via contact electrodes CC in the Y direction, corresponding to the string unit SU. The first row corresponding to the GG' line is composed of via contact electrodes CC aligned in the X direction. SGD01 CC SGD03 CC SGS03 CC SGS13 CC WL CC SGD13 CC SGD11 It has the following. The second row corresponding to the FF' line is via contact electrode CC SGD01 CC SGD03 CC SGS01 CC SGS11 CC SGD13 CC SGD11 These via contact electrodes CC correspond to all the voltages that should be supplied from the chip CP side to one memory block BLK of the memory plane MP1, MP3.

[0147] As shown in Figure 25, Chip C P and chip C M1 The configuration is substantially the same as that of the first embodiment shown in Figure 8. Chip C M2 This is chip C M1 This is almost the same as the previous example. In this embodiment, chip C M1 Among the multiple conductive layers 110 that constitute the memory plane MP1 included in chip C, the uppermost conductive layer 110 is the conductive layer 110 (SGD01) that constitutes the drain-side first selected gate line SGD01 of the memory plane MP1, and the conductive layer 110 (SGD11) that constitutes the drain-side second selected gate line SGD11. In this embodiment, chip C M1 In this embodiment, chip C is the conductive layer 110 (WL1) that constitutes the word line WL1 of the memory plane MP1, among the multiple conductive layers 110 that make up the memory plane MP1. M1Among the multiple conductive layers 110 that constitute the memory plane MP1 included in the memory plane MP1, the bottom conductive layer 110 is the conductive layer 110 (SGS01) that constitutes the first source-side selected gate line SGS01 of the memory plane MP1, and the conductive layer 110 (SGS11) that constitutes the second source-side selected gate line SGS11.

[0148] Furthermore, in this embodiment, chip C M2 Among the multiple conductive layers 110 that constitute the memory plane MP3 included in chip C, the uppermost conductive layer 110 is the conductive layer 110 (SGD03) that constitutes the drain-side first selected gate line SGD03 of the memory plane MP3, and the conductive layer 110 (SGD13) that constitutes the drain-side second selected gate line SGD13. In this embodiment, chip C M2 In this embodiment, among the multiple conductive layers 110 that constitute the memory plane MP3 included in chip C, the intermediate conductive layer 110 is the conductive layer 110 (WL1) that constitutes the word line WL1 of the memory plane MP1. M2 Among the multiple conductive layers 110 that constitute the memory plane MP3 included in the memory plane MP3, the bottom conductive layer 110 is the conductive layer 110 (SGS03) that constitutes the first source-side selected gate line SGS03 of the memory plane MP3, and the conductive layer 110 (SGS13) that constitutes the second source-side selected gate line SGS13.

[0149] As shown in Figure 25, chip C M1 Via contact electrodes CC connected to conductive layers 110(SGD01), 110(SGD11), 110(SGS01), and 110(SGS11) of the memory plane MP1, respectively. SGD01 CC SGD11 CC SGS01 CC SGS11 These are bonded to electrode P via wiring m01 and m11, respectively. 11 It is connected to the via contact electrode CC connected to the conductive layer 110 (SGD03) of the memory plane MP3. SGD03 These are wiring m03, m13, and bonded electrode P. 14 ,P 13 , Chip C M1 Intermediate via contact electrode CC that penetrates in the Z directionINT , and via wiring m01, m11, chip C M1 Bonded electrode P 11 It is connected to the via contact electrode CC connected to the conductive layer 110 (SGD13) of the memory plane MP3. SGD13 These are wiring m03, m13, and bonded electrode P. 14 ,P 13 , Chip C M1 Intermediate via contact electrode CC that penetrates in the Z direction INT , and via wiring m01, m11, chip C M1 Bonded electrode P 11 It is connected to the memory plane MP1 via contact electrode CC. SGD01 And via contact electrode CC SGS01 Between and, via contact electrode CC WL1 And via contact electrode CC SGD11 A gap is provided between them in the X direction, and an intermediate via contact electrode CC is placed in this gap. INT They are positioned accordingly.

[0150] Therefore, in the second column shown by the FF' line in Figure 24, there are six via contact electrodes CC. SGD01 CC SGD03 CC SGS01 CC SGS11 CC SGD11 CC SGD13 is chip C P to, bonded electrode P 11 ,P 12 It is connected via.

[0151] As shown in Figure 26, chip C M1 Via contact electrodes CC connected to conductive layers 110 (SGD01) and 110 (SGD11) of the memory plane MP1, respectively. SGD01 CC SGD11 These are bonded to electrode P via wiring m01 and m11, respectively. 11 It is connected to the via contact electrode CC connected to the conductive layer 110 (WL1) of the memory plane MP1 shown in Figure 25. WL1 This is via wiring m01 extending in the Y direction to the chip C shown in Figure 26.M1 Intermediate via contact electrode CC that penetrates in the Z direction INT It is connected to the upper end. Also, via contact electrode CC is connected to the conductive layer 110 (WL3) of the memory plane MP3 shown in Figure 25. WL3 , and via contact electrodes CC connected to conductive layers 110 (SGS03) and 110 (SGS13). SGS03 CC SGS13 This is via wiring m03 extending in the Y direction to the chip C shown in Figure 26. M1 Intermediate via contact electrode CC that penetrates in the Z direction INT It is connected to the lower end.

[0152] As shown in Figure 26, the intermediate via contact electrode CC INT The upper end is bonded to electrode P via wiring m01, m11. 11 It is connected to the following. Therefore, in the first column shown by the GG' line in Figure 24, there are 11 via contact electrodes CC. SGD01 CC SGD03 CC SGS03 CC SGS13 , 5 CC WL CC SGD13 CC SGD11 However, Chip C P to, bonded electrode P 11 ,P 12 It is connected via.

[0153] [Operation] Next, the operation of the memory die MD according to the third embodiment will be described. [Read operation] Figure 27 shows the main components of the memory die MD in Figure 25, illustrating the schematic of the voltages applied to each part of the memory plane MP1 and MP2 during a read operation. For the sake of simplicity, details of the voltage application timing are omitted.

[0154] First, the data DA of 1 / 2 page stored in the memory cell MC connected to the word line WL1 of the first partition block DBLK1 of the memory plane MP1 MH1 This section explains how to read the data from the first bit line, BL1.

[0155] When the sequencer SGC (Figure 1) receives a command to read data from the memory cell MC connected to the word line WL1 of the first partitioned block DBLK1, it sets the partitioned block selection signals SC1 and SC2 to the signal level that selects the first partitioned block DBLK1. The conductive layers 100 and 300, which function as source lines, are subjected to a voltage V SRC A voltage V is applied. SRC The ground voltage V SS It is larger than the ground voltage V SS It is approximately equal to this. Also, a voltage V is applied to the first bit line BL1 and the second bit line BL2 of memory plane MP1 and the first bit line BL1 and the second bit line BL2 of memory plane MP2 via the sense amplifier module SAM. DD It will be charged.

[0156] Voltage V is applied to the drain-side first selected gate line SGD01 of the selected first partition block DBLK1. SGD A voltage V is applied to the source-side first selected gate line SGS01. SGS A voltage V is applied. SGD V SS This is the gate voltage greater than or equal to the voltage V that turns on the drain-side selection transistor STD. SGS V SS This is the gate voltage greater than that which turns on the source-side selection transistor STS. Voltage V SGD and voltage V SGS They can be the same or different.

[0157] Additionally, the selection word line WL is connected to the memory cell MC from which the data is read. SEL This includes a voltage V between two or more threshold levels. CGR The voltage is applied in stages. Meanwhile, the unselected word line WL is connected to the memory cell MC from which data is not read. NSEL The voltage V READ A voltage V is applied. READ is the voltage V CGR This voltage is greater than the specified voltage and always turns on the memory cell MC, regardless of the value of the data stored in the memory cell MC.

[0158] When the above voltages are applied to the word line WL and the selection gate lines SGD01 and SGS01, the selection transistors STD and STS connected to the selected string unit SU turn ON. NSEL All connected memory cells MC will be turned on. Also, the selected word line WL SEL Among the connected memory cells MC, the threshold level is voltage V CGR Since the selected memory cell MC is larger than this value, the voltage on the first bit line BL1 is V DD Maintain the selected word line WL. SEL Among the connected memory cells MC, the threshold level is voltage V CGR Since the selected memory cell MC is smaller than this value, the voltage of the first bit line BL1 is V DD The current is discharged to the conductive layer 100 side via the drain-side selection transistor STD, memory cell MC, and source-side selection transistor STS, resulting in a voltage V SS The voltage drops to this level. By detecting the voltage state of these first bit lines BL1 with the sense amplifier module SAM, the latch circuit XDL receives 1 / 2 page of read data DA. MN1 It can be read.

[0159] On the other hand, the second partition block DBLK2 of the unselected memory planes MP1 and MP3, and the drain-side first selected gate line SGD03, drain-side second selected gate lines SGD11 and SGD13, source-side first selected gate line SGS03, and source-side second selected gate lines SGS11 and SGS13 on the first partition block DBLK1 side of memory plane MP3, are subjected to a voltage V SS (or V SS Larger than V SS A voltage close to V is applied. SSThis is the gate voltage that does not turn on the drain-side selection transistor STD and the source-side selection transistor STS. As a result, the second partition block DBLK2 of memory planes MP1 and MP3, and the first partition block DBLK1 of memory plane MP3 become floating. Therefore, the second memory region R MH2 , and the first memory region R of the memory plane MP3 MH1 No charging occurs to the conductive layer 110 located there.

[0160] Figure 28 is a diagram illustrating another read operation. Here, 1 / 2 page of data DA stored in memory cell MC connected to word line WL1 of the second division block DBLK2 of memory plane MP3 is read. MH2 This section explains how to read the data from the second bit line, BL2. Note that explanations that overlap with those in Figure 27 will be omitted.

[0161] When the sequencer SGC (Figure 2) receives a command to read data from the memory cell MC connected to the word line WL1 of the second partition block DBLK2 of the memory plane MP3, it sets the partition block selection signals SC1 and SC2 to the signal level that selects the second partition block DBLK2 of the memory plane MP3. The conductive layers 100 and 300, which function as source lines, are subjected to a voltage V SRC A voltage V is applied. In addition, a voltage V is applied to the first bit line BL1 and the second bit line BL2 of memory plane MP1 and the first bit line BL1 and the second bit line BL2 of memory plane MP3 via the sense amplifier module SAM. DD It will be charged.

[0162] Voltage V is applied to the drain-side second selected gate line SGD13 of the second partition block DBLK2 of the selected memory plane MP3. SGD When the voltage V is applied, the voltage V is applied to the source-side second selected gate line SGS13. SGS It is applied.

[0163] Additionally, the selection word line WL is connected to the memory cell MC from which the data is read. SELThis includes a voltage V between two or more threshold levels. CGR The voltage is applied in stages. Meanwhile, the unselected word line WL is connected to the memory cell MC from which data is not read. NSEL The voltage V READ It is applied.

[0164] When the above voltages are applied to the word line WL and the selection gate lines SGD1 and SGS1, the operation of the second division block DBLK2 of the memory plane MP3 is the same as the operation of the first division block DBLK1 of the memory plane MP1 in Figure 27. As a result, the latch circuit XDL receives 1 / 2 page of read data DA MN2 It can be read.

[0165] On the other hand, the first partitioned block DBLK1 of the unselected memory planes MP1 and MP3, and the drain-side first selected gate lines SGD01, SGD03, drain-side second selected gate line SGD11, source-side first selected gate lines SGS01, SGS03, and source-side second selected gate line SGS11 on the second partitioned block DBLK2 of memory plane MP1, are subjected to a voltage V SS (or V SS Larger than V SS A voltage close to [value] is applied. As a result, the first partitioned block DBLK1 of memory planes MP1 and MP3, and the second partitioned block DBLK2 of memory plane MP1 become floating. Therefore, the first memory region R MH1 , and the second memory region R of memory plane MP1 MH2 No charging occurs to the conductive layer 110 located there.

[0166] Figure 29 illustrates another read operation. This figure describes the case where data DA for one page stored in memory cells MC connected to the word line WL1 of the second partition block DBLK2 of memory plane MP1 and the first partition block DBLK1 of memory plane MP3 is read from the first bit line BL1 and the second bit line BL2. Note that explanations that overlap with the explanations of Figures 27 and 28 are omitted.

[0167] When the sequencer SGC (Figure 2) receives a command to read 1 / 2 page of data (totaling 1 page) from the second division block DBLK2 of memory plane MP1 and the first division block DBLK1 of memory plane MP3, it sets the division block selection signals SC1 and SC2 to the signal levels that select the second division block DBLK2 of memory plane MP1 and the first division block DBLK1 of memory plane MP3. A voltage V is applied to the conductive layers 100 and 300, which function as source lines. SRC A voltage V is applied. In addition, a voltage V is applied to the first bit line BL1 and the second bit line BL2 of memory plane MP1 and the first bit line BL1 and the second bit line BL2 of memory plane MP3 via the sense amplifier module SAM. DD It will be charged.

[0168] A voltage V is applied to the drain-side first selected gate line SGD03 and the drain-side second selected gate line SGD11 of the first partition block DBLK1 and the second partition block DBLK2 of the selected memory plane MP3. SGD A voltage V is applied to the first selected gate line SGS03 on the source side and the second selected gate line SGS11 on the source side. SGS It is applied.

[0169] Additionally, the selection word line WL is connected to the memory cell MC from which the data is read. SEL This includes a voltage V between two or more threshold levels. CGR The voltage is applied in stages. Meanwhile, the unselected word line WL is connected to the memory cell MC from which data is not read. NSEL The voltage V READ It is applied.

[0170] This allows 1 / 2 page of data DA to be extracted from the second partitioned block DBLK2 of the selected memory plane MP1 and the first partitioned block DBLK1 of the memory plane MP3. MN1 DA MN2 It can be read.

[0171] On the other hand, the first selected gate line SGD01 on the drain side, the second selected gate line SGD13 on the drain side, the first gate line SGS01 on the source side, and the second gate line SGS13 on the source side of the first divided block DBLK1 of the unselected memory plane MP1 and the second divided block DBLK2 of the memory plane MP3 are subjected to a voltage V SS (or V SS Larger than V SS A voltage close to [value] is applied. As a result, the first partition block DBLK1 of memory plane MP1 and the second partition block DBLK2 of memory plane MP3 become floating. Therefore, the conductive layer 110 located in these partition blocks DBLK is not charged.

[0172] Figure 30 illustrates another read operation. Here, we show an example of simultaneously reading one page of data DA from different string units SU0 and SU1 on different memory planes MP1 and MP3. Figure 30 corresponds to Figure 24.

[0173] In this example, the first partition block DBLK1 is selected in memory plane MP1, and the second partition block DBLK2 is selected in memory plane MP3. Additionally, string unit SU1 is selected in the first partition block DBLK1 of memory plane MP1, and string unit SU0 is selected in the second partition block DBLK2 of memory plane MP3.

[0174] In the first partitioned block DBLK1 of the memory plane MP1, a voltage V is applied to the drain-side first selected gate line SGD01 connected to the string unit SU0. SS A voltage V is applied to the drain-side first selected gate line SGD01 connected to the string unit SU1. SGD A voltage V is applied. Also, a voltage V is applied to the first selected gate line SGS01 on the source side. SGS It is applied.

[0175] In the first partitioned block DBLK1 of the memory plane MP3, a voltage V is applied to the drain-side first selected gate line SGD03 connected to the string unit SU0. SS A voltage V is applied to the drain-side first selected gate line SGD03 connected to the string unit SU1. SS A voltage V is applied. Also, a voltage V is applied to the first selected gate line SGS03 on the source side. SS It is applied.

[0176] On the other hand, in the second partitioned block DBLK2 of the memory plane MP1, the drain-side second selected gate line SGD11 connected to the string unit SU0 has a voltage V SS When a voltage is applied, the drain-side second selected gate line SGD11 connected to the string unit SU1 receives the voltage V SS A voltage V is applied. Also, a voltage V is applied to the source-side second selected gate line SGS11. SS It is applied.

[0177] Furthermore, in the second divided block BLK2 of the memory plane MP3, a voltage V is applied to the drain-side second selected gate line SGD13 connected to the string unit SU0. SGD A voltage V is applied to the drain-side second selected gate line SGD13 connected to the string unit SU1. SS A voltage V is applied. Also, a voltage V is applied to the source-side second selected gate line SGS13. SGS It is applied.

[0178] As a result, in the first partitioned block DBLK1 of memory plane MP1, 1 / 2 page of data DA is received from string unit SU1, and in the second partitioned block DBLK2 of memory plane MP3, 1 / 2 page of data DA is received from string unit SU0. MH1 / MP1 DA MH2 / MP3 Each of these will be read out.

[0179] [Writing operation] Figure 31 shows the main parts of the memory die MD in Figure 25, and is a schematic diagram of the voltages applied to each part during the writing operation of the memory die MD according to the third embodiment. For the sake of simplicity, the details of the voltage application timing are omitted.

[0180] Here, 1 / 2 page of data DA is sent to memory cell MC connected to word line WL1 of the first partition block DBLK1 of memory plane MP1. MH1 This section explains how to write data via the first bit line BL1.

[0181] When the sequencer SGC (Figure 1) receives a command to write data to the memory cell MC connected to the word line WL1 of the first partitioned block DBLK1 of the memory plane MP1, it sets the partitioned block selection signals SC1 and SC2 to the signal level that selects the first partitioned block DBLK1 of the memory plane MP1. The conductive layers 100 and 300, which function as source lines, are subjected to a voltage V SRC A voltage V is applied. Additionally, a voltage V corresponding to the written data is applied to the first bit line BL1 of the memory plane MP1 via the sense amplifier module SAM. DD or V SRC A voltage V is applied. That is, a voltage V is applied to the first bit line BL1 connected to the memory cell MC that increases the threshold. SRC A voltage V is applied to the first bit line BL1 connected to the memory cell MC, which does not change the threshold voltage. DD Apply the solution.

[0182] A voltage V is applied to the drain-side first selected gate line SGD01 of the first partition block DBLK1 of the selected memory plane MP1. SGDW A voltage V is applied to the source-side first selected gate line SGS01. SS A voltage V is applied. SGDW is the voltage V SRC ,V DD Larger than. Voltage V SGDW is the voltage V SRC The drain-side selection transistor STD, connected to the first bit line BL1 to which the voltage V is applied, is turned ON. DDThis is the voltage that does not turn on the drain-side selection transistor STD, which is connected to the first bit line BL1 to which the voltage is applied.

[0183] Additionally, the selection word line WL is connected to the memory cell MC where data is written. SEL The program voltage V PGM A voltage is applied, and the unselected word line WL is connected to the memory cell MC that does not write data. NSEL The write path voltage V PASS The following is applied: Program voltage V PGM The write path voltage V PASS Larger than. Write path voltage V PASS This is the voltage that turns on the memory cell MC.

[0184] When the above voltages are applied to the word line WL and the selection gate lines SGD01 and SGS0, the source-side selection transistor STS turns off, and the memory cell MC is disconnected from the conductive layer 100.

[0185] Also, the voltage applied to the first bit line BL1 is voltage V. SRC In this case, the drain-side selection transistor STD connected to the first bit line BL1 turns ON, and a voltage V is applied to the channel formed in the memory string MS. SRC The data is transferred. Meanwhile, the voltage applied to the first bit line BL1 is voltage V. DD In this case, the drain-side selection transistor STD connected to the first bit line BL1 is turned off, and the channel formed in the memory string MS becomes floating.

[0186] In this state, the selected word line WL SEL Program voltage V PGM When applied, voltage V is applied to the channel. SRCIn the memory cell MC to which the data has been transferred, electrons move from the channel to the charge storage film 132 (Figure 10) via the tunnel insulating film 131 (Figure 10), and the threshold voltage of the memory cell MC rises. The write-verify operation is the same as the read operation shown in Figure 27, so it will not be explained here. On the other hand, when voltage V is applied to the channel... SRD In memory cells (MC) where data transfer did not occur, the channel is boosted and no electron movement takes place. In this way, 1 / 2 page of data (DA) is stored in the latch circuit (XDL). MN1 This can be written to the memory cell MC of the first partitioned block DBLK1 of the memory plane MP1.

[0187] On the other hand, in the second partition block DBLK2 of the unselected memory planes MP1 and MP3, and in the first partition block DBLK1 of memory plane MP2, the first selected drain gate line SGD03, the second selected drain gate lines SGD11 and SGD13, the first selected source gate line SGS03, and the second selected source gate lines SGS11 and SGS13 are connected by a voltage V SS (or V SS Larger than V SS A voltage close to [value] is applied. As a result, the second partition block DBLK2 of the unselected memory planes MP1 and MP3, and the first partition block DBLK1 of memory plane MP2, become floating, and no write operations are performed.

[0188] [Erase operation] Figure 32 shows the main parts of the memory die MD of Figure 25, and is a schematic diagram of the voltages applied to each part during the erase operation of the memory die MD according to the third embodiment. For the sake of simplicity, the details of the voltage application timing are omitted.

[0189] This section describes the case where the first partitioned block DBLK1 of the memory plane MP1 is the memory section ERMH to be erased.

[0190] When the sequencer SGC (Figure 1) receives an erase command for the first partition block DBLK1 of the memory plane MP1, it sets the partition block selection signals SC1 and SC2 to the signal level that selects the first partition block DBLK1 of the memory plane MP1. The erase voltage V is applied to the conductive layers 100 and 300, which function as source lines. ERA The following is applied: Erasing voltage V ERA The write path voltage V PASS Larger than. Eradication voltage V ERA The program voltage V PGM It can be about the same size, or the program voltage V PGM It can be larger or smaller. Furthermore, the sense amplifier module SAM connects the first bit line BL1 and the second bit line BL2 of the memory planes MP1 and MP2, and applies an erase voltage V to these first bit line BL1 and second bit line BL2. ERA Apply the solution.

[0191] A voltage V is applied to the drain-side first selected gate line SGD01 of the first partition block DBLK1 of the selected memory plane MP1. SGD Apply the voltage V to the source-side first selected gate line SGS01. SGS The erase voltage V is applied. This generates GIDL in the channel region of the drain-side selection transistor STD corresponding to the drain-side first selection gate line SGD01, and generates electron-hole pairs. The electrons move to the bit line BL1 side, and the holes move to the memory cell MC side. The erase voltage V is also applied from the source-side conductive layer 100. ERA It will be forwarded.

[0192] Also, the word line WL has a voltage V SS A charge is applied. This causes holes diffused in the channels of the memory string MS to move through the tunnel insulating film 131 (Figure 10) to the charge storage film 132 (Figure 10), lowering the threshold of the memory cell MC.

[0193] On the other hand, in the second partition block DBLK2 of the unselected memory planes MP1 and MP2, and in the first partition block DBLK1 of the memory plane MP3, the drain-side first selected gate line SGD03, the drain-side second selected gate lines SGD11 and SGD13, the source-side first selected gate line SGS03, and the source-side second selected gate lines SGS03 and SGS13 are subject to an erase voltage V ERA This is applied. As a result, the second partition block DBLK2 of memory planes MP1 and MP2, and the first partition block DBLK1 of memory plane MP3 become floating, and no erase operation is performed.

[0194] [effect] Thus, according to the third embodiment, the drain-side selected gate lines SGD0, SGD1 and the source-side selected gate lines SGS0, SGS1 of multiple memory planes MP are divided in the X direction, and different voltages can be applied to each independently. Therefore, by dividing the memory cell array MCA into four or more sections, and making only a portion of them the target for reading, writing, etc., while leaving the other unselected areas in a floating state, the amount of charge on the word lines can be further reduced, and the read performance, write performance, and erase performance can be improved.

[0195] Furthermore, the read, write, and erase units can be set even more precisely, which reduces unnecessary power consumption when users want to operate with finer read units.

[0196] [Fourth Embodiment] Figure 33 is a diagram illustrating a semiconductor memory device according to the fourth embodiment. Figure 33 is a schematic plan view taken from the direction of arrow E in Figure 20.

[0197] As shown in Figure 33, the memory cell array MCA comprises memory plane MP1 and memory plane MP2. Memory planes MP1 and MP2 are controlled by separate row decoders RD, as also shown in Figure 19. In this case, the selective partition block DBLKSEL of the first partition block DBLK1 of memory plane MP1 and the selective partition block DBLKSEL of the first partition block DBLK1 of memory plane MP2 can be selected from different memory blocks BLK. This allows data from different memory blocks BLK to be read and written simultaneously, improving read and write efficiency.

[0198] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0199] 110...conductive layer, 120...semiconductor layer, 200, 500...semiconductor substrate, C M ,C M1 ,C M2 ...Chip, C P ...chip, BL...bit line, WL...word line, SG...selection gate line, CC...via contact electrode, CGI...wiring, MC...memory cell, R MH1 ,R MH2 ...memory area, R HU ...Hookup area.

Claims

1. Semiconductor substrate and The semiconductor substrate comprises a memory cell array disposed on one side of the semiconductor substrate in a first direction intersecting the semiconductor substrate, The memory cell array is A plurality of conductive layers extending in a second direction intersecting the first direction and aligned in the first direction, A plurality of semiconductor layers extending in the first direction and arranged in a direction intersecting the first direction, facing the plurality of conductive layers, A gate insulating film is provided between each of the plurality of semiconductor layers and the plurality of conductive layers, The semiconductor layer comprises a plurality of wirings extending in a third direction intersecting the first and second directions, aligned in the second direction, and electrically connected to one end of the semiconductor layer in the first direction, The memory cell array is Having a first region and a second region aligned in the second direction, The plurality of conductive layers are The first conductive layer closest to the semiconductor substrate, The second conductive layer furthest from the semiconductor substrate, A third conductive layer is provided between the first conductive layer and the second conductive layer, The first conductive layer is divided in the second direction to form a first divided layer located in the first region and a second divided layer located in the second region. The second conductive layer is divided in the second direction to form a third divided layer located in the first region and a fourth divided layer located in the second region. The third conductive layer is continuous across the first and second regions. The plurality of wirings comprises a first wiring located in the first region and a second wiring located in the second region. Semiconductor memory device.

2. The memory cell array is It has the first region and the second region and a third region aligned in the second direction, The third region further comprises a plurality of contact electrodes extending in the first direction, one end of which is electrically connected to the first divided layer, the second divided layer, the third divided layer, the fourth divided layer, and the third conductive layer, and the other end of which is electrically connected to the semiconductor substrate. The semiconductor memory device according to claim 1.

3. The memory cell array has, in the third region, the first conductive layer, the second conductive layer, and the third conductive layer having terraces formed in a stepped manner. The plurality of contact electrodes are connected to the terrace portion. The semiconductor memory device according to claim 2.

4. The aforementioned plurality of contact electrodes are A columnar conductive layer extending in the first direction, An insulating layer covering the side surface of the conductive column, Equipped with The semiconductor memory device according to claim 2.

5. The plurality of conductive layers and the plurality of semiconductor layers are divided in the third direction to form a plurality of blocks arranged in the third direction. The semiconductor memory device according to claim 2.

6. The first conductive layer is divided into multiple blocks in the third direction, thereby forming multiple string units arranged in the third direction. The semiconductor memory device according to claim 5.

7. A portion of the plurality of contact electrodes is electrically connected to the second conductive layer and the third conductive layer, respectively, for each block. The semiconductor memory device according to claim 5.

8. Other portions of the plurality of contact electrodes are electrically connected to the first conductive layer, one for each string unit. The semiconductor memory device according to claim 6.

9. The aforementioned semiconductor substrate is A first circuit capable of applying different voltages to the first and second divided layers, and to applying different voltages to the third and fourth divided layers, A second circuit that allows the first wiring and the second wiring to be read separately, Equipped with The semiconductor memory device according to claim 1.

10. The aforementioned semiconductor substrate is A different voltage can be applied to each of the multiple conductive layers, The first conductive layer can be subjected to different voltages for each string unit. Different voltages can be applied to the first divided layer and the second divided layer, A first circuit capable of applying different voltages to the third divided layer and the fourth divided layer, A second circuit that allows the first wiring and the second wiring to be read separately, Equipped with The semiconductor memory device according to claim 6.

11. Semiconductor substrate and A first memory chip is disposed on one side of the semiconductor substrate in a first direction intersecting the semiconductor substrate, A second memory chip is located on the semiconductor substrate on the side of the first memory chip, at a position further from the semiconductor substrate than the first memory chip, It has, The first memory chip is A plurality of first conductive layers extending in a second direction intersecting the first direction and aligned in the first direction, A plurality of first semiconductor layers extending in the first direction and arranged in a direction intersecting the first direction, facing the plurality of first conductive layers, A first gate insulating film is provided between each of the plurality of first semiconductor layers and the plurality of first conductive layers, The first semiconductor layer comprises a plurality of first wirings extending in a third direction intersecting the first and second directions, aligned in the second direction, and electrically connected to one end of the first semiconductor layer in the first direction, The second memory chip is A plurality of second conductive layers extending in the second direction and aligned in the first direction, A plurality of second semiconductor layers extending in the first direction and arranged in a direction intersecting the first direction, facing the plurality of second conductive layers, A second gate insulating film is provided between each of the plurality of second semiconductor layers and the plurality of second conductive layers, The device comprises a plurality of second wirings extending in the third direction, aligned in the second direction, and electrically connected to one end of the second semiconductor layer in the first direction, The first memory chip and the second memory chip are Having a first region and a second region aligned in the second direction, The plurality of first conductive layers are, The third conductive layer closest to the semiconductor substrate, The fourth conductive layer furthest from the semiconductor substrate, It has a fifth conductive layer provided between the third conductive layer and the fourth conductive layer, The plurality of second conductive layers are, The sixth conductive layer closest to the semiconductor substrate, The seventh conductive layer, which is furthest from the semiconductor substrate, It has an eighth conductive layer provided between the sixth conductive layer and the seventh conductive layer, The third conductive layer is divided in the second direction and comprises a first divided layer located in the first region and a second divided layer located in the second region. The fourth conductive layer is divided in the second direction and comprises a third divided layer located in the first region and a fourth divided layer located in the second region. The fifth conductive layer is continuous across the first and second regions, The sixth conductive layer is divided in the second direction and comprises a fifth divided layer located in the first region and a sixth divided layer located in the second region. The seventh conductive layer is divided in the second direction and comprises a seventh divided layer located in the first region and a sixth divided layer located in the second region. The fifth conductive layer and the eighth conductive layer are continuous across the first and second regions, respectively. The plurality of first wirings include a third wiring located in the first region and a fourth wiring located in the second region. The plurality of second wirings include a fifth wiring located in the first region and a sixth wiring located in the second region. Semiconductor memory device.

12. The first memory chip and the second memory chip are It has the first region and the second region and a third region aligned in the second direction, The first memory chip is The third region further comprises a plurality of first contact electrodes extending in the first direction, one end of which is electrically connected to the first divided layer, the second divided layer, the third divided layer, the fourth divided layer, and the fifth conductive layer, and the other end of which is electrically connected to the semiconductor substrate. The second memory chip is The third region further comprises a plurality of second contact electrodes extending in the first direction, one end of which is electrically connected to the fifth, sixth, seventh, eighth, and eighth conductive layers, respectively, and the other end of which is electrically connected to the semiconductor substrate via the first memory chip. The semiconductor memory device according to claim 11.

13. The first memory chip further comprises a plurality of third contact electrodes extending in the first direction in the third region, Among the plurality of first contact electrodes, the first contact electrodes electrically connected to the third divided layer, the fourth divided layer, and the fifth conductive layer, respectively, and among the plurality of second contact electrodes, the second contact electrodes electrically connected to the seventh divided layer, the eighth divided layer, and the eighth conductive layer, respectively, are electrically connected to each other via the third contact electrode. The semiconductor memory device according to claim 12.

14. Of the plurality of second contact electrodes, the second contact wiring electrically connected to the fifth and sixth divided layers is electrically connected to the semiconductor substrate via the third contact electrode, without being connected to the first and second divided layers. The first contact electrode connected to the first and second divided layers is not connected to the second and third contact electrodes, but is not electrically connected to the semiconductor substrate. The semiconductor memory device according to claim 13.

15. The plurality of first conductive layers and the plurality of first semiconductor layers, as well as the plurality of second conductive layers and the plurality of second semiconductor layers, are each divided in the third direction to form a plurality of blocks arranged in the third direction. The semiconductor memory device according to claim 12.

16. The third conductive layer and the sixth conductive layer divide each of the plurality of blocks further in the third direction to form a plurality of string units arranged in the third direction. The semiconductor memory device according to claim 15.

17. Some of the plurality of first contact electrodes are electrically connected to the fourth conductive layer and the fifth conductive layer, respectively, for each block. A portion of the plurality of second contact electrodes is electrically connected to the seventh conductive layer and the eighth conductive layer, respectively, for each block. The semiconductor memory device according to claim 15.

18. Other portions of the plurality of first contact electrodes are electrically connected to the third conductive layer, for each string unit. Other portions of the plurality of second contact electrodes are electrically connected to the sixth conductive layer, for each string unit. The semiconductor memory device according to claim 16.

19. The aforementioned semiconductor substrate is A first circuit capable of applying different voltages to the first and second divided layers, the third and fourth divided layers, the fifth and sixth divided layers, and the seventh and eighth divided layers, A second circuit that allows the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring to be read separately, Equipped with The semiconductor memory device according to claim 15.

20. The aforementioned semiconductor substrate is A different voltage can be applied to each of the multiple first conductive layers and the multiple second conductive layers, The third conductive layer and the sixth conductive layer can be subjected to different voltages for each string unit. Different voltages can be applied to the first divided layer and the second divided layer. Different voltages can be applied to the third and fourth divided layers. Different voltages can be applied to the fifth divided layer and the sixth divided layer. A first circuit capable of applying different voltages to the seventh and eighth divided layers, A second circuit that allows the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring to be read separately, Equipped with The semiconductor memory device according to claim 16.

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