Photodetector

Abstract

To provide a photodetector that can suppress a decrease in detection accuracy. [Solution] The photodetector 1 comprises a semiconductor layer 3 having a main surface 3a which is the light incident surface and a main surface 3b opposite to the main surface 3a, a layer structure 200 formed on the main surface 3a, metal wiring 8 located inside the layer structure 200, and a plurality of quenching elements 13. The semiconductor layer 3 has a plurality of semiconductor regions 31 of a first conductivity type, a plurality of semiconductor regions 32 of a second conductivity type that together with the plurality of semiconductor regions 31 constitute a plurality of avalanche photodiodes APDs, and a plurality of semiconductor regions 34 of a first conductivity type having an impurity concentration higher than the impurity concentration of the plurality of semiconductor regions 31. The thickness of the metal wiring 8 is greater than the distance from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200, and greater than the distance from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200.

Description

Technical Field

[0001] The present invention relates to a photodetector element.

Background Art

[0002] In Patent Document 1, as an example of a photodetector element, a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second semiconductor layer are provided. A third semiconductor layer having the same conductivity type as the semiconductor layer, a pixel isolation portion that defines a pixel region including the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer are provided. An imaging device is disclosed.

[0003] In such a photodetector element, light incident on each pixel region is photoelectrically converted and detected as a current signal. For example, in the imaging device described in Patent Document 1, after charge carriers are generated (photoelectrically converted) in the third semiconductor layer by the incidence of light, the charge carriers are multiplied in the first semiconductor layer and the second semiconductor layer to which a voltage is applied via the first electrode and the second electrode. The multiplied charge carriers are detected as a current signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the photodetector described above, an avalanche photodiode is formed in each pixel, and charge carriers generated in the semiconductor layer by incident light are multiplied by the avalanche photodiode and detected. However, the charge carriers multiplied by the avalanche photodiode may recombine, generating secondary photons. Secondary photons can be a cause of crosstalk. Specifically, secondary photons may be incident on other pixels, potentially generating new charge carriers. Such crosstalk reduces the detection accuracy of the photodetector.

[0006] The present invention aims to provide a photodetector that can suppress a decrease in detection accuracy. [Means for solving the problem]

[0007] The photodetector of the present invention comprises: [1] a first semiconductor layer having a first main surface which is a light incident surface and a second main surface opposite to the first main surface; a layer structure formed on the first main surface; metal wiring formed on the first main surface and at least a portion of which is located inside the layer structure; and a plurality of quenching elements located on the second main surface side with respect to the first semiconductor layer, wherein the first semiconductor layer comprises a plurality of first semiconductor regions of a first conductivity type; a plurality of second semiconductor regions of a second conductivity type located closer to the second main surface than the plurality of first semiconductor regions and constituting a plurality of avalanche photodiodes together with the plurality of first semiconductor regions; and a plurality of first semiconductor regions of a first conductivity type located closer to the first main surface than the plurality of first semiconductor regions and having an impurity concentration higher than the impurity concentration of the plurality of first semiconductor regions. A photodetector having a plurality of third semiconductor regions, each of the plurality of quenching elements being electrically connected to a corresponding second semiconductor region among the plurality of second semiconductor regions, the first semiconductor layer having trenches extending to separate the plurality of third semiconductor regions from each other, the metal wiring being formed on the first main surface extending along the trenches and electrically connecting the plurality of third semiconductor regions from each other, the thickness of the metal wiring being greater than the distance from the first surface of the metal wiring opposite to the first main surface to the surface of the layer structure opposite to the first main surface, and greater than the distance from the second surface of the metal wiring on the first main surface side to the surface of the layer structure on the first main surface side.

[0008] In the above-described photodetector, trenches extending to separate multiple third semiconductor regions are formed in the first semiconductor layer. This prevents secondary photons of charge carriers multiplied in an avalanche photodiode from passing through the third semiconductor region and entering adjacent avalanche photodiodes. Furthermore, the photodetector is formed on a first main surface extending along the trenches and includes metal wiring, at least a portion of which is located inside the layer structure. The thickness of the metal wiring is greater than the distance from the first surface of the metal wiring opposite to the first main surface to the surface of the layer structure opposite to the first main surface, and greater than the distance from the second surface of the metal wiring on the first main surface side to the surface of the layer structure on the first main surface side. In other words, because the thickness of the metal wiring relative to the layer structure is large, secondary photons can be prevented from passing through the layer structure and entering adjacent avalanche photodiodes by the metal wiring. Furthermore, in the above-described photodetector, the first semiconductor layer has multiple third semiconductor regions of a first conductivity type that are located closer to the first main surface than multiple first semiconductor regions and have a higher impurity concentration than the multiple first semiconductor regions. This allows for an accumulation effect through the impurity concentration gradient, thereby improving detection accuracy. In addition, the above-described photodetector includes multiple quenching elements electrically connected to multiple second semiconductor regions. This allows the photodetector to operate stably in Geiger mode. Therefore, the above-described photodetector can suppress a decrease in detection accuracy.

[0009] The photodetector of the present invention may also be [2] "the photodetector described in [1] above, wherein the layer structure comprises a first insulating layer formed on the first main surface and a second insulating layer formed on the first insulating layer, and the metal wiring is located inside the first insulating layer and the second insulating layer." In this case, for example, the first insulating layer and the second insulating layer can be formed from different materials, and a photodetector can be designed according to the required performance. Furthermore, the metal wiring can prevent secondary photons of charge carriers multiplied in an avalanche photodiode from being incident on adjacent avalanche photodiodes via the first insulating layer and the second insulating layer. That is, the metal wiring can further prevent crosstalk and further suppress the decrease in detection accuracy.

[0010] The photodetector of the present invention may also be [3] "the photodetector described in [2] above, wherein the side surface of the metal wiring is in contact with the first insulating layer and the second insulating layer." In this case, crosstalk can be further prevented by the metal wiring, and the decrease in detection accuracy can be further suppressed.

[0011] The photodetector of the present invention may also be [4] "the photodetector described in [1] above, wherein the layer structure is a single insulating layer." In this case, the photodetector can be constructed with a simpler design.

[0012] The photodetector of the present invention may also be [5] "a photodetector according to any one of [1] to [4] above, further comprising a lens portion disposed on the layer structure." In this case, the light incident on the photodetector can be efficiently focused onto the avalanche photodiode by the lens portion, thereby improving detection accuracy.

[0013] The photodetector of the present invention may also be [6] "the photodetector described in [5] above, wherein the thickness of the metal wiring is greater than the distance from the surface on the first main surface side of the lens portion to the first surface." In this case, because the thickness of the metal wiring is large, crosstalk can be further prevented by the metal wiring, and the decrease in detection accuracy can be further suppressed.

[0014] The photodetector of the present invention may also be [7] "a photodetector according to [5] or [6] above, further comprising a plurality of lens portions, each of which is a lens portion, wherein each of the plurality of lens portions is arranged to overlap with a corresponding avalanche photodiode among the plurality of avalanche photodiodes in a direction perpendicular to the first main surface, and when viewed from a direction perpendicular to the first main surface, the outer edge of each of the plurality of lens portions overlaps with the trench." In this case, if the lens portions are not arranged, the light traveling toward the trench (dead area) can be focused onto the avalanche photodiode by the lens portions. Therefore, detection accuracy can be improved.

[0015] The photodetector of the present invention may also be [8] "the photodetector according to any one of [1] to [4] above, wherein, when viewed from a direction perpendicular to the first main surface, the metal wiring is formed to cover the entire trench, and when viewed from a direction perpendicular to the first main surface, each of the plurality of avalanche photodiodes is surrounded by the metal wiring." In this case, crosstalk can be further suppressed by the metal wiring, and detection accuracy can be further improved.

[0016] The photodetector of the present invention comprises: [9] "a first semiconductor layer having a first main surface which is a light incident surface and a second main surface opposite to the first main surface; a layer structure having a first insulating layer formed on the first main surface and a second insulating layer formed on the first insulating layer; metal wiring formed on the first main surface and at least a portion of which is located inside the layer structure; and a plurality of quenching elements located on the second main surface side with respect to the first semiconductor layer, wherein the first semiconductor layer comprises a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type located closer to the second main surface than the plurality of first semiconductor regions and constituting a plurality of avalanche photodiodes together with the plurality of first semiconductor regions, and a plurality of quenching elements located closer to the first main surface than the plurality of first semiconductor regions and the plurality A photodetector having a plurality of third semiconductor regions of a first conductivity type having an impurity concentration higher than the impurity concentration of a number of first semiconductor regions, each of the plurality of quenching elements being electrically connected to a corresponding second semiconductor region from the plurality of second semiconductor regions, trenches being formed in the first semiconductor layer to separate the plurality of third semiconductor regions from each other, the metal wiring being formed on the first main surface to extend along the trenches and electrically connecting the plurality of third semiconductor regions from each other, and in a direction perpendicular to the first main surface, the surface of the metal wiring opposite to the first main surface being located further from the first main surface than the surface of the first insulating layer opposite to the first semiconductor layer.

[0017] In the above-described photodetector element, trenches extending to separate multiple third semiconductor regions from each other are formed in the first semiconductor layer. This prevents secondary photons of charge carriers multiplied in an avalanche photodiode from passing through the third semiconductor region to an adjacent avalanche photodiode. Furthermore, the photodetector element is formed on the first main surface so as to extend along the trenches and includes metal wiring, at least a portion of which is located inside the layer structure. In a direction perpendicular to the first main surface, the surface of the metal wiring opposite to the first main surface is located further from the first main surface than the surface of the first insulating layer opposite to the first semiconductor layer. As a result, due to the large thickness of the metal wiring, secondary photons can be prevented from passing through the layer structure to an adjacent avalanche photodiode. In addition, in the above-described photodetector element, the first semiconductor layer is located closer to the first main surface than multiple first semiconductor regions and has multiple third semiconductor regions of a first conductivity type having a higher impurity concentration than the impurity concentration of the multiple first semiconductor regions. This allows for an accumulation effect through the impurity concentration gradient, thereby improving detection accuracy. Furthermore, the above-mentioned photodetector includes multiple quenching elements electrically connected to multiple second semiconductor regions. This enables stable operation of the photodetector in Geiger mode. Therefore, the above-mentioned photodetector can suppress a decrease in detection accuracy. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide a photodetector that can suppress a decrease in detection accuracy. [Brief explanation of the drawing]

[0019] [Figure 1] This is a schematic plan view showing a photodetector element according to one embodiment. [Figure 2] This is a partial cross-sectional view showing the photodetector element shown in Figure 1. [Figure 3] This is an enlarged view of a portion of the cross-sectional view shown in Figure 2. [Figure 4] It is a partial plan view of the photodetector shown in FIG. 1. [Figure 5] It is a cross-sectional view showing the layer structure and metal wiring of the photodetector shown in FIG. 1. [Figure 6] It is a partial plan view of the photodetector shown in FIG. 1. [Figure 7] It is an enlarged view of a part of the plan view shown in FIG. 6. [Figure 8] It is a diagram for explaining the manufacturing method of the photodetector shown in FIG. 1. [Figure 9] It is a diagram for explaining the manufacturing method of the photodetector shown in FIG. 1. [Figure 10] It is a diagram for explaining the manufacturing method of the photodetector shown in FIG. 1. [Figure 11] It is a diagram for explaining the manufacturing method of the photodetector shown in FIG. 1. [Figure 12] It is a partial cross-sectional view showing the photodetector according to the modified example. [Figure 13] It is a partial cross-sectional view showing the photodetector according to the modified example. [Figure 14] It is a cross-sectional view showing the layer structure and metal wiring of the photodetector shown in FIG. 13. [Figure 15] It is a cross-sectional view showing the layer structure and metal wiring of the photodetector according to the modified example. [Figure 16] It is a cross-sectional view showing the layer structure and metal wiring of the photodetector according to the modified example. [Figure 17] It is a cross-sectional view showing the layer structure and metal wiring of the photodetector according to the modified example. [Figure 18] It is a partial cross-sectional view showing the photodetector according to the modified example. [Figure 19] It is a partial cross-sectional view showing the photodetector according to the modified example. [Figure 20] It is a partial plan view of the photodetector shown in FIG. 19. [Figure 21] It is a partial plan view of the photodetector according to the modified example.

BEST MODE FOR CARRYING OUT THE INVENTION

[0020] Embodiments of the present invention will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. [Configuration of the photodetector element]

[0021] The photodetector in this embodiment is a back-side incident type photosemiconductor element that detects incident light as an electric current signal. In this embodiment, the photodetector is configured as a SPAD (Single Photon Avalanche Diode) array. The photodetector configured as a SPAD array comprises a plurality of cell units, each containing an avalanche photodiode and a quenching element connected in series with each other. Each cell unit constitutes a channel that independently transmits a signal.

[0022] As shown in Figure 1, the photodetector element 1 according to this embodiment is formed in the shape of a substantially rectangular plate. In the following description, the thickness direction of the photodetector element 1 is referred to as the Z-axis direction, one direction perpendicular to the Z-axis direction is referred to as the X-axis direction, and the direction perpendicular to both the Z-axis direction and the X-axis direction is referred to as the Y-axis direction. The photodetector element 1 comprises a light-receiving area 101, a cathode area 102, an anode area 103, and a wire pad area 104.

[0023] The light-receiving area 101 is a region where charge carriers are generated by the incidence of light. In the light-receiving area 101, multiple cell units (pixels), each containing an avalanche photodiode (described later), are arranged two-dimensionally along a plane perpendicular to the Z-axis direction. In this example, the multiple cell units are arranged on a straight line along the X-axis or Y-axis direction. The cathode area 102 is a region where a cathode electrode (counter electrode layer 15, described later) electrically connected to the avalanche photodiode placed in the light-receiving area 101 is located. The cathode area 102 overlaps with the light-receiving area 101 in the Z-axis direction.

[0024] The anode area 103 is a region where an anode electrode (electrode layer 17, described later) electrically connected to the avalanche photodiode located in the light-receiving area 101 is located. When viewed from the Z-axis direction, the anode area 103 is positioned in a frame shape, surrounding the light-receiving area 101 and the cathode area 102. The cathode electrode located in the cathode area 102 and the anode electrode located in the anode area 103 are electrically connected to the substrate of the photodetector 1. Charge carriers generated in the avalanche photodiode in the light-receiving area 101 are transmitted as a current signal to the substrate via the cathode electrode and the anode electrode. The wire pad area 104 is a region where external connection pads electrically connected to the substrate are located. The current signal is processed, for example, in a circuit on the substrate, and then sent to the outside of the photodetector 1 via the pads located in the wire pad area 104.

[0025] The configuration of the photodetector 1 will be explained in more detail with reference to Figures 2 to 7. The photodetector 1 comprises a substrate 2, a semiconductor layer (first semiconductor layer) 3, a plurality of insulating films 4, a layer structure 200, metal wiring 8, a plurality of lens parts 9, a metal part 10, an insulating film 11, an insulating layer 12, a plurality of quenching elements 13, a plurality of wiring layers 14, a plurality of counter electrode layers 15, a plurality of connecting conductors 16, a plurality of electrode layers 17, a plurality of connecting conductors 18, an insulating layer 21, a plurality of connecting conductors 22, a plurality of electrode layers 23, a plurality of connecting conductors 24, and a plurality of electrode layers 25. The layer structure 200 has an insulating layer (first insulating layer) 5, a semiconductor layer (second semiconductor layer) 6, and an insulating layer (second insulating layer) 7.

[0026] Substrate 2 is a substrate on which an IC (integrated circuit), such as an ASIC, is formed. Substrate 2 processes the current signal corresponding to the charge carriers generated in the avalanche photodiode APD, which will be described later. In this example, substrate 2 is formed in the shape of a rectangular plate. Substrate 2 has a main surface 2a and a main surface 2b. Main surfaces 2a and 2b extend perpendicularly in the Z-axis direction. As shown in Figure 1, in the region of substrate 2 indicated by reference numeral 20, multiple wirings for applying a reverse bias voltage to the avalanche photodiode APD, which will be described later, are formed. In Figure 1, region 20 is hatched for ease of explanation.

[0027] The semiconductor layer 3 is formed on the main surface 2a of the substrate 2 via insulating layers 12 and 21. The semiconductor layer 3 has a main surface (first main surface) 3a and a main surface (second main surface) 3b. The main surfaces 3a and 3b extend perpendicular to the Z-axis direction. That is, in this example, the Z-axis direction is perpendicular to the main surface 3a. The main surface 3a constitutes the light incident surface of the photodetector 1. That is, the light detected by the photodetector 1 is incident into the interior of the semiconductor layer 3 from the main surface 3a. The main surface 3b is located on the opposite side of the main surface 3a in the Z-axis direction. The main surface 3b is located closer to the substrate 2 than the main surface 3a.

[0028] The semiconductor layer 3 includes a plurality of semiconductor regions (a plurality of first semiconductor regions) 31, a plurality of semiconductor regions (a plurality of second semiconductor regions) 32, a plurality of semiconductor regions 33, a plurality of semiconductor regions (a plurality of third semiconductor regions) 34, a semiconductor region 35, a frame region 36, and a semiconductor region (a fourth semiconductor region) 37.

[0029] The multiple semiconductor regions 31 are impurity-doped semiconductor regions and have a first conductivity type (P-type in this example). The multiple semiconductor regions 31 are separated from each other by trenches 40, which will be described later, and are arranged two-dimensionally along a plane perpendicular to the Z-axis direction. Each semiconductor region 31 includes a first portion 31a and a second portion 31b. The first portion 31a is formed to cover the second portion 31b. The second portion 31b is formed in the region of the semiconductor region 31 on the main surface 3b side. The impurity concentration of the second portion 31b is higher than that of the first portion 31a.

[0030] The multiple semiconductor regions 32 are impurity-doped semiconductor regions and have a second conductivity type (N-type in this example) that is different from the first conductivity type. The multiple semiconductor regions 32 are located closer to the main surface 3b than the multiple semiconductor regions 31. The position of the semiconductor regions 32 closer to the main surface 3b than the semiconductor regions 31 means that the center of the semiconductor region 32 in the Z-axis direction is closer to the main surface 3b than the center of the semiconductor region 31. The semiconductor regions 32 are formed closer to the main surface 3b than the center of the semiconductor layer 3 in the Z-axis direction. Each semiconductor region 32 is positioned to overlap with the corresponding semiconductor region 31 among the multiple semiconductor regions 31 in the Z-axis direction. The semiconductor region 32 is in contact with the second portion 31b of the semiconductor region 31.

[0031] Multiple semiconductor regions 32, together with multiple semiconductor regions 31, constitute multiple avalanche photodiodes (APDs). That is, the semiconductor layer 3 has multiple avalanche photodiodes (APDs). A corresponding pair of semiconductor regions 31 and 32 constitute one avalanche photodiode (APD). In an avalanche photodiode (APD), the second portion 31b of semiconductor region 31 and semiconductor region 32 constitute an avalanche region. The avalanche region multiplies the charge carriers generated in the first portion 31a of semiconductor region 31.

[0032] Multiple semiconductor regions 33 are impurity-doped semiconductor regions and have a second conductivity type. The semiconductor regions 33 are guard ring regions. Each semiconductor region 33 is formed around the corresponding semiconductor region 32 when viewed from the Z-axis direction. The impurity concentration of the semiconductor region 33 is lower than that of the semiconductor region 32. That is, the impurity concentration of the semiconductor region 32 is higher than that of the semiconductor region 33.

[0033] The multiple semiconductor regions 34 are impurity-doped semiconductor regions and have a first conductivity type. The multiple semiconductor regions 34 are separated from each other by trenches 40 (described later) and are arranged two-dimensionally along a plane perpendicular to the Z-axis direction. The multiple semiconductor regions 34 are located closer to the main surface 3a than the multiple semiconductor regions 31. That is, each semiconductor region 34 is formed on the corresponding semiconductor region 31. In this example, the surface of the semiconductor region 34 constitutes a part of the main surface 3a. The impurity concentration of the semiconductor region 34 is higher than the impurity concentration of the semiconductor region 31. As in this example, when the semiconductor region 31 has a first part 31a and a second part 31b with different impurity concentrations, the impurity concentration of the semiconductor region 31 corresponds to the concentration of the first part 31a. That is, the impurity concentration of the semiconductor region 31 corresponds to the part with a lower impurity concentration (first part 31a) located on the semiconductor region 34 side via the second part 31b, rather than the part with a high impurity concentration (second part 31b) that is in contact with the semiconductor region 32.

[0034] The semiconductor region 35 is a semiconductor region doped with impurities and has a first conductivity type. When viewed from the Z-axis direction, the semiconductor region 35 is formed outside the multiple semiconductor regions 31. The semiconductor region 35 is separated from the semiconductor region 31 by a trench 40, which will be described later. The impurity concentration of the semiconductor region 35 may be the same as the impurity concentration of the first portion 31a of the semiconductor region 31.

[0035] The frame region 36 is a semiconductor region doped with impurities and has a first conductivity type. When viewed from the Z-axis direction, the frame region 36 is formed in a rectangular frame shape so as to surround a plurality of avalanche photodiodes (APDs) (semiconductor regions 31 and 32). When viewed from the Z-axis direction, the frame region 36 is formed continuously. The frame region 36 is located closer to the main surface 3b than the semiconductor region 35. When the frame region 36 is located closer to the main surface 3b than the semiconductor region 35, it means that in the Z-axis direction, the center of the frame region 36 is located closer to the main surface 3b than the center of the semiconductor region 35. The frame region 36 is formed closer to the main surface 3b than the center of the semiconductor layer 3 in the Z-axis direction. The frame region 36 is located so as to overlap with a part of the semiconductor region 35 in the Z-axis direction (so as to be covered by the semiconductor region 35). The frame region 36 constitutes a part of the main surface 3b. The impurity concentration of the frame region 36 is higher than the impurity concentration of the semiconductor region 31 and the semiconductor region 35. The frame region 36 is electrically connected to the semiconductor region 31 via the semiconductor region 35, semiconductor region 37, metal wiring 8, and semiconductor region 34. The frame region 36 is electrically connected to the power supply circuit of the substrate 2 via the electrode layer 17, connecting conductor 18, connecting conductor 24, and electrode layer 25, which will be described later.

[0036] The semiconductor region 37 is a semiconductor region doped with impurities and has a first conductivity type. When viewed from the Z-axis direction, the semiconductor region 37 is formed outside the multiple semiconductor regions 31. When viewed from the Z-axis direction, the semiconductor region 37 is formed in a frame shape so as to surround the multiple frame portions 41 (multiple semiconductor regions 34). The semiconductor region 37 is separated from the semiconductor region 34 by a trench 40, which will be described later. The semiconductor region 37 is located closer to the main surface 3a than the frame region 36. The frame region 36 constitutes a part of the main surface 3a. The impurity concentration of the semiconductor region 37 is higher than the impurity concentrations of the semiconductor regions 31 and 35.

[0037] A trench 40 is formed in the semiconductor layer 3. The trench 40 is formed to extend from the main surface 3a to the main surface 3b. That is, the trench 40 penetrates the semiconductor layer 3 in the Z-axis direction. As shown in Figure 4, the trench 40 extends in a mesh-like pattern. In Figure 4, hatching is applied to the trench 40 for ease of explanation. The trench 40 includes a plurality of frame portions 41 that extend in a frame-like shape when viewed from the Z-axis direction. In this example, each of the plurality of frame portions 41 extends in a rectangular frame shape. More specifically, each frame portion 41 has a pair of first portions 411 that extend along the X-axis direction and a pair of second portions 412 that extend along the Y-axis direction. When viewed from the Z-axis direction, the width of the frame portion 41 in the X-axis direction (distance between the centers of the second portions 412) and the width of the frame portion 41 in the Y-axis direction (distance between the centers of the first portions 411) may be, for example, 5 μm or more and 25 μm or less. As shown in Figure 6, when viewed from the Z-axis direction, the inner edge 41a of the trench 40 has four corners 42. In Figure 6, for the sake of explanation, some components such as the substrate 2 are not shown. The corners 42 correspond to the parts (connection parts) where the first part 411 and the second part 412 intersect with each other. When viewed from the Z-axis direction, the corners 42 are at right angles.

[0038] Inside each frame 41, there is one semiconductor region 31, one semiconductor region 32, one semiconductor region 33, and one semiconductor region 34. The trench 40 extends to separate the multiple semiconductor regions 31 from each other. The trench 40 extends to separate the multiple semiconductor regions 34 from each other. Inside each frame 41, there is one avalanche photodiode APD (a pair of semiconductor regions 31 and 32). When viewed from the Z-axis direction, the trench 40 extends to separate the multiple avalanche photodiode APDs from each other. When viewed from the Z-axis direction, each frame 41 extends to surround the corresponding avalanche photodiode APD.

[0039] As shown in Figures 1 and 2, when viewed from the Z-axis direction, the frame region 36 has a width W1. In Figure 1, the frame region 36 is shown by a dashed line. The width W1 is the width in the direction perpendicular to the extension direction of the frame region 36. The width W1 is, for example, about 100 μm. As shown in Figure 4, when viewed from the Z-axis direction, each of the multiple regions A1 surrounded by multiple frame portions 41 of the semiconductor layer 3 has a width W2. The width W2 is the maximum width of region A1. In this example, when viewed from the Z-axis direction, region A1 has a rectangular shape. Therefore, the width W2 is the length of the diagonal of region A1 when viewed from the Z-axis direction. When viewed from the Z-axis direction, the width W1 is larger than the width W2. The width W1 is at least twice the width W2. The width W1 may also be at least four times the width W2.

[0040] As shown in Figures 1 and 2, when viewed from the Z-axis direction, the region A2 located between the frame region 36 and the multiple frame sections 41 has a width W3. In this example, when viewed from the Z-axis direction, region A2 extends in a rectangular frame shape. The width W3 is the width in the direction perpendicular to the extension direction of region A2. When viewed from the Z-axis direction, the width W1 is greater than the width W3. The width W1 is at least twice the width W3. The width W1 may also be at least four times the width W3.

[0041] As shown in Figures 6 and 7, the semiconductor region 32 is located inside the frame 41 when viewed from the Z-axis direction. When viewed from the Z-axis direction, the outer edge 32a of the semiconductor region 32 is substantially rectangular and extends along the inner edge 41a of the frame 41. The statement that the outer edge 32a extends along the inner edge 41a means that at least a portion of the outer edge 32a follows the inner edge 41a; the entire outer edge 32a does not necessarily follow the inner edge 41a. In this example, the outer edge 32a includes portions that follow each of the four sides of the substantially rectangular inner edge 41a.

[0042] When viewed from the Z-axis direction, the outer edge 32a of the semiconductor region 32 has multiple (four in this example) corners 32b. When viewed from the Z-axis direction, each corner 32b has an R-shape (round shape). Each corner 32b is formed to be convex toward the corresponding corner 42 among the multiple corners 42 that have been formed on the inner edge 41a of the frame portion 41. The corners 32b are curved so as to be convex toward the outside (corner 42) of the semiconductor region 32. As shown in Figure 7, when viewed from the Z-axis direction, each corner 32b and the corresponding corner 42 are separated by a distance D5. The distance D5 is the shortest distance between the vertex of each corner 32b and the corresponding corner 42.

[0043] Multiple insulating films 4 are formed on the main surface 3b of the semiconductor region 31. Each insulating film 4 is formed to cover the surface on the main surface 3b side of the corresponding semiconductor region 32. In this example, the insulating films 4 are formed of silicon nitride (LP-SiN). The insulating films 4 protect the semiconductor region 32 during the manufacturing process of the photodetector element 1 and can reduce variations in the characteristics of the avalanche photodiode (APD).

[0044] The layer structure 200 is formed on the main surface 3a of the semiconductor layer 3. As described above, the layer structure 200 has an insulating layer 5, a semiconductor layer 6, and an insulating layer 7. The layer structure 200 has a surface 200a and a surface 200b. Surface 200a is located on the opposite side of surface 200b in the Z-axis direction. Surface 200a is the surface of the layer structure 200 opposite to the main surface 3a. Surface 200b is the surface of the layer structure 200 on the side of the main surface 3a.

[0045] The insulating layer 5 is formed on the main surface 3a of the semiconductor layer 3. The insulating layer 5 is directly formed on the main surface 3a. The insulating layer 5 is in contact with the main surface 3a. As shown in Figure 3, the insulating layer 5 has a main surface 5a and a main surface 5b. The main surface 5a is the surface of the insulating layer 5 opposite to the semiconductor layer 3, and the main surface 5b is the surface of the insulating layer 5 on the semiconductor layer 3 side. The main surface 5b constitutes the surface 200b of the layer structure 200. The insulating layer 5 is formed to cover the semiconductor region 34 and the semiconductor region 37. Multiple through holes (contact holes) 5c are formed in the insulating layer 5. Multiple contact portions 82 of the metal wiring 8, which will be described later, are arranged in the multiple through holes 5c. The insulating layer 5 is formed of an electrically insulating material. In this example, the insulating layer 5 is an oxide film formed of SiO2.

[0046] The semiconductor layer 6 is formed on the main surface 3a of the semiconductor layer 3 via the insulating layer 5. The semiconductor layer 6 is formed directly on the insulating layer 5. The semiconductor layer 6 is in contact with the insulating layer 5. The semiconductor layer 6 is formed to cover the insulating layer 5. The semiconductor layer 6 is an undoped semiconductor layer that is not doped with impurities. As shown in Figure 2, the semiconductor layer 6 has a main surface 6a and a main surface 6b. The main surface 6a is the surface of the semiconductor layer 6 opposite to the insulating layer 5, and the main surface 6b is the surface of the semiconductor layer 6 on the insulating layer 5 side. That is, the main surface 6a is located on the opposite side of the main surface 6b in the Z-axis direction. The thickness of the semiconductor layer 6 may be, for example, several μm (2-3 μm in this example).

[0047] A textured structure 6c having an uneven shape is formed on the surface of the semiconductor layer 6. The textured structure 6c is formed on the main surface 6a of the semiconductor layer 6. In this example, an irregular (not uniform) uneven shape is formed. The textured structure 6c is formed in the region of the main surface 6a that overlaps with the semiconductor region 31 in the Z-axis direction. That is, the textured structure 6c overlaps with multiple avalanche photodiodes (APDs) in the Z-axis direction. In this example, the textured structure 6c is not formed in the region of the main surface 6a that overlaps with the semiconductor region 35 in the Z-axis direction. On the main surface 6a, the region where the textured structure 6c is formed is rougher (has greater surface roughness) and less smooth than the region where the textured structure 6c is not formed.

[0048] The insulating layer 7 is formed on the main surface 3a of the semiconductor layer 3 via the insulating layer 5 and the semiconductor layer 6. The insulating layer 7 is formed on the insulating layer 5 via the semiconductor layer 6. The insulating layer 7 is formed directly on the semiconductor layer 6. The insulating layer 7 is in contact with the main surface 6a of the semiconductor layer 6. As shown in Figure 2, the insulating layer 7 has main surfaces 7a and 7b. Main surface 7a is the surface of the insulating layer 7 opposite to the semiconductor layer 6, and main surface 7b is the surface of the insulating layer 7 on the semiconductor layer 6 side. That is, main surface 7a is located on the opposite side of main surface 7b in the Z-axis direction. Main surface 7a constitutes the surface 200a of the layer structure 200. The insulating layer 7 is formed to cover the texture structure 6c formed on the semiconductor layer 6. The insulating layer 7 penetrates into the recesses of the texture structure 6c (uneven shape). The insulating layer 7 is formed of an electrically insulating material. In this example, the insulating layer 7 is a resin layer formed of a resin material. The insulating layer 7 may be formed from a material other than resin.

[0049] The metal wiring 8 is arranged on the main surface 3a of the semiconductor layer 3. When viewed from the Z-axis direction, the metal wiring 8 extends along the trench 40. That is, the metal wiring 8 is formed on the main surface 3a so as to extend along the trench 40. When viewed from the Z-axis direction, the metal wiring 8 extends in a mesh-like pattern. At least a portion (all in this example) of the metal wiring 8 is located inside the layer structure 200. That is, the metal wiring 8 is located inside the insulating layer 5, the semiconductor layer 6, and the insulating layer 7. The metal wiring 8 is made of a metallic material. The metal wiring 8 has a main body portion 81 that extends along the trench 40 and a plurality of contact portions 82 integrally formed with the main body portion 81.

[0050] The main body portion 81 is a wiring layer having thickness in the Z-axis direction. The main body portion 81 has a surface 81a, a surface 81b, and a side surface 81c. Surface 81a is the surface of the main body portion 81 opposite to the main surface 3a of the semiconductor layer 3. Surface 81a constitutes the surface (first surface) 8a of the metal wiring 8 opposite to the main surface 3a. In the Z-axis direction, surface 81a (surface 8a) is located further from the main surface 3a than the main surface 5a of the insulating layer 5. Surface 8a protrudes from the insulating layer 5. That is, surface 8a is exposed from the insulating layer 5. In this example, surface 8a is located inside the insulating layer 7 and is in contact with the insulating layer 7.

[0051] Surface 81b is the surface on the main surface 3a side of the main body portion 81. Surface 81b constitutes the surface (second surface) 8b on the main surface 3a side of the metal wiring 8. That is, the surface 8b on the main surface 3a side of the metal wiring 8 corresponds to the surface (surface 81b) of the main body portion 81 that extends along the trench 40, not the surface of the contact portion 82 described later. Surface 81b (surface 8b) is located inside the insulating layer 5 and is in contact with the insulating layer 5. A part of the insulating layer 5 is located between surface 81b and the trench 40. Side surface 81c is the surface that connects surface 81a and surface 81b. Side surface 81c constitutes the side surface 8c that connects surface 8a and surface 8b of the metal wiring 8. Side surface 8c (side surface 81c) is in contact with the insulating layer 5, the semiconductor layer 6, and the insulating layer 7.

[0052] Multiple contact portions 82 are formed on the surface 81b of the main body portion 81. Each contact portion 82 is located within a corresponding through-hole 5c formed in the insulating layer 5. The contact portions 82 are formed in a columnar shape. Each contact portion 82 is in contact with a corresponding semiconductor region 34 or semiconductor region 37. The metal wiring 8 electrically connects the multiple semiconductor regions 34 to each other and also electrically connects the multiple semiconductor regions 34 to the semiconductor region 37.

[0053] As shown in Figure 5, the metal wiring 8 has a thickness T. The thickness T of the metal wiring 8 is the thickness of the main body 81, and in this example, it is the maximum distance from surface 81a (surface 8a) to surface 81b (surface 8b). The thickness T is greater than the distance D1 from surface 8a of the metal wiring 8 to surface 200a of the layer structure 200 (main surface 7a of the insulating layer 7). The thickness T is greater than the distance D2 from surface 8b of the metal wiring 8 to surface 200b of the layer structure 200 (main surface 5b of the insulating layer 5). In this example, the thickness T is greater than the sum of distances D1 and D2.

[0054] When viewed from the Z-axis direction, the metal wiring 8 is formed to cover the entire trench 40. The metal wiring 8 overlaps with the trench 40 in the Z-axis direction. When viewed from the Z-axis direction, each of the multiple avalanche photodiodes APD is surrounded by the metal wiring 8. When viewed from the Z-axis direction, the width W4 of the metal wiring 8 is greater than the width W5 of the trench 40. The width W4 is the width in the direction perpendicular to the extension direction of the metal wiring 8 and is the width of the main body 81. The width W5 is the width in the direction perpendicular to the extension direction of the trench 40.

[0055] Multiple lens portions 9 are arranged on a layer structure 200. The lens portions 9 are formed directly on the insulating layer 7 of the layer structure 200. The lens portions 9 are in contact with the main surface 7a of the insulating layer 7. The lens portions 9 are arranged on the semiconductor layer 6 via the insulating layer 7. More specifically, the lens portions 9 are arranged on the texture structure 6c of the semiconductor layer 6 via the insulating layer 7. The insulating layer 7 functions as a spacer positioned between the lens portions 9 and the texture structure 6c. The lens portions 9 overlap with the texture structure 6c in the Z-axis direction. The multiple lens portions 9 are arranged two-dimensionally along a plane perpendicular to the Z-axis direction. Each of the multiple lens portions 9 is arranged to overlap with the corresponding avalanche photodiode APD in the Z-axis direction. The lens portions 9 focus the light incident on the lens portions 9 onto the avalanche photodiode APD.

[0056] The lens portion 9 has a surface 9a and a surface 9b. Surface 9a is the surface of the lens portion 9 opposite to the insulating layer 7. Surface 9a is a curved surface that protrudes away from the insulating layer 7. Surface 9b is the surface of the lens portion 9 on the insulating layer 7 side. Surface 9b is a flat surface that extends perpendicular to the Z-axis direction. The thickness T of the metal wiring 8 is greater than the distance D3 from surface 9b to surface 8a. When viewed from the Z-axis direction, the outer edges 9c of each of the multiple lens portions 9 overlap with the trench 40. The outer edges 9c are located outside the outer edge of the semiconductor region 31. In this example, the outer edges 9c are rectangular in shape.

[0057] The metal part 10 is formed inside the trench 40. The metal part 10 is positioned to separate adjacent avalanche photodiodes (APDs) from each other. When viewed from the Z-axis direction, the metal part 10 extends along the trench 40.

[0058] The insulating film 11 is formed inside the trench 40. The insulating film 11 is formed between the inner surface of the trench 40 and the metal part 10. The insulating film 11 is made of an electrically insulating material. In this example, the insulating film 11 is an oxide film formed of SiO2. The insulating film 11 electrically insulates the semiconductor region 31 and the metal part 10 from each other. The insulating film 11 electrically insulates the semiconductor region 34 and the metal part 10 from each other.

[0059] The insulating layer 12 is formed on the main surface 3b of the semiconductor layer 3. The insulating layer 12 is directly formed on the main surface 3b. The insulating layer 12 is in contact with the main surface 3b. The insulating layer 12 is formed of an electrically insulating material. In this example, the insulating layer 12 is an oxide film formed of SiO2.

[0060] Multiple quenching elements 13 are located inside the insulating layer 12. The multiple quenching elements 13 are located on the main surface 3b side with respect to the semiconductor layer 3. Each of the multiple quenching elements 13 is electrically connected to the corresponding semiconductor region 32 and the counter electrode layer 15. As shown in Figure 6, when viewed from the Z-axis direction, the quenching elements 13 extend along the outer edge 32a of the semiconductor region 32 and overlap with the outer edge 32a of the semiconductor region 32. The statement that the quenching elements 13 extend along the outer edge 32a of the semiconductor region 32 means that at least a portion of the quenching elements 13 is along the outer edge 32a, and the entire quenching element 13 does not necessarily have to be along the outer edge 32a. In this example, the quenching elements 13 include portions along each of the four sides of the substantially rectangular outer edge 32a.

[0061] In this example, the quenching element 13 is a quenching resistor formed in the shape of a frame plate with a thickness along the Z-axis direction. When viewed from the Z-axis direction, the quenching element 13 is formed in the shape of a substantially rectangular frame. The quenching element 13 has a pair of first parts 131, 133 extending along the X-axis direction and a pair of second parts 132, 134 extending along the Y-axis direction.

[0062] The end 131a of the first part 131 (one end of the quenching element 13) is electrically connected to the semiconductor region 32 via the wiring layer 14. The quenching element 13 is connected in series with the semiconductor region 32 (avalanche photodiode APD). The other end 131b of the first part 131 is continuous with the end 132a of the second part 132. The other end 132b of the second part 132 is continuous with the end 133a of the first part 133. The other end 133b of the first part 133 is continuous with the end 134a of the second part 134. The other end 134b of the second part 134 (the other end of the quenching element 13) is electrically connected to the counter electrode layer 15. The end 134b of the second part 134 is not continuous with the end 131a of the first part 131. In other words, the quenching element 13 is not a closed frame when viewed from the Z-axis direction, but is formed in a frame shape with a gap in part (end 131a and end 134b are separated from each other).

[0063] Each quenching element 13 is located inside the corresponding frame portion 41 when viewed from the Z-axis direction. When viewed from the Z-axis direction, the outer edge 13a of the quenching element 13 extends along the inner edge 41a of the frame portion 41. The statement that the outer edge 13a extends along the inner edge 41a means that at least a portion of the outer edge 13a is aligned with the inner edge 41a, and the entire outer edge 13a does not necessarily have to be aligned with the inner edge 41a. In this example, the outer edge 13a includes portions that are aligned with each of the four sides of the rectangular inner edge 41a.

[0064] When viewed from the Z-axis direction, the outer edge 13a of the quenching element 13 has multiple (three in this example) corners 135. The three corners 135 correspond to the portion where the end 131b of the first portion 131 and the end 132a of the second portion 132 are continuous, the portion where the end 132b of the second portion 132 and the end 133a of the first portion 133 are continuous, and the portion where the end 133b of the first portion 133 and the end 134a of the second portion 134 are continuous.

[0065] When viewed from the Z-axis direction, each corner 135 has an R-shape (round shape). Each corner 135 is formed to be convex toward the corresponding corner 42 among the multiple corners 42 that have been formed on the inner edge 41a of the frame portion 41. The corner 135 is curved to be convex toward the outside (corner 42) of the quenching element 13. As shown in Figure 7, when viewed from the Z-axis direction, each corner 135 and the corresponding corner 42 are separated by a distance D6. Distance D6 is the shortest distance between the vertex of each corner 135 and the corresponding corner 42. In this example, distance D6 is smaller than distance D5.

[0066] Multiple counter electrode layers 15 are located inside the insulating layer 12. Multiple counter electrode layers 15 are located on the main surface 3b side with respect to the semiconductor layer 3. Each of the multiple counter electrode layers 15 is electrically connected to the corresponding quenching element 13. The counter electrode layers 15 face the semiconductor region 32 in the Z-axis direction. The counter electrode layers 15 overlap at least a portion of the semiconductor region 32 in the Z-axis direction. The counter electrode layers 15 are located between the semiconductor layer 3 and the quenching element 13 in the Z-axis direction.

[0067] As shown in Figure 6, the counter electrode layer 15 is formed to include a peripheral region R when viewed from the Z-axis direction. The peripheral region R is a region located inside the outer edge 32a of the semiconductor region 32 when viewed from the Z-axis direction, and is a virtual annular region along the outer edge 32a of the semiconductor region 32. As described above, the outer edge 32a is substantially rectangular. Therefore, in this example, the peripheral region R is a substantially rectangular annular region with an outer edge smaller than the outer edge 32a. The statement that the counter electrode layer 15 includes the peripheral region R means that the counter electrode layer 15 includes at least a part of the peripheral region R, and does not necessarily include the entire peripheral region R. For example, the counter electrode layer 15 may include 50% or more of the peripheral region R, or it may include 80% or more of the peripheral region R. When viewed from the Z-axis direction, the outer edge 15a is located inside the outer edge 32a.

[0068] The counter electrode layer 15 is formed so as to extend from the central part C to the peripheral part R of the semiconductor region 32 when viewed from the Z-axis direction. That is, the counter electrode layer 15 is formed with an extent that includes the central part C and the peripheral part R when viewed from the Z-axis direction. In this example, the size of the counter electrode layer 15 is 50% or more of the size of the semiconductor region 32 when viewed from the Z-axis direction. The size of the counter electrode layer 15 may be 80% or more of the size of the semiconductor region 32 when viewed from the Z-axis direction. When viewed from the Z-axis direction, the outer edge 15a of the counter electrode layer 15 is located inside the outer edge 32a of the semiconductor region 32.

[0069] In this example, the counter electrode layer 15 is substantially rectangular when viewed from the Z-axis direction. When viewed from the Z-axis direction, the counter electrode layer 15 has four corners (three corners 151 and one corner 152) that are convex toward the corner 42 of the trench 40. Each corner 151 has an R-shape (round shape). Each corner 151 is curved so as to be convex toward the outside (corner 42) of the counter electrode layer 15. In contrast, corner 152 is formed at a right angle. When viewed from the Z-axis direction, a notch 153 is formed on one side of the counter electrode layer 15. A wiring layer 14 connected to one end of the quenching element 13 is arranged in the region corresponding to the notch 153. The counter electrode layer 15 is made of a metallic material such as aluminum.

[0070] Except for the portions corresponding to both ends (ends 131a, 134b) of the quenching element 13, when viewed from the Z-axis direction, the outer edge 15a of the counter electrode layer 15 and the inner edge 13b of the quenching element 13 are spaced apart from each other. That is, when viewed from the Z-axis direction, the quenching element 13 is formed in the region outside the counter electrode layer 15. When viewed from the Z-axis direction, the width W6 of the quenching element 13 is greater than the distance D4 from the outer edge 15a of the counter electrode layer 15 to the inner edge 13b of the quenching element 13.

[0071] When viewed from the Z-axis direction, the quenching element 13 has an overlapping portion 136 that is located along the inner edge 13b of the quenching element 13 and overlaps with the semiconductor region 32, and a non-overlapping portion 137 that is located closer to the outer edge 13a of the quenching element 13 than the overlapping portion 136 and does not overlap with the semiconductor region 32. When viewed from the Z-axis direction, the width W7 of the overlapping portion 136 is smaller than the width W8 of the non-overlapping portion 137.

[0072] Multiple connecting conductors 16 are formed inside the insulating layer 12. The multiple connecting conductors 16 are located on the substrate 2 side with respect to the multiple counter electrode layers 15. Each connecting conductor 16 is formed in a columnar shape (cylindrical in this example) having a central axis along the Z-axis direction. Each connecting conductor 16 is electrically connected to the corresponding counter electrode layer 15 and to the corresponding connecting conductor 22 among the multiple connecting conductors 22 described later. The connecting conductors 16 are formed of a metallic material such as copper.

[0073] Multiple electrode layers 17 are formed inside the insulating layer 12. The multiple electrode layers 17 are located on the main surface 3b side with respect to the semiconductor layer 3. Each of the multiple electrode layers 17 is electrically connected to the frame region 36 via wiring such as connecting conductors. The electrode layers 17 extend perpendicularly in the Z-axis direction and face the frame region 36 in the Z-axis direction. The electrode layers 17 are formed of a metallic material such as aluminum.

[0074] Multiple connecting conductors 18 are formed inside the insulating layer 12. The multiple connecting conductors 18 are located on the substrate 2 side relative to the multiple electrode layers 17. Each connecting conductor 18 is formed in a columnar shape (cylindrical in this example) having a central axis along the Z-axis direction. Each connecting conductor 18 is electrically connected to the corresponding electrode layer 17 and to the corresponding connecting conductor 24 among the multiple connecting conductors 24 described later. The connecting conductors 18 are formed of a metallic material such as copper.

[0075] The insulating layer 21 is formed on the main surface 2a of the substrate 2. The insulating layer 21 is directly formed on the main surface 2a. The insulating layer 21 is in contact with the main surface 2a. The insulating layer 21 is also in contact with the main surface 12b of the insulating layer 12 on the side opposite to the semiconductor layer 3. The insulating layer 21 and the insulating layer 12 are laminated on the main surface 2a in this order. The insulating layer 21 is formed of an electrically insulating material. In this example, the insulating layer 21 is an oxide film formed of SiO2.

[0076] Multiple connecting conductors 22 are formed inside the insulating layer 21. Each connecting conductor 22 is formed in a columnar shape (cylindrical in this example) with a central axis along the Z-axis direction. Each connecting conductor 22 is electrically connected to the corresponding connecting conductor 16 and to the corresponding electrode layer 23 among the multiple electrode layers 23 described later. The connecting conductors 22 are formed from a metallic material such as copper.

[0077] Multiple electrode layers 23 are formed inside the insulating layer 21. The multiple electrode layers 23 are located on the substrate 2 side relative to the multiple connecting conductors 22. Each of the multiple electrode layers 23 is electrically connected to the corresponding connecting conductor 22 and the substrate 2. The electrode layers 23 extend perpendicular to the Z-axis direction. The electrode layers 23 are formed of a metallic material such as aluminum.

[0078] Multiple connecting conductors 24 are formed inside the insulating layer 21. Each connecting conductor 24 is formed in a columnar shape (cylindrical in this example) with a central axis along the Z-axis direction. Each connecting conductor 24 is electrically connected to the corresponding connecting conductor 18 and to the corresponding electrode layer 25 among the multiple electrode layers 25 described later. The connecting conductors 24 are formed of a metallic material such as copper.

[0079] Multiple electrode layers 25 are formed inside the insulating layer 21. The multiple electrode layers 25 are located on the substrate 2 side relative to the multiple connecting conductors 24. Each of the multiple electrode layers 25 is electrically connected to the corresponding connecting conductor 24 and the substrate 2. The electrode layers 25 extend perpendicular to the Z-axis direction. The electrode layers 25 are formed of a metallic material such as aluminum.

[0080] The operation of the photodetector 1 described above will now be explained. In this example, the photodetector 1 is operated when a high reverse bias voltage is applied to the avalanche photodiode APD (Geiger mode). Specifically, first, a high voltage is applied to the avalanche photodiode APD to induce the avalanche effect. Specifically, a voltage is applied between electrode layers 25 and 23 connected to the substrate 2 based on the control of the power supply circuit of the substrate 2. Electrode layer 25 is electrically connected to each avalanche photodiode APD (semiconductor region 31 and semiconductor region 32) via connecting conductor 24, connecting conductor 18, electrode layer 17, frame region 36, semiconductor region 35, semiconductor region 37, metal wiring 8, and semiconductor region 34. Electrode layer 23 is also electrically connected to the avalanche photodiode APD via connecting conductor 22, connecting conductor 16, counter electrode layer 15, quenching element 13, and wiring layer 14. Therefore, a voltage is applied to the avalanche photodiode APD by applying a voltage between electrode layer 25 and electrode layer 23.

[0081] Next, the light to be detected is incident on the avalanche photodiode APD. The light is focused by the lens 9, then passes through the insulating layer 7, the semiconductor layer 6, and the insulating layer 5 in that order, and is incident on the semiconductor region 31 from the main surface 3a. Charge carriers are generated in the semiconductor region 31 by the incident light. The generated charge carriers are multiplied in the avalanche region, which is composed of the second part 31b of the semiconductor region 31 and the semiconductor region 32. The multiplied charge carriers are sent to the substrate 2 as a current signal for each avalanche photodiode APD (each cell unit) separated by the trench 40. The current signal is sent to the substrate 2 via the counter electrode layer 15 and the electrode layer 17, etc. The circuit of the substrate 2 processes the received current signal to generate a digital signal indicating the light incident on the photodetector 1. The signal processed by the circuit of the substrate 2 is sent to the outside of the photodetector 1 via pads arranged in the wire pad area 104. [Manufacturing method for photodetectors]

[0082] Next, the manufacturing method of the photodetector 1 will be described. First, as shown in Figure 8, a laminate is prepared in which an insulating layer 12, a semiconductor layer 3, an insulating layer 5, and a semiconductor layer 60 are stacked in this order. The semiconductor layer 60 is the layer that becomes the semiconductor layer 6 through the manufacturing process of the photodetector 1 (the layer corresponding to semiconductor layer 6). In this example, the semiconductor layer 60 is a bulk layer. The semiconductor layer 60 is formed on the main surface 3a of the semiconductor layer 3 via the insulating layer 5. The semiconductor layer 60 is formed directly on the insulating layer 5. The semiconductor layer 60 is in contact with the insulating layer 5. The semiconductor layer 60 is formed to cover the insulating layer 5. The semiconductor layer 60 is an undoped semiconductor layer that is not doped with impurities. The semiconductor layer 60 has a main surface 60a and a main surface 60b. The main surface 60a is the surface of the semiconductor layer 60 opposite to the insulating layer 5, and the main surface 60b is the surface of the semiconductor layer 60 on the insulating layer 5 side. The main surface 60a is located on the opposite side of the main surface 60b in the Z-axis direction. The thickness of the semiconductor layer 60 is greater than the thickness of the semiconductor layer 6. The thickness of the semiconductor layer 60 may be, for example, several hundred μm. In this example, the thickness of the semiconductor layer 60 is 600 μm or more.

[0083] Next, as shown in Figure 9, a laminate of substrate 2 and insulating layer 21 is prepared, and insulating layer 12 and insulating layer 21 are joined to each other. At this time, insulating layer 12 and insulating layer 21 are aligned so that the connecting conductor 16 in insulating layer 12 and the connecting conductor 22 in insulating layer 21 are connected to each other, and the connecting conductor 18 in insulating layer 12 and the connecting conductor 24 in insulating layer 21 are connected to each other (see Figure 2).

[0084] Next, as shown in Figure 10, the semiconductor layer 6 is formed by polishing and thinning the semiconductor layer 60. Specifically, the main surface 60a of the semiconductor layer 60 is polished until the thickness of the semiconductor layer 60 is, for example, several tens of micrometers. In this example, the main surface 60a is polished so that the thickness of the thinned semiconductor layer 60 (semiconductor layer 6) is 10 μm or less (2 to 3 μm in this example).

[0085] Next, a textured structure 6c having an uneven shape is formed on the surface of the semiconductor layer 6. As shown in Figure 11, the textured structure 6c is formed on the main surface 6a of the semiconductor layer 6 opposite to the insulating layer 5. In this example, the textured structure 6c is formed by etching the main surface 6a. The etching may be wet etching using a liquid etchant.

[0086] Next, as shown in Figure 3, the insulating layer 7, metal wiring 8, and lens portion 9 are formed. First, the insulating layer 5 and a portion of the semiconductor layer 6 are removed, and the metal wiring 8 is formed in the removed portion. Next, the insulating layer 7 is formed to cover the texture structure 6c and the metal wiring 8. Then, multiple lens portions 9 are placed on the insulating layer 7. Through the above process, the photodetector element 1 is manufactured. [Mechanism of Action and Effects]

[0087] In the photodetector element 1, trenches 40 are formed in the semiconductor layer 3, extending to separate multiple semiconductor regions 34 from each other. This prevents secondary photons of charge carriers multiplied in the avalanche photodiode APD from passing through the semiconductor region 34 to adjacent avalanche photodiode APDs. The photodetector element 1 is also formed on the main surface 3a so as to extend along the trenches 40 and includes metal wiring 8 located inside the layer structure 200. The thickness T of the metal wiring 8 is greater than the distance D1 from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200, and greater than the distance D2 from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200. Furthermore, in the Z-axis direction, the surface 8a of the metal wiring 8 is located further from the main surface 3a than the main surface 5a of the insulating layer 5. In other words, because the thickness T of the metal wiring 8 relative to the layer structure 200 is large, the metal wiring 8 can prevent secondary photons from passing through the layer structure 200 and entering adjacent avalanche photodiodes APDs. Furthermore, in the photodetector element 1, the semiconductor layer 3 is located closer to the main surface 3a than the plurality of semiconductor regions 31 and has a plurality of first conductivity type semiconductor regions 34 having a higher impurity concentration than the plurality of semiconductor regions 31. This allows an accumulation effect to be obtained through the impurity concentration gradient, thereby improving detection accuracy. In addition, the photodetector element 1 is equipped with a plurality of quenching elements 13 electrically connected to the plurality of semiconductor regions 32. This allows the photodetector element 1 to operate stably in Geiger mode. Therefore, the decrease in detection accuracy can be suppressed with the photodetector element 1.

[0088] The layer structure 200 has an insulating layer 5 formed on the main surface 3a and an insulating layer 7 formed on the insulating layer 5. The metal wiring 8 is located inside the insulating layer 5 and the insulating layer 7. This allows, for example, the insulating layer 5 and the insulating layer 7 to be formed from different materials, enabling the design of a photodetector 1 according to the required performance. Furthermore, the metal wiring 8 prevents secondary photons of charge carriers multiplied in the avalanche photodiode APD from being incident on adjacent avalanche photodiode APDs via the insulating layer 5 and the insulating layer 7. In other words, the metal wiring 8 can further prevent crosstalk and further suppress the decrease in detection accuracy.

[0089] The side surface 8c of the metal wiring 8 is in contact with the insulating layer 5 and the insulating layer 7. This further prevents crosstalk by the metal wiring 8 and further suppresses the decrease in detection accuracy.

[0090] The photodetector 1 includes a lens portion 9 arranged on the layer structure 200. This allows the light incident on the photodetector 1 to be efficiently focused onto the avalanche photodiode APD by the lens portion 9, thereby improving detection accuracy.

[0091] The thickness T of the metal wiring 8 is greater than the distance D3 from the surface 9b of the lens portion 9 to the surface 8a of the metal wiring 8. As a result, the large thickness T of the metal wiring 8 further prevents crosstalk, and the decrease in detection accuracy can be further suppressed.

[0092] The light detection element 1 is equipped with multiple lens sections 9. Each of the multiple lens sections 9 is positioned to overlap with the corresponding avalanche photodiode APD in the Z-axis direction. When viewed from the Z-axis direction, the outer edge 9c of each of the multiple lens sections 9 overlaps with the trench 40. As a result, light that would otherwise be traveling towards the trench 40 (dead area) can be focused onto the avalanche photodiode APD by the lens sections 9. Therefore, detection accuracy can be improved.

[0093] When viewed from the Z-axis direction, the metal wiring 8 is formed to cover the entire trench 40. When viewed from the Z-axis direction, each of the multiple avalanche photodiodes (APDs) is surrounded by the metal wiring 8. This allows the metal wiring 8 to further suppress crosstalk and improve detection accuracy. [Differentiation]

[0094] The present invention is not limited to the embodiments described above. Modifications of the embodiments described above will be described below. In the following description, the differences from the embodiments described above will be mainly explained, and commonalities may be omitted.

[0095] For example, as shown in Figure 12, the frame region 36 may be formed to extend from the main surface 3b of the semiconductor layer 3 to the semiconductor region 37 in the Z-axis direction. In this example, the frame region 36 is formed to penetrate the semiconductor region 35 in the Z-axis direction. The frame region 36 is directly connected to the semiconductor region 37 without going through the semiconductor region 35. By forming the frame region 36 to extend to (connect to) the semiconductor region 37 in this way, the resistance between the frame region 36 and the semiconductor region 37 is reduced, and the potential gradient, voltage drop, and heat generation when a bias is applied to the avalanche photodiode APD via the frame region 36 and the semiconductor region 37 are suppressed. Therefore, the decrease in detection accuracy can be further suppressed.

[0096] As shown in Figure 12, the quenching element 13 may be located between the semiconductor layer 3 and the counter electrode layer 15 in the Z-axis direction. That is, the positions of the quenching element 13 and the counter electrode layer 15 in the Z-axis direction may be reversed compared to the first embodiment described above. As shown in Figure 12, when viewed from the Z-axis direction, at least a portion of the outer edge 15a of the counter electrode layer 15 may be located outside the outer edge 32a of the semiconductor region 32.

[0097] As shown in Figures 13 and 14, the layer structure 200 does not necessarily have a semiconductor layer 6. In this example, the layer structure 200 is composed of an insulating layer 5 and an insulating layer 7. That is, the layer structure 200 does not have a layer on which the texture structure 6c is formed. The insulating layer 7 is formed on the main surface 3a of the semiconductor layer 3 via the insulating layer 5. The insulating layer 7 is formed directly on the insulating layer 5. The insulating layer 7 is in contact with the main surface 5a of the insulating layer 5. In this example, the insulating layer 5 and the insulating layer 7 are formed of different materials, and an interface exists between the insulating layer 5 and the insulating layer 7.

[0098] The metal wiring 8 is located inside the insulating layer 5 and the insulating layer 7. The main body portion 81 of the metal wiring 8 is located inside the insulating layer 5 and the insulating layer 7, and the contact portion 82 of the metal wiring 8 is located inside the insulating layer 5. As shown in Figure 14, the thickness T of the metal wiring 8 is greater than the distance D1 from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200 (the main surface 7a of the insulating layer 7). The thickness T is greater than the distance D2 from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200 (the main surface 5b of the insulating layer 5). The thickness T is greater than the sum of the distances D1 and D2. The thickness T is greater than the distance D3 from the surface 9b to the surface 8a of the lens portion 9. In the photodetector element 1 according to this modified example, the thickness T of the metal wiring 8 is large, and for the reasons described above, a decrease in detection accuracy can be suppressed.

[0099] As shown in Figure 15, the main body 81 of the metal wiring 8 may be located inside the insulating layer 7, rather than inside the insulating layer 5. That is, the main body 81 may be formed on the main surface 5a of the insulating layer 5 such that the entire main body 81 is exposed from the insulating layer 5. In this example as well, the thickness T of the metal wiring 8 is greater than the distance D1 from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200 (the main surface 7a of the insulating layer 7). The thickness T is greater than the distance D2 from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200 (the main surface 5b of the insulating layer 5). The thickness T is greater than the distance D3 from the surface 9b of the lens portion 9 to the surface 8a. In the photodetector element 1 according to this modified example, the thickness T of the metal wiring 8 is large, and for the reasons described above, a decrease in detection accuracy can be suppressed.

[0100] As shown in Figure 16, the metal wiring 8 may further have wall portions 83. The wall portions 83 are formed on the surface 81b of the main body portion 81. The wall portions 83 are integrally formed with the main body portion 81. When viewed from the Z-axis direction, the wall portions 83 extend continuously along the main body portion 81. In this example, the wall portions 83 are formed in a mesh-like pattern when viewed from the Z-axis direction. Through holes 5d are formed in the insulating layer 5, and through holes 11a are formed in the insulating film 11. Each of the through holes 5d and 11a has a shape that allows the wall portions 83 to be placed. That is, each of the through holes 5d and 11a is formed continuously along the main body portion 81 when viewed from the Z-axis direction. The wall portions 83 are located inside the through holes 5d and 11a. The wall portions 83 are in contact with the metal portion 10. According to this modified example, the wall portions 83 can further prevent crosstalk and further suppress the decrease in detection accuracy. The shape of the wall portion 83 is not limited and may be formed discontinuously (in a spot-like manner) when viewed from the Z-axis direction.

[0101] As shown in Figure 17, the layer structure 200 may be a single insulating layer 201. The metal wiring 8 is located inside the single insulating layer 201. The insulating layer 201 may be formed, for example, by laminating a plurality of insulating layers 202, 203 made of the same material (e.g., SiO2) and integrating them to the extent that no interface remains. The insulating layer 201 has a main surface 201a and a main surface 201b. The main surface 201a is the surface of the insulating layer 201 opposite to the semiconductor layer 3, and the main surface 201b is the surface of the insulating layer 201 on the semiconductor layer 3 side. The main surface 201a constitutes surface 200a of the layer structure 200, and the main surface 201b constitutes surface 200b of the layer structure 200.

[0102] As shown in Figure 17, the thickness T of the metal wiring 8 is greater than the distance D1 from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200 (the main surface 201a of the insulating layer 201). The thickness T is greater than the distance D2 from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200 (the main surface 201b of the insulating layer 201). The thickness T is greater than the distance D3 from the surface 9b of the lens portion 9 to the surface 8a. In this modified example, the thickness T of the metal wiring 8 is also large, and for the reasons mentioned above, a decrease in detection accuracy can be suppressed. Furthermore, in this modified example, since the layer structure 200 is a single insulating layer 201, the photodetector 1 can be constructed with a simpler design.

[0103] In the above embodiment, the quenching element 13 is a passive quenching element composed of a quenching resistor, but the quenching element 13 may also be an active quenching element (circuit) composed of, for example, a transistor. The position of the quenching element 13 is not limited, and the quenching element 13 may be formed inside the insulating layer 21 or on the substrate 2.

[0104] The texture structure 6c formed on the semiconductor layer 6 may have a regular (consistent) uneven shape. The texture structure 6c may be formed, for example, by removing a portion of the semiconductor layer 6 using a photolithography technique with a mask.

[0105] The thickness T of the metal wiring 8 may be less than or equal to the distance D1 from the surface 8a of the metal wiring 8 to the surface 200a of the layer structure 200. The thickness T may be less than or equal to the distance D2 from the surface 8b of the metal wiring 8 to the surface 200b of the layer structure 200. The thickness T may be less than or equal to the distance D3 from the surface 9b of the lens portion 9 to the surface 8a.

[0106] A portion of the layer structure 200 (the insulating layer 5 in the above embodiment) does not necessarily have to be located between the surface 81b of the metal wiring 8 and the trench 40. In this case, the surface 81b may be in direct contact with the insulating film 11 located inside the trench 40, and for example, the insulating layer 5 may be separated into multiple parts. When viewed from the Z-axis direction, the metal wiring 8 does not necessarily have to be formed to cover the entire trench 40. When viewed from the Z-axis direction, the metal wiring 8 may be formed to cover a portion of the trench 40. The metal wiring 8 does not necessarily have to overlap with the trench 40 in the Z-axis direction. That is, when viewed from the Z-axis direction, at least a portion of the trench 40 may be exposed from the metal wiring 8. The shape of the trench 40 is not limited. For example, the frame portion 41 of the trench 40 may be formed in a polygonal frame shape other than a rectangular frame shape when viewed from the Z-axis direction.

[0107] When viewed from the Z-axis direction, the outer edges 9c of each of the multiple lens portions 9 do not necessarily have to overlap with the trench 40. For example, when viewed from the Z-axis direction, the outer edges 9c of each lens portion 9 may be located inside the corresponding frame portion 41.

[0108] When viewed from the Z-axis direction, the size of the counter electrode layer 15 may be less than 50% of the size of the semiconductor region 32. When viewed from the Z-axis direction, the outer edge 15a of the counter electrode layer 15 may be located outside the outer edge 32a of the semiconductor region 32.

[0109] The shape of the frame region 36 is not limited. For example, the frame region 36 may be formed in a polygonal shape other than a rectangular frame when viewed from the Z-axis direction. The frame region 36 may be formed discontinuously when viewed from the Z-axis direction. The width W1 of the frame region 36 may be less than twice the width W2 of region A1, or less than or equal to the width W2. The width W1 may be less than twice the width W3 of region A2, or less than or equal to the width W3.

[0110] In the embodiments and modifications described above, the photodetector 1 may be configured as a SiPM (Silicon Photomultiplier). An example of a SiPM is MPPC (Multi-Pixel Photon Counter) (registered trademark). In the photodetector 1 configured as a SiPM, a plurality of cell units, each containing an avalanche photodiode APD and a quenching element 13, are connected in parallel to each other to form a single channel.

[0111] Referring to Figure 18, an example of a photodetector element 1 configured as SiPM will be described. The electrode layer 23 in this modified example is formed to be larger than the electrode layer 23 in the first embodiment. In this example, when viewed from the Z-axis direction, each electrode layer 23 is formed to overlap with multiple (four in this example) avalanche photodiodes APD. Multiple (four in this example) connecting conductors 22 are connected to one electrode layer 23. As a result, multiple avalanche photodiodes APD are connected in parallel to each other via the electrode layer 23, and the current signals from each avalanche photodiode APD are sent to the substrate 2 in a combined state.

[0112] Referring to Figures 19 and 20, another example of the photodetector element 1 configured as SiPM will be described. Figure 20 is a plan view of the photodetector element 1 as seen from the direction from the substrate 2 toward the semiconductor layer 3. In Figure 20, some components are omitted for the sake of clarity. The photodetector element 1 according to this modified example further comprises a plurality of electrode layers 51, a plurality of connecting conductors 52, a plurality of counter electrode layers 53, a plurality of connecting conductors 54, and a plurality of electrode layers 55. In Figure 20, for the sake of clarity, some components that overlap with the counter electrode layer 53 (parts that cannot be directly seen by the counter electrode layer 53) are also shown with solid lines.

[0113] In this modified example, one end (end 131a) of the quenching element 13 is electrically connected to the semiconductor region 32 via the wiring layer 14, and the other end (end 134b) of the quenching element 13 is electrically connected to the electrode layer 51. When viewed from the Z-axis direction, each corner 135 is formed at a right angle. The shape of the corner 135 is not limited and may be other shapes such as the R-shape shown in Figure 6. The quenching element 13 is not electrically connected to the counter electrode layer 15. In this modified example, the counter electrode layer 15 is a floating electrode that is not electrically connected to other wiring or circuits. In the Z-axis direction, the counter electrode layer 15 is located at the same height (same layer) as the wiring layer 14.

[0114] Multiple electrode layers 51 are located inside the insulating layer 12. The multiple electrode layers 51 are located on the main surface 3b side with respect to the semiconductor layer 3. When viewed from the Z-axis direction, the electrode layers 51 are formed in a rectangular shape. When viewed from the Z-axis direction, the size of the electrode layers 51 is smaller than the size of the counter electrode layers 15. In the Z-axis direction, the electrode layers 51 are located at the same height (in the same layer) as the counter electrode layers 15. When viewed from the Z-axis direction, each electrode layer 51 is positioned so as to be surrounded by multiple (four in this example) counter electrode layers 15. In this example, the ends 134b of four quenching elements 13 are connected to one electrode layer 51. The electrode layers 51 are formed of a metallic material such as aluminum.

[0115] Multiple connecting conductors 52 are formed inside the insulating layer 12. The multiple connecting conductors 52 are located closer to the substrate 2 than the multiple electrode layers 51 in the Z-axis direction. Each connecting conductor 52 is formed in a columnar shape (a rectangular prism in this example) with a central axis along the Z-axis direction. Each connecting conductor 52 is electrically connected to the corresponding electrode layer 51 and the counter electrode layer 53. The connecting conductors 52 are formed from a metallic material such as copper.

[0116] The multiple counter electrode layers 53 are located inside the insulating layer 12. The multiple counter electrode layers 53 are located on the main surface 3b side with respect to the semiconductor layer 3. In the Z-axis direction, the multiple counter electrode layers 53 are located closer to the substrate 2 than the quenching element 13 and the connecting conductor 52. Each of the multiple counter electrode layers 53 is electrically connected to the corresponding connecting conductor 52 and connecting conductor 16.

[0117] The counter electrode layer 53 is formed in a substantially rectangular plate shape. When viewed from the Z-axis direction, each corner of the counter electrode layer 53 has an R-shape (round shape) and is curved so as to be convex outwards. The counter electrode layer 53 faces multiple (four in this example) semiconductor regions 32 in the Z-axis direction. The counter electrode layer 53 overlaps with multiple semiconductor regions 32 in the Z-axis direction. When viewed from the Z-axis direction, the outer edge 53a of the counter electrode layer 53 is located outside the outer edges 32a of the multiple opposing semiconductor regions 32. The counter electrode layer 53 is formed of a metallic material such as aluminum.

[0118] Multiple connecting conductors 54 are formed inside the insulating layer 12. The multiple connecting conductors 54 are located closer to the substrate 2 than the multiple electrode layers 17 in the Z-axis direction. Each connecting conductor 54 is formed in a columnar shape with a central axis along the Z-axis direction. Each connecting conductor 54 is electrically connected to the corresponding electrode layer 17 and electrode layer 55. The connecting conductors 54 are made of a metallic material such as copper.

[0119] The multiple electrode layers 55 are located inside the insulating layer 12. The multiple electrode layers 55 are located on the main surface 3b side relative to the semiconductor layer 3. In the Z-axis direction, the multiple electrode layers 55 are located closer to the substrate 2 than the multiple connecting conductors 54. In the Z-axis direction, the electrode layers 55 are located at the same height (in the same layer) as the opposing electrode layer 53. Each electrode layer 55 is electrically connected to the corresponding connecting conductor 54 and connecting conductor 18. The electrode layers 55 are formed of a metallic material such as aluminum.

[0120] In the photodetector element 1 according to this modified example, multiple avalanche photodiodes (APDs) are connected in parallel to each other via an electrode layer 51, and the current signals from each avalanche photodiode (APD) are combined and sent to the substrate 2.

[0121] In the embodiments and modifications described above, the quenching element 13, the counter electrode layer 15, and the semiconductor region 32 may have the configuration shown in Figure 21. In Figure 21, for the sake of explanation, some components other than the quenching element 13, the counter electrode layer 15, the semiconductor region 32, and the trench 40 are not shown.

[0122] When viewed from the Z-axis direction, the outer edge 15a of the counter electrode layer 15 is located outside the outer edge 32a of the semiconductor region 32. The outer edge 15a being located outside the outer edge 32a means that more than 50% of the outer edge 15a is located outside the outer edge 32a. In this example, the outer edge 15a is located outside the outer edge 32a, except for the portion where the notch 153 is formed.

[0123] Compared to the embodiments described above (for example, the example shown in Figure 6), the outer edge 15a of the counter electrode layer 15 is located near the inner edge 13b of the quenching element 13. When viewed from the Z-axis direction, the outer edge 15a may overlap with the inner edge 13b. That is, there does not need to be a gap between the outer edge 15a and the inner edge 13b. When viewed from the Z-axis direction, the outer edge 15a may be located outside the inner edge 13b and overlap with the quenching element 13. When the outer edge 15a overlaps with the inner edge 13b or is located outside the inner edge 13b, it means that 50% or more of the outer edge 15a overlaps with the inner edge 13b or is located outside the inner edge 13b.

[0124] Compared to the embodiments described above (for example, the example shown in Figure 6), the outer edge 13a of the quenching element 13 is located near the inner edge 41a of the frame portion 41 (trench 40). When viewed from the Z-axis direction, the outer edge 13a may overlap with the inner edge 41a. That is, there does not have to be a gap between the outer edge 13a and the inner edge 41a. When viewed from the Z-axis direction, the outer edge 13a may be located outside the inner edge 41a and overlap with the frame portion 41. When the outer edge 13a overlaps with the inner edge 41a or is located outside the inner edge 41a, it means that 50% or more of the outer edge 13a overlaps with the inner edge 41a or is located outside the inner edge 41a.

[0125] In the example shown in Figure 21, when viewed from the Z-axis direction, the distance between the outer edge 13a of the quenching element 13 (the portion of the outer edge 13a that follows the inner edge 41a of the frame portion 41) and the inner edge 41a of the frame portion 41 is smaller than the distance between the outer edge 32a of the semiconductor region 32 and the inner edge 13b of the quenching element 13 (the portion of the inner edge 13b that follows the outer edge 32a). When viewed from the Z-axis direction, the distance between the inner edge 13b of the quenching element 13 (the portion of the inner edge 13b that follows the outer edge 15a of the counter electrode layer 15) and the outer edge 15a of the counter electrode layer 15 is smaller than the distance between the outer edge 32a of the semiconductor region 32 and the outer edge 15a of the counter electrode layer 15 (the portion of the outer edge 15a that follows the outer edge 32a).

[0126] In this modified example, when viewed from the Z-axis direction, the outer edge 15a of the counter electrode layer 15 is located outside the outer edge 32a of the semiconductor region 32. Also, when viewed from the Z-axis direction, the distance between the inner edge 13b of the quenching element 13 and the outer edge 15a of the counter electrode layer 15 is smaller than the distance between the outer edge 32a of the semiconductor region 32 and the outer edge 15a of the counter electrode layer 15. As a result, the area of ​​the counter electrode layer 15 is increased, and the light that has passed through the semiconductor layer 3 can be reflected more reliably toward the semiconductor region 32 (the amount of reflected light can be increased).

[0127] In this modified example, when viewed from the Z-axis direction, the distance between the outer edge 13a of the quenching element 13 and the inner edge 41a of the frame portion 41 is smaller than the distance between the outer edge 32a of the semiconductor region 32 and the inner edge 13b of the quenching element 13. As a result, when viewed from the Z-axis direction, the quenching element 13 is formed further outward, allowing the quenching element 13 to be formed longer, and thus improving (shortening) the recovery time even when the pitch between multiple cell units (pixels) including the avalanche photodiode APD is small. [Explanation of Symbols]

[0128] 1...Photodetector element, 3...Semiconductor layer (first semiconductor layer), 3a...Main surface (first main surface), 3b...Main surface (second main surface), 5...Insulating layer (first insulating layer), 7...Insulating layer (second insulating layer), 8...Metal wiring, 8a...Surface (first surface), 8b...Surface (second surface), 8c...Side surface, 9...Lens part, 9c...Outer edge, 201...Insulating layer, 13...Quenching element, 40...Trench, 200...Layer structure, 200a, 200b...Surface, APD...Avalanche photodiode.

Claims

1. A first semiconductor layer having a first main surface which is the light incident surface, and a second main surface opposite to the first main surface, A layer structure formed on the first main surface, Metal wiring formed on the first main surface, with at least a portion located inside the layer structure, The first semiconductor layer comprises a plurality of quenching elements located on the second main surface side, The first semiconductor layer is Multiple first semiconductor regions of the first conductivity type, A plurality of second semiconductor regions of a second conductivity type, located closer to the second main surface than the plurality of first semiconductor regions, and together with the plurality of first semiconductor regions, constitute a plurality of avalanche photodiodes, The plurality of third semiconductor regions of the first conductivity type are located closer to the first main surface than the plurality of first semiconductor regions and have an impurity concentration higher than the impurity concentration of the plurality of first semiconductor regions, Each of the plurality of quenching elements is electrically connected to a corresponding second semiconductor region among the plurality of second semiconductor regions. The first semiconductor layer has trenches formed in it that extend to separate the plurality of third semiconductor regions from each other. The metal wiring is formed on the first main surface so as to extend along the trench and electrically connects the plurality of third semiconductor regions to one another. The thickness of the metal wiring is greater than the distance from the first surface of the metal wiring opposite to the first main surface to the surface of the layer structure opposite to the first main surface, and greater than the distance from the second surface of the metal wiring on the first main surface side to the surface of the layer structure on the first main surface side. Light detection element.

2. The layer structure comprises a first insulating layer formed on the first main surface and a second insulating layer formed on the first insulating layer. The metal wiring is located inside the first insulating layer and the second insulating layer. The photodetector according to claim 1.

3. The side surface of the metal wiring is in contact with the first insulating layer and the second insulating layer. The photodetector according to claim 2.

4. The aforementioned layer structure is a single insulating layer. The photodetector according to claim 1.

5. The layer structure further comprises a lens portion disposed on the aforementioned layer structure. The photodetector according to any one of claims 1 to 4.

6. The thickness of the metal wiring is greater than the distance from the first main surface side surface to the first surface in the lens portion. The photodetector according to claim 5.

7. It further comprises a plurality of lens parts, each of which is the aforementioned lens part, Each of the plurality of lens portions is arranged so as to overlap with a corresponding avalanche photodiode among the plurality of avalanche photodiodes in a direction perpendicular to the first main surface. When viewed from a direction perpendicular to the first main surface, the outer edges of each of the plurality of lens portions overlap with the trench. The photodetector according to claim 5.

8. When viewed from a direction perpendicular to the first main surface, the metal wiring is formed to cover the entire trench. When viewed from a direction perpendicular to the first main surface, each of the plurality of avalanche photodiodes is surrounded by the metal wiring. The photodetector according to any one of claims 1 to 4.

9. A first semiconductor layer having a first main surface which is the light incident surface, and a second main surface opposite to the first main surface, A layer structure having a first insulating layer formed on the first main surface and a second insulating layer formed on the first insulating layer, Metal wiring formed on the first main surface, with at least a portion located inside the layer structure, The first semiconductor layer comprises a plurality of quenching elements located on the second main surface side, The first semiconductor layer is Multiple first semiconductor regions of the first conductivity type, A plurality of second semiconductor regions of a second conductivity type, located closer to the second main surface than the plurality of first semiconductor regions, and together with the plurality of first semiconductor regions, constitute a plurality of avalanche photodiodes, The plurality of third semiconductor regions of the first conductivity type are located closer to the first main surface than the plurality of first semiconductor regions and have an impurity concentration higher than the impurity concentration of the plurality of first semiconductor regions, Each of the plurality of quenching elements is electrically connected to a corresponding second semiconductor region among the plurality of second semiconductor regions. The first semiconductor layer has trenches formed in it that extend to separate the plurality of third semiconductor regions from each other. The metal wiring is formed on the first main surface so as to extend along the trench and electrically connects the plurality of third semiconductor regions to one another. In a direction perpendicular to the first main surface, the surface of the metal wiring opposite to the first main surface is located further from the first main surface than the surface of the first insulating layer opposite to the first semiconductor layer. Light detection element.

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