Light-detecting device and system

Abstract

Light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to a cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and a control circuit coupled to an output of the first circuit and configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit.

Description

Technical field

[0001] The present technology relates to a light-detecting device. Specifically, the present technology relates to the light-detecting device and the system for measuring the distance to an object. Background technology

[0002] In the past, distance measurement methods known as time-of-flight (ToF) were used for electronic devices with distance measurement capabilities. ToF is a method for measuring distance by causing the electronic device to emit irradiated light towards an object and calculating the orbital time between the emission of the irradiated light and the return of the reflected irradiated light to the electronic device. In many cases, a single-photon avalanche diode (SPAD) is used as the photoelectric conversion element when the reflected light corresponding to the irradiated light is detected. However, when using a SPAD, an excess bias sometimes varies depending on the temperature. The excess bias is a value obtained by subtracting the breakdown voltage from the voltage between an anode and a cathode.Therefore, there is a possibility that the bias voltage becomes too low and the sensitivity of a photodiode decreases, and conversely, that the bias voltage becomes too high and dark current noise increases. Accordingly, solid-state image sensors were provided that monitor the electrical cathode potentials of the SPADs when a photocurrent flows and reduce the electrical anode potentials of the SPADs when the electrical cathode potentials increase. List of citations from patent literature

[0003] PTL 1: Published Japanese patent application JP 2019 075394 A

[0004] Examples of light-detecting devices are known from US 5 548 112 A, US 2010 / 0 301 194 A1 and US 2018 / 0 0180 471 A1. Summary Technical Problem

[0005] The related technology described above controls the electrical anode potentials to suppress variations in the overbias caused by temperature changes. However, a monitoring voltage (cathode voltage) used to control the electrical anode potentials follows the temperature-induced variation in the overbias, and the monitoring voltage also varies depending on whether the amount of incident light decreases or increases. Although the solid-state image sensor described above allows for the suppression of variations in the overbias caused by temperature changes, such a sensor suffers from variations in the overbias caused by variations in the monitoring voltage depending on whether the amount of incident light decreases or increases.

[0006] It is desirable to suppress a variation in the over-bias that depends on a decrease or increase in the amount of incident light by using a solid-state image sensor that controls either an electrical anode potential or an electrical cathode potential of a photoelectric conversion element based on another of the electrical anode potential and the electrical cathode potential. Solution to the problem

[0007] According to a first embodiment of the present technology, a solid-state image sensor is provided comprising: a photoelectric conversion element containing an anode and a cathode, wherein either the anode or the cathode is connected to a predetermined node; an element for providing an electrical potential, configured to provide a first electrical potential to the predetermined node; a time-detection circuit configured to detect a time at which a predetermined time interval has elapsed since the start of an increase or decrease in an electrical potential of the predetermined node from the first electrical potential;A sample-and-hold circuit configured to detect the electrical potential of a predetermined node based on an output from the time-detection circuit and to hold this electrical potential as a second electrical potential; and a control section configured to control the electrical potential of another of the anode and cathode based on this second electrical potential. This makes it possible to suppress variations in the over-bias.

[0008] Furthermore, according to the first embodiment, the time-detection circuit can include an inverter configured to invert a signal of the electrical potential of the predetermined node and output the inverted signal. This makes it possible to detect a time based on the inverted signal.

[0009] According to the first embodiment, the time-detection circuit can further include a pulse signal generation circuit configured to generate a pulse signal based on a signal obtained by delaying the inverted signal by a predetermined delay time, and the sample-and-hold circuit can detect the electrical potential of the predetermined node within a time interval equal to the pulse width of the pulse signal. This makes it possible to sample an electrical cathode potential using the pulse signal.

[0010] According to the first embodiment, the time-detection circuit can further include a delay circuit configured to delay the inverted signal by a predetermined delay time and output a delayed signal. The sample-and-hold circuit can detect the electrical potential of the predetermined node when the delayed signal is one of two different values ​​and hold the detected electrical potential when the delayed signal is the other of the two values. This allows an electrical cathode potential to be sampled using the delayed signal.

[0011] According to the first embodiment, the photoelectric conversion element, the time-detection circuit, and the sampling and holding circuit can also be installed in a pixel, the installation being carried out with respect to a plurality of pixels, and the control section can include an interpixel average detection section configured to calculate an average of the respective second electrical potentials of the plurality of pixels as an interpixel average, a time-average detection section configured to calculate a time average of the interpixel average, and an electrical potential control section configured to control the electrical potential of the other anode and cathode in such a way that the electrical potential decreases as the time average increases.This makes it possible to suppress negative influences caused by a variation in electrical potential.

[0012] Furthermore, according to the first embodiment, the time-average acquisition section can include an analog filter configured to generate the time average. This makes it possible to obtain the time average using an analog circuit.

[0013] According to the first embodiment, the time-averaged acquisition section can also include a digital filter configured to generate the time average. This makes it possible to reduce the size of a footprint.

[0014] According to the first embodiment, the section for controlling an electrical potential can also include an amplifier configured to compare the time average with a predetermined electrical potential of a power source and output the result of the comparison to the anode and cathode. This makes it possible to control electrical potentials using an analog circuit.

[0015] Furthermore, according to the first embodiment, the section for controlling an electrical potential can include a power semiconductor configured to control the electrical potential of the anode and cathode in such a way that the electrical potential decreases as the time average increases. This makes it possible to reduce the size of a footprint.

[0016] According to the first embodiment, the section for capturing an interpixel average can also include a capacitor and a plurality of resistors connected in parallel between the plurality of pixels and the capacitor. This makes it possible to obtain an interpixel average using an analog circuit.

[0017] According to the first embodiment, the section for capturing an interpixel average can also include an analog-to-digital conversion section configured to convert the second electrical potentials into digital signals, and an averaging filter configured to calculate an average of the digital signals as the interpixel average. This makes it possible to reduce the size of a footprint.

[0018] According to the first embodiment, the analog-to-digital conversion section can also include a plurality of analog-to-digital converters configured to convert the second electrical potentials of the pixels, which are distinct from one another, into digital signals. This makes it possible to convert the plurality of second electrical potentials into digital signals simultaneously.

[0019] According to the first embodiment, the analog-to-digital conversion section can also include a selector configured to select any of the respective second electrical potentials of the plurality of pixels, and an analog-to-digital converter configured to convert the selected second electrical potential into the digital signal. This makes it possible to reduce the number of analog-to-digital converters.

[0020] According to the first embodiment, the solid-state image sensor can also include an output-side buffer located between the scanning and holding circuit and the control section. This makes it possible to output the second electrical potential via the output-side buffer.

[0021] According to the first embodiment, the output buffer can also generate a differential signal based on the second electrical potential and output the generated differential signal. This makes it possible to obtain a more accurate output value.

[0022] According to the first embodiment, the solid-state image sensor can furthermore include an input-side buffer arranged between the predetermined node and the scan-and-hold circuit. This allows both the monitoring pixels and the imaging pixels to have the same breakdown voltage (VBD).

[0023] Furthermore, according to the first embodiment, the input buffer can generate a differential signal based on the second electrical potential and output the generated differential signal. This makes it possible to obtain a more accurate output value.

[0024] According to the first embodiment, the photoelectric conversion element and the element for providing an electrical potential can also be installed around the imaging pixel circuit in both an imaging pixel circuit and a monitoring pixel circuit, and the time-detection circuit and the sampling and holding circuit can be installed in the monitoring pixel circuit. This makes it possible to control an electrical potential of an anode or a cathode based on the electrical potential held by the monitoring pixel circuit.

[0025] According to the first embodiment, the cathode can also be connected to the predetermined node, and the control section can control an electrical potential of the anode. This makes it possible to control an electrical anode potential as a response to an electrical cathode potential.

[0026] According to the first embodiment, the anode can also be connected to the predetermined node, and the control section can control an electrical potential of the cathode. This makes it possible to control an electrical cathode potential in response to an electrical anode potential.

[0027] According to a second embodiment of the present technology, a distance measurement system is further provided, comprising: a light emission section configured to provide irradiation light; and a solid-state image sensor comprising a photoelectric conversion element containing an anode and a cathode, wherein either the anode or the cathode is connected to a predetermined node; an element for providing an electrical potential configured to provide a first electrical potential to the predetermined node; a time-detection circuit configured to detect a time at which a predetermined time interval has elapsed since the start of an increase or decrease in an electrical potential of the predetermined node from the first electrical potential; and a sample-and-hold circuit configured toThe circuit consists of: sensing the electrical potential of a predetermined node based on an output from the time-detection circuit and holding this electrical potential as a second electrical potential; a control section configured to control the electrical potential of another anode and cathode based on this second electrical potential; and a distance measurement section configured to measure a distance based on the cycle time between the emission time of an irradiated light and the reception time of the reflected light corresponding to the irradiated light. This makes it possible to suppress variation in over-bias and improve distance measurement accuracy.

[0028] According to one embodiment of the present technology, a light-detecting device comprises a first pixel circuit arrangement containing a first avalanche photodiode, and a second pixel circuit arrangement comprising a second avalanche photodiode, a first delay circuit having an input coupled to a cathode of the second avalanche photodiode, and a first circuit having a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit. The light-detecting device includes a control circuit coupled to an output of the first circuit and configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit.The control circuit is configured to control the potential of an anode of the second avalanche photodiode based on the output of the first circuit. The light-detecting device further includes a third pixel circuit arrangement comprising a third avalanche photodiode, a second delay circuit having an input coupled to a potential of a cathode of the third avalanche photodiode, and a second circuit having a third input coupled to the cathode of the third avalanche photodiode and a fourth input coupled to an output of the second delay circuit. The control circuit includes an averaging circuit coupled to the output of the first circuit and an output of the second circuit, configured to calculate an average value of the outputs of the first and second circuits.The control circuit averages these signals to output an interpixel average signal. It includes a time-average circuit with an input coupled to an output of the average circuit and is configured to output a time-averaged signal based on the interpixel average signal. The control circuit also includes a potential controller coupled to the anode of the first avalanche photodiode. This potential controller is configured to lower the potential of the first avalanche photodiode's anode when the time-averaged signal increases and to increase the potential of the first avalanche photodiode's anode when the time-averaged signal decreases.The control circuit contains an analog-to-digital converter configured to convert the time-averaged signal into a digital signal, and the potential controller contains power electronics configured to control the potential of the anode of the first avalanche photodiode based on the digital signal. The averaging circuit contains a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit. The first circuit contains a hold circuit, which includes a switch and a capacitor. The first circuit contains a first buffer circuit and a second buffer circuit.The first buffer circuit is coupled between the cathode of the second avalanche photodiode and the hold circuit, and the hold circuit is coupled between the first buffer circuit and the second buffer circuit. The first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode to output a first pair of differential signals containing a first positive signal and a first negative signal. The hold circuit is configured to output the first positive signal according to the first delay signal, and the second buffer circuit is configured to buffer the first negative signal and the first positive signal to output a second pair of differential signals containing a second positive signal and a second negative signal.The control circuit includes an averaging circuit containing an analog-to-digital converter (ADC) with a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive and second negative signals. The control circuit includes a first capacitor coupled to the first input of the ADC and a second capacitor coupled to the second input of the ADC. The first buffer circuit includes a first current source and a first transistor coupled to the first current source, and a second current source and a second transistor coupled to the second current source.The first transistor is coupled to a node configured to receive the cathode potential of the second avalanche photodiode and is configured to output the first positive signal according to a current from the first current source. The second transistor is coupled to a node configured to receive a ground signal and is configured to output the first negative signal according to a current from the second current source. The second buffer circuit includes a third current source and a third transistor coupled to the third current source, and a fourth current source and a fourth transistor coupled to the fourth current source.The third transistor is configured to receive the first positive signal and output the second positive signal according to a current from the third current source, and the fourth transistor is configured to receive the first negative signal and output the second negative signal according to a current from the fourth current source.According to one embodiment of the present technology, a light-detecting device comprises a first pixel circuit arrangement containing a first avalanche photodiode, and a second pixel circuit arrangement comprising a second avalanche photodiode, a first delay circuit configured to generate a first delay signal based on a first potential of a cathode of the second avalanche photodiode, and a first circuit configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal. The light-detecting device includes a control circuit configured to control a potential of an anode of the first avalanche photodiode based on the sampled second potential output by the first circuit.According to one embodiment of the present technology, a system comprises a light source and a light-detecting device, the latter including a first pixel circuit assembly comprising a first avalanche photodiode, a second pixel circuit assembly comprising a second avalanche photodiode, a first delay circuit having an input coupled to the cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit. The system includes a control circuit coupled to an output of the first circuit and configured to control the potential of an anode of the first avalanche photodiode based on the output of the first circuit.According to one embodiment of the present technology, a light-detecting device comprises a first pixel circuit arrangement containing a first avalanche photodiode, and a second pixel circuit arrangement comprising a second avalanche photodiode, a first delay circuit having an input coupled to an anode of the second avalanche photodiode, and a first circuit having a first input coupled to the anode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit, and a control circuit coupled to an output of the first circuit and configured to control a potential of a cathode of the first avalanche photodiode based on the output of the first circuit. Advantageous effects of the invention

[0029] The monitoring pixel detects a point in time at which a predetermined time interval has elapsed since a decrease in the electrical cathode potential, and captures and maintains the electrical cathode potential at that time. This makes it possible to maintain the electrical potential independently of the amount of light. It is possible to suppress any variation in bias voltage resulting from a decrease or increase in the amount of light if the control section regulates an electrical anode potential in response to the holding potential. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a block diagram illustrating a configuration example of a distance measurement module according to a first embodiment of the present technology. [ Fig. 2] Fig. Figure 2 is a diagram illustrating an example of a stacked structure of a solid-state image sensor according to the first embodiment of the present technology. [ Fig. 3] Fig. Figure 3 is a top view illustrating a configuration example of a pixel chip according to the first embodiment of the present technology. [ Fig. 4] Fig. Figure 4 is a block diagram illustrating a configuration example of a circuit chip according to the first embodiment of the present technology. [ Fig. 5] Fig. Figure 5 is a block diagram illustrating a configuration example of a circuit block according to the first embodiment of the present technology. [ Fig. 6] Fig. Figure 6 is a block diagram illustrating a configuration example of a monitoring pixel according to the first embodiment of the present technology. [ Fig. 7] Fig. Figure 7 is a circuit diagram illustrating the configuration example of the monitoring pixel according to the first embodiment of the present technology. [ Fig. 8] Fig. Figure 8 is a circuit diagram illustrating a configuration example of a pulse generation circuit according to the first embodiment of the present technology. [ Fig. 9] Fig. Figure 9 is a timing diagram illustrating an example of the operation of the pulse generation circuit according to the first embodiment of the present technology. [ Fig. 10] Fig. Figure 10 is a circuit diagram illustrating a configuration example of an imaging pixel according to the first embodiment of the present technology. [ Fig. 11] Fig. Figure 11 is a top view illustrating a configuration example of a pixel array section according to the first embodiment of the present technology. [ Fig. 12] Fig. Figure 12 is a block diagram illustrating a configuration example of the monitoring pixels, the imaging pixels and a control section according to the first embodiment of the present technology. [ Fig. 13] Fig. Figure 13 is a circuit diagram illustrating a configuration example of the control section according to the first embodiment of the present technology. [ Fig. 14] Fig. Figure 14 is a diagram illustrating an example of a variation in an electrical cathode potential and an electrical anode potential according to the first embodiment of the present technology. [ Fig. 15A] Fig. Figure 15A is a diagram illustrating an example of a variation of the over-bias voltage VEX and an electrical anode potential VSPAD according to the first embodiment. [ Fig. 15B] Fig. Figure 15B is a diagram illustrating an example of a variation of the over-bias voltage VEX according to the comparison example in which the electrical anode potential VSPAD is not controlled. [ Fig. 16A] Fig. Figure 16A is a time-lapse diagram illustrating a variation in the electrical cathode potential Vs obtained in the case of a relatively small amount of light. [ Fig. 16B] Fig. Figure 16B is a time-lapse diagram illustrating a variation in the electrical cathode potential Vs obtained in the case of a relatively large amount of light. [ Fig. 17A] Fig. Figure 17A is a time-lapse diagram illustrating an example of fluctuations in the bottom electric potential (VBT) obtained in the case of low light levels. [ Fig. 17B] Fig. Figure 17B is a time-lapse diagram illustrating an example of fluctuations in the lower electric potential VBT obtained in the case of large amounts of light. [ Fig. 18] Fig. Figure 18 is a scatter plot illustrating an example of a range of variation of the breakdown voltage according to the first embodiment of the present technology. [ Fig. 19] Fig. Figure 19 is a time sequence diagram illustrating an example of the operation of the monitoring pixel and the control section according to the first embodiment of the present technology. [ Fig. 20] Fig. Figure 20 is a flowchart illustrating an example of the operation of the solid-state image sensor according to the first embodiment of the present technology. [ Fig. 21] Fig. Figure 21 is a block diagram illustrating a configuration example of a monitoring pixel according to a first modification of the first embodiment of the present technology. [ Fig. 22] Fig. Figure 22 is a block diagram illustrating a configuration example of a control section according to a second modification of the first embodiment of the present technology. [ Fig. 23] Fig. Figure 23 is a block diagram illustrating a configuration example of a section for capturing an intermediate pixel average according to a third modification of the first embodiment of the present technology. [ Fig. 24] Fig. Figure 24 is a block diagram illustrating a configuration example of a control section according to a fourth modification of the first embodiment of the present technology. [ Fig. 25] Fig. Figure 25 is a block diagram illustrating a configuration example of a control section according to a fifth modification of the first embodiment of the present technology. [ Fig. 26] Fig. Figure 26 is a circuit diagram illustrating a configuration example of a monitoring pixel according to a sixth modification of the first embodiment of the present technology. [ Fig. 27] Fig. Figure 27 is a circuit diagram illustrating a configuration example of a section for capturing an interpixel average according to the sixth modification of the first embodiment of the present technology. [ Fig. 28] Fig. Figure 28 is a block diagram illustrating a configuration example of a monitoring pixel according to a second embodiment of the present technology. [ Fig. 29] Fig. Figure 29 is a circuit diagram illustrating the configuration example of the monitoring pixel according to the second embodiment of the present technology. [ Fig. 30] Fig. Figure 30 is a time sequence diagram illustrating an example of the operation of the monitoring pixel and a control section according to the second embodiment of the present technology. [ Fig. 31] Fig. Figure 31 is a circuit diagram illustrating a configuration example of a monitoring pixel according to a modification of the second embodiment of the present technology. [ Fig. 32] Fig. Figure 32 is a circuit diagram illustrating a configuration example of a buffer according to the modification of the second embodiment of the present technology. [ Fig. 33] Fig. Figure 33 is a block diagram that shows an example of a schematic configuration of a vehicle control system. [ Fig. 34] Fig. Figure 34 is a diagram to assist in explaining an example of installation positions of a section for detecting information from outside the vehicle and an imaging section. [Description of embodiments]

[0030] The following describes embodiments for implementing the present technology (hereinafter referred to as embodiments). The description is given in the following order. 1. First embodiment (example, in which an electrical cathode potential is maintained at a detected time) 2. Second embodiment (example in which a buffer is omitted, but an electrical cathode potential of the detected time is maintained) 3. Application examples for a mobile object <Erste Ausführungsform> “Configuration example of a distance measurement module”

[0031] Fig. Figure 1 is a block diagram illustrating a configuration example of a distance measuring module 100 according to a first embodiment of the present technology. The distance measuring module 100 is configured to measure a distance to an object. The distance measuring module 100 includes a light emission section 110, a synchronization control section 120, and a solid-state image sensor (or a light-detecting device) 200. The distance measuring module 100 is installed in a smartphone, a personal computer, a vehicle-mounted device, or the like, and is used to measure a distance.

[0032] The synchronization control section 120 operates the light emission section 110 and the solid-state image sensor 200 synchronously. The synchronization control section 120 provides the light emission section 110 and the solid-state image sensor 200 with a clock signal of a predetermined frequency (such as 10 to 20 MHz) as a synchronization signal CLKp via signal lines 128 and 129.

[0033] The light emission section 110 provides intermittent light as irradiation light synchronized with the synchronization signal CLKp from the synchronization control section 120. For example, near-infrared light is used as the irradiation light.

[0034] The solid-state image sensor 200 is configured to receive reflected light from the incident light source and measures the orbital period between a light emission time, specified by the synchronization signal CLKp, and a light reception time of the reflected light. The solid-state image sensor 200 calculates the distance to an object from this orbital period, generates distance data, and outputs the distance data.

[0035] Note that although the light emission section 110, the solid-state image sensor 200, and the synchronization control section 120 are installed in the same distance measurement module 100, it is also possible to install them in different devices. A system comprising the light emission section 110, the solid-state image sensor 200, and the synchronization control section 120 is an example of a distance measurement system according to an embodiment of the present technology. “Configuration example of a solid-state image sensor”

[0036] Fig. Figure 2 is a diagram illustrating an example of a stacked structure of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 comprises a circuit chip 202 and a pixel chip 201, which is stacked above the circuit chip 202. These chips are electrically connected by a connection section such as a contact hole. Note that these chips can be connected via a copper-copper bond or a contact bump instead of the contact hole.

[0037] Fig. Figure 3 is a top view illustrating a configuration example of the pixel chip 201 according to the first embodiment of the present technology. The pixel chip 201 includes a rectangular light-receiving section 210. In the light-receiving section 210, a plurality of photoelectric conversion elements 211 and a plurality of photoelectric conversion elements 212 are arranged in an array.

[0038] The photoelectric conversion elements 211 are arranged linearly in an array along a boundary of the light-receiving section 210. For example, photoelectric conversion elements 211 are arranged in a line at the upper end of the light-receiving section 210 in an array. On the other hand, the photoelectric conversion elements 212 are arranged in an array in the form of a two-dimensional grid. Among the photoelectric conversion elements 211 and 212, the photoelectric conversion elements 212 are used to generate pixel data from image data. On the other hand, the photoelectric conversion elements 211 are used to monitor the electrical potentials of any of the cathodes and anodes (for example, the electrical potentials of the cathodes).

[0039] Fig. Figure 4 is a block diagram illustrating a configuration example of a circuit chip 202 according to the first embodiment of the present technology. The circuit chip 202 includes a time-time generation section 220, a circuit block 300, a histogram generation section 250, an output interface 260, multiplexers 231 and 232, and time-to-digital converters 241 and 242.

[0040] The timing generation section 220 is configured to generate a control signal RCH synchronously with the synchronization signal CLKp. The timing generation section 220 provides the control signal RCH to the circuit block 300.

[0041] In circuit block 300, (not illustrated) individual pixel circuits of a multitude of monitoring pixels and a multitude of imaging pixels are arranged in an array. Details of the respective circuit configurations of the monitoring pixels and the imaging pixels are described later. The imaging pixel generates a pulse signal in response to the arrival of a photon and provides this pulse signal to the multiplexer 231 or 232.

[0042] Multiplexer 231 sequentially selects an odd-numbered row of the imaging pixels and provides pulse signals to the selected row for the time-to-digital converter 241. Multiplexer 232 sequentially selects an even-numbered row of the imaging pixels and provides pulse signals to the selected row for the time-to-digital converter 242.

[0043] The time-to-digital converter 241 is configured to convert the time until the rise of pulse signals in an odd-numbered series into digital signals. The digital signals indicate the detection times of a photon. The time-to-digital converter 241 provides the digital signals to the histogram generation section 250. The time-to-digital converter 242 is configured to convert the time until the rise of pulse signals in an even-numbered series into digital signals. The time-to-digital converter 242 provides the digital signals to the histogram generation section 250.

[0044] The multiplexers 231 and 232 and the time-to-digital converters 241 and 242 enable the processing of pulse signals in two series simultaneously. Note that it is also possible for the solid-state image sensor to process 200 pulse signals series by series. In this case, a single circuit chip contains one of the multiplexers 231 / 232 and one of the time-to-digital converters 241 / 242.

[0045] The histogram generation section 250 is configured to generate a histogram based on the digital signals from the time-to-digital converters 241 and 242. The histogram is a graphical representation illustrating the detection frequencies or frequencies of the respective detection times specified by the digital signals. The histogram generation section 250 generates the histogram for each imaging pixel and calculates a time point for each peak value as the light reception time of reflected light. Next, for each imaging pixel, the histogram generation section 250 converts the orbital period between the light emission time of an irradiation light, specified by the synchronization signal, and the light reception time of the reflected light into a distance to the object.The histogram generation section 250 generates distance data, which specifies the calculated distance, for each imaging pixel and outputs the distance data to the outside via the output interface 260.

[0046] Fig. Figure 5 is a block diagram illustrating a configuration example of circuit block 300 according to the first embodiment of the present technology. Circuit block 300 includes a plurality of monitoring pixel circuits 310, a plurality of imaging pixel circuits 380, and a control section (or control circuit) 500.

[0047] The monitoring pixel circuit 310 is provided for each photoelectric conversion element 211 and is connected to the corresponding photoelectric conversion element 211. The photoelectric conversion element 211 and the monitoring pixel circuit 310, which is connected to the photoelectric conversion element 211, serve as a single monitoring pixel. The monitoring pixel is a pixel used to monitor the electrical potentials of any of the cathodes and anodes (for example, the electrical potentials of the cathodes) of the photoelectric conversion elements 211 and 212.

[0048] The imaging pixel circuit 380 is provided for each photoelectric conversion element 212 and is connected to the corresponding photoelectric conversion element 212. The photoelectric conversion element 212 and the imaging pixel circuit 380, corresponding to the photoelectric conversion element 212, serve as a single imaging pixel. The imaging pixel is a pixel designed to generate a pulse signal in response to the arrival of a photon.

[0049] The control section 500 is configured to control electrical potentials of each of the cathodes and anodes (for example, electrical potentials of the anodes) of the photoelectric conversion elements 211 and 212 on the basis of electrical potentials of a monitoring target (such as the cathodes) of the monitoring pixels. “Configuration example of a surveillance pixel”

[0050] Fig. Figure 6 is a block diagram illustrating a configuration example of a monitoring pixel (or first pixel circuit arrangement) 401 according to the first embodiment of the present technology. As described above, a circuit comprising the photoelectric conversion element 211 of the pixel chip 201 and the monitoring pixel circuit 310 of the circuit chip 202 serves as the single monitoring pixel 401. The monitoring pixel circuit 310 also includes a p-channel metal-oxide-semiconductor (pMOS) transistor 311, a timing detection circuit (or delay circuit) 320, a sample-and-hold circuit (or hold circuit) 330, and buffers (or buffer circuits) 340 and 350.

[0051] The pMOS transistor 311 is arranged between an electrical potential VE of a power source and the photoelectric conversion element 211. A control signal RCH from the timing generation section 220 is also fed into a gate of the pMOS transistor 311. When a low-level control signal RCH is applied, the pMOS transistor 311 provides the electrical potential VE of the power source to a connection node 312 to the photoelectric conversion element 211. Note that the electrical potential VE of a power source is an example of a predetermined electrical potential according to an embodiment of the present technology, and the pMOS transistor 311 is an example of an element for providing an electrical potential according to an embodiment of the present technology.Furthermore, the connecting node 312 is an example of a predetermined node according to an embodiment of the present technology.

[0052] The photoelectric conversion element 211 is configured to output a photocurrent by photoelectric conversion in response to an incident photon. For example, the SPAD is used as the photoelectric conversion element 211. One cathode of the photoelectric conversion element 211 is connected to the connection node 312, and the cathode's electrical potential Vs is the electrical potential of a monitoring target. On the other side, one anode of the photoelectric conversion element 211 is connected to the control section 500, and the control section 500 controls the anode's electrical potential VSPAD.

[0053] The buffer 340 is arranged between the connection node 312 and the sample-and-hold circuit 330. Note that the buffer 340 is an example of an input-side buffer according to one embodiment of the present technology.

[0054] The time-detection circuit 320 is configured to monitor the electrical cathode potential Vs and detects a point in time at which a predetermined time interval has elapsed since the electrical cathode potential Vs began to decrease from the electrical potential provided by the pMOS transistor 311 (i.e., the electrical potential VE of the power source). If the electrical cathode potential Vs is the monitoring target, the electrical cathode potential Vs will decrease below the electrical potential VE of the power source when a photocurrent flows in response to an incident photon. Note that, as will be described later, it is also possible for the monitoring pixel 401 to monitor the electrical anode potential.If the electrical anode potential is monitored, the time-detection circuit 320 detects a time at which a predetermined period of time has elapsed since the electrical anode potential began to increase.

[0055] The sample-and-hold circuit 330 is configured to detect and hold the electrical cathode potential Vs based on the time detected by the time-detection circuit 320. The sample-and-hold circuit 330 outputs the held electrical signal as the hold potential Vs_SH to the buffer 350.

[0056] The buffer 350 is arranged between the sampling and holding circuit 330 and the control section 500. Note that the buffer 350 is an example of an output-side buffer according to one embodiment of the present technology. Note that the buffer 350 is not necessary and it is possible to omit it. Furthermore, it is also possible to install two or more buffers 340 / 350.

[0057] Fig. Figure 7 is a circuit diagram illustrating the configuration example of the monitoring pixel 401 according to the first embodiment of the present technology. The timing detection circuit 320 includes an inverter 321 and a pulse generation circuit 370. The sample-and-hold circuit 330 also includes a sample switch 331 and a capacitor 332. The buffer 350 includes an nMOS transistor 351 and an electrical current source 352.

[0058] Inverter 321 in the time-detection circuit 320 is configured to invert a signal of the electrical cathode potential Vs and output the inverted signal to the pulse generation circuit 370. Pulse generation circuit 370 is also configured to delay the inverted signal from inverter 321 by a predetermined delay time and generate a pulse signal SW based on the delayed signal. Pulse generation circuit 370 provides the pulse signal SW to the sampling switch 331.

[0059] The sampling switch 331 in the sampling and holding circuit 330 is configured to detect (in other words, sample) the electrical cathode potential Vs via the buffer 340 within a time interval equal to the pulse width of the pulse signal SW. The capacitor 332 is configured to hold the sampled electrical cathode potential Vs as the holding potential Vs_SH.

[0060] In buffer 350, the nMOS transistor 351 is arranged between an electrical potential of a power source and the electrical current source 352. The holding potential Vs_SH is also fed into a gate of the nMOS transistor 351 by the sampling and holding circuit 330. Furthermore, a back-gate of the nMOS transistor 351 is connected to a junction between the nMOS transistor 351 and the electrical current source 352. This junction is connected to the control section 500.

[0061] Note that the circuit configuration of buffer 340 is similar to that of buffer 350.

[0062] Fig. Figure 8 is a circuit diagram illustrating a configuration example of the pulse generation circuit 370 according to the first embodiment of the present technology. The pulse generation circuit 370 includes a delay circuit 371, an inverter 376, a delay circuit 377, a NAND gate 378, and an inverter 379. The delay circuit 371 includes an electrical current source 372, a pMOS transistor 373, an n-channel metal-oxide-semiconductor (nMOS) transistor 334, and a capacitor 375.

[0063] The delay circuit 371 is configured to delay an inverted signal VA from the inverter 321 by a predetermined time. In the delay circuit 371, the pMOS transistor 373, the nMOS transistor 374, and the electrical current source 372 are connected in series between an electrical potential of the power source and an electrical ground potential. Furthermore, the gates of the pMOS transistor 373 and the nMOS transistor 374 are connected to a common output terminal of the inverter 321. The capacitor 375 is arranged between an electrical ground potential and a junction that connects the pMOS transistor 373 to the nMOS transistor 374. The junction also outputs a delayed signal VB, which is obtained by delaying the inverted signal VA.

[0064] Inverter 376 is configured to invert the delayed signal VB. Inverter 376 outputs an inverted signal VC to the delay circuit 377 and the NAND gate 378.

[0065] The delay circuit 377 is configured to delay the inverted signal VC by a predetermined delay time. The circuit configuration of the delay circuit 377 is similar to that of the delay circuit 371. The delay circuit 377 outputs a delayed signal VD to the NAND gate 378.

[0066] The NAND gate 378 is configured to output a signal of the NAND of the inverted signal VC and the delayed signal VD as an output signal to the inverter 379.

[0067] Inverter 379 is configured to invert the output signal from NAND gate 378. Inverter 379 outputs the inverted signal as a pulse signal SW to the sample-and-hold circuit 330.

[0068] Fig. Figure 9 is a timing diagram illustrating an example of the operation of the pulse generation circuit 370 according to the first embodiment of the present technology.

[0069] It is assumed that at time T1, the inverted signal VA from inverter 321 rises from a low level to a high level. The delay circuit 371 delays the inverted signal VA and outputs a delayed signal VB.

[0070] Furthermore, inverter 376 inverts the delayed signal VB. The inverted signal VC rises at time T2. Delay circuit 377 delays the inverted signal VC and outputs the delayed signal VD.

[0071] Furthermore, at time T2, inverter 379 inverts the NAND gate of the inverted signal VC and the delayed signal VD, generating the pulse signal SW. The pulse width of the pulse signal SW is a time interval between time T2 and time T3. “Configuration example of an imaging pixel”

[0072] Fig. Figure 10 is a circuit diagram illustrating a configuration example of an imaging pixel 402 according to the first embodiment of the present technology. As described above, a circuit comprising the photoelectric conversion element 212 of the pixel chip 201 and the imaging pixel circuit 380 of the circuit chip 202 serves as the single imaging pixel 402. The imaging pixel circuit 380 comprises a pMOS transistor 381 and an inverter 382.

[0073] A connection structure between the pMOS transistor 381 and the photoelectric conversion element 212 is similar to the connection structure between the pMOS transistor 311 and the photoelectric conversion element 211 in the monitoring pixel 401.

[0074] The inverter 382 is configured to invert a signal of an electrical cathode potential of the photoelectric conversion element 212 and to provide the inverted signal as a pulse signal of the imaging pixel 402 to the multiplexer 231 (or the multiplexer 232).

[0075] Fig. Figure 11 is a top view illustrating a configuration example of a pixel array section 400 according to the first embodiment of the present technology. The pixel array section 400 includes the light-receiving section 210 of the pixel chip 201 and the circuit block 300 of the circuit chip 202.

[0076] In pixel array section 400, a plurality of monitoring pixels 401 and a plurality of imaging pixels 402 are arranged in an array. The monitoring pixels 401 are arranged linearly in an array along a boundary of pixel array section 400. For example, the monitoring pixels 401 are arranged in a line at the top of pixel array section 400. On the other side, the imaging pixels 402 are arranged in an array in the form of a two-dimensional grid.

[0077] Fig. Figure 12 is a block diagram illustrating a configuration example of the monitoring pixels 401, the imaging pixels 402, and the control section 500 according to the first embodiment of the present technology. The control section 500 includes an intermediate pixel average acquisition section (or average value circuit) 510, a time average acquisition section (or time average value circuit) 520, and an electrical potential control section (or potential controller) 530.

[0078] Each of the multiple monitoring pixels 401 provides the holding potential Vs_SH to section 510 for capturing an intermediate pixel average. A holding potential of an m-th monitoring pixel 401 is referenced as Vs_SHm (m being an integer).

[0079] Section 510, for capturing an intermediate pixel average, is configured to calculate an average of the respective holding potentials Vs_SHm of the multitude of monitoring pixels 401 as the intermediate pixel average Vs_SHAVp. Section 510, for capturing an intermediate pixel average, provides the intermediate pixel average Vs_SHAVp to the time-average acquisition section 520.

[0080] The time-averaged acquisition section 520 is configured to calculate a time average Vs_SHAVt of the intermediate pixel averages Vs_SHAVp. Time-averaged acquisition section 520 provides the time average Vs_SHAVt to section 530 for controlling an electrical potential.

[0081] Electrical Potential Control Section 530 is configured to control the electrical anode potential VSPAD such that the electrical anode potential VSPAD decreases as the time average Vs_SHAVt of the held electrical cathode potential increases. All anodes of the plurality of monitoring pixels 401 and the plurality of imaging pixels 402 are common to Electrical Potential Control Section 530, and Electrical Potential Control Section 530 controls the electrical potentials of the anodes. Note that Electrical Potential Control Section 530 controls electrical cathode potentials if the monitoring pixels 401 are monitoring electrical anode potentials.

[0082] Furthermore, in monitoring pixel 401, either the anode or the cathode of the photoelectric conversion element 211 (for example, the cathode) is connected to the connection node 312. The pMOS transistor 311 provides the electrical potential VE of a power source to the connection node 312 in response to the control signal RCH.

[0083] The time-detection circuit 320 detects a point in time at which a predetermined time interval has elapsed since the electrical cathode potential Vs of the connection node 312 began to decrease from the electrical potential VE of a power source. This point in time corresponds to a point in time at which a predetermined delay time has elapsed since the electrical cathode potential fell below a threshold of the inverter 321.

[0084] The sampling and holding circuit 330 detects and holds the electrical cathode potential Vs as the holding potential Vs_SH on the basis of the time detected by the time detection circuit 320.

[0085] Next, the control section 500 controls the other of the anode and the cathode of the photoelectric conversion element 211 (for example, the anode) in such a way that the electrical potential becomes lower when the holding potential Vs_SH becomes higher.

[0086] Furthermore, in monitoring pixel 401, the buffer 340 is installed in a stage upstream of the sampling and holding circuit 330. This makes it possible to standardize the capacitances of the respective connection nodes of monitoring pixel 401 and imaging pixel 402. This connection node is the connection between the photoelectric conversion element and the pMOS transistor. This makes it possible to standardize the respective breakdown voltages VBD of monitoring pixel 401 and imaging pixel 402. “Configuration example of a control section”

[0087] Fig. Figure 13 is a circuit diagram illustrating a configuration example of the control section 500 according to the first embodiment of the present technology. The interpixel average acquisition section 510 contains a plurality of resistors 511 and a capacitor 512. The resistors 511 are assigned to the respective monitoring pixels 401. The time-average acquisition section 520 contains a variable resistor 521 and a variable capacitor 522. The electrical potential control section 530 contains an amplifier 531.

[0088] The resistor 511 in section 510 for capturing an interpixel average has one end connected to the corresponding monitoring pixel 401 and the other end connected to one end of capacitor 512 and the time-average capture section 520. In other words, the array of resistors 511 is connected in parallel between the array of monitoring pixels 401 and capacitor 512. The other end of capacitor 512 is connected to an electrical ground potential. The resistors 511 make it possible to generate an average electrical potential of the holding voltages Vs_SHm of the array of monitoring pixels 401 as the interpixel average Vs_SHAVp, and capacitor 512 holds the interpixel average Vs_SHAVp. By capturing the interpixel average, it is possible to suppress adverse effects caused by variations in the holding potentials Vs_SH between pixels.

[0089] Furthermore, the variable resistor 521 in the time-averaged acquisition section 520 has one end connected to section 510 for acquiring an interpixel average and the other end connected to one end of the variable capacitor 522 and section 530 for controlling an electrical potential. The other end of the variable capacitor 522 is connected to an electrical ground potential. A circuit containing the variable resistor 521 and the variable capacitor 522 serves as an analog low-pass filter that generates the time average VS_SHAVt of the interpixel averages Vs_SHAVp. Note that the circuit containing the variable resistor 521 and the variable capacitor 522 is an example of an analog filter according to one embodiment of the present technology.

[0090] The time average Vs_SHAVt is fed into an inverting input (-) of amplifier 531 in section 530 to control an electrical potential, and a predetermined electrical potential from a power source is fed into a non-inverting input (+). Amplifier 531 generates a comparison result between the time average Vs_SHAVt and the predetermined electrical potential of a power source as the VSPAD, using the following expression, and provides the VSPAD to the anodes of monitoring pixel 401 and imaging pixel 402. VSPAD=Av(VREF−Vs_SHAVt)

[0091] In the above expression, Av represents a gain of amplifier 531 and VREF represents a target value of VSPAD.

[0092] Fig. Figure 14 is a diagram illustrating an example of variation in the electrical cathode potential Vs and the electrical anode potential VSPAD according to the first embodiment of the present technology. The pMOS transistor 311 provides the electrical potential VE of a power source, and the electrical cathode potential Vs then becomes the electrical potential VE of the power source. When a photon enters, the electrical cathode potential Vs decreases to a lower electrical potential VBT and increases to the initial electrical potential VE of the power source by recharging.

[0093] The voltage between the electrical potential VE of a power source and the lower electrical potential VBT is referred to as excess bias VEX. Similarly, the voltage between the lower electrical potential VBT and the electrical anode potential VSPAD is referred to as breakdown voltage VBD. If the electrical potential VE of a power source and the electrical anode potential VSPAD are constant, the excess bias VEX varies depending on the temperature and the breakdown voltage VBD.

[0094] If the bias voltage VEX becomes small, the sensitivities of the photodiodes in the imaging pixels 402 decrease when the photon enters. In such a case, the pulse signals of the imaging pixels 402 are not generated, even when the photon enters, and the photon detection efficiency (PDE) decreases. Therefore, the control section 500 reduces the electrical anode potential VSPAD as the holding potential increases when the electrical cathode potential Vs decreases. This makes it possible to increase the breakdown voltage VBD, increase the bias voltage VEX, and improve the PDE.

[0095] Fig. 15A and Fig. Figure 15B contains diagrams illustrating examples of a variation of the over-bias VEX and an electrical anode potential VSPAD according to the first embodiment of the present technology and a comparative example. Fig. Figure 15A is a diagram illustrating an example of a variation of the over-bias voltage VEX and the electrical anode potential VSPAD according to the first embodiment. Fig. Figure 15B is a diagram illustrating an example of a variation in the over-bias voltage VEX according to the comparison example, in which the electrical anode potential VSPAD is not controlled. Fig. 15A and Fig. In 15B, vertical axes represent electrical potentials and horizontal axes represent temperatures. Furthermore, in Fig. 15A and Fig. 15B assume that the amount of incident light is constant and that the holding potential Vs_SH is essentially the same as the lower electric potential VBT.

[0096] The holding potential (the lower electrical potential VBT) increases as the temperature rises. Therefore, as in Fig. Figure 15A illustrates how control section 500 increases the electrical anode potential VSPAD by a value corresponding to the increase. As a result, it is possible to maintain the over-bias voltage VEX at a constant value, regardless of temperature variations. This makes it possible to suppress a reduction in the PDE caused by temperature variations.

[0097] On the other hand, in the comparative example where the electrical anode potential VSPAD is not controlled, as in Fig. Figure 15B illustrates that the lower electrical potential VBT increases as the temperature rises, thereby decreasing the over-bias VEX. This causes a reduction in the PDE.

[0098] As in Fig. 15A and Fig. As illustrated in Figure 15B, it is possible to suppress a reduction in PDE caused by temperature variation under the control of control section 500. However, a monitoring voltage (such as the electrical cathode potentials) for observing the lower electrical potential VBT follows the variation in the overbias caused by temperature, and the monitoring voltage also varies depending on a decrease or increase in the amount of incident light.

[0099] Fig. 16A and Fig. Figure 16B are time sequence diagrams illustrating a variation in an electrical cathode potential Vs obtained in the case of a large amount of light and a variation in an electrical cathode potential Vs obtained in the case of a small amount of light, according to the first embodiment of the present technology. Fig. Figure 16A is a time-lapse diagram illustrating a variation in the electrical cathode potential Vs obtained in the case of a relatively small amount of light. Fig. Figure 16B is a time-lapse diagram illustrating a variation in the electrical cathode potential Vs obtained in the case of a relatively large amount of light. Fig. 16A and Fig. 16B assumes that the temperature is constant.

[0100] In the case of low light levels, as in Fig. Figure 16A illustrates that a recharge occurs at time T1, and the electric cathode potential Vs becomes an electric potential VE of a power source. When the photon enters at time T10, the electric cathode potential Vs begins to decrease. After time T12, the electric cathode potential Vs becomes constant. The electric potential obtained at time T12 is a lower electric potential VBT1.

[0101] In the case of a large amount of light, as in Fig. Figure 16B illustrates that an electrical cathode potential Vs up to time T12 has the same trend curve (locus) as Fig. 16A. After time T12, however, a leakage current increases in response to the amount of light, and the electrical cathode potential Vs decreases further. Subsequently, the electrical cathode potential Vs reaches a lower electrical potential VBT2 immediately before time T2, at which recharging occurs again. The lower electrical potential VBT2 is lower than the lower electrical potential VBT1, which is maintained in the case of low light levels.

[0102] As described above, even when the temperature is constant, the lower electrical potential VBT varies due to a decrease or increase in the amount of incident light. Therefore, if the control section 500 controls the electrical anode potential VSPAD based on the lower electrical potential VBT, this results in a voltage variation to suppress any variation in the over-bias caused by a decrease or increase in the amount of light.

[0103] Accordingly, the time-detection circuit 320 in the monitoring pixel 401 sets a delay time and a threshold VT and detects time T12 in such a way that time T12 is a time at which the delay time has elapsed since time T11. Next, the sample-and-hold circuit 330 detects the electrical cathode potential Vs of time T12 and holds it as the hold potential Vs_SH. As in Fig. 16A and Fig. As illustrated in Figure 16B, regardless of the decrease or increase in the amount of light, the curve of the electrical cathode potential Vs in Fig. 16A up to time T12 the same as the curve of the electrical cathode potential Vs in Fig. 16B. Therefore, it is possible to uniformly suppress a variation in the over-bias caused by a decrease or increase in the amount of light if the control section 500 controls the electrical anode potential VSPAD in response to the holding potential Vs_SH at any given time. This makes it possible to further improve the PDE. Note that the time interval between time T10 and time T12 is an example of a predetermined time interval according to one embodiment of the present technology.

[0104] Fig. 17A and Fig. Figure 17B are time-lapse diagrams illustrating examples of fluctuations in the lower electrical potential VBT obtained in the case of the large amount of light and fluctuations in the lower electrical potential VBT obtained in the case of the small amount of light according to the first embodiment of the present technology. Fig. Figure 17A is a time-lapse diagram illustrating an example of fluctuations in the lower electrical potential VBT obtained in the case of low light levels. Fig. Figure 17B is a time-lapse diagram illustrating an example of fluctuations in the lower electric potential VBT observed in the case of a large amount of light. Additionally, dashed lines indicate time averages of the lower electric potentials VBT.

[0105] Fig. Figure 18 is a scatter plot illustrating an example of a variation range of the breakdown voltage VBD according to the first embodiment of the present technology. Fig. Figure 18 represents a vertical axis representing the breakdown voltage VBD and a horizontal axis representing the number of pixels (monitor pixels and imaging pixels). Furthermore, each plotted point represents the breakdown voltage VBD of a single pixel, and a solid curve represents the boundary of a set of plotted points. As in Fig. As illustrated in example 18, the distribution of the breakdown voltage VBD is similar to a normal distribution.

[0106] Fig. Figure 19 is a timing diagram illustrating an example of the operation of the monitoring pixel 401 and the control section 500 according to the first embodiment of the present technology. The monitoring pixel 401 is recharged at time T1, and the electrical cathode potential Vs becomes an electrical potential VE of a power source. When a photon enters at time T10, the electrical cathode potential Vs then begins to decrease.

[0107] If the electrical cathode potential Vs falls below a threshold VT of the inverter 321 at time T11, an inverted signal of the inverter 321 increases and the pulse generation circuit 370 generates a pulse signal SW at time T12 after a delay of the inverted signal by a delay time.

[0108] The sampling and holding circuit 330 detects the electrical cathode potential Vs within a time span of the pulse width of the pulse signal SW and holds it as the holding potential Vs_SH.

[0109] Furthermore, at time T1, the connection node 312 switches from a high impedance state (Hi-Z) to a low impedance state (Low-Z) due to recharging. Subsequently, before time T12, the connection node 312 switches back to the high impedance state.

[0110] The magnitude of the decrease in the electrical cathode potential Vs after time T12 varies depending on the amount of light. However, at time T12, the sampling and holding circuit 330 maintains the electrical cathode potential Vs. This makes it possible to maintain the holding potential Vs_SH at a constant value regardless of the amount of light. Therefore, it is possible to suppress any variation in the overvoltage caused by a decrease or increase in the amount of light when the control section 500 controls the electrical anode potential VSPAD in response to the holding potential Vs_SH. “Operational example of a solid-state image sensor”

[0111] Fig. Figure 20 is a flowchart illustrating an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation begins, for example, when a predetermined application for measuring a distance is executed.

[0112] The monitoring pixel 401 detects a time point at which a delay time has elapsed since the electrical cathode potential Vs fell below the threshold VT (step S901). Next, the monitoring pixel 401 detects and maintains the electrical cathode potential Vs based on this time point (step S902). The control section 500 controls the electrical anode potential VSPAD in such a way that the electrical anode potential VSPAD decreases as the holding potential increases (step S903). After step S903, the monitoring pixel 401 repeats step S901 and the subsequent steps.

[0113] As described above, according to the first embodiment of the present technology, the monitoring pixel 401 detects a point in time at which a predetermined time interval has elapsed since the decrease of an electrical cathode potential and captures and maintains the electrical cathode potential at that time. This makes it possible to maintain the electrical potential independently of the amount of light. It is possible to suppress a variation in bias voltage resulting from a decrease or increase in the amount of light when the control section 500 controls an electrical anode potential in response to the holding potential. "First modification"

[0114] In the first embodiment described above, the monitoring pixel 401 monitors the electrical cathode potential Vs of the photoelectric conversion element 211 and controls the electrical anode potential based on the electrical cathode potential Vs. However, it is also possible for the monitoring pixel 401 to monitor the electrical anode potential instead of the electrical cathode potential. Such a monitoring pixel 401 according to the first modification of the first embodiment differs from the monitoring pixel 401 according to the first embodiment in that the monitoring pixel 401 according to the first modification monitors the electrical anode potential of the photoelectric conversion element 211 and controls the electrical cathode potential based on the electrical anode potential.

[0115] Fig. Figure 21 is a block diagram illustrating a configuration example of the monitoring pixel 401 according to the first modification of the first embodiment of the present technology. In the monitoring pixel 401 according to the first modification of the first embodiment, the anode of the photoelectric conversion element 211 is connected to the connection node 312, and the cathode is connected to the control section 500. Furthermore, the pMOS transistor 311 is arranged between the connection node 312 and the electrical ground potential VS.

[0116] Note that a connection structure between the photoelectric conversion element 212 and the pMOS transistor 381 in an imaging pixel 402 is similar to that of the monitoring pixel 401.

[0117] The time-detection circuit 320 detects a point in time at which a predetermined time interval has elapsed since the electrical anode potential became higher than the electrical ground potential VS. In this case, for example, it is only necessary for the time-detection circuit 320 to contain the inverters in two stages or to contain a buffer instead of the inverter.

[0118] As described above, according to the first modification of the first embodiment of the present technology, the monitoring pixel 401 detects a point in time at which a predetermined time interval has elapsed since the increase in the electrical anode potential, and captures and maintains the electrical anode potential at that time. This makes it possible to maintain the electrical potential independently of the amount of light. It is possible to suppress a variation in bias voltage resulting from a decrease or increase in the amount of light when the control section 500 controls the electrical cathode potential in response to the holding potential. "Second modification"

[0119] In the first embodiment described above, the function of the control section 500 is implemented by an analog circuit. However, analog circuits generally have a larger circuit size than digital circuits. Therefore, this can lead to an increase in the footprint. A control section 500 according to the second modification of the first embodiment differs from the control section 500 according to the first modification in that the control section 500 according to the second modification is a digital circuit.

[0120] Fig. Figure 22 is a block diagram illustrating a configuration example of the control section 500 according to the second modification of the first embodiment of the present technology. In the control section 500 according to the second modification of the first embodiment, the section 510 for capturing an interpixel average includes an analog-to-digital conversion section 513 and an averaging filter 515. Additionally, the time-averaged acquisition section 520 includes a digital low-pass filter 524. The section 530 for controlling an electrical potential includes an integrated power circuit (IC) 533.

[0121] The analog-to-digital conversion section 513 is configured to convert the respective holding potentials of the multiple monitoring pixels 401 into digital signals. The analog-to-digital conversion section 513 contains multiple analog-to-digital converters (ADCs) 514. The ADCs 514 are assigned to the respective monitoring pixels 401. The ADC 514 converts the holding potential Vs_SHm of the corresponding monitoring pixel 401 into a digital signal and provides the digital signal to the average value filter 515.

[0122] The average value filter 515 is a digital filter to calculate an average value of the respective digital signals of the multitude of monitoring pixels 401 as an intermediate pixel average Vs_SHAVp.

[0123] The 524 digital low-pass filter is a digital filter that allows low-frequency components to pass through. These low-frequency components are lower than a predetermined cutoff frequency. This makes it possible to obtain a time average (Vs_SHAVt) of the interpixel averages (Vs_SHAVp).

[0124] The power IC 533 is configured to control the electrical anode potential VSPAD in such a way that the electrical anode potential VSPAD decreases as the time average Vs_SHAVt increases. Note that the power IC 533 is an example of a power semiconductor according to one embodiment of the present technology.

[0125] As in Fig. As illustrated in Figure 22, it is possible to reduce the size of the base area of ​​the control section 500 if the function of the control section 500 is implemented by the digital circuit.

[0126] As described above, according to the second modification of the first embodiment of the present technology, the control section 500 contains the digital circuitry. This makes it possible to reduce the footprint compared to the analog circuitry. "Third modification"

[0127] In the second modification of the first embodiment described above, the section 510 for capturing an intermediate pixel average includes the ADCs 514 corresponding to the respective monitoring pixels 401. In this case, however, the number of ADCs 514 increases as the number of monitoring pixels 401 increases. A section 510 for capturing an intermediate pixel average according to the third modification of the first embodiment differs from the section 510 for capturing an intermediate pixel average according to the second modification of the first embodiment in that, according to the third modification, a plurality of monitoring pixels 401 share a single ADC 514.

[0128] Fig. Figure 23 is a block diagram illustrating a configuration example of section 510 for capturing an intermediate pixel average according to the third modification of the first embodiment of the present technology. Section 510 for capturing an intermediate pixel average according to the third modification of the first embodiment differs from section 510 for capturing an intermediate pixel average according to the second modification of the first embodiment in that an analog-to-digital conversion section 513 according to the third modification includes a single selector 516 and the single ADC 514.

[0129] Selector 516 is configured to sequentially select any of the respective holding potentials Vs_SHm from the multitude of monitoring pixels 401. Selector 516 provides the selected holding potential to ADC 514. Each time a holding potential is selected, ADC 514 converts the holding potential into a digital signal and provides the digital signal to average-value filter 515.

[0130] As in Fig. As illustrated by example in Figure 23, it is possible for the multiple monitoring pixels 401 to share the single ADC 514 because the selector 516 is installed. This makes it possible to reduce the circuit size compared to the case where the ADCs 514 are provided for the respective monitoring pixels 401.

[0131] As described above, according to the third modification of the first embodiment of the present technology, the selector 516 is installed to select any one of the respective holding potentials Vs_SHm of the plurality of monitoring pixels 401. This allows the plurality of monitoring pixels 401 to share the single ADC 514. "Fourth Modification"

[0132] In the first embodiment described above, one function of the control function 500 is implemented by the analog circuit. However, analog circuits generally have a larger circuit size than digital circuits. Therefore, this can lead to an increase in the footprint. A control section 500 according to the fourth modification of the first embodiment differs from the control section 500 according to the first modification in that the control section 500 according to the fourth modification contains digital circuits.

[0133] Fig. Figure 24 is a block diagram illustrating a configuration example of the control section 500 according to the fourth modification of the first embodiment of the present technology. In the control section 500 according to the fourth modification of the first embodiment, the time-average acquisition section 520 includes an ADC 523 and the digital low-pass filter 524, and the section 530 for controlling an electrical potential includes the power IC 533. Furthermore, the circuit configuration of the section 510 for acquiring an interpixel average according to the fourth modification of the first embodiment is similar to that of the first embodiment.

[0134] The ADC 523 is configured to convert an analog interpixel average Vs_SHAVp into a digital signal and to provide the digital signal to the digital low-pass filter 524.

[0135] As described above, according to the fourth modification of the first embodiment of the present technology, the time-averaged detection section 520 and the section 530 for controlling an electrical potential contain digital circuits. This makes it possible to reduce the footprint compared to the analog circuit. "Fifth modification"

[0136] In the first embodiment described above, the function of the control section 500 is implemented by the analog circuit. However, analog circuits generally have a larger circuit size than digital circuits. This can therefore lead to an increase in the footprint. A control section 500 according to the fifth modification of the first embodiment differs from the control section 500 according to the first modification in that the control section 500 according to the fifth modification includes a digital circuit.

[0137] Fig. Figure 25 is a block diagram illustrating a configuration example of the control section 500 according to the fifth modification of the first embodiment of the present technology. In the control section 500 according to the fifth modification of the first embodiment, the section 530 for controlling an electrical potential includes an ADC 532 and the power IC 533. Furthermore, the circuit configurations of the section 510 for acquiring an interpixel average and the time-average acquisition section 520 according to the fifth modification of the first embodiment are similar to those of the first embodiment.

[0138] The ADC 532 is configured to convert an analog time average Vs_SHAVt into a digital signal and to provide the digital signal to the power IC 533.

[0139] As described above, according to the fifth modification of the first embodiment of the present technology, section 530 for controlling an electrical potential includes the digital circuit. This makes it possible to reduce the size of the footprint compared to the analog circuit. "Sixth modification"

[0140] In the first embodiment described above, buffers 340 and 350 output asymmetric signals (single-ended signals). However, if the number of monitoring pixels 401 increases, and therefore the signal lines transmitting the asymmetric signals have longer wire lengths, the wiring resistance increases. This can lead to insufficient drive forces for buffers 340 and 350. Buffers 340 and 350 according to the sixth modification of the first embodiment differ from those of the first embodiment in that the buffers 340 and 350 according to the sixth modification output differential signals.

[0141] Fig. Figure 26 is a circuit diagram illustrating a configuration example of a monitoring pixel 401 according to the sixth modification of the first embodiment of the present technology. In the monitoring pixel 401 according to the sixth modification of the first embodiment, the buffer 340 contains electrical current sources 341 and 343 and pMOS transistors 342 and 344. Furthermore, the buffer 350 contains electrical current sources 352 and 354 and nMOS transistors 351 and 353.

[0142] In buffer 340, the electrical current source 341 and the pMOS transistor 342 are connected in series between an electrical potential of a power source and an electrical ground potential. The electrical current source 341 is connected to one side of the power source, and a gate of the pMOS transistor 342 is connected to the connection node 312. Furthermore, a connection node between the electrical current source 341 and the pMOS transistor 342 is connected to the sampling switch 331.

[0143] The electrical current source 343 and the pMOS transistor 344 are connected in series between an electrical potential of a power source and an electrical ground potential. The electrical current source 343 is connected to the power source, and one gate of the pMOS transistor 344 is connected to the electrical ground potential. Furthermore, a connection node between the electrical current source 343 and the pMOS transistor 344 is connected to the buffer 350.

[0144] In buffer 350, the nMOS transistor 351 and the electrical current source 352 are connected in series between an electrical potential of a power source and an electrical ground potential. The electrical current source 352 is connected to ground, and a gate of the nMOS transistor 351 is connected to the sampling switch 331. Furthermore, a connection node between the nMOS transistor 351 and the electrical current source 352 is connected to the control section 500 via a signal line 358.

[0145] The nMOS transistor 353 and the electrical current source 354 are connected in series between an electrical potential of a power source and an electrical ground potential. The electrical current source 354 is connected to ground, and one gate of the nMOS transistor 353 is connected to the buffer 340. Furthermore, a connection node between the nMOS transistor 353 and the electrical current source 354 is connected to the control section 500 via a signal line 359.

[0146] The in Fig. Figure 26 illustrates an exemplary connection structure enabling buffer 340 to generate a differential signal based on an electrical cathode potential Vs and to output the generated differential signals, and allows buffer 350 to generate a differential signal based on a holding potential Vs_SH and to output the generated differential signal.

[0147] Fig. Figure 27 is a circuit diagram illustrating a configuration example of a section 501 for capturing an interpixel average according to the sixth modification of the first embodiment of the present technology. The section 501 for capturing an interpixel average according to the sixth modification of the first embodiment includes capacitors 518 and 519 and an ADC 517.

[0148] The positive sides of each differential signal from the multiple monitoring pixels 401 are connected to capacitor 518 and an input terminal on the positive side of ADC 517. Similarly, the negative sides of each differential signal from the multiple monitoring pixels 401 are connected to capacitor 519 and the input terminal on the positive side of ADC 517. ADC 517 converts the differential signals into digital signals and outputs these digital signals to the time-averaged acquisition section 520.

[0149] As described above, in the sixth modification of the first embodiment of the present technology, buffers 340 and 350 output differential signals. This makes it possible to obtain more accurate output values ​​than in the case of asymmetrical signal output. <2. Second embodiment>

[0150] In the first embodiment described above, the monitoring pixel 401 contains the buffers (340 and 350) in two stages. However, such a monitoring pixel consumes more electrical power and requires a longer response time than in the case where it contains a buffer in a single stage. Here, the response time means the time from the moment a photon arrives until an electrical cathode potential is maintained. A monitoring pixel 401 according to the second embodiment differs from the monitoring pixel 401 according to the first embodiment in that one buffer is omitted from the monitoring pixel 401 according to the second embodiment.

[0151] Fig. Figure 28 is a block diagram illustrating a configuration example of the monitoring pixel 401 according to the second embodiment of the present technology. The monitoring pixel 401 according to the second embodiment differs from the monitoring pixel 401 according to the first embodiment in that the monitoring pixel 401 according to the second embodiment does not contain the buffer 340.

[0152] Fig. Figure 29 is a circuit diagram illustrating the configuration example of the monitoring pixel 401 according to the second embodiment of the present technology. In the monitoring pixel 401 according to the second embodiment, the timing detection circuit 320 contains the delay circuit 371 instead of the pulse generation circuit 370. Furthermore, the buffer 350 contains an electrical current source 355 and pMOS transistors 356 and 357.

[0153] The circuit configuration of the delay circuit 371 according to the second embodiment is similar to that of the first embodiment. The delay circuit 371 delays an inverted signal from the inverter 321 by a predetermined delay time and provides a delayed signal SW' to the sampling switch 331.

[0154] The sampling and holding circuit 330 detects the electrical cathode potential Vs in the case where the delayed signal SW' is at a high level, and holds the detected electrical potential in the case where the delayed signal SW' is at a low level.

[0155] Furthermore, in buffer 350, the electrical current source 355 and the pMOS transistors 356 and 357 are connected in series between an electrical potential of a power source and an electrical ground potential. A trigger signal Tr is applied to a gate of pMOS transistor 356, and the hold potential Vs_SH of the sample-and-hold circuit 330 is applied to a gate of pMOS transistor 357. The trigger signal Tr is the same signal as the delayed signal SW'. The pMOS transistor 357 is switched off when the sample-and-hold circuit 330 is switched on, and the pMOS transistor 357 is switched on when the sample-and-hold circuit 330 is switched off. Additionally, a connection node between the pMOS transistors 356 and 357 is connected to the control section 500.

[0156] As in Fig. In Figure 29, which is shown as an example, buffer 340 has been omitted. Therefore, it is possible to reduce the power consumption by the amount of power consumed by buffer 340, and it is possible to shorten the response time by the amount of time taken by buffer 340. Furthermore, it is possible to design a wider voltage range for the electrical cathode potential Vs than in the case where the buffers are provided in two stages. This makes it possible to extend the dynamic range by the extended voltage range.

[0157] Fig. Figure 30 is a time sequence diagram illustrating an example of the operation of the monitoring pixel 401 and the control section 500 according to the second embodiment of the present technology.

[0158] Within a time interval from time T1 immediately after a recharge to time T12, after a delay time has elapsed, the time-detection circuit 320 delays an inverted signal and outputs a delayed signal SW' at a high level. Within a time interval from time T12 until time T2 of the next recharge, the time-detection circuit 320 also delays the inverted signal and outputs a delayed signal SW' at a low level.

[0159] The sample-and-hold circuit 330 samples the electrical cathode potential Vs when the delayed signal SW' is high-level. During this high-level period, the electrical cathode potential Vs decreases, and this variation in the electrical cathode potential Vs is monitored. Conversely, the sample-and-hold circuit 330 holds the electrical cathode potential Vs when the delayed signal SW' is low-level. The delayed signal SW' drops at time T12. Therefore, the electrical potential is held at time T12 in a manner similar to the first embodiment.

[0160] Note that the first to fifth modifications of the first embodiment are applicable to the second embodiment.

[0161] As described above, in the second embodiment of the present technology, buffer 340 is omitted. Therefore, compared to the case where the buffers are provided in two stages, it is possible to reduce power consumption and shorten the response time. "Modification"

[0162] In the second embodiment described above, the buffer 350 outputs an asymmetric signal. However, if the number of monitoring pixels 401 increases, and therefore the signal lines transmitting the asymmetric signals have longer wire lengths, the wiring resistance increases. This can lead to the driving force of the buffer 350 being insufficient. A buffer 350 according to the modification of the second embodiment differs from the buffer 350 according to the first embodiment in that the buffer 350 according to this modification outputs a differential signal.

[0163] Fig. Figure 31 is a circuit diagram illustrating a configuration example of a monitoring pixel 401 according to the modification of the second embodiment of the present technology. In the monitoring pixel 401 according to the modification of the second embodiment, the time-detection circuit 320 further includes a D flip-flop 322.

[0164] A delayed signal from the delay circuit 371 is fed into a clock pin of flip-flop 322. Additionally, an inverted signal of the control signal RCH is fed into a set pin of flip-flop 322, and a low level is fed into a reset pin. The output pin of flip-flop 322 is connected to the sampler switch 331 and the buffer 350.

[0165] Fig. Figure 32 is a circuit diagram illustrating a configuration example of the buffer 350 according to the modification of the second embodiment of the present technology. The buffer 350 according to the modification of the second embodiment differs from the buffer 350 according to the second embodiment in that the buffer 350 according to this modification further includes an electrical current source 361 and pMOS transistors 362 and 363.

[0166] The electrical current source 361 and the pMOS transistors 362 and 363 are connected in series between an electrical potential of a power source and an electrical ground potential. Furthermore, the gates of the pMOS transistors 356 and 362 are connected to the timing detection circuit 320. Additionally, a gate of the pMOS transistor 357 is connected to the sampling switch 331, and a gate of the pMOS transistor 363 is connected to the electrical ground potential.

[0167] A connection node between the pMOS transistors 356 and 357 and a connection node between the pMOS transistors 362 and 363 are connected to the control section 500 via the signal lines 358 and 359.

[0168] The in Fig. The exemplary configuration shown in Figure 32 enables the buffer 350 to generate a differential signal based on the holding potential Vs_SH and to output the generated differential signal to the control section 500.

[0169] As described above, according to the modification of the second embodiment of the present technology, buffer 350 outputs the differential signal. This makes it possible to obtain a more accurate output value than in the case of an asymmetric signal output. <3. Application examples for a mobile object>

[0170] The technology according to one embodiment of the present disclosure (the present technology) can be used for various products. For example, the technology according to one embodiment of the present disclosure can be implemented as a device that is mounted on any type of mobile object, such as a vehicle, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, or a robot.

[0171] Fig. Figure 33 is a block diagram illustrating an example of a schematic configuration of a vehicle control system as an example of a system for controlling mobile bodies for which the technology according to an embodiment of the present disclosure can be used.

[0172] The vehicle control system 12000 comprises a multitude of electronic control units interconnected via a communication network 12001. In the Fig. In the example shown in Figure 33, the vehicle control system 12000 comprises a powertrain control unit 12010, a body control unit 12020, a unit 12030 for detecting information from outside the vehicle, a unit 12040 for detecting information from inside the vehicle, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / video output section 12052, and an interface 12053 of the vehicle-mounted network are illustrated as a functional configuration of the integrated control unit 12050.

[0173] The 12010 drive system control unit controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the 12010 drive system control unit serves as a control device for a drive force generation device to generate the vehicle's drive force, such as an internal combustion engine, a drive motor, or the like; a drive force transmission mechanism to transfer the drive force to the wheels; a steering mechanism to adjust the vehicle's steering angle; a braking device that generates the vehicle's braking force; and the like.

[0174] The 12020 body control unit controls the operation of various types of devices integrated into a vehicle body, according to different programs. For example, the 12020 body control unit serves as a control device for a keyless entry system, a smart key system, automatic windows, or various types of lights such as headlights, taillights, brake lights, turn signals, fog lights, and the like. In this case, radio waves transmitted by a mobile device as an alternative to a key, or signals from various types of switches, can be fed into the 12020 body control unit.The body control unit 12020 receives these injected radio waves or signals and controls a door locking device, the automatic window device, the lights or the like of the vehicle.

[0175] The external information detection unit 12030 detects information about the external environment of the vehicle containing the vehicle control system 12000. For example, the external information detection unit 12030 is connected to an imaging section 12031. The external information detection unit 12030 causes the imaging section 12031 to take an image of the vehicle's external environment and receives the captured image. Based on the received image, the external information detection unit 12030 can perform processing to detect an object such as a person, a vehicle, an obstacle, a traffic sign, a marking on a road surface, or the like, or processing to detect the distance to it.

[0176] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can also output the electrical signal as an image or as information about a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light or invisible light such as infrared radiation.

[0177] Unit 12040 for detecting information from inside the vehicle detects information about or from inside the vehicle. Unit 12040 for detecting information from inside the vehicle is, for example, connected to section 12041 for detecting a driver state, which detects the driver's condition. Section 12041 for detecting a driver state includes, for example, a camera that records the driver. Based on detection information input from section 12041 for detecting a driver state, unit 12040 for detecting information from inside the vehicle can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0178] The microcomputer 12051 can calculate a control target value for the drive force generation device, the steering mechanism or the braking device based on information about the interior or external environment of the vehicle, which information is obtained by the unit 12030 for detecting information from outside the vehicle or the unit 12040 for detecting information from inside the vehicle, and can issue a control command to the drive system control unit 12010.For example, the 12051 microcomputer can perform cooperative control intended to implement functions of an Advanced Driver Assistance System (ADAS), the functions of which include collision avoidance or impact mitigation for the vehicle, following based on a following distance, driving at a constant speed, warning of a vehicle collision, warning of a vehicle lane deviation, or the like.

[0179] Furthermore, the microcomputer 12051 can perform cooperative control intended for automated driving, which allows the vehicle to drive autonomously without dependence on driver intervention or the like, by controlling the drive force generation device, steering mechanism, braking device or the like based on information about the external environment or the interior of the vehicle, which information is obtained by the unit 12030 for detecting information from outside the vehicle or the unit 12040 for detecting information from inside the vehicle.

[0180] The microcomputer 12051 can also issue a control command to the body control unit 12020 based on information about the vehicle's external environment, which is obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent (or alternatively reduce) glare by controlling the headlights according to the position of a vehicle ahead or an oncoming vehicle, detected by the external information detection unit 12030, to switch from high beam to low beam.

[0181] The audio / video output section 12052 transmits an output signal of sound and / or image to an output device that can convey information visually or audibly to an occupant of the vehicle or the vehicle's external environment. For example, Fig. 33 are specified as the output device a loudspeaker 12061, a display section 12062 and a dashboard 12063. The display section 12062 can, for example, include a vehicle-mounted display and / or a head-up display.

[0182] Fig. Figure 34 is a diagram illustrating an example of an installation position of the imaging section 12031.

[0183] In Fig. 34 includes the imaging section 12031 imaging sections 12101, 12102, 12103, 12104 and 12105.

[0184] Imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, located at positions on the front of the vehicle 12100, on the side mirrors, on the rear bumper, and on the tailgate, as well as on the upper part of the windshield inside the vehicle. Imaging section 12101 at the front and imaging section 12105 at the upper part of the windshield inside the vehicle primarily receive an image in front of the vehicle 12100. Imaging sections 12102 and 12103 at the side mirrors primarily receive an image of the sides of the vehicle 12100. Imaging section 12104 at the rear bumper or tailgate primarily receives an image behind the vehicle 12100.The imaging section 12105, located on the upper part of the windshield inside, is primarily used to detect a vehicle ahead, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane or the like.

[0185] Note that Fig. Figure 34 illustrates an example of photographic areas of imaging sections 12101 to 12104. An imaging area 12111 represents the imaging area of ​​imaging section 12101 located at the front. Imaging areas 12112 and 12113 represent the imaging areas of imaging sections 12102 and 12103, respectively, located at the side mirrors. An imaging area 12114 represents the imaging area of ​​imaging section 12104 located at the rear bumper or tailgate. For example, a bird's-eye view image, as seen from above, is obtained by superimposing image data captured by imaging sections 12101 to 12104.

[0186] At least one of the imaging sections 12101 to 12104 can have a function for obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera composed of a multitude of imaging elements, or it can be an imaging element containing pixels for phase difference detection.

[0187] The microcomputer 12051 can, for example, determine a distance to any three-dimensional object within the imaging areas 12111 to 12114 and a change in distance over time (relative speed in relation to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby, in particular, extract the nearest three-dimensional object, such as a vehicle traveling ahead, which is on a path of the vehicle 12100 and which is traveling at a predetermined speed (for example, 0 km / h or higher) in essentially the same direction as the vehicle 12100.Furthermore, the 12051 microcomputer can predefine a following distance to be maintained from a vehicle ahead and perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), or similar functions. Consequently, it is possible to execute cooperative control intended for automated driving, allowing the vehicle to drive autonomously without driver intervention.

[0188] The microcomputer 12051 can, for example, classify three-dimensional object data about three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a vehicle of average size, a large vehicle, a pedestrian, a telephone pole, and other three-dimensional objects based on the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually detect and obstacles that are difficult for the driver of vehicle 12100 to visually detect. The microcomputer 12051 then determines a collision risk, which indicates the likelihood of a collision with each obstacle.In a situation where the risk of collision is equal to or greater than a set value, and thus a collision is possible, the microcomputer 12051 issues a warning to the driver via the speaker 12061 or the display section 12062 and initiates a forced braking or evasive steering maneuver via the drive system control unit 12010. The microcomputer 12051 can thus assist the driver in avoiding a collision.

[0189] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared radiation. For example, the microcomputer 12051 can detect a pedestrian by determining whether a pedestrian is present in photographed images from imaging sections 12101 to 12104. Such pedestrian detection is achieved, for example, by a procedure to extract characteristic points from the photographed images of the imaging sections 12101 to 12104 as infrared cameras and a procedure to determine whether it is the pedestrian by performing pattern matching processing on a series of characteristic points that define the object's outline.When the microcomputer 12051 determines that a pedestrian is present in the photographed images from imaging sections 12101 to 12104, and thus detects the pedestrian, the audio / video output section 12052 controls the display section 12062 so that a square outline is displayed for emphasis, superimposed on the detected pedestrian. The audio / video output section 12052 can also control the display section 12062 to display a symbol or similar element representing the pedestrian at a desired position.

[0190] Above, an example of a vehicle control system was described for which the technology according to one embodiment of the present disclosure can be used. The technology according to one embodiment of the present disclosure can be used from the configuration described above for unit 12030 to detect information from outside the vehicle. Specifically, it is possible to use the distance measurement module 100 of Fig. 1 for use in unit 12030 for detecting information from outside the vehicle. The use of the technology according to an embodiment of the present disclosure for unit 12030 for detecting information from outside the vehicle makes it possible to suppress a variation in overvoltage caused by a decrease or increase in the amount of light and to determine accurate distance information.

[0191] Note that the embodiments described above are merely examples of the present technology, and aspects in these embodiments correspond to aspects specifying the respective technology in the claims. Likewise, the aspects specifying the technology in the claims correspond to aspects in the embodiments of the present technology that are given designations identical to those of the aspects specifying the technology in the claims. However, the present technology is not limited to these embodiments and can be embodied by making various modifications to them without departing from the core of the present technology.

[0192] Please note that the effects described in this description are for illustrative purposes only and the technology is not limited to them. Furthermore, other effects may occur.

[0193] Note that the technology in question can also be configured as outlined below. (1) A solid-state image sensor comprising: a photoelectric conversion element comprising an anode and a cathode, wherein either the anode or the cathode is connected to a predetermined node; an element for providing an electrical potential, configured to provide an initial electrical potential to the predetermined node; a time-detection circuit configured to detect a time at which a predetermined time interval has elapsed since the start of an increase or decrease in an electrical potential of the predetermined node from the first electrical potential; a sample-and-hold circuit configured to detect the electrical potential of the predetermined node based on an output from the time-detection circuit and to hold the electrical potential as a second electrical potential; and a control section configured to maintain one electrical potential of the anode and the cathode based on the second electrical potential. (2) The solid-state image sensor according to (1) wherein the time-detection circuit includes an inverter configured to invert a signal of the electrical potential of the predetermined node and to output the inverted signal. (3) The solid-state image sensor according to one or more of (1) to (2), wherein The time detection circuit further includes a pulse signal generation circuit configured to generate a pulse signal based on a signal obtained by delaying the inverted signal by a predetermined delay time, and The sampling and holding circuit detects the electrical potential of the predetermined node within a time span of a pulse width of the pulse signal. (4) The solid-state image sensor according to one or more of (1) to (3), wherein The time-detection circuit further includes a delay circuit configured to delay the inverted signal by a predetermined delay time and to output a delayed signal, and The sampling and holding circuit detects the electrical potential of the predetermined node in the case where the delayed signal is one of two values ​​that are different from each other, and holds the detected electrical potential in the case where the delayed signal is the other of the two values. (5) The solid-state image sensor according to one or more of (1) to (4), wherein the photoelectric conversion element, the time-detection circuit, and the sample-and-hold circuit are installed in a pixel, the installation being carried out with respect to a plurality of pixels, and the control section a section for capturing an interpixel average, configured to calculate as an interpixel average an average of the respective second electrical potentials of the plurality of pixels, and a time-averaged acquisition section configured to calculate a time average of the interpixel average, and It includes a section for controlling an electrical potential, configured to control the electrical potential of the anode and cathode in such a way that the electrical potential decreases as the time average increases. (6) The solid-state image sensor according to one or more of (1) to (5), wherein the time average acquisition section contains an analog filter configured to generate the time average. (7) The solid-state image sensor according to one or more of (1) to (6), wherein the time average acquisition section contains a digital filter configured to generate the time average. (8) The solid-state image sensor according to one or more of (1) to (7), wherein the section for controlling an electrical potential includes an amplifier configured to compare the time average with a predetermined electrical potential of a power source and output a result of the comparison to the other of the anode and the cathode. (9) The solid-state image sensor according to one or more of (1) to (8), wherein the section for controlling an electrical potential includes a power semiconductor configured to control the electrical potential of the anode and the cathode in such a way that the electrical potential decreases as the time average increases. (10) The solid-state image sensor according to one or more of (1) to (9), wherein the section for capturing an intermediate pixel average a capacitor and contains a multitude of resistors connected in parallel between the multitude of pixels and the capacitor. (11) The solid-state image sensor according to one or more of (1) to (10), wherein the section for capturing an intermediate pixel average an analog-to-digital conversion section configured to convert the second electrical potentials into digital signals, and It contains an average value filter configured to calculate an average of the digital signals as the interpixel average. (12) The solid-state image sensor according to one or more of (1) to (11), wherein the analog-to-digital conversion section contains a multitude of analog-to-digital converters configured to convert the second electrical potentials of the pixels, which are different from each other, into the digital signals. (13) The solid-state image sensor according to one or more of (1) to (12), which includes the analog-to-digital conversion section a selector configured to select any one of the respective second electrical potentials of the plurality of pixels, and contains an analog-to-digital converter configured to convert the selected second electrical potential into the digital signal. (14) The solid-state image sensor according to one or more of (1) to (13), further comprising an output-side buffer located between the sampling and holding circuit and the control section. (15) The solid-state image sensor according to one or more of (1) to (14), wherein the output buffer generates a differential signal based on the second electrical potential and outputs the generated differential signal. (16) The solid-state image sensor according to one or more of (1) to (15), further comprising an input-side buffer that is positioned between the predetermined node and the sample-and-hold circuit. (17) The solid-state image sensor according to one or more of (1) to (16), wherein the input-side buffer generates a differential signal based on the second electrical potential and outputs the generated differential signal. (18) The solid-state image sensor according to one or more of (1) to (17) wherein the photoelectric conversion element and the element for providing an electrical potential are installed in each of an imaging pixel circuit and a monitoring pixel circuit around the imaging pixel circuit and The time-detection circuit and the sample-and-hold circuit are installed in the monitoring pixel circuit. (19) The solid-state image sensor according to one or more of (1) to (18), wherein the cathode is connected to the predetermined node and The control section controls an electrical potential of the anode. (20) The solid-state image sensor according to one or more of (1) to (19), wherein the anode is connected to the predetermined node and The control section controls an electrical potential of the cathode. (21) A distance measuring system comprising: a light emission section configured to provide irradiation light; and a solid-state image sensor containing a photoelectric conversion element comprising an anode and a cathode, wherein either the anode or the cathode is connected to a predetermined node; an element for providing an electrical potential configured to provide a first electrical potential to the predetermined node; a time-detection circuit configured to detect a time at which a predetermined time interval has elapsed since the start of an increase or decrease in an electrical potential of the predetermined node from the first electrical potential; a sample-and-hold circuit configured to acquire the electrical potential of the predetermined node based on an output from the time-detection circuit and to hold the electrical potential as a second electrical potential; a control section configured toto control an electrical potential of another of the anode and the cathode based on the second electrical potential, and a distance measurement section configured to measure a distance based on a period of time between a light emission time of the irradiation light and a light reception time of the reflected light corresponding to the irradiation light. (22) A light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to a cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and a control circuit coupled to an output of the first circuit and configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit. (23) The light-detecting device according to (22), wherein the control circuit is configured to control a potential of an anode of the second avalanche photodiode based on the output of the first circuit. (24) The light-detecting device according to one or more of (22) to (23), further comprising: a third pixel circuit arrangement that a third avalanche photodiode, a second delay circuit which has an input coupled to a potential of a cathode of the third avalanche photodiode, and a second circuit which includes a third input coupled to the cathode of the third avalanche photodiode and a fourth input coupled to an output of the second delay circuit. (25) The light-detecting device according to one or more of (22) to (24), wherein the control circuit includes an averaging circuit coupled to the output of the first circuit and an output of the second circuit and configured to average the outputs of the first circuit and the second circuit to provide an inter-pixel average signal. (26) The light-detecting device according to one or more of (22) to (25), wherein the control circuit includes a time-averaged value circuit which has an input coupled to an output of the averaged value circuit and is configured to output a time-averaged signal based on the inter-pixel average signal. (27) The light-detecting device according to one or more of (22) to (26), wherein the control circuit includes a potential controller coupled to the anode of the first avalanche photodiode. (28) The light-detecting device according to one or more of (22) to (27), wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode so that it is lower when the time-averaged signal increases, and wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode so that it is higher when the time-averaged signal decreases. (29) The light-detecting device according to one or more of (22) to (28), wherein the control circuit includes an analog-to-digital converter configured to convert the time-averaged signal into a digital signal, and wherein the potential controller includes power electronics configured to control the potential of the anode of the first avalanche photodiode based on the digital signal. (30) The light-detecting device according to one or more of (22) to (29), wherein the average-value circuit includes a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit. (31) The light-detecting device according to one or more of (22) to (30), wherein the first circuit includes a holding circuit which includes a switch and a capacitor. (32) The light-detecting device according to one or more of (22) to (31), wherein the first circuit includes a first buffer circuit and a second buffer circuit, wherein the first buffer circuit is coupled between the cathode of the second avalanche photodiode and the holding circuit, and wherein the holding circuit is coupled between the first buffer circuit and the second buffer circuit. (33) The light-detecting device according to one or more of (22) to (32), wherein the first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode in order to output a first pair of differential signals containing a first positive signal and a first negative signal, wherein the holding circuit is configured to output the first positive signal according to the first delay signal, and wherein the second buffer circuit is configured to buffer the first negative signal and the first positive signal in order to output a second pair of differential signals containing a second positive signal and a second negative signal. (34) The light-detecting device according to one or more of (22) to (33), wherein the control circuit includes an average value circuit which an analog-to-digital converter (ADC) having a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive signal and the second negative signal, a first capacitor coupled to the first input of the ADC, and has a second capacitor that is coupled to the second input of the ADC. (35) The light-detecting device according to one or more of (22) to (34), wherein the first buffer circuit comprises a first current source and a first transistor coupled to the first current source and a second current source and a second transistor coupled to the second current source. (36) The light-detecting device according to one or more of (22) to (35), wherein the first transistor is coupled to a node configured to receive the potential of the cathode of the second avalanche photodiode and configured to output the first positive signal according to a current from the first current source, and wherein the second transistor is coupled to a node configured to receive a ground signal and configured to output the first negative signal according to a current from the second current source. (37) The light-detecting device according to one or more of (22) to (36), wherein the second buffer circuit includes a third current source and a third transistor coupled to the third current source and a fourth current source and a fourth transistor coupled to the fourth current source. (38) The light-detecting device according to one or more of (22) to (37), wherein the third transistor is configured to receive the first positive signal and to output the second positive signal according to a current from the third current source, and wherein the fourth transistor is configured to receive the first negative signal and to output the second negative signal according to a current from the fourth current source. (39) A light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit configured to generate a first delay signal based on a first potential of a cathode of the second avalanche photodiode, and a first circuit configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal; and a control circuit configured to control a potential of an anode of the first avalanche photodiode based on the sampled second potential output by the first circuit. (40) A system comprising: a light source; and a light-detecting device that a first pixel circuit arrangement containing a first avalanche photodiode, a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to a cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and includes a control circuit that is coupled to an output of the first circuit and is configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit. (41) A light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to an anode of the second avalanche photodiode; and a first circuit comprising a first input coupled to the anode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and a control circuit coupled to an output of the first circuit and configured to control a potential of a cathode of the first avalanche photodiode based on the output of the first circuit.

[0194] It should be understood by the person skilled in the art that, depending on design requirements and other factors, various modifications, combinations, partial combinations and changes may occur, provided they are within the scope of the attached claims or their equivalents. [List of reference symbols] 100 Distance measuring module 110 Light Emission Section 120 Synchronization Control Section 200 solid-state image sensor 201 pixel chip 202 Circuit chip 210 light-receiving section 211, 212 photoelectric conversion element 220 Time-Generation Section 231, 232 Multiplexer 241, 242 Time-to-Digital Converter 250 Histogram generation section 260 output interface 300 circuit block 310 surveillance pixel circuit 311, 342, 344, 356, 357, 362, 363, 373, 381 pMOS transistors 320 Time-detection circuit 321, 376, 379, 382 Inverter 322 Flipflop 330 Sampling and Hold Circuit 331 scanning switches 332, 375, 512, 518, 519 capacitor 340, 350 buffer 341, 343, 352, 354, 355, 361, 372 electrical power source 370 Impulse generation circuit 371, 377 Delay circuit 351, 353, 374 nMOS transistor 378 NAND gates 380 imaging pixel circuit 400 pixel array section 401 surveillance pixels 402 imaging pixels 500 Control section 510 Section for capturing an intermediate pixel average 511 Resistor 513 Analog-to-Digital Conversion Section 514, 517, 523, 532 ADC 515 Average Value Filter 516 Selector 520 Time Average Recording Section 521 variable resistor 522 variable capacitor 524 digital low-pass filter 530 Section for controlling an electrical potential 531 amplifiers 533 Power IC 12031 Imaging Section

Claims

[1] Light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to a cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and a control circuit coupled to an output of the first circuit and configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit. [2] Light-detecting device according to claim 1, wherein the control circuit is configured to control a potential of an anode of the second avalanche photodiode based on the output of the first circuit. [3] Light-detecting device according to claim 1, further comprising: a third pixel circuit arrangement that a third avalanche photodiode, a second delay circuit which has an input coupled to a potential of a cathode of the third avalanche photodiode, and a second circuit containing a third input coupled to the cathode of the third avalanche photodiode and a fourth input coupled to an output of the second delay circuit. [4] Light-detecting device according to claim 3, wherein the control circuit includes an averaging circuit coupled to the output of the first circuit and an output of the second circuit and configured to average the outputs of the first circuit and the second circuit to provide an inter-pixel average signal. [5] Light-detecting device according to claim 4, wherein the control circuit includes a time-averaged value circuit which has an input coupled to an output of the averaged value circuit and is configured to output a time-averaged signal based on the inter-pixel average signal. [6] Light-detecting device according to claim 5, wherein the control circuit includes a potential controller coupled to the anode of the first avalanche photodiode. [7] Light-detecting device according to claim 6, wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode such that it is lower when the time-averaged signal increases, and wherein the potential controller is configured to control the potential of the anode of the first avalanche photodiode such that it is higher when the time-averaged signal decreases. [8] Light-detecting device according to claim 6, wherein the control circuit includes an analog-to-digital converter configured to convert the time-averaged signal into a digital signal, and wherein the potential controller includes power electronics configured to control the potential of the anode of the first avalanche photodiode based on the digital signal. [9] Light-detecting device according to claim 6, wherein the average value circuit includes a capacitor, a first resistor coupled between the capacitor and the first delay circuit, and a second resistor coupled between the capacitor and the second delay circuit. [10] Light-detecting device according to claim 1, wherein the first circuit includes a holding circuit which includes a switch and a capacitor. [11] Light-detecting device according to claim 10, wherein the first circuit comprises a first buffer circuit and a second buffer circuit, wherein the first buffer circuit is coupled between the cathode of the second avalanche photodiode and the holding circuit and wherein the holding circuit is coupled between the first buffer circuit and the second buffer circuit. [12] Light-detecting device according to claim 11, wherein the first buffer circuit is configured to buffer the potential of the cathode of the second avalanche photodiode in order to output a first pair of differential signals containing a first positive signal and a first negative signal, wherein the holding circuit is configured to output the first positive signal according to the first delay signal, and wherein the second buffer circuit is configured to buffer the first negative signal and the first positive signal in order to output a second pair of differential signals containing a second positive signal and a second negative signal. [13] Light-detecting device according to claim 12, wherein the control circuit includes an average value circuit which an analog-to-digital converter (ADC) having a first input configured to receive the second positive signal, a second input configured to receive the second negative signal, and an output configured to output a digital signal based on the second positive signal and the second negative signal, a first capacitor coupled to the first input of the ADC, and It contains a second capacitor that is coupled to the second input of the ADC. [14] Light-detecting device according to claim 12, wherein the first buffer circuit comprises a first current source and a first transistor coupled to the first current source and a second current source and a second transistor coupled to the second current source. [15] Light-detecting device according to claim 14, wherein the first transistor is coupled to a node configured to receive the potential of the cathode of the second avalanche photodiode and configured to output the first positive signal according to a current from the first current source, and wherein the second transistor is coupled to a node configured to receive a ground signal and configured to output the first negative signal according to a current from the second current source. [16] Light-detecting device according to claim 14, wherein the second buffer circuit includes a third current source and a third transistor coupled to the third current source and a fourth current source and a fourth transistor coupled to the fourth current source. [17] Light-detecting device according to claim 16, wherein the third transistor is configured to receive the first positive signal and to output the second positive signal according to a current from the third current source, and wherein the fourth transistor is configured to receive the first negative signal and to output the second negative signal according to a current from the fourth current source. [18] Light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit configured to generate a first delay signal based on a first potential of a cathode of the second avalanche photodiode, and a first circuit configured to sample a second potential of the cathode of the second avalanche photodiode and output the sampled second potential based on the first delay signal; and a control circuit configured to control a potential of an anode of the first avalanche photodiode based on the sampled second potential output by the first circuit. [19] System, exhibiting: a light source; and a light-detecting device that a first pixel circuit arrangement containing a first avalanche photodiode, a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to a cathode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the cathode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and includes a control circuit that is coupled to an output of the first circuit and is configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit. [20] Light-detecting device comprising: a first pixel circuit arrangement containing a first avalanche photodiode; a second pixel circuit arrangement that a second avalanche photodiode, a first delay circuit which has an input coupled to an anode of the second avalanche photodiode, and a first circuit comprising a first input coupled to the anode of the second avalanche photodiode and a second input coupled to an output of the first delay circuit; and a control circuit coupled to an output of the first circuit and configured to control a potential of a cathode of the first avalanche photodiode based on the output of the first circuit.

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