Signal processing device, signal processing method, and program

Abstract

The present invention provides a signal processing device, a signal processing method, and a program that suppress the reduction in throughput in the average value calculation process, which calculates the average value of data propagating through an optical fiber for each channel. [Solution] The signal processing device includes a supply unit that supplies the same clock to the multiple ADCs when the multiple signals input to each of the multiple ADCs are not the same, and supplies the multiple ADCs with clocks that are not the same when the multiple signals are the same, and an average value output unit that outputs the average of the multiple digital values ​​output from each of the multiple ADCs as a first average value when the multiple signals are not the same, and outputs the average of the first average values ​​in the multiple ADCs as a second average value when the multiple signals are the same.

Description

Technical Field

[0001] The present disclosure relates to a signal processing apparatus, a signal processing method, and a program.

Background Art

[0002] Patent Document 1 discloses a technique for reducing crosstalk between cores of an optical fiber using MIMO (Multiple-Input Multiple-Output) technology.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The preprocessing of MIMO includes an average value calculation process for calculating the average value of data received via an optical fiber for each channel. When the number of channels of the second optical fiber is less than the number of channels of the first optical fiber and the same number of average value calculation units as the number of channels of the first optical fiber are used, the throughput of the average value calculation process for the data transmitted via the second optical fiber decreases.

[0005] The present disclosure has been made to solve such problems, and an object thereof is to provide a signal processing apparatus, a signal processing method, and a program that suppress a decrease in throughput in an average value calculation process for calculating the average value of data transmitted by an optical fiber for each channel.

Means for Solving the Problems

[0006] The signal processing apparatus according to the present disclosure is A supply unit that, when multiple signals input to multiple ADCs (Analog-to-Digital Converters) are not identical to each other, supplies the same clock to the multiple ADCs, and when multiple signals are identical to each other, supplies the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average value output unit outputs the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, as a first average value; if the multiple signals are identical to each other, the average value of the first average values ​​from the multiple ADCs is output as a second average value. It is equipped with.

[0007] The signal processing method relating to this disclosure is: If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the same clock is supplied to each of the multiple ADCs; if the multiple signals are identical to each other, different clocks are supplied to each of the multiple ADCs. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, is output as the first average value. If the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value.

[0008] The program related to this disclosure is If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the process involves supplying the same clock to each of the multiple ADCs, and if the multiple signals are identical to each other, supplying the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, is output as the first average value; if the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value. Have the computer execute it. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide a signal processing device, a signal processing method, and a program that suppress the reduction in throughput in an average value calculation process that calculates the average value of data transmitted by optical fiber for each channel. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram illustrates an example of processing for data transmitted via MCF. [Figure 2] This diagram illustrates an example of processing data transmitted via SCF. [Figure 3] This is a block diagram illustrating the configuration of the signal processing device described herein. [Figure 4] This is a flowchart illustrating the signal processing method described herein. [Figure 5] This is a block diagram illustrating the configuration of the signal processing device described herein. [Figure 6] This diagram illustrates the operation of the MIMO preprocessing circuit described herein. [Figure 7] This is a block diagram illustrating the configuration of the signal processing device described herein. [Figure 8] This diagram illustrates the DC offset processing when data is transmitted via MCF. [Figure 9] This diagram illustrates the DC offset processing when data is transmitted via SCF. [Figure 10] This diagram illustrates the process of calculating the second average value when there are four ADCs. [Figure 11] This is a block diagram illustrating the configuration of the average value calculation unit related to this disclosure. [Figure 12] This is a block diagram illustrating the hardware configuration of the signal processing device described herein.

Mode for Carrying Out the Invention

[0011] Background Leading to the Embodiment FIG. 1 is a diagram for explaining an example of processing data transmitted via an MCF (Multi Core Fiber). The MCF includes a first core and a second core.

[0012] The signal processing apparatus 10 includes a clock generation unit 11, ADCs (Analog-to-Digital Converters) 121 to 124, MIMO (Multiple-Input Multiple-Output) preprocessing circuits 131 to 134, and a MIMO circuit 14. When not distinguishing between ADCs 121 to 124 from each other, they may simply be referred to as ADC 12. When not distinguishing between MIMO preprocessing circuits 131 to 134 from each other, they may simply be referred to as MIMO preprocessing circuit 13.

[0013] The clock generation unit 11 generates a 16 GHz clock. The clock generation unit 11 supplies the clock to ADCs 121 to 124.

[0014] An x polarization component (also referred to as x data) of the signal light transmitted via the first core is input to ADC 121. The x data is an analog signal. ADC 121 samples the x data of the first core at the edge of the clock, converts the sampled x data into a digital value (also referred to as a sample), and outputs it to MIMO preprocessing circuit 131.

[0015] A y polarization component (also referred to as y data) of the signal light transmitted via the first core is input to ADC 122. The y data is an analog signal. ADC 122 samples the y data of the first core at the edge of the clock, converts the sampled y data into a digital value, and outputs it to MIMO preprocessing circuit 132. When not distinguishing between x data and y data from each other, they may simply be referred to as data.

[0016] The x data from the second core is input to ADC123. ADC123 samples the x data from the second core at the clock edge, converts the sampled x data into a digital value, and outputs it to MIMO preprocessing circuit 133.

[0017] The ADC124 receives the y data from the second core. The ADC124 samples the y data from the second core at the clock edge, converts the sampled y data into a digital value, and outputs it to the MIMO preprocessing circuit 134.

[0018] The MIMO preprocessing circuit 13 performs preprocessing on the digital values ​​output from the corresponding ADC 12 for MIMO processing. The preprocessing includes an average value calculation process to calculate the average value of the digital values. The MIMO preprocessing circuit 13 outputs the preprocessed data to the MIMO circuit 14. The MIMO circuit 14 performs MIMO processing using the preprocessed data.

[0019] The sampling rate of each ADC 121-124 is 16 Gsps (samples per second). Each of the MIMO preprocessing circuits 131-134 outputs a preprocessed sample. The output of each of the MIMO preprocessing circuits 131-134 is also 16 Gsps.

[0020] Figure 2 illustrates an example of processing data transmitted via an SCF (Single Core Fiber). The SCF includes a first core. Explanations that overlap with those in Figure 1 are omitted.

[0021] The x data from the first core is input to the ADC121. The ADC121 samples the x data from the first core at the clock edge, converts the sampled x data into a digital value, and outputs it to the MIMO preprocessing circuit 131.

[0022] The ADC122 receives the y data from the first core as input. The ADC122 samples the y data from the first core at the clock edge, converts the sampled x data into a digital value, and outputs it to the MIMO preprocessing circuit 132.

[0023] The x data from the first core is input to the ADC123. The ADC123 samples the x data from the first core at the clock edge, converts the sampled x data into a digital value, and outputs it to the MIMO preprocessing circuit 133.

[0024] The ADC124 receives the y data from the first core as input. The ADC124 samples the y data from the first core at the clock edge, converts the sampled y data into a digital value, and outputs it to the MIMO preprocessing circuit 134.

[0025] ADCs 121 and 123 perform AD conversion on the same data. MIMO preprocessing circuits 131 and 133 perform MIMO preprocessing on the same data. Therefore, the MIMO preprocessing results output from MIMO preprocessing circuits 131 and 133 are identical. Similarly, the MIMO preprocessing results output from MIMO preprocessing circuits 132 and 134 are also identical. Consequently, the output of MIMO preprocessing circuits 131 and 133 is 16 Gsps, and the output of MIMO preprocessing circuits 132 and 134 is also 16 Gsps. In other words, the output of MIMO preprocessing circuits 131-134 drops from 64 Gsps to 32 Gsps.

[0026] Thus, the related signal processing device 10 has a problem in that throughput decreases when MIMO processing is performed on data transmitted via SCF. The inventors of the present invention conceived of the signal processing device according to this disclosure from the problems of the signal processing device 10.

[0027] The specific configuration of this embodiment will be described below with reference to the drawings. The following description illustrates preferred embodiments of the present invention, and the scope of the present invention is not limited to these embodiments. In the following description, the same reference numerals indicate substantially the same function.

[0028] Embodiment 1 Figure 3 is a block diagram showing an example configuration of the signal processing device 100 according to this disclosure. The signal processing device 100 may be a computer that operates by a processor executing a program stored in memory, or it may be an electronic circuit.

[0029] The signal processing device 100 includes a supply unit 101 and an average value output unit 102. The supply unit 101 and the average value output unit 102 may be software or modules whose processing is performed by the processor executing a program stored in memory. Alternatively, the supply unit 101 and the average value output unit 102 may be hardware such as an electronic circuit or a semiconductor chip.

[0030] The supply unit 101 supplies the same clock to multiple ADCs if the multiple signals input to each ADC are not the same. If the multiple signals are the same, the supply unit 101 supplies the multiple ADCs with clocks that are not the same. The supply unit 101 may be a selector circuit that selects which clock to supply to the ADCs. Alternatively, the supply unit 101 may be a control unit that transmits a control signal to adjust the phase of the clock.

[0031] The average value output unit 102 outputs the average of multiple digital values ​​output from one ADC, which is each of the multiple ADCs, as the first average value when the multiple signals are not identical to each other. The average value output unit 102 outputs the average of the first average values ​​from the multiple ADCs as the second average value when the multiple signals are identical to each other. The average value output unit 102 may be a selector circuit, or it may be an arithmetic unit that calculates the first and second average values.

[0032] Figure 4 is a flowchart illustrating the signal processing method according to this disclosure. First, the supply unit 101 supplies a clock to the multiple ADCs based on whether the signals input to the multiple ADCs are identical to each other (step S101). Next, the average value output unit 102 outputs a first average value or a second average value based on whether the signals input to the multiple ADCs are identical to each other (step S102).

[0033] As explained above, when identical signals are input to the ADC, the signal processing device 100 supplies the ADC with clocks that are not identical to each other and calculates a second average value. As a result, since multiple ADCs can process non-identical data while calculating a single average value, the signal processing device 100 can suppress a decrease in throughput.

[0034] Embodiment 2 Embodiment 2 is a specific example of Embodiment 1. Figure 5 is a block diagram illustrating the configuration of the signal processing device 200 according to the present disclosure. Comparing Figure 1 and Figure 5, the signal processing device 200 further comprises splitters 151-152, analog switches 161-162, a phase adjuster 17, and a selector 18. When the splitters 151-152 are not distinguished from each other, they may simply be referred to as splitter 15. When the analog switches 161-162 are not distinguished from each other, they may simply be referred to as analog switch 16. The selector 18 corresponds to the supply unit 101 described above.

[0035] Each component of the signal processing device 200 may be software or a module whose processing is performed by the processor executing a program stored in memory. Alternatively, each component of the signal processing device 200 may be hardware such as a circuit or a semiconductor chip.

[0036] The x and y data of the first core shown in Figure 5 may be the data of the first core of the SCF or the data of the first core of the MCF. The x and y data of the second core are the data of the second core of the MCF. When data is transmitted via the SCF, the x and y data of the second core do not need to be input to the analog switch 16.

[0037] The x-data from the first core is input to splitter 151. The y-data from the first core is input to splitter 152. The x-data from the second core is input to analog switch 161. The y-data from the second core is input to analog switch 162.

[0038] The splitter 151 splits the x data of the first core into two data points. One of the two data points is input to the ADC 121. The other data point is input to the analog switch 161.

[0039] The splitter 152 splits the y data of the first core into two data points. One of the two data points is input to the ADC 122. The other data point is input to the analog switch 162.

[0040] When data is transmitted via SCF, analog switch 161 outputs x data from the first core of SCF to ADC 123. When data is transmitted via MCF, analog switch 161 outputs x data from the second core of MCF to ADC 123.

[0041] When data is transmitted via SCF, analog switch 162 outputs the y data of the first core of SCF to ADC 124. When data is transmitted via MCF, analog switch 162 outputs the y data of the second core of MCF to ADC 124.

[0042] The phase adjuster 17 adjusts the phase of the clock generated by the clock generation unit 11. The phase adjuster is also called the phase adjustment unit. The phase adjuster 17 outputs a first clock and a second clock. The first clock is a clock whose phase has been changed by 0° from the clock generated by the clock generation unit 11. In other words, the first clock is a clock generated by the clock generation unit 11. The second clock is a clock whose phase has been changed by 180° from the clock generated by the clock generation unit 11.

[0043] The phase adjuster 17 outputs a first clock to ADC 123, ADC 124, and selector 18. The phase adjuster 17 also outputs a second clock to selector 18.

[0044] Selector 18 selects either the first clock or the second clock and supplies the selected clock to ADCs 121 and 122. When data is transmitted via SCF, selector 18 selects the second clock. When data is transmitted via MCF, selector 18 selects the first clock.

[0045] Therefore, the timing at which ADC123 samples the x data of the first core of the SCF is not the same as the timing at which ADC121 samples the x data of the first core of the SCF. The timing at which ADC124 samples the y data of the first core of the SCF is not the same as the timing at which ADC122 samples the y data of the first core of the SCF. Therefore, the value sampled by ADC121 is not the same as the value sampled by ADC123. The value sampled by ADC122 is not the same as the value sampled by ADC124. The signal processing device 200 can achieve a throughput of (16+16)Gsps×2=64Gsps even for data transmitted through one core.

[0046] The signal processing device 200 may include a control unit (not shown) that transmits a selection signal to the selector 18. The control unit may further transmit selection signals to selectors 1313, 1333, and 28, which will be described later. The control unit may transmit control signals to analog switches 161 and 162.

[0047] The signal processing device 200 may include a receiving unit (not shown) that receives x data and y data via an MCF or SCF. The receiving unit may perform coherent detection, separating the signal light transmitted via the MCF or SCF into x-polarized and y-polarized components, and interfering each polarization component with local light emission to detect the signal (e.g., x data, y data).

[0048] Data transmitted through one channel of an optical fiber other than the SCF may be input to splitter 151 or 152. One channel may correspond to one core of the SCF.

[0049] Data transmitted through a first channel of an optical fiber other than the MCF may be input to the splitter 151, and data transmitted through a second channel of an optical fiber other than the MCF may be input to the analog switch 161. Data transmitted through a first channel of an optical fiber other than the MCF may be input to the splitter 152, and data transmitted through a second channel of an optical fiber other than the MCF may be input to the analog switch 162. Multiple channels, including the first channel and the second channel, may each correspond to multiple cores of the MCF.

[0050] Figure 6 is a diagram illustrating the operation of MIMO preprocessing circuits 131 and 133. MIMO preprocessing circuit 131 comprises an arithmetic circuit 1311, an average value calculation unit 1312, a selector 1313, and an arithmetic circuit 1314. MIMO preprocessing circuit 133 comprises an arithmetic circuit 1331, an average value calculation unit 1332, a selector 1333, and an arithmetic circuit 1334. Selectors 1313 and 1333 correspond to the average value output unit 102 described above.

[0051] The signal processing device 200 includes an adder 21 and a bit shift operation unit 22.

[0052] The average value calculation unit 1312 calculates the average value (also referred to as the first average value) of the data acquired from the ADC 121 via the arithmetic circuit 1311. The arithmetic circuit 1311 may also perform processes such as removing noise from the data output from the ADC 121.

[0053] The average value calculation unit 1332 calculates the average value (also referred to as the first average value) of the data acquired from the ADC 123 via the arithmetic circuit 1331. The arithmetic circuit 1331 may also perform processes such as removing noise from the data output from the ADC 123.

[0054] The adder 21 calculates the sum of the average values ​​calculated by the average value calculation unit 1312 and the average values ​​calculated by the average value calculation unit 1332. The bit shift calculation unit 22 performs an operation to divide the sum calculated by the adder 21 by the number of ADCs that receive the same data (e.g., 2). The bit shift calculation unit 22, for example, shifts the sum calculated by the adder 21 one bit to the right. The calculation result by the bit shift calculation unit 22 represents the average of the average values ​​calculated by the average value calculation unit 1312 and the average values ​​calculated by the average value calculation unit 1332 (also called the second average value). The second average value is the average of the data including the data sampled by ADC 121 and the data sampled by ADC 123.

[0055] The selector 1313 selects either the first average value calculated by the average value calculation unit 1312 or the second average value calculated by the bit shift calculation unit 22, and outputs the selected average value to the calculation circuit 1314. When data is transmitted via MCF, the selector 1313 selects the first average value. When data is transmitted via SCF, the selector 1313 selects the second average value. The calculation circuit 1314 performs calculations using the average value.

[0056] The selector 1333 selects either the first average value calculated by the average value calculation unit 1332 or the second average value calculated by the bit shift calculation unit 22, and outputs the selected average value to the calculation circuit 1334. When data is transmitted via MCF, the selector 1333 selects the first average value. When data is transmitted via SCF, the selector 1333 selects the second average value. The calculation circuit 1334 performs calculations using the average value.

[0057] The operation of MIMO preprocessing circuits 132 and 134 is the same as that of MIMO preprocessing circuits 131 and 133. Figure 7 is a block diagram illustrating the configuration of the signal processing device 200 according to this disclosure. Comparing Figure 5 and Figure 7, Figure 7 adds the above-mentioned adder 21 and bit shift operation unit 22. In addition, an adder 31 and a bit shift operation unit 32 are added. The adder 31 calculates the sum of the average values ​​calculated by MIMO preprocessing circuit 132 and the average values ​​calculated by MIMO preprocessing circuit 134. The bit shift operation unit 32 performs an operation to divide the sum calculated by the adder 31 by the number of ADCs (e.g., 2) that receive the same data from each other.

[0058] MIMO preprocessing includes, for example, DC (Direct Current) offset processing, normalization processing, distortion compensation processing, and chromatic dispersion compensation. Figure 8 illustrates the DC offset processing when data is transmitted via MCF. Note that the MIMO preprocessing circuit 131 may perform processing other than DC offset processing (e.g., normalization processing) using the average value.

[0059] The MIMO preprocessing circuit 131 includes an average value calculation unit 1312, a data holding circuit 1315, and an arithmetic circuit 1314. If the data acquired by the MIMO preprocessing circuit 131 is A, the data holding circuit 1315 holds data A. Data A may contain multiple digital values. The average value calculation unit 1312 calculates the average value B, which is the average value of data A. The arithmetic circuit 1314 subtracts the average value B from data A and outputs the subtraction result as the arithmetic result C. The MIMO preprocessing circuit 133 operates in the same manner as the MIMO preprocessing circuit 131.

[0060] Figure 9 is a diagram illustrating DC offset processing when data is transmitted via SCF. The MIMO preprocessing circuit 133 includes an average value calculation unit 1332, a data holding circuit 1335, and an arithmetic circuit 1334. If the data acquired by the MIMO preprocessing circuit 133 is A', the data holding circuit 1335 holds the data A'. The average value calculation unit 1332 calculates the average value B', which is the average value of the data A'.

[0061] The addition unit 21 and the bit shift operation unit 22 calculate the average value D from the average value B calculated by the average value calculation unit 1312 and the average value B' calculated by the average value calculation unit 1332.

[0062] The calculation circuit 1314 of the MIMO preprocessing circuit 131 subtracts the average value D selected by the selector 1313 from the data A held by the data holding circuit 1315, and outputs the subtraction result as calculation result C. The calculation circuit 1334 of the MIMO preprocessing circuit 133 subtracts the average value D selected by the selector 1333 from the data A' held by the data holding circuit 1335, and outputs the subtraction result as calculation result C'. The calculation circuits 1314 and 1334 are also referred to as offset adjustment units.

[0063] The number of ADC12s that receive the same data input to each other, for example, the number of cores in the MCF, may be 3 or more (e.g., 4, 12). Figure 10 is a diagram illustrating the process of calculating a second average value when there are 4 ADC12s that receive the same data input to each other. The signal processing device 200 shown in Figure 10 includes MIMO preprocessing circuits 131, 133, 135, 137, an adder 211, 212, 213, and a bit shift operation unit 22.

[0064] The adder 211 calculates the sum of the first average values ​​calculated by the MIMO preprocessing circuit 131 and the first average values ​​calculated by the MIMO preprocessing circuit 133. The adder 212 calculates the sum of the first average values ​​calculated by the MIMO preprocessing circuit 135 and the first average values ​​calculated by the MIMO preprocessing circuit 137. The adder 213 calculates the sum of the first average values ​​calculated by the MIMO preprocessing circuits 131, 133, 135, and 137 by adding the sum calculated by the adder 211 and the sum calculated by the adder 212. The bit shift operation unit 22 calculates the second average value by shifting the sum of the first average values ​​calculated by the adder 213 two bits to the right.

[0065] Referring again to Figure 9, the number of samples input as data A or A' when data is transmitted via SCF (e.g., 100) may be half the number of samples input as data A or A' when data is transmitted via MCF (e.g., 200). When data is transmitted via SCF, the amount of data processed by the averaging unit 1312 per cycle is, for example, 2 data / 1 cycle. When data is transmitted via MCF, the amount of data processed by the averaging unit 1312 per cycle is, for example, 4 data / 1 cycle. The averaging unit 1312 may be configured to calculate the average value of non-identical amounts of data.

[0066] In general, if the signals input to ADC121 and 123 are not identical, the average value calculation unit 1312 may receive m digital values ​​per cycle. If the signals input to ADC121 and 123 are identical, the average value calculation unit 1312 may receive n digital values ​​per cycle. m and n are integers greater than or equal to 2, and m is an integer multiple of n. m / n corresponds to the number of ADC12s to which identical signals are input.

[0067] Figure 11 is a block diagram illustrating the configuration of the average value calculation unit 1312. The average value calculation unit 1312 comprises addition units 23, 24, and 25, bit shift operation units 26 and 27, and a selector 28. The selector 28 is also referred to as the selection unit.

[0068] When data is transmitted via SCF, ADC121 outputs data0~1 to average value calculation unit 1312. When data is transmitted via MCF, ADC121 outputs data0~3 to average value calculation unit 1312. Adder 23 calculates the sum of data0~1. Adder 24 calculates the sum of data2~3. Adder 25 adds the sum calculated by adder 23 and the sum calculated by adder 24 to calculate the sum of data0~3. Bit shift calculation unit 26 shifts the sum of data0~1 calculated by adder 25 one bit to the right. In other words, bit shift calculation unit 26 calculates the average value of the sum of data0~1 divided by 2. Bit shift calculation unit 27 shifts the sum of data0~3 calculated by adder 25 two bits to the right. In other words, bit shift calculation unit 27 calculates the average value of the sum of data0~3 divided by 4. Selector 28 selects either the average value calculated by bit shift calculation unit 26 or the average value calculated by bit shift calculation unit 27, and outputs the selected average value. Selector 28 selects the average value calculated by bit shift calculation unit 26 when data is transmitted via SCF. Selector 28 selects the average value calculated by bit shift calculation unit 27 when data is transmitted via MCF.

[0069] Embodiment 2 makes it possible to make the data transfer rate (baud rate) of the MIMO preprocessing circuit the same when data is transmitted through two cores and when data is transmitted through one core. Embodiment 2 can calculate the average value of data transmitted through each of multiple types of optical fibers with different numbers of cores. In other words, it is not necessary to manufacture a signal processing device corresponding to the number of cores of the optical fiber, and the manufacturing cost of the signal processing device can be reduced.

[0070] Figure 12 is a block diagram showing an example of the hardware configuration of signal processing devices 100 and 200 (hereinafter referred to as signal processing devices 100, etc.). Referring to Figure 12, signal processing devices 100, etc. include a network interface 1001, a processor 1002, and memory 1003. The network interface 1001 is used to communicate with other network node devices that constitute the communication system.

[0071] The processor 1002 reads and executes software (computer programs) from memory 1003, thereby performing the processes shown in steps S101 to S102 of Figure 4. The processor 1002 may be, for example, a microprocessor, an MPU, or a CPU. The processor 1002 may include multiple processors.

[0072] Memory 1003 is composed of a combination of volatile and non-volatile memory. Memory 1003 may also include storage located away from the processor 1002. In this case, the processor 1002 may access memory 1003 via an I / O (Input / Output) interface, which is not shown.

[0073] In the example shown in Figure 12, memory 1003 is used to store a group of software modules. The processor 1002 can perform the processing in steps S101 to S102 by reading these software modules from memory 1003 and executing them.

[0074] As explained with reference to Figure 12, each of the processors in the signal processing device 100, etc., in the above-described embodiment executes one or more programs that include a set of instructions for causing a computer to perform the algorithm described with reference to the drawings.

[0075] In the examples described above, the program includes a set of instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically or otherwise propagating signals.

[0076] Furthermore, the technical concepts in this disclosure are not limited to the embodiments described above, and may be modified as appropriate without departing from the spirit of the invention.

[0077] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0078] Each drawing is merely illustrative to illustrate one or more embodiments. Each drawing may be associated with one or more other embodiments rather than with only one specific embodiment. As those skilled in the art will understand, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings, for example, to create embodiments not explicitly shown or described. Not all features or steps shown in any one drawing to illustrate an exemplary embodiment are necessarily required, and some features or steps may be omitted. The order of steps shown in any of the drawings may be changed as appropriate.

[0079] Some or all of the above embodiments may also be described as follows, but are not limited to the following:

[0080] Some or all of the elements (e.g., configuration and function) described in Appendices 2 to 8 that are dependent on Appendice 1 may also be dependent on Appendices 9 and 10 in the same way as those described in Appendices 2 to 8. Some or all of the elements described in any appendice may be applicable to various hardware, software, recording means, systems, and methods for recording software.

[0081] (Note 1) A supply unit that, when multiple signals input to multiple ADCs (Analog-to-Digital Converters) are not identical to each other, supplies the same clock to the multiple ADCs, and when multiple signals are identical to each other, supplies the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average value output unit outputs the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, as a first average value; if the multiple signals are identical to each other, the average value of the first average values ​​from the multiple ADCs is output as a second average value. A signal processing device equipped with the following features. (Note 2) The signal processing device includes an adder that calculates the sum of the first average values ​​of the plurality of ADCs, and a bit shift operation unit that divides the sum by the number of the plurality of ADCs. The signal processing device described in Appendix 1. (Note 3) The plurality of ADCs include a first ADC and a second ADC, The supply unit supplies a first clock to the first ADC, The signal processing device includes a phase adjustment unit that outputs a second clock whose phase is 180° different from the first clock, The supply unit supplies the first clock to the second ADC if the multiple signals are not identical to each other, and supplies the second clock to the second ADC if the multiple signals are identical to each other. The signal processing device described in Appendix 1 or 2. (Note 4) Each of the multiple signals, which are not identical to one another, is transmitted through multiple channels of the first optical fiber. Multiple identical signals are obtained by splitting a signal transmitted through one channel of a second optical fiber. The signal processing device described in Appendix 3. (Note 5) Each of the multiple channels of the first optical fiber corresponds to a multiple core of an MCF (Multi Core Fiber), One of the channels of the second optical fiber corresponds to one core of an SCF (Single Core Fiber). The signal processing device described in Appendix 4. (Note 6) Equipped with a splitter and analog switches, The splitter divides the signal transmitted through the first core of the MCF or the first core of the SCF, One of the signals split by the splitter is input to the first ADC. The analog switch outputs the other half of the signal split by the splitter to the second ADC when the splitter splits the signal transmitted through the first core of the SCF, and outputs the signal transmitted through the second core of the MCF to the second ADC when the splitter splits the signal transmitted through the first core of the MCF. The signal processing device described in Appendix 5. (Note 7) The signal processing device includes an average value calculation unit that calculates the first average value, If the multiple signals are not identical to each other, the average value calculation unit receives m (where m is an integer of 2 or more) digital values ​​per cycle. If the multiple signals are identical to each other, the average value calculation unit receives n (where n is an integer of 2 or more) digital values ​​per cycle. m is an integer multiple of n, m / n corresponds to the number of the multiple ADCs, The average value calculation unit includes a selection unit that selects either the average value of m digital values ​​or the average value of n digital values ​​as the first average value. The signal processing device described in Appendix 2. (Note 8) The system includes an offset adjustment unit that subtracts the first average value or the second average value from each of the multiple digital values ​​output from one of the ADCs. The signal processing device described in Appendix 1 or 2. (Note 9) If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the same clock is supplied to each of the multiple ADCs; if the multiple signals are identical to each other, different clocks are supplied to each of the multiple ADCs. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, is output as the first average value. If the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value. Signal processing method. (Note 10) If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the process involves supplying the same clock to each of the multiple ADCs, and if the multiple signals are identical to each other, supplying the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, is output as the first average value; if the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value. A program that causes a computer to execute something. [Explanation of symbols]

[0082] 10, 100, 200 signal processing device 11 Clock generation unit 12, 121, 122, 123, 124 ADC 13, 131, 132, 133, 134, 135, 137 MIMO preprocessing circuits 1311, 1331, 1314, 1334 arithmetic circuit 1312, 1332 Average Value Calculation Unit 1315, 1335 Data retention circuit 14 MIMO circuits 15, 151, 152 Splitter 16, 161, 162 Analog Switches 17 Phase Adjuster 18, 1313, 1333, 28 Selectors 21, 211, 212, 213, 23, 24, 25, 31 Addition section 22, 26, 27, 32-bit shift operation unit 101 Supply section 102 Average Value Output Section 1001 Network Interface 1002 Processor 1003 memory

Claims

1. A supply unit that, when multiple signals input to multiple ADCs (Analog-to-Digital Converters) are not identical to each other, supplies the same clock to the multiple ADCs, and when multiple signals are identical to each other, supplies the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average value output unit outputs the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, as the first average value, and if the multiple signals are identical to each other, the average value of the first average value from the multiple ADCs is output as the second average value. A signal processing device equipped with the following features.

2. The signal processing device includes an adder that calculates the sum of the first average values ​​of the plurality of ADCs, and a bit shift operation unit that divides the sum by the number of ADCs. The signal processing apparatus according to claim 1.

3. The plurality of ADCs include a first ADC and a second ADC, The supply unit supplies a first clock to the first ADC, The signal processing device includes a phase adjustment unit that outputs a second clock whose phase is 180° different from the first clock, The supply unit supplies the first clock to the second ADC if the multiple signals are not identical to each other, and supplies the second clock to the second ADC if the multiple signals are identical to each other. The signal processing apparatus according to claim 1 or 2.

4. Each of the multiple signals, which are not identical to one another, is transmitted through multiple channels of the first optical fiber. Multiple identical signals are obtained by splitting a signal transmitted through one channel of the second optical fiber. The signal processing apparatus according to claim 3.

5. Each of the multiple channels of the first optical fiber corresponds to a multiple core of an MCF (Multi-Core Fiber), One of the channels of the second optical fiber corresponds to one core of an SCF (Single Core Fiber). The signal processing apparatus according to claim 4.

6. Equipped with a splitter and analog switches, The splitter divides the signal transmitted through the first core of the MCF or the first core of the SCF, One of the signals split by the splitter is input to the first ADC. The analog switch outputs the other half of the signal split by the splitter to the second ADC when the splitter splits the signal transmitted through the first core of the SCF, and outputs the signal transmitted through the second core of the MCF to the second ADC when the splitter splits the signal transmitted through the first core of the MCF. The signal processing apparatus according to claim 5.

7. The signal processing device includes an average value calculation unit that calculates the first average value, If the multiple signals are not identical to each other, the average value calculation unit receives m (where m is an integer of 2 or more) digital values ​​per cycle. If the multiple signals are identical to each other, the average value calculation unit receives n (where n is an integer of 2 or more) digital values ​​per cycle. m is an integer multiple of n, m / n corresponds to the number of the multiple ADCs, The average value calculation unit includes a selection unit that selects either the average value of m digital values ​​or the average value of n digital values ​​as the first average value. The signal processing apparatus according to claim 2.

8. The system includes an offset adjustment unit that subtracts the first average value or the second average value from each of the multiple digital values ​​output from one of the ADCs. The signal processing apparatus according to claim 1 or 2.

9. If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the same clock is supplied to each of the multiple ADCs; if the multiple signals are identical to each other, different clocks are supplied to each of the multiple ADCs. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one of the multiple ADCs is output as the first average value. If the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value. Signal processing method.

10. If the multiple signals input to each of the multiple ADCs (Analog-to-Digital Converters) are not identical to each other, the process involves supplying the same clock to each of the multiple ADCs, and if the multiple signals are identical to each other, supplying the multiple ADCs with clocks that are not identical to each other. If the multiple signals are not identical to each other, the average of the multiple digital values ​​output from one ADC, which is each of the multiple ADCs, is output as the first average value; if the multiple signals are identical to each other, the average of the first average values ​​from the multiple ADCs is output as the second average value. A program that causes a computer to execute something.

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