Gate driver

Abstract

This invention provides a gate driver that can switch the gate driving capability to three or more levels using a single logic signal. [Solution] The gate driver (401) includes a first terminal (T1) configured to receive a logic signal and a second terminal (T2) configured to receive a pulse signal. The gate driver is configured to drive a switch element (402) in accordance with the pulse signal. The gate driver is configured such that, on either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic signal, the gate driving capability of the switch element is increased by one step to turn on the switch element, and if the logic signal is a second logic signal, the gate driving capability is decreased by one step to turn on the switch element.

Description

Technical Field

[0001] The present disclosure relates to a gate driver.

Background Art

[0002] Conventionally, gate drivers for driving power devices such as MOSFETs [metal oxide semiconductor field effect transistors] or IGBTs [insulated gate bipolar transistors] have been used in various applications.

[0003] As an example of the prior art related to the above, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In the conventional gate driver, there was room for consideration regarding the method of switching the gate driving ability.

[0006] The gate driver disclosed in this specification includes a first terminal configured to receive a logic signal and a second terminal configured to receive a pulse signal. The gate driver is configured to drive a switching element according to the pulse signal. The gate driver is configured to increase the gate driving ability of the switching element by one step when turning on the switching element if the logic signal is a first logic at either the rising edge or the falling edge of the pulse signal, and to decrease the gate driving ability by one step when turning on the switching element if the logic signal is a second logic.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 shows the basic configuration of a signal transmission device. [Figure 2] Figure 2 shows the basic structure of a transformer chip. [Figure 3] Figure 3 is a perspective view of a semiconductor device used as a 2-channel transformer chip. [Figure 4] Figure 4 is a plan view of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a plan view showing the layer in the semiconductor device of Figure 3 where the low-potential coil is formed. [Figure 6] Figure 6 is a plan view showing the layer in the semiconductor device of Figure 3 where the high-potential coil is formed. [Figure 7] Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. [Figure 8] Figure 8 shows an enlarged view (separated structure) of region XIII shown in Figure 7. [Figure 9] Figure 9 is a schematic diagram showing an example of a transformer chip layout. [Figure 10] Figure 10 shows a comparative example of a gate driver and a first embodiment. [Figure 11] Figure 11 shows the gate drive capability switching settings in the comparative example. [Figure 12] Figure 12 is a timing chart showing an example of the transition of settings when turning the switch element ON and when turning the switch element OFF in a comparative example. [Figure 13] Figure 13 shows the gate drive capability switching settings in the first embodiment. [Figure 14] Figure 14 is a timing chart showing an example of the transition of settings when turning the switch element ON and when turning the switch element OFF in the first embodiment when increasing the gate driving capability of the switch element. [Figure 15]FIG. 15 is a timing chart showing transition examples of settings when turning on the switch element and settings when turning off the switch element in the case of reducing the gate driving ability of the switch element in the first embodiment. [Figure 16] FIG. 16 is a timing chart showing transition examples of settings when turning on the switch element and settings when turning off the switch element in the case of maintaining the gate driving ability of the switch element at the second stage in the first embodiment. [Figure 17] FIG. 17 is a diagram showing a first modification example of the switching setting of the gate driving ability in the first embodiment. [Figure 18] FIG. 18 is a diagram showing a second modification example of the switching setting of the gate driving ability in the first embodiment. [Figure 19] FIG. 19 is a diagram showing a second embodiment of the gate driver. [Figure 20] FIG. 20 is a diagram showing a configuration example of two drivers. [Figure 21] FIG. 21 is a timing chart showing transition examples of settings when turning on the switch element and settings when turning off the switch element in the case of increasing the gate driving ability of the switch element in the second embodiment. [Figure 22] FIG. 22 is a timing chart showing transition examples of settings when turning on the switch element and settings when turning off the switch element in the case of reducing the gate driving ability of the switch element in the second embodiment. [Figure 23] FIG. 23 is a timing chart showing transition examples of settings when turning on the switch element and settings when turning off the switch element in the case of maintaining the gate driving ability of the switch element at the second stage in the third embodiment. [Figure 24] FIG. 24 is a diagram showing a third embodiment of the gate driver.

[0008] [Detailed Description] <Signal Transmission Device (Basic Configuration)> FIG. 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 in this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p (VCC1-GND1 system) to the secondary circuit system 200s (VCC2-GND2 system) while insulating between the primary circuit system 200p and the secondary circuit system 200s, and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by encapsulating a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC1 (for example, up to 7V with respect to the GND1 reference). For example, a pulse transmission circuit 211, buffers 212 and 213 are integrated in the controller chip 210.

[0010] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to an input pulse signal IN. More specifically, when notifying that the input pulse signal IN is at a high level, the pulse transmission circuit 211 performs pulse driving (single-shot or multiple-shot transmission pulse output) of the transmission pulse signal S11, and when notifying that the input pulse signal IN is at a low level, it performs pulse driving of the transmission pulse signal S21. That is, the pulse transmission circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives an input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives an input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates on a power supply voltage VCC2 (for example, up to 30V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0014] Buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0015] Buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates an output pulse signal OUT by driving a driver 224 in response to received pulse signals S12 and S22 input via buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. For example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0018] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0019] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0020] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0024] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0026] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0027] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0030] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0031] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0032] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0043] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0044] Referring to Figures 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0049] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0050] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0052] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0056] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0057] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0059] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0060] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0061] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0062] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0063] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0064] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0065] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0067] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0069] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0070] Referring to Figures 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0073] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0074] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0075] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0081] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0083] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0084] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0085] Referring to Figures 6 and 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In a plan view, the high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0088] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. Each of the multiple pad plug electrodes 82 has a planar area less than the planar area of ​​the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23. In this form, the dummy pattern 85 is routed at a line density equal to the line density of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0095] The dummy pattern 85 includes a floating dummy pattern formed electrically in a floating state within the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern may be formed with ends or without ends.

[0097] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated.

[0098] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. A floating dummy pattern may consist of multiple floating lines.

[0099] Referring to Figure 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 7, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] Referring to Figures 5 to 7, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0104] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0105] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0106] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0108] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0110] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0112] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0113] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0114] Referring to Figures 7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, which electrically isolates the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0120] Referring to Figure 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0127] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0129] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0130] Embodiments of the present disclosure can be implemented in other forms. In the embodiments described above, an example was given in which a first functional device 45 and a second functional device 60 are formed. However, a form may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0132] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0135] <Trans arrangement> Figure 9 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is positioned directly below each of the secondary coils L1s to L4s, facing them respectively.

[0139] Specifically, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Similarly, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Furthermore, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Similarly, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0142] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0144] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0148] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between their respective primary coils. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transformer chip 300.

[0151] Furthermore, as shown in Figure 9, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0153] <Gate Driver (Comparative Example)> Figure 10 shows a comparative example of the gate driver 401 (an example of a circuit configuration to be compared with the embodiment described later). The gate driver 401 in this comparative example is a semiconductor device configured to drive a power element, which is a switch element 402.

[0154] The gate driver 401 in this comparative example corresponds to a modified version of the signal transmission device 200 described above. The gate driver 401 in this comparative example receives a logic signal DRVSEL and a pulse signal PLS as two types of input pulse signals IN. For example, a PWM (pulse width modulation) signal is used as the pulse signal PLS, but the pulse signal PLS may be a pulse signal other than a PWM signal.

[0155] The gate driver 401 in this comparative example includes a terminal T1 configured to receive a logic signal DRVSEL and a terminal T2 configured to receive a pulse signal PLS.

[0156] The gate driver 401 in this comparative example transmits information of the logic signal DRVSEL from the primary circuit system 200p (VCC1-GND1 system, see Figure 1) to the secondary circuit system 200s (VCC2-GND2 system, see Figure 1) while isolating the primary circuit system 200p from the secondary circuit system 200s, and also transmits information of the pulse signal PLS from the primary circuit system 200p to the secondary circuit system 200s. Therefore, the gate driver 401 in this comparative example comprises two transformers 231 (see Figure 1) and two transformers 232 (see Figure 1). The two transformers 231 are a transformer 231 for transmitting information of the logic signal DRVSEL and a transformer 231 for transmitting information of the pulse signal PLS. The two transformers 232 are a transformer 232 for transmitting information of the logic signal DRVSEL and a transformer 232 for transmitting information of the pulse signal PLS.

[0157] In the gate driver 401 of this comparative example, the pulse receiving circuit 223 (see Figure 1) drives four drivers 224 (see Figure 1) according to the information of the logic signal DRVSEL and the pulse signal PLS, thereby generating four output pulse signals OUT1H, OUT2H, OUT1L, and OUT2L.

[0158] The gate driver 401 of this comparative example includes a terminal T3 configured to output an output pulse signal OUT1H, a terminal T4 configured to output an output pulse signal OUT2H, a terminal T5 configured to output an output pulse signal OUT1L, and a terminal T6 configured to output an output pulse signal OUT2L.

[0159] The output pulse signal OUT1H is supplied to the gate of, for example, a PMOS (p-channel metal-oxide semiconductor) field-effect transistor Q1H. The output pulse signal OUT2H is supplied to the gate of, for example, a PMOS field-effect transistor Q2H. The output pulse signal OUT1L is supplied to the gate of, for example, an NMOS (n-channel metal-oxide semiconductor) field-effect transistor Q1L. The output pulse signal OUT2L is supplied to the gate of, for example, an NMOS field-effect transistor Q2L. Other active elements may be used instead of the PMOS field-effect transistor Q1H. Similarly, other active elements may be used instead of the PMOS field-effect transistor Q2H, other active elements may be used instead of the NMOS field-effect transistor Q1L, and other active elements may be used instead of the NMOS field-effect transistor Q2L.

[0160] The current capability of PMOS field-effect transistor Q2H is higher than that of PMOS field-effect transistor Q1H. In other words, the drain current of PMOS field-effect transistor Q2H in the saturation region is greater than the drain current of PMOS field-effect transistor Q1H in the saturation region.

[0161] The current capability of NMOS field-effect transistor Q2L is higher than that of NMOS field-effect transistor Q1L. In other words, the drain current of NMOS field-effect transistor Q2L in the saturation region is greater than the drain current of NMOS field-effect transistor Q1L in the saturation region.

[0162] The power supply voltage VCC2 is applied to the sources of the PMOS field-effect transistors Q1H and Q2H. The drain of PMOS field-effect transistor Q1H is connected to the gate of switch element 402 via resistor R1H. The drain of PMOS field-effect transistor Q2H is connected to the gate of switch element 402 via resistor R2H.

[0163] A ground voltage GND2 is applied to the sources of NMOS field-effect transistors Q1L and Q2L. The drain of NMOS field-effect transistor Q1L is connected to the gate of switch element 402 via resistor R1L. The drain of NMOS field-effect transistor Q2L is also connected to the gate of switch element 402 via resistor R2L.

[0164] The gate driver 401 in this comparative example may incorporate at least a portion of the PMOS field-effect transistors Q1H and Q2H, resistors R1H and R2H, NMOS field-effect transistors Q1L and Q2L, resistors R1H and R2H, and the switch element 402.

[0165] The gate driver 401 in this comparative example is configured to drive the switch element 402 in response to the pulse signal PLS. Specifically, the gate driver 401 in this comparative example turns on the switch element 402 when the pulse signal PLS is at a HIGH level, and turns off the switch element 402 when the pulse signal PLS is at a LOW level.

[0166] The gate driver 401 in this comparative example is configured to switch its gate driving capability in two stages according to the logic signal DRVSEL. Specifically, as shown in Figure 11, when the logic signal DRVSEL is at a LOW level, the gate driver 401 in this comparative example turns on only the PMOS field-effect transistor Q1H when turning on the switch element 402, and turns on only the NMOS field-effect transistor Q1L when turning off the switch element 402. Also, as shown in Figure 11, when the logic signal DRVSEL is at a HIGH level, the gate driver 401 in this comparative example turns on both the PMOS field-effect transistors Q1H and Q2H when turning on the switch element 402, and turns on both the NMOS field-effect transistors Q1L and Q2L when turning off the switch element 402.

[0167] Therefore, in the gate driver 401 of this comparative example, the settings for turning the switch element 402 ON and the settings for turning the switch element 402 OFF progress as shown in the timing chart in Figure 12, for example.

[0168] The gate driver 401 in this comparative example can only switch its gate driving capability in two stages using a single logic signal, DRVSEL.

[0169] <Gate driver (first embodiment)> The first embodiment of the gate driver 401 has the same configuration as the comparative example of the gate driver 401, as shown in Figure 10.

[0170] The gate driver 401 of this embodiment is configured to switch its gate driving capability in three stages according to the logic signal DRVSEL. Specifically, as shown in Figure 13, when the logic signal DRVSEL is at a LOW level, the gate driver 401 of this embodiment lowers the gate driving capability of the switch element 402 by one stage when turning on the switch element 402 at the rising edge of the pulse signal PLS. Also, as shown in Figure 13, when the logic signal DRVSEL is at a LOW level, the gate driver 401 of this embodiment lowers the gate driving capability of the switch element 402 by one stage when turning off the switch element 402 at the falling edge of the pulse signal PLS. Furthermore, as shown in Figure 13, when the logic signal DRVSEL is at a HIGH level, the gate driver 401 of this embodiment raises the gate driving capability of the switch element 402 by one stage when turning on the switch element 402. Furthermore, as shown in Figure 13, in this embodiment, when the logic signal DRVSEL is at a HIGH level, the gate driver 401 increases the gate driving capability of the switch element 402 by one level when turning off the switch element 402 on the falling edge of the pulse signal PLS.

[0171] However, if the gate drive capability of the switch element 402 when it is turned on is not the minimum or maximum value (in this embodiment, it is the second stage gate drive capability), the gate driver 401 of this embodiment will lower the gate drive capability of the switch element 402 when it is turned on by one stage if the logic signal DRVSEL is LOW twice consecutively on the rising edge of the pulse signal PLS. Conversely, if the gate drive capability of the switch element 402 when it is turned on is not the minimum or maximum value, the gate driver 401 of this embodiment will leave the gate drive capability of the switch element 402 at the second stage without changing it if the logic signal DRVSEL is LOW only once on the rising edge of the pulse signal PLS. Note that although it is stated here as "LOW twice consecutively", "twice" may be changed to any number of times, three or more.

[0172] Furthermore, if the gate drive capability of the switch element 402 when it is turned on is not the minimum or maximum value (in this embodiment, it is the second stage gate drive capability), the gate driver 401 of this embodiment increases the gate drive capability of the switch element 402 when it is turned on by one stage if the logic signal DRVSEL is at a HIGH level twice in a row on the rising edge of the pulse signal PLS. Conversely, if the gate drive capability of the switch element 402 when it is turned on is not the minimum or maximum value, the gate driver 401 of this embodiment does not change the gate drive capability of the switch element 402 when it is turned on by keeping it at the second stage if the logic signal DRVSEL is at a HIGH level only once on the rising edge of the pulse signal PLS. Note that although it is stated here as "two consecutive HIGH levels", "two times" may be changed to any number of times, three or more.

[0173] Furthermore, if the gate drive capability of the switch element 402 when it is turned off is not the minimum or maximum value (in this embodiment, it is the second stage gate drive capability), the gate driver 401 of this embodiment will lower the gate drive capability of the switch element 402 by one stage if the logic signal DRVSEL is LOW twice consecutively on the falling edge of the pulse signal PLS. Conversely, if the gate drive capability of the switch element 402 when it is turned off is not the minimum or maximum value, the gate driver 401 of this embodiment will leave the gate drive capability of the switch element 402 at the second stage without changing it if the logic signal DRVSEL is LOW only once on the falling edge of the pulse signal PLS. In other words, the gate driver 401 of this embodiment can easily maintain the gate drive capability of the switch element 402 when it is turned off. Note that although it is stated here as "LOW twice consecutively", "twice" may be changed to any number of times, three or more.

[0174] Furthermore, if the gate drive capability of switch element 402 when it is turned off is not the minimum or maximum value (in this embodiment, it is the second stage gate drive capability), the gate driver 401 of this embodiment increases the gate drive capability of switch element 402 when it is turned off by one stage if the logic signal DRVSEL is at a HIGH level twice in a row on the falling edge of the pulse signal PLS. Conversely, if the gate drive capability of switch element 402 when it is turned off is not the minimum or maximum value, the gate driver 401 of this embodiment does not change the gate drive capability of switch element 402 when it is turned on by keeping it at the second stage if the logic signal DRVSEL is at a HIGH level only once on the falling edge of the pulse signal PLS. In other words, the gate driver 401 of this embodiment can easily maintain the gate drive capability of switch element 402 when it is turned on. Note that although it is stated here as "two consecutive HIGH levels", "two times" may be changed to any number of times, three or more.

[0175] Therefore, when the gate driver 401 of this embodiment increases the gate driving capability of the switch element 402, the settings for turning the switch element 402 ON and the settings for turning the switch element 402 OFF progress as shown in the timing chart in Figure 14, for example.

[0176] Furthermore, when the gate driver 401 of this embodiment reduces the gate driving capability of the switch element 402, the settings for turning the switch element 402 ON and turning the switch element 402 OFF progress as shown in the timing chart in Figure 15, for example.

[0177] Furthermore, when the gate driver 401 of this embodiment maintains the gate driving capability of the switch element 402 in the second stage, the settings for turning the switch element 402 ON and the settings for turning the switch element 402 OFF progress as shown in the timing chart in Figure 16, for example.

[0178] Figure 17 shows a first modified example of the gate drive capability switching setting in the first embodiment. In the first modified example shown in Figure 17, the gate drive capability of the switch element 402 is increased by one level when the logic signal DRVSEL is at a LOW level, and when the switch element 402 is turned off at the falling edge of the pulse signal PLS, the gate drive capability of the switch element 402 is decreased by one level when the logic signal DRVSEL is at a HIGH level. This differs from the basic setting shown in Figure 13.

[0179] Figure 18 shows a second modified example of the gate drive capability switching setting in the first embodiment. The first modified example shown in Figure 18 differs from the basic setting shown in Figure 13 in that, when the logic signal DRVSEL is at a LOW level, the gate drive capability of the switch element 402 is lowered by one level when the switch element 402 is turned off at the rising edge of the pulse signal PLS, and when the logic signal DRVSEL is at a HIGH level, the gate drive capability of the switch element 402 is raised by one level when the switch element 402 is turned off at the rising edge of the pulse signal PLS.

[0180] Note that in Figures 13, 17, and 18, the LOW and HIGH levels of the logic signal DRVSEL may be swapped. Also, in Figures 13, 17, and 18, the rising edge and falling edge may be swapped.

[0181] Furthermore, by modifying the gate driver 401 of this embodiment by increasing the number of output pulse signals and increasing the number of PMOS field-effect transistors and NMOS field-effect transistors provided between it and the gate of the switch element 402, it becomes possible to switch between four or more stages of gate driving capability.

[0182] <Gate driver (second embodiment)> Figure 19 shows a second embodiment of the gate driver 401. The gate driver 401 of this embodiment is a semiconductor device configured to drive a power element, a switch element 402, with a constant current. In this specification, constant current means a current that is constant under ideal conditions, and in reality, it is a current that may fluctuate slightly due to temperature changes, etc.

[0183] The following will primarily describe the differences between this embodiment and the first embodiment, while the similarities between this embodiment and the first embodiment will be omitted as appropriate.

[0184] The gate driver 401 of this embodiment is equipped with terminals T7 to T10 instead of terminals T3 to T6.

[0185] Terminal T7 is configured to receive a reference voltage REFH. The reference voltage REFH is a voltage corresponding to the current Ion that flows into the gate of the switch element 402 when the switch element 402 is on.

[0186] Terminal T8 is configured to output the output pulse signal OUTH.

[0187] Terminal T9 is configured to output the output pulse signal OUTL.

[0188] Terminal T10 is configured to receive a reference voltage REFL. The reference voltage REFL is a voltage corresponding to the current Ioff that flows out from the gate of the switch element 402 when the switch element 402 is off.

[0189] The output pulse signal OUTH is supplied to the gate of, for example, a PMOS field-effect transistor QH. The output pulse signal OUTL is supplied to the gate of, for example, an NMOS field-effect transistor Q2H. Other active elements may be used instead of the PMOS field-effect transistor QH. Similarly, other active elements may be used instead of the NMOS field-effect transistor QL.

[0190] The source of the PMOS field-effect transistor QH is connected to the first terminal of resistor RH. The power supply voltage VCC2 is applied to the second terminal of resistor RH. The drain of the PMOS field-effect transistor QH is connected to the gate of switch element 402. Therefore, the current Ion is divided by the power supply voltage VCC2, the reference voltage REPH, and the resistance value R of resistor RH. H It is expressed as follows: Ion = (VCC2 - REPH) / R H

[0191] The source of the NMOS field-effect transistor QL is connected to the first terminal of resistor RL. A ground voltage GND2 is applied to the second terminal of resistor RL. The drain of the NMOS field-effect transistor QL is connected to the gate of switch element 402. Therefore, the current Ioff is given by the ground voltage GND2, the reference voltage REFL, and the resistance value R of resistor RL. L It is expressed as follows: Ioff = (REFL - GND2) / R L

[0192] In the gate driver 401 of this comparative example, the pulse receiving circuit 223 (see Figure 1) drives two drivers 224 (see Figure 1) according to the information of the logic signal DRVSEL and the pulse signal PLS, thereby generating two output pulse signals OUTH and OUTL.

[0193] Figure 20 shows an example configuration of two drivers 224.

[0194] The driver 224 comprises an operational amplifier 2241, a variable voltage source 2242, and an NMOS field-effect transistor 2243.

[0195] A reference voltage REFH is supplied to the inverting input terminal of the operational amplifier 2241. The negative terminal of the variable voltage source 2242 is connected to the non-inverting input terminal of the operational amplifier 2241. The power supply voltage VCC2 is applied to the positive terminal of the variable voltage source 2242. The value of the positive-negative voltage (positive voltage) of the variable voltage source 2242 is switched in steps based on the control signal CTLH. The number of switching steps based on the control signal CTLH should be three or more.

[0196] The output terminal of the operational amplifier 2241 is connected to the drain of the NMOS field-effect transistor 2243. A reference voltage REPH is applied to the source of the NMOS field-effect transistor 2243. The signal PLS_a is supplied to the gate of the NMOS field-effect transistor 2243. An output pulse signal OUTH is generated at the connection node between the output terminal of the operational amplifier 2241 and the drain of the NMOS field-effect transistor 2243.

[0197] The control signal CTLH and signal PLS_a are generated by the pulse receiving circuit 223. The pulse receiving circuit 223 generates the control signal CTLH according to the information of the logic signal DRVSEL and the pulse signal PLS. The pulse receiving circuit 223 also generates signal PLS_a according to the information of the pulse signal PLS, such that the timing of the rising edge and falling edge of the pulse signal PLS coincides and the timing of the falling edge and rising edge of the pulse signal PLS coincides. Therefore, when the pulse signal PLS is at a LOW level, the value of the output pulse signal OUTH is approximately equal to the value of the reference voltage REPH, and the PMOS field-effect transistor QH is turned off. When the pulse signal PLS is at a HIGH level, the operational amplifier 2241 adjusts the output pulse signal OUTH so that the reference voltage REPH approaches the voltage obtained by subtracting the positive-negative voltage (positive voltage) of the variable voltage source 2242 from the power supply voltage VCC2, and the current Ion becomes a constant current.

[0198] The other driver 224 comprises an operational amplifier 2244, a variable voltage source 2245, and an NMOS field-effect transistor 2246.

[0199] A reference voltage REFL is supplied to the inverting input terminal of the operational amplifier 2244. The positive terminal of the variable voltage source 2245 is connected to the non-inverting input terminal of the operational amplifier 2244. Ground voltage GND2 is applied to the negative terminal of the variable voltage source 2245. The value of the positive-negative voltage (positive voltage) of the variable voltage source 2242 is switched in steps based on the control signal CTLL. The number of switching steps based on the control signal CTLL should be three or more.

[0200] The output terminal of the operational amplifier 2244 is connected to the drain of the NMOS field-effect transistor 2246. Ground voltage GND2 is applied to the source of the NMOS field-effect transistor 2246. The signal PLS_b is supplied to the gate of the NMOS field-effect transistor 2246. An output pulse signal OUTL is generated at the connection node between the output terminal of the operational amplifier 2244 and the drain of the NMOS field-effect transistor 2246.

[0201] The control signals CTLL and PLS_b are generated by the pulse receiving circuit 223. The pulse receiving circuit 223 generates the control signal CTLL according to the information of the logic signal DRVSEL and the pulse signal PLS. The pulse receiving circuit 223 also generates the signal PLS_b according to the information of the pulse signal PLS, such that the timing of the rising and falling edges of the pulse signal PLS coincides with that of the pulse signal PLS. Therefore, when the pulse signal PLS is at a HIGH level, the value of the output pulse signal OUTL is approximately equal to the value of the ground voltage GND2, and the NMOS field-effect transistor QL is turned off. When the pulse signal PLS is at a LOW level, the operational amplifier 2244 adjusts the output pulse signal OUTL so that the reference voltage REFL approaches the voltage obtained by adding the positive-negative voltage (positive voltage) of the variable voltage source 2242 to the ground voltage GND2, and the current Ioff becomes a constant current.

[0202] When the gate driver 401 of this embodiment increases the gate driving capability of the switch element 402, the settings for turning the switch element 402 ON and the settings for turning the switch element 402 OFF progress as shown in the timing chart in Figure 21, for example.

[0203] Furthermore, when the gate driver 401 of this embodiment reduces the gate driving capability of the switch element 402, the settings for turning the switch element 402 ON and turning the switch element 402 OFF progress as shown in the timing chart in Figure 22, for example.

[0204] Furthermore, when the gate driver 401 of this embodiment maintains the gate driving capability of the switch element 402 in the second stage, the settings for turning the switch element 402 ON and the settings for turning the switch element 402 OFF progress as shown in the timing chart in Figure 23, for example.

[0205] <Gate driver (third embodiment)> Figure 24 shows a third embodiment of the gate driver 401. The gate driver 401 in this embodiment is a semiconductor device configured to drive a power element, a switch element 402, with a constant current.

[0206] The following will primarily describe the differences between this embodiment and the second embodiment, while the similarities between this embodiment and the second embodiment will be omitted as appropriate.

[0207] The gate driver 401 of this embodiment includes a terminal T11 configured to receive a signal DIS. Signal DIS is a logic signal. A HIGH level signal DIS serves as a reset signal to reset the gate drive capability of the switch element 402 to its minimum value. A LOW level signal DIS does not serve as a reset signal to reset the gate drive capability of the switch element 402 to its minimum value. Note that the HIGH and LOW levels of signal DIS may be swapped, with a LOW level signal DIS serving as the reset signal to reset the gate drive capability of the switch element 402 to its minimum value.

[0208] In this embodiment, the gate driver 401 is configured to reset the gate driving capability when turning on the switch element 402 and the gate driving capability when turning off the switch element 402 to their minimum values ​​when the above-mentioned reset signal is supplied to terminal T11. This makes it possible to reduce the gate driving capability of the switch element 402 to its minimum value all at once without gradually decreasing it.

[0209] The gate driver 401 of this embodiment includes a terminal T12 configured to receive the signal SKIP. The signal SKIP is a logic signal. A HIGH level signal SKIP serves as a set signal to set the gate drive capability of the switch element 402 to its maximum value. A LOW level signal SKIP does not serve as a set signal to set the gate drive capability of the switch element 402 to its maximum value. Note that the HIGH and LOW levels of the signal SKIP may be swapped, and a LOW level signal SKIP may serve as a set signal to set the gate drive capability of the switch element 402 to its maximum value.

[0210] In this embodiment, the gate driver 401 is configured to set the gate drive capability for turning on the switch element 402 and the gate drive capability for turning off the switch element 402 to their respective maximum values ​​when the above-mentioned set signal is supplied to terminal T12. This makes it possible to increase the gate drive capability of the switch element 402 all at once to its maximum value without increasing it in steps.

[0211] In this embodiment, the gate driver 401 is configured to include both terminal T11 and terminal T12, but it is also possible for only one of terminals T11 or T12 to be provided on the gate driver 401.

[0212] The gate driver 401 of this embodiment is configured with terminals T11 and T12 added to the gate driver 401 of the second embodiment, but at least one of terminals T11 and T12 may be added to the gate driver 401 of the first embodiment.

[0213] <Note> The gate driver described herein allows switching the gate driving capability to three or more levels using a single logic signal. Further details regarding the above disclosure are provided below.

[0214] [Note 1] A first terminal (T1) configured to receive a logic signal, A second terminal (T2) configured to receive a pulse signal, Equipped with, The switch element (402) is configured to be driven in accordance with the pulse signal, A gate driver (401) is configured such that, on either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic, the gate driving capability of the switch element is increased by one step when turning on the switch element, and if the logic signal is a second logic, the gate driving capability is decreased by one step when turning on the switch element.

[0215] [Note 2] The gate driver described in Appendix 1, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when turning off the switch element if the logic signal is a first logic, and decreases by one step when turning off the switch element if the logic signal is a second logic.

[0216] [Note 3] The gate driver described in Appendix 1, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when turning off the switch element if the logic signal is second logic, and the gate driving capability is decreased by one step when turning off the switch element if the logic signal is first logic.

[0217] [Note 4] The gate driver described in Appendix 1, configured such that, on either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic, the gate driving capability of the switch element to be driven is increased by one step when turning off the switch element, and if the logic signal is a second logic, the gate driving capability of the switch element to be turned off is decreased by one step when turning off the switch element.

[0218] [Note 5] If the gate drive capability is not at its minimum or maximum value, The gate driver described in Appendix 1, configured such that, at either the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one level when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times, and the gate driving capability is decreased by one level when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times.

[0219] [Note 6] If the gate drive capability is not at its minimum or maximum value, The gate drive capability is increased by one level when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times at either the rising edge or falling edge of the pulse signal, and the gate drive capability is decreased by one level when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times. If the gate drive capability is not at its minimum or maximum value, The gate driver described in Appendix 2, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when the switch element is turned off if the logic signal is a third predetermined number of consecutive first logic sequences, and the gate driving capability is decreased by one step when the switch element is turned off if the logic signal is a fourth predetermined number of consecutive second logic sequences.

[0220] [Note 7] If the gate drive capability is not at its minimum or maximum value, The gate drive capability is increased by one level when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times at either the rising edge or falling edge of the pulse signal, and the gate drive capability is decreased by one level when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times. If the gate drive capability is not at its minimum or maximum value, The gate driver described in Appendix 3, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when the switch element is turned off if the logic signal is a third predetermined number of consecutive second logic sequences, and the gate driving capability is decreased by one step when the switch element is turned off if the logic signal is a fourth predetermined number of consecutive first logic sequences.

[0221] [Note 8] If the gate drive capability is not at its minimum or maximum value, The gate driver described in Appendix 4, configured such that, at either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic for a first predetermined number of consecutive times, the gate driving capability for turning off the switch element and the gate driving capability for turning off the switch element are each increased by one step, and if the logic signal is a second logic for a second predetermined number of consecutive times, the gate driving capability for turning on the switch element and the gate driving capability for turning off the switch element are each decreased by one step.

[0222] [Note 9] A gate driver according to any one of the appendices 1 to 8, configured to control the gate current of the switch element so that the gate current of the switch element becomes a constant current at each stage of the gate driving capability.

[0223] [Note 10] It includes a third terminal (T11) configured to receive a reset signal for resetting the gate drive capability to its minimum value, A gate driver according to any one of the appendices 1 to 9, configured to reset the gate drive capability when turning on the switch element and the gate drive capability when turning off the switch element to their minimum values ​​when the reset signal is supplied to the third terminal.

[0224] [Note 11] It is equipped with a fourth terminal (T12) configured to receive a set signal for setting the gate drive capability to its maximum value, A gate driver according to any one of the appendices 1 to 10, configured to set the gate drive capability when turning on the switch element and the gate drive capability when turning off the switch element to their respective maximum values ​​when the set signal is supplied to the fourth terminal.

[0225] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive. Moreover, the technical scope of this disclosure is defined by the claims and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0226] 5 Semiconductor Equipment 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformers 22 Low-potential coil (primary coil) 23. High-potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42. First Main Surface 43 Second Main Surface 44A~44D Chip sidewall 45. First Functional Device 51 Insulating layer 52 Insulation main surface 53A~53D Insulating sidewall 55. Bottom insulating layer 56. Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second Functional Device 61 Seal conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Sea via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-voltage connection wiring 73 Pull-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrodes 77 Circuit board plug electrodes 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrodes 81 High-potential connection wiring 82 Pad plug electrodes 85 Dummy Patterns 86 High-Potential Dummy Pattern 87. First High-Potential Dummy Pattern 88. Second High-Potential Dummy Pattern 89 First area 90 Second area 91 Third area 92 First connection section 93 Pattern 1 94 Pattern 2 95 Pattern 3 96 First outer line 97 Second outer perimeter line 98 First Intermediate Line 99 First connection line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First Inorganic Insulating Layer 142 Second Inorganic Insulating Layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 buffers 220 Driver chip (second chip) 221, 222 buffers 223 Pulse receiving circuit (RS flip-flop) 224 drivers 230 Transchip (Third Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformers 231p, 232p primary coil 231s, 232s Secondary coil 300 Transchips 301 First Transformer 302 Second Transformer 303 Third Transformer 304 4th Transformer 305 First guard ring 306 Second guard ring 401 Gate driver 402 Switch element 2241, 2244 Operational amplifier 2242, 2245 Variable voltage source 2243, 2246 NMOS field-effect transistor a1~a8 Pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 Pads (corresponding to the second current supply pads) d1~d4 Pads (corresponding to the second voltage measurement pads) e1, e2 Pads L1p, L2p Primary coils L1s, L2s, L3s, L4s Secondary coils Q1H, Q2H, QH PMOS field-effect transistors Q1L, Q2L, QL NMOS field-effect transistors R1H, R2H, R1L, R2L, RH, RL Resistors T1~T12 Terminals T21, T22, T23, T24, T25, T26 External terminals X First direction X21, X22, X23 Internal terminals Y Second direction Y21, Y22, Y23 Wires Z Normal direction Z21, Z22, Z23 Vias

Claims

1. A first terminal configured to receive a logic signal, A second terminal configured to receive pulse signals, Equipped with, The switch element is configured to drive in accordance with the pulse signal, A gate driver configured such that, on either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic, the gate driving capability of the switch element is increased by one step when turning on the switch element, and if the logic signal is a second logic, the gate driving capability is decreased by one step when turning on the switch element.

2. The gate driver according to claim 1, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when turning off the switch element if the logic signal is a first logic, and the gate driving capability is decreased by one step when turning off the switch element if the logic signal is a second logic.

3. The gate driver according to claim 1, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when turning off the switch element if the logic signal is a second logic, and the gate driving capability is decreased by one step when turning off the switch element if the logic signal is a first logic.

4. The gate driver according to claim 1, wherein, on either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic, the gate driving capability of the switch element to be driven is increased by one step when turning off the switch element, and if the logic signal is a second logic, the gate driving capability of the switch element is decreased by one step when turning off the switch element.

5. If the gate drive capability is not at its minimum or maximum value, The gate driver according to claim 1, configured such that, at either the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times, and the gate driving capability is decreased by one step when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times.

6. If the gate drive capability is not at its minimum or maximum value, The gate drive capability is increased by one level when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times at either the rising edge or falling edge of the pulse signal, and the gate drive capability is decreased by one level when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times. If the gate drive capability is not at its minimum or maximum value, The gate driver according to claim 2, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when the switch element is turned off if the logic signal is a third predetermined number of consecutive first logic signals, and the gate driving capability is decreased by one step when the switch element is turned off if the logic signal is a fourth predetermined number of consecutive second logic signals.

7. If the gate drive capability is not at its minimum or maximum value, The gate drive capability is increased by one level when the switch element is turned on if the logic signal is a first logic for a first predetermined number of consecutive times at either the rising edge or falling edge of the pulse signal, and the gate drive capability is decreased by one level when the switch element is turned on if the logic signal is a second logic for a second predetermined number of consecutive times. If the gate drive capability is not at its minimum or maximum value, The gate driver according to claim 3, configured such that, on the other of the rising edge or falling edge of the pulse signal, the gate driving capability is increased by one step when the switch element is turned off if the logic signal is second logic for a third predetermined number of consecutive times, and the gate driving capability is decreased by one step when the switch element is turned off if the logic signal is first logic for a fourth predetermined number of consecutive times.

8. If the gate drive capability is not at its minimum or maximum value, The gate driver according to claim 4, configured such that, at either the rising edge or falling edge of the pulse signal, if the logic signal is a first logic for a first predetermined number of consecutive times, the gate driving capability for turning off the switch element and the gate driving capability for turning off the switch element are each increased by one step, and if the logic signal is a second logic for a second predetermined number of consecutive times, the gate driving capability for turning on the switch element and the gate driving capability for turning off the switch element are each decreased by one step.

9. The gate driver according to any one of claims 1 to 8, configured to control the gate current of the switch element so that the gate current of the switch element becomes a constant current at each stage of the gate driving capability.

10. It includes a third terminal configured to receive a reset signal for resetting the gate drive capability to its minimum value, The gate driver according to any one of claims 1 to 8, configured to reset the gate driving capability when turning on the switch element and the gate driving capability when turning off the switch element to their minimum values ​​when the reset signal is supplied to the third terminal.

11. It is equipped with a fourth terminal configured to receive a set signal for setting the gate drive capability to its maximum value, The gate driver according to any one of claims 1 to 8, wherein when the set signal is supplied to the fourth terminal, the gate driving capability when turning on the switch element and the gate driving capability when turning off the switch element are set to their respective maximum values.

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