Semiconductor equipment

Abstract

During the memory retention period, the memory contents can be retained even when power is not supplied. Furthermore, one of the objectives is to provide a new semiconductor device with a structure that has no limit on the number of write cycles. Let's assume that. [Solution] A first channel formation region is made of a semiconductor material other than an oxide semiconductor. A first transistor and an oxide semiconductor material are used above the first transistor. The second transistor has a second channel forming region, and a capacitive element, and the second One of the second source electrode or second drain electrode of the lampistor and one of the electrodes of the capacitive element A "device" is an electrically connected semiconductor device.

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using semiconductor elements and a method for manufacturing the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile ones in which the stored content is lost when the power supply is cut off, and non-volatile ones in which the stored content is retained even when the power supply is cut off.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting the transistors that make up the memory elements and accumulating electric charges in the capacitors.

[0004] Based on the above principle, in DRAM, when information is read, the electric charges in the capacitors are lost. Therefore, every time information is read, a rewrite operation is required again. Also, there is a leakage current in the transistors that make up the memory elements, and electric charges flow out or in even when the transistors are not selected. As a result, the data retention period is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce the power consumption. Also, since the stored content is lost when the power supply is cut off, another memory device using magnetic materials or optical materials is required for long-term memory retention.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM stores the stored content using circuits such as flip-flops. ​​​​​​​​​​​Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Also, in order to retain charge on the floating gate, or to remove that charge This requires a high voltage, as well as a circuit to handle it. Furthermore, charge retention... Alternatively, removal can take a relatively long time, and speeding up writing and erasing is not easy. That's another problem. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 [Overview of the project] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, power is not supplied during the memory retention period. A new structure that can retain memory content even in difficult situations and has no limit on the number of write cycles. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0011] The disclosed invention constructs a semiconductor device using a highly purified oxide semiconductor. Transistors constructed using ionized oxide semiconductors have extremely low leakage current. It is possible to retain information over a long period of time.

[0012] One aspect of the disclosed invention is a first channel-type semiconductor using a semiconductor material other than an oxide semiconductor. The formation region, the impurity region which is provided so as to sandwich the first channel formation region, and the first channel A first gate insulating layer on the layer formation region, a first gate electrode on the first gate insulating layer, and It comprises a first source electrode and a first drain electrode electrically connected to a pure matter region. A first transistor and a second source electrode and a second drain electrode above the first transistor. The inlet electrode is electrically connected to the second source electrode and the second drain electrode, and the oxide semiconductor is electrically connected to the second source electrode and the second drain electrode. A second channel formation region using a conductive material, and a second channel formation region on the second channel formation region A second transistor having a gate insulating layer and a second gate electrode on a second gate insulating layer The device has a second source electrode or a second drain electrode of the second transistor. One electrode of the capacitor and one electrode of the capacitive element are electrically connected in this semiconductor device.

[0013] In the above, the capacitive element comprises a second source electrode or a second drain electrode and a second gauge It can be composed of a gate insulating layer and electrodes for a capacitive element on a second gate insulating layer. .

[0014] Furthermore, in the above, the third source electrode and the third drain electrode above the first transistor The electrode is electrically connected to the third source electrode and the third drain electrode, and is an oxide semiconductor. A third channel-forming region using biomaterial, and a third channel on the third channel-forming region A third transistor having a gate insulating layer and a third gate electrode on a third gate insulating layer. It has a source line, a bit line, a word line, a first signal line, a second signal line, and a third The gate electrode, one of the second source electrode or the second drain electrode, and the electrode of the capacitive element. One of them is electrically connected to the source wire and the third source electrode. The bit line and the third drain electrode are electrically connected, and the first signal line and the second saw The other of the drain electrode or the second drain electrode is electrically connected to the second signal line and the second The gate electrode is electrically connected to the word line and the other electrode of the capacitive element. It can be configured in a continuous manner.

[0015] Furthermore, in the above, the first transistor enables the logic circuit (arithmetic circuit) or the drive circuit. A path can be constructed.

[0016] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. No. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation and do not require any special mention. This also includes the inverted versions, unless otherwise specified.

[0017] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0018] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It is assumed that this is possible.

[0019] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0020] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0021] In one aspect of the present invention, a transistor using a material other than an oxide semiconductor and an oxide semiconductor A semiconductor device relating to the stacked structure of the transistors used is provided.

[0022] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0023] Furthermore, the semiconductor device according to the disclosed invention does not require a high voltage for writing information, and There is no problem with the degradation of the child. For example, unlike conventional non-volatile memory, electrons to the floating gate Because there is no need to inject or extract electrons from the floating gate, the gate insulation layer does not deteriorate. These problems do not occur at all. In other words, the semiconductor device relating to the disclosed invention is not a non-volatile Unlike conventional memory, there is no limit to the number of rewrite cycles, resulting in a dramatic improvement in reliability. Furthermore, information is written depending on whether the transistor is on or off. Therefore, high-speed operation can be easily achieved. Also, there is no need for an operation to erase information. There are also advantages.

[0024] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation. Therefore, by using this, various circuits requiring high-speed operation (logic circuits, drive circuits, etc.) can be implemented. This makes it possible to suitably achieve the above.

[0025] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0026] [Figure 1] Conceptual diagram of a semiconductor device. [Figure 2] Cross-sectional view of a semiconductor device. [Figure 3] Cross-sectional view of a semiconductor device. [Figure 4] Cross-sectional view of a semiconductor device. [Figure 5] Circuit diagram of a semiconductor device. [Figure 6] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 7] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 8] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 9] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 10] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 11] Cross-sectional view of the manufacturing process for SOI substrates. [Figure 12] Cross-sectional view of the manufacturing process for semiconductor devices. [Figure 13] Circuit diagram of a semiconductor device. [Figure 14] Circuit diagram of a semiconductor device. [Figure 15] Circuit diagram of a semiconductor device. [Figure 16] A diagram illustrating electronic devices using semiconductor devices. [Figure 17] A diagram showing the results of the memory window width investigation. [Modes for carrying out the invention]

[0027] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0028] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0029] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0030] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. The following will be explained with reference to Figures 1 to 5. Note that in the circuit diagrams, oxide semiconductors are used. Sometimes, the sign "OS" is added to indicate that it is a transistor.

[0031] <Outline of Semiconductor Device Configuration> Figure 1 is a conceptual diagram showing an example of the configuration of a semiconductor device. The device typically has memory circuits at the top and logic circuits (processing) that require high-speed operation at the bottom. It is a multilayer semiconductor device that has a circuit (also called a drive circuit) and drive circuits.

[0032] The semiconductor device shown in Figure 1 has a memory cell array 10 at the top and a column decoder at the bottom. 20, Raw Decoder 30, IO Controller 40, IO Buffer 50, Command Buffer A semiconductor device having drive circuits such as 60, address buffer 70, controller 80, etc. It is a memory device. It may also have arithmetic circuits such as a CPU at the bottom. While a memory device was shown as an example of a semiconductor device, one aspect of the disclosed invention is related to this. Not limited.

[0033] <Cross-sectional configuration of a semiconductor device> Figure 2 is a cross-sectional view showing an example of a specific configuration of a semiconductor device. Figure 2(A) shows the first example. Figure 2(B) shows the cross-section of the semiconductor device in question, and Figure 2(B) shows the cross-section of the semiconductor device in the second example, respectively. As shown below, the semiconductor device shown in Figures 2(A) and 2(B) has an oxide semiconductor in the lower part. It has a transistor (transistor 170 or transistor 570) made of the following material, It has a transistor 162 and a capacitive element 164 made of oxide semiconductor at the top. Transistors using materials other than oxide semiconductors are easy to operate at high speeds, and logic circuits It is used in (also called arithmetic circuits), etc. On the other hand, transistors using oxide semiconductors are These properties are used in memory circuits and other applications.

[0034] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the invention is to use an oxide semiconductor in transistor 162 to hold information. Since the focus is on its application, it is not necessary to limit the specific configuration of the semiconductor device shown here to that which is not applicable. .

[0035] The transistor 170 in Figure 2(A) includes a semiconductor material (e.g., silicon). A channel formation region 116 provided on the substrate 100, and a portion sandwiching the channel formation region 116 The impurity region 114 and the high-concentration impurity region 120 (these together are simply impurity) (Also called the pure material region) and a gate insulating layer 108 provided on the channel forming region 116, A gate electrode 110 provided on the gate insulating layer 108 is electrically connected to the impurity region. Source electrode or drain electrode 130a, and source electrode or drain electrode 130b It has.

[0036] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Furthermore, when viewed from a direction perpendicular to the surface of the substrate 100, the sidewall insulating layer 118 does not overlap. The region includes a high-concentration impurity region 120, and metal compounds are in contact with the high-concentration impurity region 120. Region 124 exists. Also, on the substrate 100, there is an element area surrounding the transistor 170. An insulating layer 106 is provided, and an interlayer insulating layer 126 covers the transistor 170. and an interlayer insulating layer 128 is provided. Source electrode or drain electrode 130a, The source electrode or drain electrode 130b is connected to the interlayer insulating layer 126 and the interlayer insulating layer 12 It is electrically connected to the metal compound region 124 through the opening formed in 8. , source electrode or drain electrode 130a, and source electrode or drain electrode 130 b is connected to the high-concentration impurity region 120 and the impurity region 114 via the metal compound region 124. They are electrically connected. Furthermore, due to the integration of transistor 170, etc., side warp In some cases, the insulating layer 118 may not be formed.

[0037] In Figure 2(B), transistor 570 is located on the nitrogen-containing layer 502 and the oxide film 512. A channel-forming region 534 is provided in a layer containing a conductive material (e.g., silicon), and A low-concentration impurity region 532 and a high-concentration impurity region are provided so as to sandwich the channel-forming region 534. The material region 530 (these are also collectively simply called the impurity region) and the channel formation region 534 A gate insulating layer 522a provided on top, and a gate electric field provided on the gate insulating layer 522a Electrode 524 and source electrode or drain electrode 540a electrically connected to the impurity region, It has a source electrode or a drain electrode 540b.

[0038] Here, a sidewall insulating layer 528 is provided on the side of the gate electrode 524. Furthermore, when viewed from a direction perpendicular to the surface of the base substrate 500, the sidewall insulating layer 528 overlaps. The region that is not covered has a high-concentration impurity region 530. Also, the region that covers the transistor 570 In addition, interlayer insulating layers 536 and 538 are provided. Source electrode or The rain electrode 540a and the source electrode or drain electrode 540b are separated by the interlayer insulating layer 53 Through the openings formed in 6 and the interlayer insulating layer 538, the high-concentration impurity region 530 and electrical It is connected to the sidewall insulation due to the integration of transistor 570, etc. In some cases, layer 528 may not be formed.

[0039] In Figures 2(A) and 2(B), the transistor 162 is provided on the insulating layer 138. Source electrode or drain electrode 142a, and source electrode or drain electrode 142 b, the source electrode or drain electrode 142a, and the source electrode or drain electrode 1 42b are electrically connected to the oxide semiconductor layer 144, the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and the gate insulating layer 146 that covers the oxide semiconductor layer 144, and the gate electrode 148a provided so as to overlap the oxide semiconductor layer 144 on the gate insulating layer 146.

[0040] Here, it is desirable that the oxide semiconductor layer 144 is highly purified by sufficiently removing impurities such as hydrogen and by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / c m 3 or less, desirably 5×10 18 atoms / cm 3 or less, more desirably 5×10 1 7 atoms / cm 3 or less. Note that the hydrogen concentration in the above-mentioned oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spect rometry). Thus, in the oxide semiconductor layer 144 in which the hydrogen concentration is sufficiently reduced and highly purified, and the defect levels in the energy gap caused by oxygen deficiency are reduced by supplying sufficient oxygen, the carrier concentration is 1×10 12 / cm 3 or less, desirably 1×10 11 / cm 3 or less, more desirably 1.45×10 10 / cm 3 or less. For example, the off-current density at room temperature (the off-current divided by the channel width of The values ​​range from 10 zA / μm to 100 zA / μm (1 zA (zeptoampere) is 1 × 10⁻¹⁰ -2 1 A) It will be of this degree. In this way, the oxide semi-metallic (intrinsic) or substantially i-metallic oxide semi-metallic By using a conductor, a transistor 162 with extremely excellent off-current characteristics can be obtained. ru.

[0041] In addition, in transistor 162 of Figure 2, the oxide semiconductor layer 144 is not processed in an island shape. This prevents contamination of the oxide semiconductor layer 144 by etching during processing.

[0042] The capacitive element 164 consists of a source electrode or drain electrode 142a, an oxide semiconductor layer 144, and a gate It consists of a core insulating layer 146 and an electrode 148b. That is, the source electrode or the electrode The rain electrode 142a functions as one electrode of the capacitive element 164, and electrode 148b is a capacitive electrode. It will function as the other electrode of the quantitative element 164.

[0043] In addition, in the capacitive element 164 of Figure 2, an oxide semiconductor layer 144 and a gate insulating layer 146 are stacked. By doing so, insulation is provided between the source electrode or drain electrode 142a and electrode 148b. It is possible to ensure sufficient sexual compatibility.

[0044] Furthermore, in transistor 162 and capacitive element 164, the source electrode or drain electrode The ends of electrode 142a and the source electrode or drain electrode 142b are tapered. It is preferable to do so. Here, the taper angle is, for example, 30° to 60°. The taper angle refers to the tapered shape of a layer (for example, the source electrode or drain electrode 1). When 42a) is observed from a direction perpendicular to its cross-section (the plane perpendicular to the surface of the substrate), This shows the inclination angle formed by the side and bottom surfaces of the layer. Source electrode or drain electrode 142a, source electrode By making the end of the electrode or drain electrode 142b tapered, the oxide semiconductor layer This is because it improves the coverage of 144 and prevents breakage at the edges.

[0045] Furthermore, an interlayer insulating layer 150 is provided on top of the transistor 162 and the capacitive element 164. Furthermore, an interlayer insulating layer 152 is provided on top of the interlayer insulating layer 150.

[0046] <Variations of semiconductor device> Figure 3 is a cross-sectional view showing a modified configuration of a semiconductor device. Figure 3(A) shows the first modified configuration. Figure 3(B) shows a cross-section of a semiconductor device relating to the first example, and Figure 3(B) shows a cross-section of a semiconductor device relating to the second modified example. Each is shown below. Note that the semiconductor devices shown in Figure 3(A) and Figure 3(B) are both... This corresponds to a modified version of the configuration shown in 2(A).

[0047] The difference between the semiconductor device shown in Figure 3(A) and the semiconductor device shown in Figure 2(A) is the interlayer insulation. Whether or not there are insulating layers 132 and 134 between the edge layer 128 and the insulating layer 138 Yes. Here, hydrogen-doped silicon nitride is used for the insulating layer 132, and insulating layer 1 34 uses silicon nitride without added hydrogen. Also, the insulating layer 138 is oxidized. It is preferable that the material be made of silicon.

[0048] Thus, the lower layer has an insulating layer 132 made of hydrogen-doped silicon nitride, and the upper layer has water By adopting a configuration having an insulating layer 134 made of silicon nitride without added elements, The material (e.g., silicon) that constitutes the channel formation region 116 of the transistor 170 contains hydrogen By supplying this, the characteristics of transistor 170 are improved, and the oxide semiconductor is used This prevents hydrogen, which causes deterioration of the characteristics of the lampistor 162, from entering the oxide semiconductor layer 144. This is possible. Furthermore, the insulating layer 132, which is made of hydrogen-doped silicon nitride, It can be formed by methods such as CVD. Furthermore, hydrogen-free silica nitride... The insulating layer 134 made of concrete can be formed by sputtering or other methods. In this case, for example, the film deposition atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon, For the puttering target, a silicon material that does not contain hydrogen should be used.

[0049] The difference between the semiconductor device shown in Figure 3(B) and the semiconductor device shown in Figure 2(A) is the interlayer insulation. The question is whether or not there is an insulating layer 134 between the edge layer 128 and the insulating layer 138. Here, insulating Layer 134 uses silicon nitride without added hydrogen. Also, interlayer insulating layer 12 For layer 6, hydrogen-doped silicon nitride is used. Interlayer insulating layer 128 and insulating layer 138 It is preferable that the material used is silicon oxide.

[0050] Thus, it has an interlayer insulating layer 126 made of hydrogen-doped silicon nitride, and hydrogen is added By adopting a configuration having an insulating layer 134 made of silicon nitride that has not undergone transient Hydrogen is supplied to the material (e.g., silicon) that constitutes the channel formation region 116 of the sta 170. This improves the characteristics of transistor 170, and also improves the characteristics of transistors using oxide semiconductors. To prevent hydrogen, which causes deterioration of the properties of TA162, from entering the oxide semiconductor layer 144. This can be done. Furthermore, the interlayer insulating layer 126, which is made of hydrogen-doped silicon nitride, is plasma C It can be formed by methods such as the VD method. Also, silicon nitride without added hydrogen. The insulating layer 134 can be formed by sputtering or the like. For example, the film deposition atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon, and spa For the tarring target, a silicon material that does not contain hydrogen should be used.

[0051] <Modified examples of the transistor and capacitive elements at the top> Next, a modified example of the upper transistor 162 and capacitive element 164 in Figure 2 is shown in Figure 4. show.

[0052] The transistor and capacitance elements shown in Figure 4(A) are located at the top of the semiconductor device in Figure 2. This is one of the modifications of a transistor and a capacitive element.

[0053] The difference between the configuration shown in Figure 4(A) and the configuration shown in Figure 2 is that the oxide semiconductor layer is formed in an island-like manner. It lies in the point where it is located. In other words, in the configuration shown in Figure 2, the oxide semiconductor layer 144 is the insulating layer 138, Source electrode or drain electrode 142a, and source electrode or drain electrode 142b It covers the entire thing. In contrast, in the configuration shown in Figure 4(A), island-shaped oxide semiconductor layers 144 is an insulating layer 138, a source electrode or drain electrode 142a, and a source electrode or it covers a part of the drain electrode 142b. Here, the island-shaped oxide semiconductor layer 144 The ends are preferably tapered. The taper angle is, for example, 30° to 60°. The following is preferable.

[0054] Furthermore, in the capacitive element 164, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and electrode 148b is This can be sufficiently secured.

[0055] The transistor and capacitance elements shown in Figure 4(B) are located at the top of the semiconductor device in Figure 2. This is one of the modifications of a transistor and a capacitive element.

[0056] The difference between the configuration shown in Figure 4(B) and the configuration shown in Figure 2 is that the insulating layer 143 is the source electrode or These are formed on the drain electrode 142a and the source electrode or drain electrode 142b. It is located at the point where it is. Furthermore, the oxide semiconductor layer 144 is the insulating layer 143, source electrode or drain Formed to cover the in electrode 142a and the source electrode or drain electrode 142b The point is that the oxide semiconductor layer 144 is located through an opening provided in the insulating layer 143. It is provided in contact with the source electrode or drain electrode 142a.

[0057] The presence of the insulating layer 143 provides a barrier between the gate electrode and the source electrode or drain electrode. The capacitance formed is reduced, which allows for faster transistor operation.

[0058] The transistors and capacitive elements shown in Figure 4(C) are the same as the transistors in Figures 4(A) and 4(B). It has a configuration that differs slightly from that of capacitors and other capacitive elements.

[0059] The difference between the configuration shown in Figure 4(C) and the configuration shown in Figure 4(A) is that the insulating layer 143 is the source power Formed on the electrode or drain electrode 142a and the source electrode or drain electrode 142b The point is that it is done. Furthermore, the oxide semiconductor layer 144 is the insulating layer 143, the source electrode and It is shaped to cover the drain electrode 142a and the source electrode or drain electrode 142b. The point is that it has been accomplished. Also, the difference between the configuration shown in Figure 4(C) and the configuration shown in Figure 4(B) The key feature is that the oxide semiconductor layer 144 is formed in an island-like manner. This configuration is shown in Figure 4(A The effects of the configuration shown in Figure 4(B) and the effects of the configuration shown in Figure 4(B) can be obtained together.

[0060] <Circuit configuration and operation of semiconductor devices> Next, an example of the circuit configuration of the above semiconductor device and its operation will be described. Figure 5 is shown in Figure 2. This is an example of a circuit configuration using the semiconductor device shown.

[0061] In the semiconductor device shown in Figure 5(A-1), the first wiring (1st Line: source line and The source electrode of transistor 160 (also called the second wire) is electrically connected to the second wire (2n The d line (also called the bit line) and the drain electrode of transistor 160 are electrically connected. It is connected. Also, the third wire (3rd Line: also called the 1st signal line) and the transistor The source electrode or drain electrode of the zista 162 is electrically connected to the fourth electrode The line (4th Line: also called the second signal line) and the gate electrode of transistor 162 are , electrically connected. And the gate electrode of transistor 160 and transistor The other of the source or drain electrode of 162 is electrically connected to one of the electrodes of the capacitive element 164. It is connected to the fifth line (also called the word line) and the capacitive element 164. The other end of the electrode is electrically connected.

[0062] Here, transistors 160 and 162 use the oxide semiconductor described above. A transistor is applied. The above-mentioned transistor using an oxide semiconductor has an off-current. It has the characteristic of being extremely small. Therefore, transistor 162 is turned off. This allows the potential of the gate electrode of transistor 160 to be maintained for an extremely long period of time. This is possible. And, by having the capacitive element 164, the gateway of transistor 160 The charge applied to the electrode is easily retained, and the retained information can be easily read out. Yes. Furthermore, the oxide semiconductor transistor 162 has a channel length (L) of 10 nm. Since the wavelength is 1000nm or less, power consumption is low and the operating speed is extremely high. It has the following characteristics.

[0063] In the semiconductor device shown in Figure 5(A-1), the potential of the gate electrode of transistor 160 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0064] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential is set so that transistor 162 is turned on, thereby turning on transistor 162. As a result, the potential of the third wiring is controlled by the gate electrode of transistor 160 and the capacitive element 1 It is given to 64. That is, a predetermined charge is given to the gate electrode of transistor 160. (to be written). Here, a charge that gives two different potential levels (hereinafter referred to as Low level) It is assumed that either a low charge or a high-level charge is given. Then, the fourth The potential of the wiring is set to the potential at which transistor 162 is in the OFF state, and transistor 162 By turning it off, the charge applied to the gate electrode of transistor 160 is retained. To be held (retained).

[0065] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0066] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, when the appropriate potential (readout potential) is applied to the fifth wiring, the gate of transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then a High level will be applied to the gate electrode of transistor 160. Apparent threshold V when charge is given th_H The gate of 160 transistors Apparent threshold V when a low-level charge is applied to the electrode th_L Lower This is for the purpose of turning on transistor 160. Here, the apparent threshold voltage is the voltage that turns transistor 160 "on". This refers to the potential of the fifth wiring necessary to achieve the above. V th_H and V th_L By setting the potential V0 to the intermediate potential, the transistor 160 The charge applied to the gate electrode can be determined. For example, during writing, High level If a charge is applied, the potential of the fifth wire is V0 (>V th_H ) If that's the case, Lampistor 160 will be in the "on state". If a low-level charge is applied, The potential of the fifth wire is V0( <V th_L Even if this happens, transistor 160 remains in the "off state". It remains as is. Therefore, by looking at the potential of the second wire, the retained information can be read. It can be released.

[0067] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell is used. It is necessary to be able to read the information. In this way, the information of a predetermined memory cell is read, and To prevent reading information from external memory cells, a transistor 1 is used between each memory cell. If 60 is connected in parallel, the number of memory cells that are not to be read out is the first of the memory cells that are not to be read out. For wiring 5, regardless of the gate electrode state, transistor 160 is in the "off state". A potential such that, that is, V th_H A smaller potential should be applied. Also, each memory cell When transistors 160 are connected in series between them, the target of reading is For the fifth wiring of the memory cell, regardless of the state of the gate electrode, transistor 1 The potential at which 60 is in the "on state," that is, V th_L A higher potential in the fifth wiring Give it to them.

[0068] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. The potential is set to such a state, and transistor 162 is turned on. This changes the potential of the third wiring. (The potential related to the new information) is applied to the gate electrode of transistor 160 and the capacitive element 164. It is then given. After that, the potential of the fourth wire is set to the potential at which transistor 162 turns off. By turning off transistor 162, the gate voltage of transistor 160 is turned off. The poles become charged with new information.

[0069] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0070] Note that the source or drain electrode of transistor 162 is connected to the gate of transistor 160. By being electrically connected to the electrode, it is used as a non-volatile memory element. It performs the same function as the floating gate of a ting-gate transistor. In the figure, the source electrode or drain electrode of transistor 162 and the gate of transistor 160. The part where the electrode is electrically connected is sometimes called the floating gate section (FG). When the transistor 162 is off, the floating gate section FG is embedded in the insulator. It can be seen that charge is held in the floating gate portion FG. Oxide semiconductor The off-current of transistor 162 using silicon is 1 Because it is less than 1 in 0,000,000, the floating gate is due to leakage in transistor 162. It is possible to ignore the loss of charge accumulated in part FG. In other words, an oxide semiconductor is used. The transistor 162 makes it possible to realize a non-volatile memory device.

[0071] For example, the off-current density of transistor 162 at room temperature is 10 zA (1 zA (Zeptoampere A) is 1 x 10 -21 A) When the capacitance value of the capacitive element 164 is approximately 1pF. to at least 10 6 It is possible to retain data for more than a second. However, if this retention time is exceeded, It goes without saying that this will vary depending on the characteristics and capacitance of the transistor.

[0072] Furthermore, in this case, the gate issue that has been pointed out in conventional floating-gate transistors The problem of degradation of the tunnel insulating film (tunnel insulating film) does not exist. In other words, the conventional problem is The goal was to eliminate the degradation of the gate insulating film when injecting electrons into the floating gate. This is possible. This means that, in principle, there is no limit to the number of write cycles. Furthermore, in conventional floating-gate transistors, the necessary processes for writing and erasing are required. The high voltage required is also unnecessary.

[0073] The semiconductor device shown in Figure 5(A-1) consists of elements such as transistors that make up the semiconductor device. It can be replaced with a circuit like the one in Figure 5(A-2), which includes resistance and capacitance. It is possible. In other words, in Figure 5(A-2), transistor 160 and capacitive element 164, Each of these is thought to consist of a resistor and a capacitor. R1 and C1 These are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the same as that of the capacitive element 164. This corresponds to the resistance value of the insulating layer that makes up 64. Also, R2 and C2 are, respectively, These are the resistance and capacitance values ​​of transistor 160, where resistance R2 is when transistor 160 is ON. This corresponds to the resistance value due to the gate insulating layer in the current state, and the capacitance value C2 is the so-called gate capacitance (gate This corresponds to the capacitance value formed between the source electrode or drain electrode. The resistance value R2 is the resistance value between the gate electrode of transistor 160 and the channel formation region. Since this is merely an illustration, some of the connections are shown with dotted lines to clarify this point.

[0074] The resistance between the source and drain electrodes when transistor 162 is in the off state (actual) If ROS is defined as the effective resistance (also called ROS), then R1 and R2 are such that R1 ≥ ROS (R1 is less than or equal to ROS). (Above), if R2 ≥ ROS (R2 is greater than or equal to ROS), then the charge retention period (information retention) The duration (which can also be called the lifespan) is primarily determined by the off-current of transistor 162. This will happen.

[0075] Conversely, if the relationship is not satisfied, the off-current of transistor 162 is sufficiently small. However, it becomes difficult to ensure a sufficient retention period. This occurs in transistors other than transistor 162. This is because the leakage is large. For this reason, the semiconductor device disclosed in this embodiment It is desirable that the above-mentioned relationship is satisfied.

[0076] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2 (C1 is greater than or equal to C2). By increasing C1, the potential of the floating gate section FG is controlled by the fifth wiring. When performing such operations (for example, during reading), the potential fluctuation of the fifth wiring can be kept low. That is the reason.

[0077] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are controlled by the gate insulating layer of transistors 160 and 162. It is controlled. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to set these appropriately so that the above relationship is satisfied.

[0078] The semiconductor device shown in Figure 5(B) does not include the transistor 160 shown in Figure 5(A-1). This is a semiconductor device with a configuration. In the semiconductor device shown in Figure 5(B), the first wiring (1st Line (also called the first signal line) and the source or drain electrode of transistor 162 One side is electrically connected to the second wiring (also called the 2nd Line or 2nd signal line). And, it is electrically connected to the gate electrode of transistor 162. And, The source electrode or drain electrode of the sta 162 and the other electrode of the capacitive element 164 are , electrically connected, a third wire (also called a capacitance line), and a capacitance element 1 The other of the 64 electrodes is electrically connected.

[0079] Here, the transistor 162 is a transistor using the oxide semiconductor described above. The aforementioned transistors using oxide semiconductors have the characteristic of having an extremely low off-current. It has. Therefore, by turning off transistor 162, the capacitive element 164 It is possible to maintain the applied potential for an extremely long period of time. The conductor-based transistor 162 has a channel length (L) of 10 nm to 1000 nm. Therefore, it has the characteristics of low power consumption and extremely high operating speed.

[0080] The semiconductor device shown in Figure 5(B) has the characteristic that the potential applied to the capacitive element 164 can be maintained. By utilizing the characteristics, information can be written, stored, and read in the following ways.

[0081] First, we will explain how to write and store information. For simplicity, we will use the third distribution. Assume the potential of the wires is fixed. First, set the potential of the second wire to transistor 162 The potential is set to turn on, and transistor 162 is turned on. This results in the first The potential of the wiring is applied to one of the electrodes of the capacitive element 164. That is, capacitive element 164 A predetermined charge is applied (written) to it. Then, the potential of the second wiring is set by the transistor. By setting the potential to the OFF state of transistor 162, the transistor 162 is turned OFF. The charge applied to the capacitive element 164 is retained (held). Transistor 162 is as described above. As such, the off-current is extremely small, allowing it to retain charge for extended periods.

[0082] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, if the potential of the second wiring is set to the potential at which transistor 162 turns ON, the capacitance element Depending on the amount of charge held in child 164, the first wiring takes on a different potential. Therefore, By observing the potential of the first wire, the stored information can be read.

[0083] Note that once the information is read, the charge on the capacitive element 164 is lost, so writing to it again will not work. It is important to note that this should be done.

[0084] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the second wiring is set when transistor 162 is ON. The potential is set to such a state, and transistor 162 is turned on. This sets the potential of the first wiring. (A potential related to new information) is applied to one of the electrodes of the capacitive element 164. Then, the second The potential of the wiring is set to the potential at which transistor 162 is in the OFF state, and transistor 162 By turning it off, the capacitive element 164 is in a state where it is given a charge related to new information. To become.

[0085] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. This enables high-speed operation of semiconductor devices.

[0086] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as the majority carrier. This concerns the case where a st(s) is used, but instead of an n-type transistor, a large number of holes are used. It goes without saying that a p-type transistor can be used as the carrier.

[0087] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0088] (Embodiment 2) In this embodiment, a method for fabricating a semiconductor device using an oxide semiconductor is described, specifically, as shown in Figure 2. The method for fabricating transistor 162 in the section will be explained using Figure 6. Note that Figure 6 is the main... This document describes the manufacturing process of transistor 162, so Detailed explanations of transistors such as transistor 170 located below 62 will be omitted.

[0089] First, an insulating layer 138 is formed on the interlayer insulating layer 128. Then, a conductive layer is formed on the insulating layer 138. A conductive layer is formed, and the conductive layer is selectively etched to form a source electrode or drain electrode 142a This forms the source electrode or drain electrode 142b (see Figure 6(A)).

[0090] The insulating layer 138 functions as a base layer and is formed using methods such as PVD or CVD. It is possible. In addition, the insulating layer 138 is made of silicon oxide, silicon oxynitride, and silicon nitride. Using materials containing inorganic insulating materials such as hafnium oxide, aluminum oxide, and tantalum oxide. It can be formed in this way. Furthermore, the insulating layer 138 is made to contain as little hydrogen and water as possible. It is desirable to form it. Alternatively, a configuration without the insulating layer 138 is also possible.

[0091] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above, are used as components. Alloys such as manganese, magnesium, zirconium, and beryllium can be used. You may use any of the following materials, or a combination of several of them. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Materials may be made using elements selected from these, or combinations of several of these elements.

[0092] The conductive layer may be a single layer or a laminated structure of two or more layers. For example, titanium Single-layer structures of silicon films and titanium nitride films, single-layer structures of silicon-containing aluminum films, aluminum A two-layer structure in which a titanium film is laminated on a titanium film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated. Oh, when the conductive layer is a single-layer structure of titanium film or titanium nitride film, it has a tapered shape. Source electrode or drain electrode 142a, and source electrode or drain electrode 142 One advantage is that it is easy to process into form b.

[0093] Furthermore, the conductive layer may be formed using a conductive metal oxide. These include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and oxide Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxidation Indium zinc oxide alloy (In2O3-ZnO), or these metal oxide materials Products containing lycon or silicon oxide can be used.

[0094] Etching of the conductive layer involves the formation of the source electrode or drain electrode 142a, and the saw It is preferable that the end of the drain electrode 142b be tapered. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 14 is formed later by etching it into a tapered shape. This improves the coverage of 6 and prevents stepped breakage. Note that the taper angle is the taper A layer having a shape (for example, a source electrode or drain electrode 142a) is defined in cross-section (substrate). When observed from a direction perpendicular to the surface (orthogonal to the surface), the angle of inclination between the side and bottom surfaces of the layer. This indicates.

[0095] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. , and the distance from the lower end of the source electrode or drain electrode 142b. Note that the mask type used when forming transistors with a channel length (L) of less than 25 nm When performing exposure, use ultra-ultraviolet light with a short wavelength of several nanometers to several tens of nanometers. It is preferable to perform mask formation exposure using ultraviolet light. This exposure has high resolution and a large depth of field. Therefore, the subsequent formation of transistors The filament length (L) can also be set to 10 nm or more and 1000 nm or less (1 μm), and It is possible to increase the operating speed of the circuit. Also, miniaturization reduces the power consumption of semiconductor devices. It is also possible to reduce it.

[0096] Note that the source electrode or drain electrode 142a and the source electrode or drain electrode 1 An insulating layer may be formed on 42b. By providing this insulating layer, later formed A gate electrode, a source electrode or drain electrode 142a, and a source electrode or drain It is possible to reduce the parasitic capacitance between the rain electrode 142b and the electrode.

[0097] Next, source electrode or drain electrode 142a, and source electrode or drain electrode 1 An oxide semiconductor layer 144 is formed to cover 42b (see Figure 6(B)).

[0098] The oxide semiconductor layer 144 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O, or a three-component metal oxide. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, and monocrystalline metal oxides It can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O systems. .

[0099] In particular, In-Ga-Zn-O oxide semiconductor materials have sufficiently high resistance in the absence of an electric field. Because the current can be made sufficiently small, and the field effect mobility is also high, semiconductors It is suitable as a semiconductor material for use in the device.

[0100] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m There are instances where it is expressed as (m>0, m is not necessarily a natural number). Also, M is used instead of Ga. Using InMO3(ZnO) m It is expressed as (m>0, m: not necessarily a natural number) There are oxide semiconductor materials. Here, M is gallium (Ga), aluminum (Al), Selected from iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. This indicates one or more metallic elements. For example, M could be Ga, Ga, and Al. Applying Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. This is possible. Note that the above composition is derived from the crystal structure and is merely an example. It should be noted that this is merely a consequence of that.

[0101] For fabricating the oxide semiconductor layer 144 by sputtering, the target is In:Ga: We use a material represented by the empirical formula Zn=1:x:y (where x is greater than or equal to 0, and y is between 0.5 and 5). It is preferable to do so. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A target having the composition ratio of ] can be used. Also, In2O3:Ga2O Targets with a composition ratio of 3:ZnO=1:1:1 [molar ratio], or In2O3:G Targets with a composition ratio of a2O3:ZnO=1:1:4 [molar ratio], or In2O A target with a composition ratio of 3:ZnO=1:2 [molar ratio] can also be used.

[0102] In this embodiment, the amorphous oxide semiconductor layer 144 is made of an In-Ga-Zn-O gold The material will be formed by sputtering using an oxide target.

[0103] The relative density of metal oxides in the metal oxide target is 80% or more, preferably 95% or more. More preferably, it is 99.9% or more. Using a metal oxide target with a high relative density makes it possible to form an oxide semiconductor layer 144 with a dense structure.

[0104] The formation atmosphere of the oxide semiconductor layer 144 is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (preferably 10 ppb or less). That is.

[0105] When forming the oxide semiconductor layer 144, for example, a workpiece is held in a processing chamber maintained in a reduced-pressure state, and the workpiece is heated so that the temperature of the workpiece is 100°C or higher and lower than 550°C, preferably 200°C or higher and 4 00°C or lower. Alternatively, the temperature of the workpiece when forming the oxide semiconductor layer 144 may be room temperature. Then, while removing moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and the oxide semiconductor layer 144 is formed using the above target. By forming the oxide semiconductor layer 144 while heating the workpiece, impurities contained in the oxide semiconductor layer 144 can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber. By forming the oxide semiconductor layer 144 while heating the workpiece, impurities contained in the oxide semiconductor layer 144 can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber. Since it can be removed, the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0106] As the formation conditions of the oxide semiconductor layer 144, for example, the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere, or an argon (argon flow rate ratio 100%) atmosphere, or also a mixed atmosphere of oxygen and argon, and the like conditions can be applied. Note that when using a pulsed direct current (DC) power supply, it is preferable because it can reduce the powdery substances (also called particles, dust) formed during film formation and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer 144 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. By using the oxide semiconductor layer 144 with such a thickness, it is possible to suppress the short-channel effect associated with miniaturization. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the application of the semiconductor device, etc., the thickness can also be selected according to the material used, the application, etc. and the like. Before forming the oxide semiconductor layer 144 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove the deposits on the formation surface (for example, the surface of the interlayer insulating layer 128). Here, reverse sputtering means a method of modifying the surface by causing ions to collide with the processing surface, which is opposite to the normal sputtering where ions are caused to collide with the sputtering target. As a method of causing ions

[0107] to collide with the processing surface, a high-frequency voltage is applied to the processing surface side in an argon atmosphere to generate plasma near the object to be processed. In normal sputtering, ions are caused to collide with the sputtering target, while in reverse sputtering, ions are caused to collide with the processing surface to modify the surface. This includes methods for generating plasma. Note that nitrogen, helium, etc., can be used instead of an argon atmosphere. An atmosphere containing oxygen or other substances may also be applied.

[0108] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144. This first heat treatment removes excess hydrogen (water and hydroxyl groups) from the oxide semiconductor layer 144. This removes the defects, improves the structure of the oxide semiconductor layer, and reduces the defect levels in the energy gap. This is possible. The temperature of the first heat treatment is, for example, 300°C or more and less than 550°C, or 40°C. The temperature should be between 0°C and 500°C.

[0109] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be carried out under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere. Prevent leakage and ensure that no water or hydrogen is introduced.

[0110] Heat treatment equipment is not limited to electric furnaces; it also utilizes heat conduction or thermal radiation from a heated medium such as gas. A device that heats the object to be processed may be used. For example, GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment. ) The device can be used. The LRTA device uses halogen lamps and metal halide lamps. xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) emitted from lamps such as fountains. A GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is argon. An inert gas such as a noble gas or nitrogen that does not react with the object to be treated by heat treatment is used.

[0111] For example, as the first heat treatment, the object to be treated can be put into a heated inert gas atmosphere and heated for several minutes before taking out the object to be treated from the inert gas atmosphere to perform a GRTA treatment. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, it can be applied even under temperature conditions exceeding the heat resistance temperature of the object to be treated. During the treatment, the inert gas may be switched to a gas containing oxygen. This is because by performing the first heat treatment in an atmosphere containing oxygen, the defect levels in the energy gap caused by oxygen deficiency can be reduced.

[0112] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc. ) and containing no water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0113] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor layer 144 that is extremely close to or of type i (intrinsic semiconductor), a transistor with extremely excellent characteristics can be realized.

[0114] By the way, since the above heat treatment (the first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. Dehydrogenation treatment is performed after the formation of the oxide semiconductor layer or the gate insulating layer, and after the formation of the gate electrode. It can also be done at later times, such as afterwards. Hydrogenation treatment can be performed multiple times, not just once.

[0115] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see Figure 6(C)). The gate insulating layer 146 can be formed using methods such as CVD or sputtering. The gate insulating layer 146 is made of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. Hfnium, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf SixOy (x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-added hafnium aluminate (H fAl x O y N z It is preferable to form it such that it includes (x>0, y>0, z>0), etc. Yes. The gate insulating layer 146 may be a single-layer structure or a multi-layer structure. Also, The thickness is not particularly limited, but when miniaturizing semiconductor devices, the operation of the transistor To ensure this, it is desirable to make it thin. The wavelength can be between m and 100 nm, preferably between 10 nm and 50 nm.

[0116] As described above, thinning the gate insulating layer 146 can lead to gate rifts caused by the tunneling effect, etc. Gate leakage becomes a problem. To resolve the gate leakage problem, the gate insulating layer 146 is coated with oxide. Humium, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy( x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x >0, y>0, z>0), nitrogen-added hafnium aluminate (HfAl x O y N z Using high-dielectric constant (high-k) materials such as (x>0, y>0, z>0) is recommended. i. By using a high-k material for the gate insulating layer 146, electrical characteristics can be ensured, This allows for a larger film thickness to suppress gate leakage. A film containing the material, silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide It may also be a laminated structure with a film containing one of the following: aluminum oxide, etc.

[0117] After the formation of the gate insulating layer 146, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The heat treatment temperature should be between 200°C and 450°C, preferably 25°C. The temperature range is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour under a nitrogen atmosphere. Yes, that's fine. By performing a second heat treatment, variations in the electrical characteristics of the transistors are reduced. This is possible. Also, if the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 By supplying oxygen to the oxide semiconductor layer 144, oxygen vacancies are filled, and an i-type (intrinsic) semiconductor is formed. Alternatively, it is possible to form an oxide semiconductor layer that is very close to type i.

[0118] In this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146. The timing of the second heat treatment is not particularly limited thereto. For example, after the formation of the gate electrode You may perform the second heat treatment. Alternatively, you may perform the second heat treatment immediately after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to let them sleep.

[0119] Next, in the region on the gate insulating layer 146 that overlaps with the oxide semiconductor layer 144, the gate electrode Form 148a (see Figure 6(D)). The gate electrode 148a is on the gate insulating layer 146. This is formed by first forming a conductive layer, and then selectively etching the conductive layer. This can be done. The conductive layer that becomes the gate electrode 148a can be made using PVD methods such as sputtering. These can be formed using CVD methods such as plasma CVD. For details, see source electrode. Alternatively, the same applies to the case of drain electrode 142a, etc., and these descriptions can be taken into consideration. When forming the gate electrode 148a, the electrode 14 of the capacitive element 164 in the previous embodiment 8b can be formed together.

[0120] Next, an interlayer insulating layer 150 and an interlayer insulating layer are placed on the gate insulating layer 146 and the gate electrode 148a. An insulating layer 152 is formed (see Figure 6(E)). Interlayer insulating layer 150 and interlayer insulating layer 152 These can be formed using methods such as PVD and CVD. Also, silicon oxide and nitrogen oxides can be used. Inorganic materials such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide. It can be formed using a material containing insulating material. In this embodiment, interlayer insulation Although the invention is described as having a laminated structure of layer 150 and an interlayer insulating layer 152, one aspect of the disclosed invention is not limited to this. Not specified. It can be a single layer or a laminated structure of three or more layers. Also, interlayer insulating layer It is also possible to have a configuration that does not include this feature.

[0121] Furthermore, it is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming an interlayer insulating layer 152 so that the surface is flat, the semiconductor device can be miniaturized. Even in combination, electrodes, wiring, etc., can be suitably formed on the interlayer insulating layer 152. This is for the purpose of flattening the interlayer insulating layer 152, such as CMP (chemical mechanical polishing). This can be done using the method.

[0122] Thus, the transistor 162 using the highly purified oxide semiconductor layer 144 is completed. (See Figure 6(E)).

[0123] The transistor 162 shown in Figure 6(E) consists of an oxide semiconductor layer 144 and an oxide semiconductor layer 14 Source electrode or drain electrode 142a, source electrode or drain electrode electrically connected to 4. The electrode 142b, the oxide semiconductor layer 144, the source electrode or drain electrode 142a, and A gate insulating layer 146 covering the drain electrode or drain electrode 142b, and gate insulating layer 146 The upper gate electrode 148a and the interlayer insulation on the gate insulating layer 146 and gate electrode 148a It has a layer 150 and an interlayer insulating layer 152 on the interlayer insulating layer 150.

[0124] In the transistor 162 shown in this embodiment, the oxide semiconductor layer 144 is made highly pure. Because it is contained, its hydrogen concentration is 5 × 10 19 atoms / cm 3 The following is preferable: 5x 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 below Furthermore, the carrier density of the oxide semiconductor layer 144 is as follows in a typical silicon wafer. Carrier density (1 × 10⁻⁶) 14 / cm 3 A sufficiently small value (for example, 1) compared to the degree ×10 12 / cm 3 Less than, more preferably 1.45 × 10 10 / cm 3 Take the value less than (). And this makes the off-current sufficiently small. For example, at room temperature of transistor 162. The off-current density (off-current divided by the transistor channel width) is 10 zA / μm From 100 zA / μm (1 zA (zeptampere) is 1 × 10⁻¹⁶ -21 A) It will be around that level.

[0125] By using the highly purified and intrinsically purified oxide semiconductor layer 144 in this way, transient The off-current of the transistor can be significantly reduced. And by using such a transistor... This makes it possible to obtain a semiconductor device that can retain its memory contents for an extremely long period of time.

[0126] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0127] (Embodiment 3) In this embodiment, a tracer is used using an oxide semiconductor (particularly an oxide semiconductor having an amorphous structure). The method for fabricating the transistor will be explained using Figure 7. This transistor is the same as the one used in the previous implementation. This can be used in place of transistor 162, etc. in the configuration. The transistor according to the embodiment has some configurations that are the same as the transistor according to the previous embodiment. It is included. Therefore, the following will mainly discuss the differences. Also, the following will discuss the differences. I will explain using a top-gate transistor as an example, but the configuration of a transistor is top-gate It is not limited to the T-shape.

[0128] First, an insulating layer 202 is formed on the workpiece 200. Then, an oxide layer is formed on the insulating layer 202. A conductive layer 206 is formed (see Figure 7(A)).

[0129] The object to be processed 200 is, for example, the interlayer insulating layer 128 in the previous embodiment. For surface 200, it is desirable that the arithmetic mean roughness (Ra) be 1 nm or less. The size is 0.5 nm or less. With the miniaturization of semiconductor devices, the masks used for patterning are changing. The requirements for exposure conditions are increasing, but by creating such a highly flat surface, the requirements for exposure conditions are increasing. This is because it makes it easier to handle even when the demand is high. Furthermore, the arithmetic mean roughness mentioned above includes, for example... Therefore, measurements can be taken in an area of ​​10 μm × 10 μm.

[0130] The insulating layer 202 corresponds to the insulating layer 138 in the previous embodiment and functions as a base layer. For details, refer to the previous embodiment. Note that the configuration does not include an insulating layer 202. It is also possible to do so.

[0131] The oxide semiconductor layer 206 corresponds to the oxide semiconductor layer 144 in the previous embodiment. For details regarding the materials that can be used, the manufacturing method, and other aspects, please refer to the previous embodiments. ru.

[0132] In this embodiment, the amorphous oxide semiconductor layer 206 is made of an In-Ga-Zn-O gold It is formed by a sputtering method using an oxide target.

[0133] Next, the oxide semiconductor layer 206 is processed by methods such as etching using a mask. Island-shaped oxide semiconductor layers 206a are formed.

[0134] For etching the oxide semiconductor layer 206, dry etching and wet etching are both possible. You may use this. Of course, you can also use both in combination. Oxide semiconductors To enable etching of the body layers into the desired shape, etching conditions (etching) are adjusted according to the material. The etching gas, etching solution, etching time, temperature, etc. should be set as appropriate.

[0135] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), tetrachloride There are also gases containing fluorine (such as carbon (CCl4)). Additionally, there are fluorine-containing gases (fluorinated gases, for example, tetrafluoride). Carbon (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane ( CHF3, etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases. Gases to which noble gases such as argon (Ar) have been added may also be used.

[0136] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the workpiece side) The amount of power used, the electrode temperature on the workpiece side, etc., should be set as appropriate.

[0137] Etching solutions used in wet etching include a solution of phosphoric acid, acetic acid, and nitric acid. It can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. That's fine.

[0138] The edges of the oxide semiconductor layer 206a are preferably etched to form a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. Oh, the taper angle refers to the tapered shape of a layer (for example, an oxide semiconductor layer 206a). When observed from a direction perpendicular to the cross-section (the plane perpendicular to the surface of the object being treated), the side of the layer This shows the inclination angle formed by the bottom surface. The edges of the oxide semiconductor layer 206a are tapered. By etching, the source electrode or drain electrode 208a, which is formed later, The coating properties of the drain electrode or drain electrode 208b are improved, preventing step breakage. .

[0139] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 206a. i. This first heat treatment removes excess hydrogen (water and hydroxyl groups) from the oxide semiconductor layer 206a. Removes (including) defects, improves the structure of the oxide semiconductor layer, and reduces defect levels in the energy gap. This is possible. For details, please refer to the previous embodiment. Furthermore, when heat treatment (first heat treatment) is performed after etching, wet etching is used. Even in such cases, etching can be performed at a high etching rate, One advantage is that it can shorten the etching time.

[0140] The first heat treatment is performed on the oxide semiconductor layer 2 before it is processed into an island-shaped oxide semiconductor layer 206a. It can also be done in 06. In that case, after the first heat treatment, the workpiece 20 is removed from the heating device. The zeros will be extracted, and the photolithography process will be performed.

[0141] By the way, the heat treatment described above (the first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. Hydrogenation treatment is performed after the formation of the oxide semiconductor layer, or on the oxide semiconductor layer 206a, or This occurs at timings such as after the drain electrodes are stacked and after the gate insulating layer is formed. It is also possible to perform such dehydration and dehydrogenation treatments multiple times, not just once. You can go several times.

[0142] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. Then, the conductive layer is selected. Etched to target source electrode or drain electrode 208a, source electrode or drain Form electrode 208b (see Figure 7(B)). Conductive layer, source electrode or drain electrode For details on electrode 208a, source electrode or drain electrode 208b, and other information, please refer to the previous article. You can refer to descriptions regarding the conductive layer in the application, as well as the source electrode or drain electrode, etc. .

[0143] Next, a gate insulating layer 212 is formed in contact with a portion of the oxide semiconductor layer 206a (Figure 7(C) (See reference). For details of the gate insulating layer 212, see the gate insulating layer in the previous embodiment. You can refer to the descriptions regarding these matters.

[0144] After the formation of the gate insulating layer 212, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. Details of the second heat treatment can also be considered in the previous embodiment. .

[0145] In this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 212. The timing of the second heat treatment is not particularly limited thereto. For example, after the formation of the gate electrode Heat treatment method 2 may also be performed.

[0146] Next, in the region on the gate insulating layer 212 that overlaps with the oxide semiconductor layer 206a, the gate electric A electrode 214 is formed (see Figure 7(D)). The gate electrode 214 is located on the gate insulating layer 212. This method involves forming a conductive layer and then selectively patterning that conductive layer. This can be done. For details, please refer to the previous embodiment. Note that the formation of the gate electrode 214 At the same time, the electrodes of the capacitive element in the previous embodiment can be formed.

[0147] Next, an interlayer insulating layer 216 and an interlayer insulating layer are placed on the gate insulating layer 212 and the gate electrode 214. A marginal layer 218 is formed (see Figure 7(E)). For details, please refer to the previous embodiment. It is also possible to omit the interlayer insulating layer.

[0148] Based on the above, transistors using a highly purified amorphous oxide semiconductor layer 206a 250 is completed (see Figure 7(E)). Note that depending on the heat treatment conditions, the oxide semiconductor layer In some cases, crystalline components may be present in 206a.

[0149] By using the highly purified and intrinsically purified oxide semiconductor layer 206a in this way, The off-current of the transistor can be sufficiently reduced. And, using such a transistor This allows for the creation of a semiconductor device capable of retaining memory contents for an extremely long period of time. .

[0150] In this embodiment, a top-gate type transistor is used, wherein the source electrode and the We have described a configuration in which the lower part of the rain electrode and the upper part of the oxide semiconductor layer are in contact, but in reality The transistors to which this configuration can be applied are not limited to top gates. A transistor of a certain type, comprising the upper part of the source electrode and drain electrode, and an oxide semiconductor layer. In configurations where the lower part is in contact (such as the configurations shown in Figures 2 and 4), a part of the configuration of this embodiment can be applied. It can be used. Also, a bottom-gate type transistor, wherein the source electrode and Configurations in which the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact, or bottom gate type A lampistor comprising the upper part of the source electrode and drain electrode, and the lower part of the oxide semiconductor layer Some of the configurations of this embodiment can also be applied to configurations where contact occurs. Furthermore, this embodiment enables the realization of various transistors equipped with an amorphous oxide semiconductor. It can be expressed

[0151] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0152] (Embodiment 4) In this embodiment, a method for fabricating a transistor using an oxide semiconductor is described using Figure 8. This will be explained. In this embodiment, the oxide semiconductor layer is a first oxide having a crystalline region. A semiconductor layer and a second oxide semiconductor layer grown from the crystalline region of the first oxide semiconductor layer. The case in which this is used will be explained in detail. The transistor in question is the same as in the previous embodiment. This can be used in place of transistor 162, etc. The transistor in question shares some configuration elements with the transistor in the previous embodiment. Therefore, the following will primarily discuss the differences.

[0153] Furthermore, if the required thickness can be secured with only the first oxide semiconductor layer, the second oxide semiconductor layer A body layer is not necessary. Furthermore, the following explanation will use a top-gate transistor as an example. However, the transistor configuration is not limited to the top-gate type.

[0154] First, an insulating layer 302 is formed on the workpiece 300. Then, the first An oxide semiconductor layer is formed, and at least the surface of the first oxide semiconductor layer is treated by a first heat treatment. The region containing the element is crystallized to form the first oxide semiconductor layer 304 (see Figure 8(A)). .

[0155] Details of the workpiece 300 (such as surface details) can be found in the previous embodiment.

[0156] The insulating layer 302 functions as a base layer. Details of the insulating layer 302 will be explained in the previous section. The method of installation should be taken into consideration. Furthermore, a configuration without the insulating layer 302 is also acceptable.

[0157] The first oxide semiconductor layer is formed in the same manner as the oxide semiconductor layer in the previous embodiment. This is possible. For this reason, details of the first oxide semiconductor layer and its deposition method are as follows. The embodiment should be considered. However, in this embodiment, the first heat treatment is performed on the first To intentionally crystallize the oxide semiconductor layer, an oxide semiconductor that is prone to crystallization is used. It is desirable to form a first oxide semiconductor layer. Examples of such oxide semiconductors include For example, ZnO is one such example. Also, In-Ga-Zn-O oxide semiconductors are also an example. For example, substances with a high concentration of Zn tend to crystallize easily, and metallic elements (In, Ga, and Z) If the proportion of Zn in n) is 60 atom% or more, it is not suitable for this purpose. It is desirable that the thickness of the first oxide semiconductor layer be between 1 nm and 10 nm. In this embodiment, the thickness is set to 3 nm as an example. However, the oxide semiconductor to which it is applied The appropriate thickness varies depending on the material and the application of the semiconductor device, so the thickness depends on the material used and You can choose according to your needs and preferences.

[0158] The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The following applies. Furthermore, the heat treatment time should preferably be between 1 minute and 24 hours. The temperature and duration of the heat treatment vary depending on the type of oxide semiconductor used.

[0159] Furthermore, it is desirable that the atmosphere for the first heat treatment be one that does not contain hydrogen, water, or other harmful substances. For example, nitrogen, oxygen, and noble gases (helium, neon, argon, etc.) from which water has been sufficiently removed. It can create an atmosphere.

[0160] Heat treatment devices utilize not only electric furnaces but also heat conduction from heated gases or other media, or heat radiation. Therefore, a device that heats the object to be processed can be used. For example, LRTA (Lamp R Rapid Thermal Annealing (GRTA) device, GRTA (Gas Rapid Th RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment. l) A device can be used. The LRTA device uses halogen lamps, metal halide lamps. Xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) from lamps such as lamps. The GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is Argonaut. Noble gases such as nitrates, or inert gases such as nitrogen, that do not react with the material being treated by heat treatment. This is used.

[0161] As a result of the first heat treatment described above, a region including at least the surface of the first oxide semiconductor layer becomes crystallized. The crystalline region extends from the surface of the first oxide semiconductor layer to the interior of the first oxide semiconductor layer. This is a region formed by the progression of crystal growth toward the surface. Furthermore, this crystalline region is... It may contain plate-like crystals with an average thickness of 1 nm to 10 nm. Furthermore, the crystalline region is The oxide semiconductor layer may contain crystals oriented along its c-axis in a direction approximately perpendicular to the surface. Here, "approximately parallel" refers to a state within ±10° of the parallel direction, and "approximately perpendicular" refers to a state of perpendicular. This refers to a state within ±10° of the direction.

[0162] Furthermore, the first heat treatment forms a crystalline region, and the hydrogen in the first oxide semiconductor layer It is desirable to remove (water and hydroxyl groups, etc.). When removing hydrogen, etc., Nitrogen and acid with a purity of 6N (99.9999%) or higher (i.e., impurity concentration of 1 ppm or less). The first heat treatment should be performed in an atmosphere of a noble gas (helium, neon, argon, etc.). More preferably, the purity should be 7N (99.99999%) or higher (i.e., the concentration of impurities should be 0.1%). The atmosphere is less than ppm. Furthermore, it is preferable to have an ultra-dry air with H2O at 20 ppm or less. Alternatively, the first heat treatment may be performed in ultra-dry air containing 1 ppm or less of H2O.

[0163] Furthermore, the first heat treatment forms a crystalline region and supplies oxygen to the first oxide semiconductor layer. It is desirable to supply oxygen. For example, by making the heat treatment atmosphere an oxygen atmosphere, the first oxidation It can supply oxygen to the semiconductor layer.

[0164] In this embodiment, the first heat treatment is performed at 700°C for 1 hour under a nitrogen atmosphere. By removing hydrogen and other elements from the oxide semiconductor layer and then switching to an oxygen atmosphere, the first Oxygen is supplied into the oxide semiconductor layer. The main purpose of the first heat treatment is to change the shape of the crystalline region. Because it is already in the process, separate treatments can be carried out to remove hydrogen and other substances, or to supply oxygen. For example, after heat treatment to remove hydrogen, etc., or treatment to supply oxygen. It is possible to perform heat treatment for crystallization.

[0165] This first heat treatment removes crystalline regions and hydrogen (including water and hydroxyl groups). A first oxide semiconductor layer is obtained, which is then treated and supplied with oxygen.

[0166] Next, on the first oxide semiconductor layer 304 having a crystalline region in at least the surface region, A second oxide semiconductor layer 305 is formed (see Figure 8(B)). If the required thickness can be achieved with layer 304 alone, the second oxide semiconductor layer 305 is unnecessary. Yes. In this case, the process involving the second oxide semiconductor layer 305 can be omitted.

[0167] The second oxide semiconductor layer 305 is formed in the same manner as the oxide semiconductor layer in the previous embodiment. This is possible. Therefore, the details of the second oxide semiconductor layer 305 and its deposition method are described below. In this case, the above embodiment should be considered. However, the second oxide semiconductor layer 305 is the It is desirable to form the first oxide semiconductor layer 304 thicker than the first oxide semiconductor layer. The sum of the thicknesses of layer 304 and the second oxide semiconductor layer 305 is preferably 1 nm or more and 50 nm or less. The second oxide semiconductor layer 305 is formed such that it is between 1 nm and 10 nm in size. Desirable. In this embodiment, the thickness is 7 nm as an example. Note that the oxide semiconductor to be applied The appropriate thickness varies depending on the conductive material and the application of the semiconductor device, so the thickness used is... You should choose according to the materials and intended use.

[0168] The second oxide semiconductor layer 305 is made of a material with the same main components as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with closely spaced lattice constants after crystallization (mismatch of 1% or less). When using such materials, in the crystallization of the second oxide semiconductor layer 305 This facilitates crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed. Furthermore, if the main component material is the same, the interfacial properties and electrical properties will also be good.

[0169] Furthermore, if the desired film quality can be obtained by crystallization, a second method using materials with different main components may be used. An oxide semiconductor layer 305 may be formed.

[0170] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystal region is used as a seed to grow crystals and form a second oxide semiconductor layer 306 (Figure 8( See C). If the second oxide semiconductor layer 305 is not formed, this step can be omitted. can.

[0171] The temperature for the second heat treatment is 550°C to 850°C, preferably 600°C to 750°C. The following applies. The heating time for the second heat treatment shall be 1 minute or more and 100 hours or less, preferably 5 hours or less. The maximum treatment time is 20 hours or less, typically 10 hours. Furthermore, in the second heat treatment, Ideally, the atmosphere should not contain hydrogen, water, or other similar substances.

[0172] The details of the atmosphere and the effects of the heat treatment are the same as in the first heat treatment. The heat treatment apparatus capable of performing this is the same as in the case of the first heat treatment. For example, the heating of the second heat treatment Sometimes the inside of the furnace is filled with a nitrogen atmosphere, and during cooling, the inside of the furnace is filled with an oxygen atmosphere, Hydrogen and other substances can be removed using an atmospheric environment, while oxygen can be supplied using an oxygen atmosphere.

[0173] By performing the second heat treatment described above, the first oxide semiconductor layer 304 is formed Crystal growth is advanced from the crystalline region to the entire second oxide semiconductor layer 305, and the second oxide semiconductor A conductive layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like can be removed. This allows for the formation of a second oxide semiconductor layer 306 to which oxygen is supplied. Heat treatment can also be used to improve the orientation of the crystalline regions of the first oxide semiconductor layer 304. be.

[0174] For example, an In-Ga-Zn-O based oxide semiconductor material is used for the second oxide semiconductor layer 306. If present, the second oxide semiconductor layer 306 is InGaO3(ZnO) m (m: What is a natural number?) Crystals represented as (not limited to) or In2Ga2ZnO7(In:Ga:Zn:O=2:2: It may contain crystals represented by a ratio of 1:7 (atom ratio). Such crystals undergo a second heat treatment. By principle, the c-axis is oriented so that it is approximately perpendicular to the surface of the second oxide semiconductor layer 306. It is oriented toward.

[0175] Here, the crystal described above is ray-like, parallel to the a-axis and b-axis. It has a layered structure. Each layer also contains either In, Ga, or Zn. In terms of structure, the aforementioned crystal consists of a layer containing In and a layer that does not contain In (Ga The structure has layers (or layers containing Zn) stacked in the c-axis direction.

[0176] In an In-Ga-Zn-O oxide semiconductor crystal, the in-plane direction of the In-containing layer, In other words, conductivity is good in the directions parallel to the a-axis and b-axis. This is In-G In α-Zn-O oxide semiconductor crystals, electrical conductivity is primarily controlled by In. The 5s orbital of one In overlaps with the 5s orbital of an adjacent In, thus the carrier This is due to factors such as the formation of an apus.

[0177] Furthermore, the first oxide semiconductor layer 304 has an amorphous region at the interface with the insulating layer 302. In the case of the structure, a second heat treatment is performed to form on the surface of the first oxide semiconductor layer 304. Crystal growth progresses from the crystalline region toward the first oxide semiconductor layer 304 toward the bottom. In some cases, the amorphous region may crystallize. Furthermore, the materials constituting the insulating layer 302 and the heat treatment Depending on the conditions, the amorphous region may remain.

[0178] Furthermore, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 have the same main component oxide When using a semiconductor material, as shown in Figure 8(C), the first oxide semiconductor layer 304 and The second oxide semiconductor layer 306 may have the same crystal structure. Therefore, see Figure 8. (C) shows the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 as indicated by the dotted line. The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. In some cases, these can be considered to belong to the same layer.

[0179] Next, the first oxide semiconductor layer 304 and The second oxide semiconductor layer 306 is processed to form island-shaped first oxide semiconductor layers 304a and the A second oxide semiconductor layer 306a is formed (see Figure 8(D)). Note that here, the second heat After processing, the island-shaped oxide semiconductor layer is fabricated, but the island-shaped oxide semiconductor layer A second heat treatment may be performed after processing. In this case, when wet etching is used. Even if there is, etching can be performed at a high etching rate, One advantage is that it can shorten the time required for the process.

[0180] For etching the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, Either dry etching or wet etching can be used. Of course, a combination of both is also possible. They can also be used together. The material allows the oxide semiconductor layer to be etched into the desired shape. Etching conditions (etching gas, etching solution, etching time, temperature, etc.) should be adjusted according to the material. ) are set as appropriate. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 The etching can be performed in the same manner as etching the oxide semiconductor layer in the previous embodiment. Yes, it is possible. For details, please refer to the previous embodiment.

[0181] Furthermore, the region within the oxide semiconductor layer that forms the channel has a flat surface. This is desirable. For example, the height difference (PV) on the surface of the second oxide semiconductor layer 306 is, In the region overlapping with the electrode (channel formation region), the size is 1 nm or less (preferably 0.5 nm). It is preferable that the height difference is less than or equal to m. The height difference mentioned above may include, for example, a 10 μm × 10 μm difference. It can be measured within a specific area.

[0182] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. The electrode layer is selectively etched to remove the source electrode or drain electrode 308a, and the source electrode Alternatively, the drain electrode 308b is formed (see Figure 8(D)). For details, see the previous implementation. You should consider the form.

[0183] Furthermore, in the process shown in Figure 8(D), the first oxide semiconductor layer 304a or the second oxide semiconductor layer Body layer 306a, source electrode or drain electrode 308a, source electrode or drain electrode The crystalline layer in contact with electrode 308b may be in an amorphous state. Therefore, the first oxide semiconductor Not all regions of the body layer 304a and the second oxide semiconductor layer 306a are necessarily crystalline. .

[0184] Next, a gate insulating layer 312 is formed in contact with a portion of the second oxide semiconductor layer 306a. For further details, please refer to the previous embodiment. Subsequently, on the gate insulating layer 312, In the region where the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a overlap, A gate electrode 314 is formed. Then, a layer is placed on the gate insulating layer 312 and the gate electrode 314. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed (see Figure 8(E)). For details, see below. The above embodiment should be considered.

[0185] After the formation of the gate insulating layer 312, a third heat is applied under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The temperature for the third heat treatment is preferably between 200°C and 450°C. The temperature range is between 250°C and 350°C. For example, 250°C for 1 hour in an oxygen-containing atmosphere. Heat treatment can be performed. By performing a third heat treatment, the electrical characteristics of the transistor can be improved. This can reduce rattling. Also, if the gate insulating layer 312 is an insulating layer containing oxygen... In addition, oxygen can be supplied to the second oxide semiconductor layer 306a.

[0186] In this embodiment, the third heat treatment is performed after the formation of the gate insulating layer 312. The timing of the third heat treatment is not limited to this. Also, the timing of other treatments such as the second heat treatment may vary. Therefore, when oxygen is supplied to the second oxide semiconductor layer 306a, the third heat treatment is omitted. It's okay to abbreviate it.

[0187] Based on the above, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are The transistor 350 used is now complete (see Figure 8(E)).

[0188] The first oxide semiconductor layer 304a and the second oxide semiconductor layer are thus purified and intrinsically activated. By using the monocrystalline semiconductor layer 306a, the off-current of the transistor can be sufficiently reduced. And by using such transistors, it is possible to store the contents of memory for an extremely long period of time. A semiconductor device capable of holding is obtained.

[0189] In this embodiment, a top-gate type transistor is used, wherein the source electrode and the We have described a configuration in which the lower part of the rain electrode and the upper part of the oxide semiconductor layer are in contact, but in reality The transistors to which this configuration can be applied are not limited to top gates. A transistor of a certain type, comprising the upper part of the source electrode and drain electrode, and an oxide semiconductor layer. In configurations where the lower part is in contact (such as the configurations shown in Figures 2 and 4), a part of the configuration of this embodiment can be applied. It can be used. Also, a bottom-gate type transistor, wherein the source electrode and Configurations in which the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact, or bottom gate type A lampistor comprising the upper part of the source electrode and drain electrode, and the lower part of the oxide semiconductor layer Some of the configurations of this embodiment can also be applied to configurations where contact occurs. In addition, this embodiment provides various transients having an oxide semiconductor layer having a crystalline region It is possible to achieve this.

[0190] Furthermore, in this embodiment, the oxide semiconductor layer is a first oxide semiconductor having a crystalline region. Body layer 304a and a second acid grown from the crystalline region of the first oxide semiconductor layer 304a Because a synthetic semiconductor layer 306a is used, the field-effect mobility is improved, resulting in good electrical characteristics. A transistor can be realized with a field-effect mobility μ > 100 cm. 2 It is also possible to achieve / V·s. This makes it possible to implement various logic circuits that require high-speed operation. It is also possible to apply the above transistor to this.

[0191] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0192] (Embodiment 5) In this embodiment, a method for fabricating a transistor using an oxide semiconductor is described using Figure 9. This will be explained. This transistor replaces transistor 162, etc., in the previous embodiment. It can be used in this manner. Note that the transistor according to this embodiment is a part The configuration is the same as the transistor in the previous embodiment. Therefore, in the following, we will mainly... The differences will be discussed below. Furthermore, a top-gate transistor will be used as an example. To explain further, transistor configurations are not limited to the top-gate type.

[0193] First, an insulating layer 402 is formed on the workpiece 400. Then, an oxide layer is formed on the insulating layer 402. A semiconductor layer 406 is formed (see Figure 9(A)). For details, please refer to the previous embodiment. That's all you need to do.

[0194] Next, the oxide semiconductor layer 406 is processed by methods such as etching using a mask. An island-shaped oxide semiconductor layer 406a is formed, and a guide is provided to cover the oxide semiconductor layer 406a. The electrical layer 408 and the insulating layer 410 are formed (see Figure 9(B)). Note that the insulating layer 410 is not necessary. Although not a component of the material, it selectively forms the sides of the source or drain electrode that are later formed. It is effective for oxidation. Also, the gate electrode and the source electrode or drain electrode It is also effective in reducing the volume between them.

[0195] For details regarding the formation of the island-shaped oxide semiconductor layer 406a and heat treatment, please refer to the previous embodiment. This can be taken into consideration. Furthermore, details of the conductive layer 408 can also be taken into consideration in the previous embodiment. That's all you need to do.

[0196] The insulating layer 410 can be formed using methods such as CVD or sputtering. The insulating layer 410 is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and acid It is preferable to form it to contain hafnium oxide, tantalum oxide, etc. Note that the insulating layer 4 10 may be a single-layer structure or a multi-layer structure. The thickness of the insulating layer 410 is not particularly limited. Although not specified, it can be, for example, between 10 nm and 200 nm.

[0197] Next, the conductive layer 408 and the insulating layer 410 are selectively etched to form the source electrode or Rain electrode 408a, source electrode or drain electrode 408b, insulating layer 410a, insulating layer Form 410b (see Figure 9(C)). For details, see the source electrode in the previous embodiment. This is similar to the drain electrode formation process. Note that aluminum, titanium, molybdenum, Materials such as copper are suitable for subsequent plasma oxidation treatment, and the source electrode or dray It is suitable as a material for the in-electrode 408a, source electrode, or drain electrode 408b.

[0198] Next, an oxidation treatment is performed to supply oxygen to the oxide semiconductor layer 406a (see Figure 9(D)). ). By this oxidation treatment, a portion of the source electrode or drain electrode 408a (in particular, its The oxidized region 411a is located on the side surface, and the source electrode or drain electrode 408b Oxidation region 411b is formed in a part of it (particularly the part corresponding to its side) (Figure 9(D (See reference). In addition, this oxidation treatment causes the source electrode or drain electrode 408a, and An oxidation region is also formed on the outer periphery of the drain electrode or drain electrode 408b.

[0199] The oxidation process involves using oxygen plasma excited by microwaves (300 MHz to 300 GHz). It is preferable to use a plasma oxidation treatment (plasma oxidation treatment) with microwaves. By exciting the rasma, a high-density plasma is realized, damaging the oxide semiconductor layer 406a. This is because it can significantly reduce the impact.

[0200] More specifically, for example, the frequency is 300MHz to 300GHz (typically 2.45GHz). (Hz), pressure 50 Pa to 5000 Pa (typically 500 Pa), temperature of the workpiece 2 The temperature should be between 00°C and 400°C (typically 300°C), and the above-mentioned method should be performed using a mixed gas of oxygen and argon. It can perform the process.

[0201] As a result of the above oxidation treatment, oxygen is supplied to the oxide semiconductor layer 406a, While sufficiently reducing damage to the oxide semiconductor layer 406a, energy caused by oxygen deficiency - The number of defect levels in the gap can be reduced. In other words, the oxide semiconductor layer 406a The characteristics can be further improved.

[0202] Furthermore, while sufficiently reducing damage to the oxide semiconductor layer 406 Any method that can supply oxygen to a is suitable for plasma oxidation treatment using microwaves. It is not limited to this. For example, methods such as heat treatment in an oxygen-containing atmosphere can also be used. ru.

[0203] In addition, a process to remove water, hydrogen, etc. from the oxide semiconductor layer 406a is performed in conjunction with the above oxidation treatment. This may be done. In this case, for example, plasma treatment using gases such as nitrogen or argon may be performed. It can be used.

[0204] Furthermore, the oxidized regions 411a and 411b formed by the above oxidation treatment are trans If the ZISTA 450 is miniaturized (for example, if the channel length is less than 1000 nm) It is particularly effective for (combination). With the miniaturization of transistors, the gate insulating layer is Although it is required to reduce the thickness, having the oxidized region allows for a thinner gate insulating layer. Poor molding or coverage can result in the gate electrode and the source electrode or drain electrode. This is because it prevents short circuits in the electrodes. The oxidation region should be 5 nm or larger (preferably). A thickness of 10 nm or more is sufficient for it to be sufficiently effective.

[0205] Furthermore, the above oxidation treatment is also effective from the viewpoint of improving the film quality of the exposed insulating layer 402.

[0206] Note that the source electrode or drain electrode 408a, or the source electrode or drain electrode 408 In that they play a role in preventing oxidation of the upper part of b, insulating layers 410a and 410b are heavy This is essential. To perform the above plasma treatment while leaving the mask used during etching intact... This is because it involves great difficulty.

[0207] Next, without exposing it to the atmosphere, a gate insulating layer in contact with a portion of the oxide semiconductor layer 406a Form 412. Then, superimpose it with the oxide semiconductor layer 406a on the gate insulating layer 412. A gate electrode 414 is formed in the region, and a layer is placed on the gate insulating layer 412 and the gate electrode 414. An interlayer insulating layer 416 and an interlayer insulating layer 418 are formed (see Figure 9(E)). For details, see below. The previous embodiment can be considered.

[0208] With the above steps, the 450 transistor using an oxide semiconductor is completed.

[0209] In this embodiment, in order to supply oxygen to the oxide semiconductor layer 406a, the oxide semiconductor layer 4 O6a has been treated with oxygen plasma. As a result, the characteristics of transistor 450 are further improved. The cost will be high. Also, the region corresponding to the side of the source electrode or drain electrode will be oxidized. Therefore, the gate electrode may be affected by the thinning of the gate insulating layer. This prevents short circuits between the source electrode (or drain electrode). Also, oxidation region 4 Due to the oxidation region 411b, an appropriate offset region is created, thus forming an oxide semiconductor. The change in the electric field from the layer to the interface with the source electrode (or drain electrode) is kept low. It is also possible to do so.

[0210] Furthermore, by providing an insulating layer on the source electrode and drain electrode, the source electrode and By reducing the capacitance (parasitic capacitance) formed between the drain electrode and the gate electrode, further It is possible to achieve high-speed operation.

[0211] In this embodiment, a top-gate type transistor is used, wherein the source electrode and the We have described a configuration in which the lower part of the rain electrode and the upper part of the oxide semiconductor layer are in contact, but in reality The transistors to which this configuration can be applied are not limited to bottom gate transistors. A transistor of type [type], with the source electrode and drain electrode lower part and an oxide semiconductor layer A part of the configuration of this embodiment can be applied to a configuration in which the upper part is in contact with the upper part. In other words, This embodiment provides an oxide semiconductor supplied with oxygen, an electrode having an oxidation region, and the like. A variety of transistors can be realized.

[0212] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0213] (Embodiment 6) In this embodiment, a method for fabricating a semiconductor device using semiconductor materials other than oxide semiconductors, specifically... Specifically, regarding the method of fabricating transistor 170 at the bottom of Figure 2(A), see Figures 10 and 2. We will explain using (A).

[0214] First, prepare a substrate 100 containing semiconductor material (see Figure 10(A)). The substrate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate It is possible to apply plates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Yes. Here, when a single-crystal silicon substrate is used as the substrate 100 containing semiconductor material. An example of this will be shown. Generally speaking, a "SOI substrate" is a substrate with silicon on an insulating surface. This refers to a substrate having a layered structure, but in this specification, it refers to a substrate having a layer other than silicon on the insulating surface. The concept is used to include substrates with a semiconductor layer made of the material S. The semiconductor layer of the "OI substrate" is not limited to a silicon layer. Furthermore, the SOI substrate may have a gas This includes configurations in which a semiconductor layer is provided on an insulating substrate such as a lath substrate, with an insulating layer in between. It shall be considered as such.

[0215] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 10(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0216] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area where there is no semiconductor material (the exposed area) is removed. This removes the other semiconductor material. A semiconductor region 104 is formed, separated from the other region (see Figure 10(B)). Dry etching is preferred for this process, but wet etching may also be used. The etching gas and etching solution should be selected appropriately according to the material to be etched. It is possible.

[0217] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 10(B)). (See image). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0218] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0219] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide Mu, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0) , y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-added hafnium aluminate (HfAl x O y N z ( It is preferable to have a single-layer or multi-layer structure of the film including x>0, y>0, z>0, etc. Alternatively, By high-density plasma treatment and thermal oxidation treatment, the surface of the semiconductor region 104 is oxidized and nitrided. The above insulating layer may be formed by the above. High-density plasma treatment may be performed using, for example, He, Ar Mixed gases such as noble gases like Kr and Xe, oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen are used. This can be done. Also, the thickness of the insulating layer can be, for example, 1 nm to 100 nm. The wavelength can be between 10 nm and 50 nm.

[0220] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using [a specific method]. Furthermore, using semiconductor materials such as polycrystalline silicon, conductive [a specific method] can be used. A layer containing the material may be formed. The formation method is not particularly limited and may include vapor deposition, CVD, and sputtering. Various film deposition methods such as taring and spin coating can be used. The example shown illustrates a case where a layer containing a conductive material is formed using a metallic material. Let's assume that.

[0221] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 10(C)).

[0222] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see Figure 10(C)). Then, By adding phosphorus (P) or arsenic (As) to the semiconductor region 104, impurity regions with shallow junction depths are created. Region 114 is formed (see Figure 10(C)). Note that an n-type transistor is formed here. Although phosphorus or arsenic is added for this purpose, when forming a p-type transistor, boron (B) is used. Or impurities such as aluminum (Al) can be added. As a result, a channel formation region 116 is formed below the gate insulating layer 108 of the semiconductor region 104. This is done (see Figure 10(C)). Here, the concentration of the added impurities can be set as appropriate. However, when semiconductor devices are miniaturized to a high degree, it is desirable to increase their concentration. Furthermore, this process employs the step of forming an impurity region 114 after forming an insulating layer 112. However, the process may also involve forming the insulating layer 112 after forming the impurity region 114.

[0223] Next, the sidewall insulating layer 118 is formed (see Figure 10(D)). The edge layer 118 is formed after the insulating layer is formed so as to cover the insulating layer 112, and an anisotropic layer is formed on the insulating layer. By performing a high etching process, it can be formed in a self-aligned manner. Also, at this time The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110 and the impurity region 11 It is best to expose the top surface of 4. Note that the sidewall insulating layer 118 is intended for high integration and other purposes. They may not be formed for the purpose of targeting.

[0224] Next, to cover the gate electrode 110, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed in the region in contact with the impurity region 114. By adding substances such as As, a high-concentration impurity region 120 is formed (see Figure 10(E)). Next, the above insulating layer is removed, and the gate electrode 110, sidewall insulating layer 118, high concentration impurities are removed. A metal layer 122 is formed to cover the material region 120, etc. (see Figure 10(E)). 122 uses various film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed. The metal layer 122 reacts with the semiconductor material constituting the semiconductor region 104. It is desirable to form the metal compound using a metal material that results in a low-resistance metal compound. Examples of such metallic materials include titanium, tantalum, tungsten, nickel, and corn. Examples include Baltic and platinum.

[0225] Next, heat treatment is applied to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 10(F)). Furthermore, when using polycrystalline silicon or the like as the gate electrode 110, the gate electrode 11 A metal compound region will also be formed in the area that comes into contact with the metal layer 122 of 0.

[0226] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that can achieve heat treatment in a very short time. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0227] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 10(G)). Interlayer insulating layers 126 and 128 oxidize Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, t It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic resin. Although the invention has a laminated structure of an interlayer insulating layer 126 and an interlayer insulating layer 128, one aspect of the disclosed invention is It is not limited to this. It may be a single layer or a laminated structure of three or more layers. Interlayer insulating layer After the formation of 128, its surface is planarized by CMP or etching. It is desirable.

[0228] Subsequently, openings are formed in the interlayer insulating layers 126 and 128 that extend to the metal compound region 124. The opening is then fitted with a source electrode or drain electrode 130a, and a source electrode or drain Form electrode 130b (see Figure 10(H)). Source electrode or drain electrode 130a The source electrode or drain electrode 130b is, for example, used in PVD or CV in the region including the aperture. After forming a conductive layer using methods such as the D method, etching or CMP is used. This can be formed by removing a portion of the above conductive layer.

[0229] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the formation surface (such as the native oxide film) is reduced, and the lower electrode (here, the metal compound region 124) It has the function of reducing contact resistance with ). Furthermore, the titanium nitride film formed thereafter is It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by a plating method.

[0230] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface including the drain electrode 130b, in subsequent processes This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc.

[0231] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, An electrode that comes into contact with the source electrode 110 can be formed together. It can be used as a drain electrode 130a, a source electrode, or a drain electrode 130b. There are no particular limitations on the materials used; various conductive materials can be used. For example, molybdenum Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Scandinavian Conductive materials such as aluminum can be used. Also, considering the subsequent heat treatment, The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are subjected to heat treatment. It is desirable to form it using a material that has sufficient heat resistance to withstand the stresses.

[0232] As a result, a transistor 170 is formed using a substrate 100 containing semiconductor material (Figure See 10(H). Transistor 170 using materials other than oxide semiconductors is capable of high-speed operation. Since it is possible, the transistor can be used to construct logic circuits (also called arithmetic circuits), etc. This is possible. Furthermore, a drive circuit for driving the memory circuit shown in the previous embodiment, etc. It can also be used for this purpose.

[0233] Furthermore, electrodes, wiring, insulating layers, etc., may be formed after the above process. Wiring structure By adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, We can provide highly integrated semiconductor devices.

[0234] For example, an insulating layer 138 may be formed after the above process, and an opening may be formed in the insulating layer 138. Furthermore, an electrode 142c connected to the source electrode or drain electrode 130a is placed in the opening. An electrode 142d may be formed which is connected to the source electrode or drain electrode 130b. (See Figure 2(A)).

[0235] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0236] (Embodiment 7) In this embodiment, a method for fabricating a semiconductor device using semiconductor materials other than oxide semiconductors, specifically... Specifically, regarding the method of fabricating transistor 570 at the bottom of Figure 2(B), see Figures 11 and 1 We will explain using 2. Below, we will first describe S, which has a single crystal semiconductor layer provided on a base substrate. The method for fabricating an OI substrate will be explained with reference to Figure 11, and then the SOI substrate will be used The method for fabricating transistors will be explained with reference to Figure 12.

[0237] <Method for fabricating SOI substrates> First, prepare the base board 500 (see Figure 11(A)). The base board 500 is as follows: An insulating substrate can be used. Specifically, aluminosilicate glass, aluminum Various types of glass used in the electronics industry, such as minoborsilicate glass and bariumborosilicate glass. Examples include lath substrates, quartz substrates, ceramic substrates, and sapphire substrates. Also, silica nitride Using a ceramic substrate with a coefficient of thermal expansion close to that of silicon, which is mainly composed of silicon and aluminum oxide. That's fine.

[0238] Furthermore, the base substrate 500 can be a single-crystal silicon substrate, a single-crystal germanium substrate, or other semiconductor substrates. A glass substrate may be used. When a semiconductor substrate is used as the base substrate 500, a glass substrate may be used. Compared to using plates or similar materials, the upper limit of the heat treatment temperature is increased, thus enabling the production of high-quality SOI substrates. This makes it easier to do so. Here, the semiconductor substrate is solar cell grade silicon (SOG-Si A substrate such as a solar-grade silicon substrate may also be used. Conductive substrates may also be used. For example, when using solar cell-grade silicon or polycrystalline semiconductor substrates. This allows for reduced manufacturing costs compared to using single-crystal silicon substrates, etc. ru.

[0239] In this embodiment, we will describe the case in which a glass substrate is used as the base substrate 500. By using an inexpensive glass substrate that can be made to a large area as the base substrate 500, low cost It is possible to achieve a more streamlined design.

[0240] It is preferable to clean the surface of the base substrate 500 in advance. Specifically, for a base substrate of 500, a hydrochloric acid-hydrogen peroxide mixed solution (HPM) and sulfuric acid-hydrogen peroxide solution are used. Hydrogen peroxide mixed solution (SPM), ammonia hydrogen peroxide mixed solution (APM), dilute hydrofluoric acid Ultrasonic cleaning is performed using (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. By performing this cleaning process, the flatness of the base substrate 500 surface is improved, and - This enables the removal of abrasive particles remaining on the surface of the substrate 500.

[0241] Next, a nitrogen-containing layer 502 (for example, a silicon nitride film (SiN)) is applied to the surface of the base substrate 500. x ) and silicon nitride film (SiN x O y Includes a nitrogen-containing insulating film such as (x>y). A layer is formed (see Figure 11(B)). The nitrogen-containing layer 502 is formed by CVD, sputtering. It can be formed using laws and regulations.

[0242] The nitrogen-containing layer 502 formed in this embodiment is later bonded to a single-crystal semiconductor layer. This layer (bonding layer) serves to achieve this. In addition, the nitrogen-containing layer 502 contains sodium contained in the base substrate. It can also be used as a barrier layer to prevent impurities such as sodium (Na) from diffusing into the single-crystal semiconductor layer. It works.

[0243] As described above, in this embodiment, the nitrogen-containing layer 502 is used as a bonding layer, so its surface It is preferable to form the nitrogen-containing layer 502 such that it has a predetermined flatness. Specifically, , the average surface roughness (Ra, also called arithmetic mean roughness) is 0.5 nm or less, and the mean square roughness ( Rms) is 0.60 nm or less, more preferably the average surface roughness is 0.35 nm or less, and the square aspect ratio is 0.60 nm or less. A nitrogen-containing layer 502 is formed such that the uniform roughness is 0.45 nm or less. Surface roughness and mean square roughness can be measured, for example, in a 10 μm × 10 μm area. Film thickness is... The wavelength should be between 10 nm and 200 nm, preferably between 50 nm and 100 nm. As shown above, improving the flatness of the surface prevents bonding defects in the single-crystal semiconductor layer. It is possible.

[0244] Next, prepare the bond substrate. Here, a single-crystal semiconductor substrate 510 is used as the bond substrate. (See Figure 11(C)). Note that a single crystal is used as the bond substrate here. The crystallinity of the bond substrate does not need to be limited to a single crystal.

[0245] Examples of single-crystal semiconductor substrates 510 include single-crystal silicon substrates and single-crystal germanium substrates. Using single-crystal semiconductor substrates made of Group 14 elements, such as plates and single-crystal silicon germanium substrates. This can be done by using compound semiconductor substrates such as gallium arsenide or indium phosphide. It is also possible to do this. Commercially available silicon substrates include those with a diameter of 5 inches (125 mm) and 6 inches. (150mm), 8 inches (200mm) in diameter, 12 inches (300mm) in diameter, 1 A typical example is a circular one measuring 6 inches (400 mm). Note that single-crystal semiconductor substrate 5 The shape of 10 is not limited to a circle; for example, it may be processed into a rectangle or other shape. Crystal semiconductor substrate 510 is processed using the CZ (Czochralski) method or the FZ (Floating Zone) method. It can be manufactured using the following method.

[0246] An oxide film 512 is formed on the surface of the single-crystal semiconductor substrate 510 (see Figure 11(D)). From the viewpoint of removing contaminants, before the formation of the oxide film 512, a hydrochloric acid-hydrogen peroxide mixed solution (HPM) is used. ), sulfuric acid hydrogen peroxide solution (SPM), ammonia hydrogen peroxide solution (APM) Dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc., are used for single-phase bonding. It is preferable to clean the surface of the crystalline semiconductor substrate 510. Dilute hydrofluoric acid and ozonated water are alternately used. It may be discharged and used for washing.

[0247] The oxide film 512 may be a single layer or a multilayer of, for example, a silicon oxide film or a silicon oxide nitride film. It can be formed by the following. The method for producing the above oxide film 512 is thermal oxidation, CVD Methods include sputtering and other methods. Also, when forming oxide film 512 using the CVD method... To achieve good bonding, tetraethoxysilane (abbreviation: TEOS: chemistry) is used. It is preferable to form a silicon oxide film using an organosilane such as Si(OC2H5)4). It's nice.

[0248] In this embodiment, a single crystal semiconductor substrate 510 is subjected to thermal oxidation treatment to form an oxide film 512 (Here, SiO x A film is formed. Thermal oxidation treatment involves adding halogens to an oxidizing atmosphere. It is preferable to do so.

[0249] For example, a single-crystal semiconductor substrate 510 is subjected to thermal oxidation treatment in an oxidizing atmosphere with added chlorine (Cl). By performing this process, a chlorinated oxide film 512 can be formed. In this case, The oxide film 512 becomes a film containing chlorine atoms. This chlorine oxidation causes exogenous impurities Pure heavy metals (e.g., Fe, Cr, Ni, Mo, etc.) are collected to form metal chlorides. This can be removed to the outside, thereby reducing contamination of the single-crystal semiconductor substrate 510. Furthermore, after bonding it to the base substrate 500, impurities such as Na from the base substrate are fixed in place. This prevents contamination of the single-crystal semiconductor substrate 510.

[0250] Furthermore, the halogen atoms to be included in the oxide film 512 are not limited to chlorine atoms. It may contain fluorine atoms. A method for fluorine-oxidizing the surface of a single-crystal semiconductor substrate 510 and For example, methods include immersion in an HF solution followed by thermal oxidation in an oxidizing atmosphere, or using NF3. One method involves adding the substance to an oxidizing atmosphere and performing thermal oxidation treatment.

[0251] Next, ions are accelerated by an electric field and irradiated onto the single-crystal semiconductor substrate 510, and by adding them, single-crystal A brittle region 514 with damaged crystal structure is formed at a predetermined depth in the crystalline semiconductor substrate 510 (Figure 1). 1(E)).

[0252] The depth of the region where the brittle region 514 is formed depends on the kinetic energy of the ions, their mass and charge, and the ion's energy. It can be adjusted by the angle of incidence of the ion, etc. Also, the embrittlement region 514 is the average of the ions It forms in a region at approximately the same depth as the penetration depth. Therefore, at the depth where ions are added, single ions form. The thickness of the single-crystal semiconductor layer separated from the crystalline semiconductor substrate 510 can be adjusted. The thickness of the single-crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm or more. The average penetration depth should be adjusted to be around 00 nm or less.

[0253] The irradiation treatment with these ions can be carried out using an ion doping device or an ion implantation device. It is possible. A typical example of an ion doping device is one that generates by plasma excitation of process gases. There is a non-mass separation type device that irradiates the object to be treated with all the ion species. This means that the ionic species in the rasma will be irradiated onto the object to be treated without mass separation. In contrast, Ion implantation devices are mass-separation type devices. In ion implantation devices, ion species in the plasma are processed. The ions are separated by mass, and a specific mass of ion species is irradiated onto the object to be treated.

[0254] In this embodiment, hydrogen is added to the single-crystal semiconductor substrate 510 using an ion doping device. Let's explain an example of adding gas. A gas containing hydrogen is used as the source gas. Ion is irradiated. Regarding n, H3 + It would be good to increase the ratio of H + H2 + H3 + Total H3 in relation to quantity + The proportion of [the specified value] should be 50% or more (more preferably 80% or more). H3 + By increasing the proportion of [this component], the efficiency of ion irradiation can be improved.

[0255] Note that the added ions are not limited to hydrogen. Other ions such as helium may also be added. Furthermore, the added ions are not limited to just one type; multiple types of ions may be added. For example However, when irradiating with hydrogen and helium simultaneously using an ion doping device, separate Compared to irradiation during the manufacturing process, the number of steps can be reduced, and the subsequent single-crystal semiconductor... It is possible to suppress surface roughness of the layer.

[0256] Furthermore, when forming the embrittlement region 514 using an ion doping device, heavy metals are also added simultaneously. Although it may be added, ion illumination through the oxide film 512 containing halogen atoms By performing this procedure, contamination of the single-crystal semiconductor substrate 510 by these heavy metals can be prevented. can.

[0257] Next, the base substrate 500 and the single-crystal semiconductor substrate 510 are placed facing each other, and the nitrogen-containing layer 502 The surface and the oxide film 512 are brought into close contact. This brings the base substrate 500 and the single crystal semiconductor substrate into close contact. The board 510 is bonded to the other board (see Figure 11(F)).

[0258] During bonding, a 0.0 mm mark is applied to one location on the base substrate 500 or the single-crystal semiconductor substrate 510. 001 N / cm 2 More than 100N / cm 2 For example, 1 N / cm 2 More than 20N / cm 2 It is desirable to apply the following pressure. Applying pressure brings the bonding surfaces closer together and tightly adheres to each other. In the area where they are in close contact, a bond is formed between the nitrogen-containing layer 502 and the oxide film 512, and in that area Spontaneous point junctions extend across almost the entire surface. These junctions involve van der Waals forces and hydrogen The bonding is active and can be performed at room temperature.

[0259] Before bonding the single-crystal semiconductor substrate 510 and the base substrate 500, It is preferable to perform surface treatment on the surface related to the single crystal semiconductor. This improves the bonding strength at the interface between the body substrate 510 and the base substrate 500.

[0260] Surface treatments include wet treatment, dry treatment, or a combination of wet and dry treatment. Combining can be used. Also, different wet treatments can be used in combination. You can use one method, or you can combine different dry treatments.

[0261] Furthermore, after bonding, heat treatment may be performed to increase the bonding strength. The processing temperature is set to a temperature at which separation does not occur in the embrittlement region 514 (for example, above room temperature, up to 400°C). (Less than) Also, while heating within this temperature range, the nitrogen-containing layer 502 and the oxide film 512 The parts may be joined together. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, or RTA (instantaneous). Thermal annealing (Rapid Thermal Annealing) equipment, microwave heating equipment, etc. These can be used. However, the above temperature conditions are merely examples, and the disclosed invention may vary. This interpretation is not intended to be limited to this one aspect.

[0262] Next, by performing a heat treatment, the single-crystal semiconductor substrate 510 is separated in the embrittlement region. A single-crystal semiconductor layer 5 is placed on the base substrate 500 via a nitrogen-containing layer 502 and an oxide film 512. Forms 16 (see Figure 11(G)).

[0263] Furthermore, it is desirable that the heat treatment temperature during the above separation is as low as possible. The lower the temperature at which the process is performed, the more effectively surface roughening of the single-crystal semiconductor layer 516 can be suppressed. For example, the heat treatment temperature during the above separation should be between 300°C and 600°C. A temperature between 400°C and 500°C is more effective.

[0264] Furthermore, after separating the single-crystal semiconductor substrate 510, 50 is applied to the single-crystal semiconductor layer 516. Heat treatment is performed at a temperature of 0°C or higher to reduce the concentration of hydrogen remaining in the single-crystal semiconductor layer 516. You may do so.

[0265] Next, by irradiating the surface of the single-crystal semiconductor layer 516 with laser light, the surface flatness is determined. A single-crystal semiconductor layer 518 is formed with improved properties and reduced defects. Heat treatment may be performed instead of irradiation treatment.

[0266] In this embodiment, immediately after the heat treatment related to the separation of the single-crystal semiconductor layer 516, Although laser light irradiation is performed, one aspect of the disclosed invention shall not be construed as being limited to this. i. After the heat treatment for separating the single-crystal semiconductor layer 516, an etching treatment is performed, and the single-crystal semiconductor The laser irradiation treatment may be performed after removing the areas with many defects on the surface of the conductive layer 516. Then, the flatness of the surface of the single-crystal semiconductor layer 516 is improved, and then the laser light irradiation treatment is performed. This is also acceptable. Note that the etching processes mentioned above include wet etching and dry etching. Either of these may be used. In addition, in this embodiment, the laser light is irradiated as described above. After injection, a thin-film thinning process may be performed to reduce the thickness of the single-crystal semiconductor layer 516. For thinning the semiconductor layer 516, either dry etching or wet etching is used, You can use both.

[0267] Through the above process, an SOI substrate having a single-crystal semiconductor layer 518 with good properties can be obtained. It is possible (see Figure 11(H)).

[0268] <Method for fabricating transistors> Next, please refer to Figure 12 for the method of fabricating transistor 570 using the SOI substrate described above. I will explain it.

[0269] Figure 12(A) is a cross-sectional view showing a portion of the SOI substrate prepared by the method shown in Figure 11.

[0270] First, the single-crystal semiconductor layer 518 is processed into an island shape to form the semiconductor layer 520 (Figure 12(B) (See reference). Furthermore, the threshold voltage of the transistor is controlled before and after this process. Then, impurities that impart n-type conductivity or p-type conductivity are added to the semiconductor layer. This is also possible. If the semiconductor is silicon, the impurities that impart n-type conductivity include, for example, Phosphorus and arsenic can be used. In addition, impurities that impart p-type conductivity include For example, boron, aluminum, gallium, etc., can be used.

[0271] Next, an insulating layer 522 is formed to cover the semiconductor layer 520 (see Figure 12(C)). The marginal layer 522 will later become the gate insulating layer. Here, plasma CVD is used. Therefore, a silicon oxide film will be formed as a single layer. The material and formation method of the insulating layer 522 are as follows. Refer to the description of the gate insulating layer (gate insulating layer 108, etc.) according to the previous embodiment. It is possible.

[0272] Next, a conductive layer is formed on the insulating layer 522, and then the conductive layer is selectively etched to form a semiconductor A gate electrode 524 is formed above the body layer 520 (see Figure 12(D)). Gate electrode 52 The material and forming method of 4 are the gate electrode (gate electrode 110, etc.) according to the previous embodiment. You can refer to the information regarding this matter.

[0273] Next, using the gate electrode 524 as a mask, impurities that impart a single conductivity type are added to the semiconductor layer 520. It is added to form impurity region 526 (see Figure 12(E)). Note that here, n-type Phosphorus (P) or arsenic (As) is added to form a transistor, but p-type transistors When forming a t-type material, impurities such as boron (B) and aluminum (Al) are added. Good. Here, the concentration of the added impurities can be set as appropriate.

[0274] Next, a sidewall insulating layer 528 is formed on the side of the gate electrode 524. The insulating layer 528 is formed so as to cover the insulating layer 522 and the gate electrode 524. Subsequently, by applying a highly anisotropic etching process to the insulating layer, it is formed in a self-aligned manner. This can be done. Also, at this time, the insulating layer 522 is partially etched to form the gate insulating layer 5 It is preferable to form 22a while exposing the impurity region 526.

[0275] Next, using the gate electrode 524 and the sidewall insulating layer 528 as a mask, a single conductivity type is used. The impurity elements to be added are added to the impurity region 526. The impurity elements added are of the same conductivity type as the impurity elements added in the previous step. The concentration is made higher than in the previous step. The addition of the impurity element results in the semiconductor layer 520 It has a pair of high-concentration impurity regions 530 and a pair of low-concentration impurity regions 532, and a channel formation Region 534 is formed (see Figure 12(G)). The high-concentration impurity region 530 is the source region. It functions as a region or drain region.

[0276] Furthermore, if the semiconductor layer 520 is made of a silicon-containing material, the source region and drain To further reduce the resistance of the region, a portion of the semiconductor layer 520 is silicided. A region may be formed. Silicide is a process in which a metal is brought into contact with a semiconductor layer and heat treatment is performed (for example). This process involves reacting silicon and metal in a semiconductor layer using methods such as GRTA and LRTA. If a silicide region is formed, it will be a cobalt silicide or nickel silicide. Good. If the semiconductor layer 520 is thin, the silicide reaction will proceed to the bottom of the semiconductor layer 520. It is also acceptable. Metal materials that can be used for silicide formation include titanium, nickel, and Streptomycin, molybdenum, cobalt, zirconium, hafnium, tantalum, vanadium Examples include neodymium, chromium, platinum, and palladium. Also, for applications such as laser light irradiation. Therefore, a silicide region can be formed.

[0277] Next, an interlayer insulating layer 536 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 538 (see Figure 12(H)). Interlayer insulating layer 536 and interlayer insulating layer 538 oxidize Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, t It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic resin. Although the invention has a laminated structure of an interlayer insulating layer 536 and an interlayer insulating layer 538, one aspect of the disclosed invention is It is not limited to this. It may be a single layer or a laminated structure of three or more layers. Interlayer insulating layer After the formation of 538, its surface is planarized by CMP or etching. It is desirable.

[0278] Next, openings are formed in the interlayer insulating layers 536 and 538 that extend to the high-concentration impurity region 530. The opening is then fitted with a source electrode or drain electrode 540a, and the source electrode or drain electrode Form electrode 540b (see Figure 12(H)). Source electrode or drain electrode 540a, The material and fabrication method of the source electrode or drain electrode 540b are as follows: Refer to the description regarding electrode 130a, source electrode or drain electrode 130b, etc. stomach.

[0279] As a result, transistor 570 using an SOI substrate is formed (see Figure 12(H)). Transistor 570, which uses materials other than oxide semiconductors, is capable of high-speed operation. These transistors can be used to construct logic circuits (also known as arithmetic circuits), etc. Furthermore, it can also be used as a drive circuit for driving the memory circuit shown in the above embodiment. Cut.

[0280] Furthermore, electrodes, wiring, insulating layers, etc., may be formed after the above process. Wiring structure By adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, We can provide highly integrated semiconductor devices.

[0281] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0282] (Embodiment 8) In this embodiment, the application example of the semiconductor device shown in the embodiment is shown in Figures 13 and 1. I will explain using number 4.

[0283] Figures 13(A) and 13(B) show the semiconductor device (hereinafter referred to as memory) shown in Figure 5(A-1). This is a circuit diagram of a semiconductor device formed using multiple (also written as Ru190) components. Figure 13(A ) is a circuit diagram of a so-called NAND-type semiconductor device in which memory cells 190 are connected in series. Figure 13(B) shows a so-called NOR type semiconductor, in which memory cells 190 are connected in parallel. This is a circuit diagram of a conductive device.

[0284] The semiconductor device shown in Figure 13(A) has source line SL, bit line BL, first signal line S1, and m lines. The second signal line S2, m word lines WL, and multiple memory cells 190(1,1)~190 (m, 1) is arranged in a vertical row of m units × horizontal column of 1 unit. Note that in Figure 13(A) The configuration has one source line SL and one bit line BL, but is not limited to this. No. By having n source lines SL and n bit lines BL, it is possible to create m rows x n columns. A configuration having a memory cell array of the following types may also be used.

[0285] In each memory cell 190, the gate electrode of transistor 160 and transistor 162 One of the source or drain electrodes of the capacitor and one of the electrodes of the capacitive element 164 are electrically connected. They are connected. Also, the first signal line S1 and the source electrode or drain of transistor 162 are connected. The other electrode is electrically connected to the second signal line S2 and the gate of transistor 162. The electrodes are electrically connected. And the word line WL and the electrode of the capacitive element 164 The other is electrically connected.

[0286] Furthermore, the source electrode of the transistor 160 of the memory cell 190 is adjacent to the memory cell The drain electrode of transistor 160 is electrically connected to the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. It is electrically connected to 160 source electrodes. However, it is connected in series to multiple memory cells. Of these, the drain of the transistor 160 of the memory cell 190 located at one end The electrodes are electrically connected to the bit lines. Also, multiple memory cells connected in series... The source electrode of the transistor 160 of the memory cell 190 located at the other end is It is electrically connected to the source wire.

[0287] The semiconductor device shown in Figure 13(A) performs line-by-line writing and reading operations. The write operation is performed as follows: A transistor is connected to the second signal line S2 of the line to be written. Apply a potential that turns on transistor 162, and turn on transistor 162 in the row to be written. This will connect the first signal line S1 to the gate electrode of transistor 160 in the specified row. A potential is applied, and a predetermined charge is given to the gate electrode. In this way, the specified Data can be written to the memory cells of a row.

[0288] Furthermore, the reading operation is performed as follows: First, the word lines WL other than the line to be read. Regardless of the charge on the gate electrode of transistor 160, transistor 160 is in the ON state. By applying a suitable potential, the transistors 160 other than those in the row being read are turned ON. Then, the gate electrode of transistor 160 is connected to the word line WL of the row to be read. The charge determines the potential such that the on or off state of transistor 160 is selected. (Apply the readout potential). Then, apply a constant potential to the source line SL and connect it to the bit line BL. The readout circuit (not shown) is set to the operating state. Here, the source line SL-bit Multiple transistors 160 between the T-line BL are ON except for the row being read, The conductance between source line SL and bit line BL is measured by transistor 1 of the row performing the readout. Determined by state 60. In other words, the gauge of transistor 160 of the row being read. The potential of the bit line BL read by the readout circuit will vary depending on the charge present on the electrode. To retrieve data, you can read it from the memory cell of the specified row.

[0289] The semiconductor device shown in Figure 13(B) has n source lines SL, bit lines BL, and a first signal line S1, m second signal lines S2 and word line WL, and multiple memory cells 190(1, 1 )~190(m, n) are memos arranged in a matrix of m rows x n columns. It has a recell array 181. The gate electrode of each transistor 160 and transistor 16 One of the source or drain electrodes of the 2 and one of the electrodes of the capacitive element 164 are electrically connected. It is connected to the source line SL and the source electrode of transistor 160. The bit line BL and the drain electrode of transistor 160 are electrically connected. Furthermore, the first signal line S1 and the source electrode or drain electrode of transistor 162 The other side is electrically connected to the second signal line S2 and the gate electrode of transistor 162. , electrically connected. And the word line WL and the other electrode of the capacitive element 164 are electrically connected. They are connected by energy.

[0290] The semiconductor device shown in Figure 13(B) performs line-by-line writing and reading operations. The write operation is performed in the same manner as the semiconductor device shown in Figure 13(A) above. Readout The operation is performed as follows: First, a transient is sent to the word line WL other than the line being read. Regardless of the charge on the gate electrode of transistor 160, the potential at which transistor 160 turns off is such that the transistor 160 is turned off. This sets transistor 160 to the OFF state for all rows except the one being read. Then, read The charge from the gate electrode of transistor 160 is applied to the word line WL of the row where the output is performed. , a potential (readout potential) such that the ON or OFF state of transistor 160 is selected. ) is given. Then, a constant potential is applied to the source line SL and the reading connected to the bit line BL is given. The output circuit (not shown) is set to the operating state. Here, the connection between the source line SL and the bit line BL The inductance is determined by the state of transistor 160 in the row being read out. Furthermore, the charge on the gate electrode of transistor 160 in the row being read out causes the read The potential of bit line BL read by the output circuit takes on different values. In this way, the specified line Data can be read from the memory cell.

[0291] Next, Figure 1 shows an example of a readout circuit that can be used in semiconductor devices such as the one shown in Figure 13. I will explain using number 4.

[0292] Figure 14(A) shows a schematic of the readout circuit. This readout circuit uses a transistor and a sensor. It has a amp circuit.

[0293] During read operation, terminal A is connected to the bit line to which the memory cell to be read is connected. Furthermore, a bias potential Vbias is applied to the gate electrode of the transistor, and the voltage at terminal A The position is controlled.

[0294] The memory cell 190 exhibits different resistance values ​​depending on the data stored. Specifically, If the transistor 160 of the selected memory cell 190 is in the ON state, it will be in a low-resistance state. If transistor 160 of the selected memory cell 190 is in the off state, it will be in a high-resistance state. .

[0295] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A. On the other hand, when the memory cell is in the low-resistance state, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "0") corresponding to the potential of terminal A.

[0296] Thus, by using the read circuit, data can be read from the memory cell. Note that the read circuit of this embodiment is an example. Other known circuits may be used. In addition, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected. FIG. 14(B) shows a differential sense amplifier as an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output. FIG. 14(C) shows a latch-type sense amplifier as an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signal Sp is set to High and the control signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials to be compared are applied to V1 and V2. After that, when the control signal Sp is set to Low and the control signal Sn is set to High to supply the power supply potential (Vdd), the comparison

[0297] is performed.

[0298]

[0299]

[0300] If the input potentials V1in and V2in satisfy V1in > V2in, the output of V1 is Hi gh and the output of V2 is Low. If V1in < V2in, the output of V1 is L ow and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified.

[0299] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0300] (Embodiment 9) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment will be described with reference to FIG. 15.

[0301] FIG. 15(A) shows an example of a semiconductor device having a configuration corresponding to a so-called DRAM (Dynamic Random Access Memory). The memory cell array 620 shown in FIG. 15(A) has a configuration in which a plurality of memory cells 630 are arranged in a matrix. The memory cell array 620 has m first wirings and n second wirings. Note that the memory cell 630 corresponds to the semiconductor device shown in FIG. 5(B). In this embodiment, the first wiring in FIG. 5(B) is referred to as a bit line BL, and the second wiring is referred to as a word line WL.

[0302] The memory cell 630 is composed of a transistor 631 and a capacitor element 632. The gate electrode of the transistor 631 is connected to the first wiring (word line WL). Also, one of the source electrode or drain electrode of the transistor 631 is connected to the second wiring (bit It is connected to wire BL, and the other of the source electrode or drain electrode of transistor 631. It is connected to one of the electrodes of the capacitive element. The other electrode of the capacitive element is connected to the capacitance line CL. It is connected to and a constant potential is applied. Transistor 631 has, in the previous embodiment The transistor shown is applicable.

[0303] The transistor shown in the previous embodiment has the characteristic of having an extremely small off-current. Therefore, the semiconductor device shown in Figure 15(A), which is recognized as a so-called DRAM, is a semiconductor device. When this transistor is applied, it is possible to obtain a virtually non-volatile memory.

[0304] Figure 15(B) shows what is known as SRAM (Static Random Access Module). An example of a semiconductor device with a configuration equivalent to a memory cell is shown. Figure 15(B) shows a memory cell. The array 640 has a configuration in which multiple memory cells 650 are arranged in a matrix. Yes, it is possible. Also, the memory cell array 640 has a first wiring (word line WL), a second wiring ( It has multiple bit lines (BL) and a third line (inverting bit line / BL).

[0305] The memory cell 650 has a first transistor 651 to a sixth transistor 656. The first transistor 651 and the second transistor 652 are selected transistors. It works. Also, of the third transistor 653 and the fourth transistor 654, one of them is It is an n-channel transistor (here, the fourth transistor 654), and the other is a p-channel transistor. This is a channel-type transistor (in this case, the third transistor 653). The CMOS circuit is composed of transistor 653 and a fourth transistor 654. Similarly, the CMOS circuit is powered by the fifth transistor 655 and the sixth transistor 656. It is composed of.

[0306] The first transistor 651, the second transistor 652, the fourth transistor 654, Transistor 656 is an n-channel type transistor, and in the above embodiment... The transistors shown can be applied. The third transistor 653 and the fifth transistor The 655 transistor is a p-channel transistor made of oxide semiconductor or other materials. It can be formed using materials such as silicon.

[0307] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0308] (Embodiment 10) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, This will be explained using Figure 16. In this embodiment, a computer and a mobile phone (mobile Telephones (also called mobile phones), personal information terminals (including portable game consoles, audio playback devices, etc.) (m), digital cameras, digital video cameras, etc., electronic paper, television Electronic devices such as televisions or television receivers use the aforementioned semiconductor equipment. This section explains when to apply the setting.

[0309] Figure 16(A) shows a notebook-type personal computer, consisting of chassis 701, chassis 702, It consists of a display unit 703, a keyboard 704, etc., and a casing 701 and a casing 702. Inside, the semiconductor device shown in the previous embodiment is provided. The device allows for high-speed writing and reading of information, long-term storage, and erasure. Power consumption has been significantly reduced. Therefore, information can be written and read at high speed. A notebook-type personal computer that can retain data for a specified period and has significantly reduced power consumption. The computer will be realized.

[0310] Figure 16(B) shows a personal digital assistant (PDA), and the main body 711 has a display unit 713 and an external A separate interface 715 and operation buttons 714 are provided. It is equipped with a stylus 712 for operating the end. Inside the main body 711, as in the previous embodiment, A semiconductor device is provided as shown. The semiconductor device shown in the above embodiment is used for writing information. And it has fast readout, long-term storage capability, and significantly reduced power consumption. Therefore, it allows for high-speed writing and reading of information, and enables long-term memory retention. Furthermore, this will result in a portable information terminal with significantly reduced power consumption.

[0311] Figure 16(C) shows an e-reader 720 with electronic paper installed, consisting of a casing 721 and a casing 72 It consists of two enclosures, 721 and 723, respectively, each containing a display unit 7 25 and a display unit 727 are provided. The housing 721 and housing 723 are connected by the shaft portion 737 It is connected and can open and close using the shaft portion 737 as an axis. Unit 21 includes a power supply 731, operation keys 733, a speaker 735, etc. (Cabinet 721) At least one of the housings 723 is provided with the semiconductor device shown in the previous embodiment. The semiconductor device shown in the above embodiment allows for high-speed writing and reading of information, and for long periods of time. It is capable of retaining data while significantly reducing power consumption. Therefore, writing information is easy. A power supply that offers high-speed read / recall, long-term storage, and significantly reduced power consumption. The children's book will be published.

[0312] Figure 16(D) shows a mobile phone, which consists of two casings, casing 740 and casing 741. Furthermore, the casings 740 and 741 slide and unfold as shown in Figure 16(D). It can be transformed from a separate state to an overlapping state, and can be miniaturized to suit portability. The enclosure 741 includes a display panel 742, a speaker 743, a microphone 744, and an operating panel. Key 745, pointing device 746, camera lens 747, external connection terminal 74 It is equipped with 8, etc. Also, the housing 740 has a solar cell 749 that charges the mobile phone. It also features an external memory slot 750, etc. Furthermore, the antenna is built into the housing 741. It is provided. At least one of the housings 740 and 741 is equipped with the semiconductor equipment shown in the previous embodiment. A place is provided. The semiconductor device shown in the previous embodiment is for writing and reading information. It is fast, capable of long-term memory retention, and has significantly reduced power consumption. Therefore, it offers high-speed information writing and reading, long-term memory retention, and low power consumption. A mobile phone with significantly reduced noise levels will be realized.

[0313] Figure 16(E) shows a digital camera, consisting of a main unit 761, a display unit 767, an eyepiece unit 763, and a control panel. It consists of a power switch 764, a display unit 765, a battery 766, etc. A semiconductor device as shown in the previous embodiment is provided inside 761. This semiconductor device allows for high-speed writing and reading of information and long-term storage. Furthermore, power consumption is significantly reduced. Therefore, information can be written and read at high speed. This resulted in a digital camera capable of long-term memory retention while significantly reducing power consumption. It will be done.

[0314] Figure 16(F) shows a television device 770, consisting of a housing 771, a display unit 773, and a stand. It consists of 775 and others. The television device 770 is operated by the casing 771. This can be done using the switch or the remote control unit 780. The housing 771 and the remote control unit The machine 780 is equipped with the semiconductor device shown in the previous embodiment. The semiconductor device shown allows for high-speed writing and reading of information and long-term storage. Furthermore, power consumption is significantly reduced. Therefore, information writing and reading are fast. A television system that is fast, capable of long-term memory retention, and has sufficiently reduced power consumption. It will be realized.

[0315] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with reduced power consumption can be realized. [Examples]

[0316] The number of rewriteable cycles of a semiconductor device according to one embodiment of the disclosed invention was investigated. This example Now, let's explain the results of this survey with reference to Figure 17.

[0317] The semiconductor device used in the investigation is the one with the circuit configuration shown in Figure 5(A-1). Furthermore, an oxide semiconductor was used for the transistor corresponding to transistor 162. A capacitance element with a capacitance value of 0.33 pF was used as the capacitor corresponding to sub-element 164.

[0318] The investigation involved determining the initial memory window width and the number of times data was retained and written. This was done by comparing it with the memory window width after iteration. Data retention and Data is written by applying 0V to the wiring corresponding to the third wiring in Figure 5(A-1), or Apply either 5V, and apply either 0V or 5V to the wire corresponding to the fourth wire. This was done by doing so. If the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to TA162 is in the off state, the floating gate section FG The given potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, then Since the transistor corresponding to transistor 162 is in the ON state, the wiring corresponding to the third wiring The potential of the line is applied to the floating gate section FG.

[0319] Memory window width is one of the indicators that show the characteristics of a storage device. Here, different memory The potential Vcg of the wiring corresponding to the fifth wiring in between states, and the potential of the wiring corresponding to transistor 160 The shift of the curve (Vcg-Id curve) that shows the relationship with the drain current Id of a transistor. This refers to the quantity ΔVcg. A different memory state is when the floating gate FG is at 0V. When the voltage is set to 5V, (hereinafter referred to as the Low state) and the floating gate FG is set to 5V This refers to the given state (hereinafter referred to as the High state). In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in both the Low and High states. In the case of displacement, Vds was assumed to be 1V.

[0320] Figure 17 shows the initial memory window width and 1 × 10 9 Notes after making a post The results of the re-window width investigation are shown. In Figure 17, the solid line represents the first write operation, and the broken line... The line is 1 x 10 9 This shows the [number]th entry. Also, in both the solid and dashed lines, the curve on the left is H The curve on the right shows the write state in the igh state, and the curve on the left shows the write state in the low state. Also, the horizontal axis is The vertical axis shows Vcg(V) and Id(A). From Figure 17, 1 × 10 9 Before this post Later, the memory window was swept by the potential Vcg in the High and Low states. It can be confirmed that the width has not changed. 1×10 9 Before and after each write operation, memory The fact that the end width does not change means that, at least during this time, the characteristics of the semiconductor device do not change. This indicates that...

[0321] As described above, a semiconductor device according to one aspect of the disclosed invention performs holding and writing multiple times. The properties do not change even after repeated use. In other words, according to one aspect of the disclosed invention, it is extremely reliable. This means that highly efficient semiconductor devices will be realized. [Explanation of symbols]

[0322] 10 memory cell arrays 20-column decoder 30 Low Decoders 40 I / O controllers 50 I / O buffers 60 command buffers 70 Address Buffers 80 Controllers 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 132 Insulating layer 134 Insulating layer 138 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 142c electrode 142d electrode 143 Insulating layer 144 Oxide semiconductor layer 146 Gate Insulation Layer 148a Token 148b Electrode 150 interlayer insulating layer 152 Interlayer insulating layer 160 transistors 162 transistors 164 Capacitive elements 170 transistors 181 memory cell array 190 memory cells 200 Items to be processed 202 Insulating layer 206 oxide semiconductor layer 206a Oxide Semiconductor Layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate Insulation Layer 214 Grid gate 216 Interlayer insulating layer 218 Interlayer insulating layer 250 transistors 300 Items to be processed 302 Insulating layer 304 First oxide semiconductor layer 304a First oxide semiconductor layer 305 Second oxide semiconductor layer 306 Second oxide semiconductor layer 306a Second oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate Insulation Layer 314 gate 316 Interlayer insulating layer 318 Interlayer insulating layer 350 transistors 400 Items to be processed 402 Insulating layer 406 oxide semiconductor layer 406a Oxide Semiconductor Layer 408 Conductive layer 408a Source electrode or drain electrode 408b Source electrode or drain electrode 410 Insulating layer 410a Insulating layer 410b Insulating layer 411a Oxidized area 411b Oxidized region 412 Gate Insulation Layer 414 gate 416 Interlayer insulating layer 418 Interlayer insulating layer 450 transistors 500 base board 502 Nitrogen-containing layer 510 Single-crystal semiconductor substrate 512 Oxide film 514 Embrittlement area 516 Single-crystal semiconductor layer 518 Single-crystal semiconductor layer 520 Semiconductor Layers 522 Insulating layer 522a Gate Insulation Layer 524 Shutdown gate 526 Impurity region 528 Sidewall insulation layer 530 High concentration impurity region 532 Low concentration impurity region 534 Channel formation region 536 Interlayer insulating layer 538 Interlayer insulating layer 540a Source electrode or drain electrode 540b Source electrode or drain electrode 570 transistors 620 memory cell array 630 memory cells 631 transistors 632 Capacitive elements 640 memory cell array 650 memory cells 651 transistors 652 transistors 653 Transistors 654 transistors 655 transistors 656 transistors 701 cabinet 702 cabinet 703 Display section 704 Keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Buttons 715 External Interface 720 eBooks 721 cabinet 723 cabinet 725 Display section 727 Display section 731 Power supply 733 Operation Keys 735 Speakers 737 Shaft 740 cabinets 741 cabinets 742 Display Panel 743 Speakers 744 Microphone 745 Operation Keys 746 Pointing devices 747 Camera Lenses 748 External connection terminal 749 solar cells 750 external memory slots 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television equipment 771 cabinet 773 Display section 775 Stand 780 Remote Control Unit

Claims

1. A semiconductor device having a first transistor, a charge holding part, a first wiring, and a second wiring, The first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first oxide semiconductor layer having a channel-forming region. The off-current density at room temperature in the first transistor is from 10 zaA / μm to 100 zaA / μm. The first gate electrode is electrically connected to the first wiring, One of the first source electrode and the first drain electrode is electrically connected to the second wiring. A semiconductor device in which the other of the first source electrode and the first drain electrode is electrically connected to the charge holding portion.

2. A semiconductor device having a first transistor, a charge holding part, a first wiring, and a second wiring, The first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first oxide semiconductor layer having a channel-forming region. The first oxide semiconductor layer has a hydrogen concentration of 5 × 10 １９ atoms / cm ３ It has the following region: The first gate electrode is electrically connected to the first wiring, One of the first source electrode and the first drain electrode is electrically connected to the second wiring. A semiconductor device in which the other of the first source electrode and the first drain electrode is electrically connected to the charge holding portion.

3. A semiconductor device having a first transistor, a charge holding part, a first wiring, and a second wiring, The first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first oxide semiconductor layer having a channel-forming region. The off-current density at room temperature in the first transistor is from 10 zaA / μm to 100 zaA / μm. The first oxide semiconductor layer has a hydrogen concentration of 5 × 10 １９ atoms / cm ３ It has the following region: The first gate electrode is electrically connected to the first wiring, One of the first source electrode and the first drain electrode is electrically connected to the second wiring. A semiconductor device in which the other of the first source electrode and the first drain electrode is electrically connected to the charge holding portion.

4. In any one of claims 1 to 3, It further has a third wiring, The charge holding portion has a capacitive element, One electrode of the capacitive element is electrically connected to the other of the first source electrode and the first drain electrode. The other electrode of the capacitive element is electrically connected to the third wiring, thereby forming a semiconductor device.

5. In any one of claims 1 to 3, It further comprises a second transistor, a third wire, a fourth wire, and a fifth wire. The charge holding portion has a capacitive element, The second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second oxide semiconductor layer having a channel-forming region. The second gate electrode is electrically connected to the other of the first source electrode and the first drain electrode. One electrode of the capacitive element is electrically connected to the second gate electrode. The other electrode of the capacitive element is electrically connected to the third wiring. One of the second source electrode and the second drain electrode is electrically connected to the fourth wiring. A semiconductor device in which the other end of the second source electrode and the second drain electrode is electrically connected to the fifth wiring.

6. In claim 5, A semiconductor device in which, if R1 is the resistance value due to the insulating layer of the capacitive element, R2 is the resistance value due to the gate insulating layer when the second transistor is ON, and ROS is the resistance value between the first source electrode and the first drain electrode when the first transistor is OFF, then R1 ≥ ROS and R2 ≥ ROS.

7. In claim 5, A semiconductor device in which, if the capacitance value of the aforementioned capacitive element is C1 and the gate capacitance of the second transistor is C2, then C1 ≥ C2.

8. In any one of claims 1 to 3, It further comprises a second transistor, a third wiring, and a fourth wiring. The charge holding unit has a third transistor, The second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second oxide semiconductor layer having a channel-forming region. The third transistor comprises a third gate electrode, a third source electrode, a third drain electrode, and a third oxide semiconductor layer having a channel-forming region. The other of the first source electrode and the first drain electrode is electrically connected to the third gate electrode. One of the second source electrode and the second drain electrode is electrically connected to the third wiring. One of the third source electrode and the third drain electrode is electrically connected to the fourth wiring. A semiconductor device in which the other end of the third source electrode and the third drain electrode is electrically connected to the other end of the second source electrode and the second drain electrode.

9. In any one of claims 1 to 4, The first oxide semiconductor layer is a semiconductor device having an In-O based oxide semiconductor.

10. In any one of claims 5 to 7, The semiconductor device has an In-O based oxide semiconductor as the second oxide semiconductor layer.

11. In claim 8, The second oxide semiconductor layer has an In-O based oxide semiconductor, The third oxide semiconductor layer is a semiconductor device having an In-O based oxide semiconductor.

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