Vertical resonator type surface-emitting laser element and method for manufacturing the same

Abstract

To provide a vertical-cavity surface-emitting laser element capable of improving reliability. [Solution] A vertical-cavity surface-emitting laser element according to one embodiment comprises a semiconductor substrate, a first contact layer of a first conductivity type provided on the semiconductor substrate, a mesa structure provided on the first contact layer, and a first electrode electrically connected to the mesa structure via the first contact layer. The mesa structure includes a first mirror layer, at least one AlAs oxide layer provided on the first mirror layer, at least one active layer provided above or below the AlAs oxide layer, a second mirror layer provided on the active layer, a second contact layer of a second conductivity type provided on the second mirror layer, a second electrode provided on the second contact layer, and an insulating region provided on the sidewall of the mesa structure. The length of the AlAs oxide layer from the sidewall is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more.

Description

[Technical Field]

[0001] This disclosure relates to a vertical cavity surface-emitting laser element and a method for manufacturing the same. [Background technology]

[0002] Vertical cavity surface-emitting laser elements (VCSELs), also known as VCSELs, are a type of semiconductor laser element that resonates light perpendicular to the substrate surface and emits laser light in the same direction. When multiple VCSEL elements are arranged in a two-dimensional array on a wafer, the number of VCSEL elements can be increased by narrowing the pitch between them, thereby reducing manufacturing costs.

[0003] When considering pitch reduction for GaAs-based (gallium arsenide) VCSEL elements, the oxidation length of the AlAs (aluminum arsenide) layer is a crucial parameter. In GaAs-based VCSEL elements, the AlAs oxide layer is frequently used as a means of narrowing the current and optical paths. The shorter this oxidation length, the smaller the mesa diameter of the VCSEL element can be. As a result, the pitch spacing between VCSEL elements also becomes narrower. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2021 / 192533 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, a shorter AlAs oxide length can lead to decreased reliability. One reason for this decreased reliability is that shorter AlAs oxide lengths allow carriers to spread more easily to the sidewalls of the mesa structure. These sidewalls contain fine defects caused by damage during the etching process used to manufacture the mesa structure. When carriers spread to these defects, the reliability of the device tends to decrease.

[0006] This disclosure provides a vertical cavity type surface-emitting laser element and a method for manufacturing the same that can improve reliability. [Means for solving the problem]

[0007] A vertical resonator type surface-emitting laser element according to one embodiment of the present disclosure is Semiconductor substrate and A first contact layer of a first conductivity type is provided on the semiconductor substrate, A mesa structure provided on the first contact layer, The system comprises a first electrode electrically connected to the mesa structure via the first contact layer, The aforementioned mesa structure is The first mirror layer, A first mirror layer is provided with at least one AlAs oxide layer, At least one active layer provided above or below the AlAs oxide layer, A second mirror layer provided on the active layer, A second contact layer of second conductivity type provided on the second mirror layer, A second electrode provided on the second contact layer, The mesa structure includes an insulating region provided on the side wall, The length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more.

[0008] The above vertical cavity surface emitting laser device may further include at least one tunnel junction layer provided between the active layer and the first mirror layer or between the active layer and the second mirror layer.

[0009] The upper end of the insulating region is located on the upper surface of the mesa structure, The lower end of the insulating region may be located on the upper surface of the AlAs oxide layer disposed at the lowermost layer of the mesa structure among the at least one AlAs oxide layer.

[0010] The upper end of the insulating region is located between the active layer and the second mirror layer, The lower end of the insulating region may be located on the upper surface of the AlAs oxide layer disposed at the lowermost layer of the mesa structure among the at least one AlAs oxide layer.

[0011] The second mirror layer is divided into a semiconductor mirror layer thinner than the first mirror layer and a dielectric mirror layer provided on the semiconductor mirror layer, The upper end of the insulating region may be located between the semiconductor mirror layer and the dielectric mirror layer.

[0012] The first electrode is commonly connected to a plurality of mesa structures through the first contact layer, The second contact layer and the second electrode may be provided for each of the plurality of mesa structures.

[0013] The first mirror layer may be divided into an upper mirror layer and a lower mirror layer facing each other with the first contact layer interposed therebetween.

[0014] The ion species included in the insulating region are H + , He + , Li + , Be + , B + , C + , N + , O [[ID=*47]] + , Ne + , Ar +Either of these is acceptable.

[0015] The insulating region does not necessarily have to overlap with the second electrode in the in-plane direction.

[0016] A method for manufacturing a vertical resonator type surface-emitting laser element according to one embodiment of this disclosure is as follows: A step of forming a laminate on a semiconductor substrate in which a first contact layer of a first conductivity type, a first mirror layer, at least one AlAs layer, and at least one active layer are stacked. A step of forming an insulating region in the laminate by implanting ions from the upper surface of the laminate using a first photoresist patterned to mask non-ion implanted regions, A step of forming a mesa structure in which the insulating region is formed on the side wall by etching a part of the laminate using a second photoresist patterned to mask the non-etched region, The process includes oxidizing at least one AlAs layer to form an AlAs oxide layer, The length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more. [Brief explanation of the drawing]

[0017] [Figure 1] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the first embodiment. [Figure 2] This is a cross-sectional view showing the process of forming a laminate according to the first embodiment on a semiconductor substrate. [Figure 3] This is a cross-sectional view showing the process of forming an insulating region in a laminate by ion implantation. [Figure 4] This is a cross-sectional view showing the process of etching the insulating region and the first mirror layer. [Figure 5] This is a cross-sectional view showing the process of oxidizing the first AlAs layer and the second AlAs layer. [Figure 6A]This graph shows an example of aging test results. [Figure 6B] This graph shows an example of aging test results. [Figure 6C] This graph shows an example of test results for the optical output characteristics of a VCSEL element, depending on the distance D from the tip of the AlAs oxide layer to the insulating region. [Figure 7] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the second embodiment. [Figure 8] This is a cross-sectional view showing the process of forming a laminate according to the second embodiment on a semiconductor substrate. [Figure 9] This is a cross-sectional view showing the process of forming an insulating region by implanting ions from the regrowth interface. [Figure 10] This is a cross-sectional view showing the process of forming the second mirror layer and the second contact layer on the laminate. [Figure 11] This is a cross-sectional view showing the process of etching the second mirror layer, the second contact layer, the insulating region, and the first mirror layer. [Figure 12] This is a cross-sectional view showing the process of oxidizing the first AlAs layer, the second AlAs layer, and the third AlAs layer. [Figure 13] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the third embodiment. [Figure 14] This is a cross-sectional view showing the process of forming a laminate according to the third embodiment on a semiconductor substrate. [Figure 15] This is a cross-sectional view showing the process of forming an insulating region by implanting ions from the surface of the second contact layer. [Figure 16] This is a cross-sectional view showing the process of forming a dielectric mirror layer on top of the insulating region and the second contact layer. [Figure 17] This is a cross-sectional view showing the process of etching the dielectric mirror layer. [Figure 18] This is a cross-sectional view showing the process of etching the insulating region and the first mirror layer. [Figure 19] This is a cross-sectional view showing the process of oxidizing the first AlAs layer, the second AlAs layer, and the third AlAs layer. [Figure 20] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the fourth embodiment. [Figure 21] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the fifth embodiment. [Figure 22] This is a cross-sectional view showing the structure of the main part of the VCSEL element according to the sixth embodiment. [Figure 23] This is a cross-sectional view showing the process of forming a laminate according to the sixth embodiment on a semiconductor substrate. [Figure 24] This is a cross-sectional view showing the process of forming a second electrode on the second contact layer. [Figure 25] This is a cross-sectional view showing the process of forming an insulating region by ion implantation using the second electrode as a mask. [Figure 26] This is a cross-sectional view showing the process of etching the insulating region and the first mirror layer. [Figure 27] This is a cross-sectional view showing the process of oxidizing the first AlAs layer and the second AlAs layer. [Modes for carrying out the invention]

[0018] Hereinafter, embodiments of the vertical cavity surface-emitting laser element (hereinafter referred to as VCEL element) according to this disclosure will be described with reference to the drawings. In the following embodiments, the main components of the VCEL element will be described, but the VCEL element may have components and functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0019] (First Embodiment) Figure 1 is a cross-sectional view showing the structure of the main part of a VCSEL element according to the first embodiment. In the following description, two mutually orthogonal in-plane directions will be referred to as the x-direction and the y-direction. The out-of-plane direction orthogonal to the x-direction and the y-direction will be referred to as the z-direction. The VCSEL element 1 shown in Figure 1 comprises a semiconductor substrate 110, a first contact layer 120, a first electrode 130, and a mesa structure 200.

[0020] The semiconductor substrate 110 is, for example, a GaAs substrate. A first contact layer 120 is formed on the semiconductor substrate 110.

[0021] The first contact layer 120 is an n-type (first conductivity type) semiconductor layer containing, for example, AlGaAs (aluminum gallium arsenide). The first electrode 130 is formed on the first contact layer 120.

[0022] The first electrode 130 contains a metal such as Ti, Pt, or Au. The first electrode 130 is electrically connected to the mesa structure 200 via the first contact layer 120. In this embodiment, an opening is formed in the center of the first electrode 130, and the mesa structure 200 is placed within this opening.

[0023] The mesa structure 200 has a so-called two-multistack configuration via a tunnel junction. Specifically, the mesa structure 200 has a first mirror layer 211, a first AlAs oxide layer 221, a first active layer 231, a first tunnel junction layer 241, a second AlAs oxide layer 222, a second active layer 232, a second mirror layer 212, a second contact layer 250, and a second electrode 260 stacked on top of each other.

[0024] The first mirror layer 211 is located at the bottom of the mesa structure 200. In the first mirror layer 211, two semiconductor layers with different refractive indices are alternately stacked in the z direction.

[0025] The first AlAs oxide layer 221 is placed on top of the first mirror layer 211. The first AlAs oxide layer 221 functions as a means of narrowing the optical path of light reflected by the first mirror layer 211.

[0026] The first active layer 231 is placed on top of the first AlAs oxide layer 221. The first active layer 231 emits and amplifies spontaneous emission light through carrier recombination. The first active layer 231 is an InGaAs-based semiconductor layer having an oscillation wavelength of 920 nm to 960 nm.

[0027] The first tunnel junction layer 241 is placed on top of the first active layer 231. The first tunnel junction layer 241 joins the first laminate, which consists of the first mirror layer 211 to the first active layer 231, and the second laminate, which consists of the second AlAs oxide layer 222 to the second mirror layer 212.

[0028] The second AlAs oxide layer 222 is placed on top of the first tunnel junction layer 241. The second AlAs oxide layer 222 functions as a means of narrowing the optical path of light reflected by the second mirror layer 212.

[0029] The second active layer 232 is placed on top of the second AlAs oxide layer 222. The second active layer 232, like the first active layer 231, is an InGaAs-based semiconductor layer having an oscillation wavelength of 920 nm to 960 nm.

[0030] The second mirror layer 212 is placed on top of the second active layer 232. In the second mirror layer 212, similar to the first mirror layer 211, two semiconductor layers with different refractive indices are alternately stacked in the z direction.

[0031] The second contact layer 250 is placed on top of the second mirror layer 212. The second contact layer 250 is, for example, a p-type (second conductivity type) semiconductor layer.

[0032] The second electrode 260 is provided on the second contact layer 250. The second electrode 260 contains a transparent metal such as ITO and is formed in a circular shape with an opening that exposes the central region of the mesa structure 200.

[0033] In the VCSEL element 1 according to this embodiment, when a voltage is applied between the second electrode 260 and the first electrode 130, a current is injected into the mesa structure 200. This injected current generates spontaneous emission light through carrier recombination in the first active layer 231 and the second active layer 232. The spontaneous emission light propagates in the stacking direction (Z direction) of the mesa structure 200 and is repeatedly reflected between the second mirror layer 212 and the first mirror layer 211.

[0034] The second mirror layer 212 and the first mirror layer 211 are configured to reflect specific colored light (e.g., red light). Therefore, wavelength components of specific colored light in the spontaneously emitted light form standing waves, which are amplified by the first active layer 231. When the injected current exceeds a threshold, the light forming the standing waves generates laser oscillation. The resulting laser light (see arrow in Figure 1) passes through the second mirror layer 212 and is emitted to the upper side of the VCSEL element 1.

[0035] In the VCSEL element 1 according to this embodiment, if the length L1 in the y-direction of the first AlAs oxide layer 221 and the second AlAs oxide layer 222 is short, carrier diffusion is more likely to occur to the sidewall portion of the mesa structure 200. As a result, defects in the sidewall portion extend to the optical field due to carrier stress, which can reduce reliability. In particular, carrier diffusion is more likely in the upper first active layer 231, the second active layer 232, and the first tunnel junction layer 241.

[0036] Therefore, in this embodiment, by providing an insulating region 270 in the mesa structure 200, carrier diffusion to the side walls is suppressed, thereby improving reliability.

[0037] The manufacturing process of the VCSEL element 1 according to this embodiment will be described below with reference to Figures 2 to 5.

[0038] First, as shown in Figure 2, a laminate 200A is formed on a semiconductor substrate 110 by sequentially stacking a first contact layer 120, a first mirror layer 211, a first AlAs layer 221A, a first active layer 231, a first tunnel junction layer 241, a second AlAs layer 222A, a second active layer 232, a second mirror layer 212, and a second contact layer 250. The semiconductor layers within this laminate 200A are formed, for example, using a metal-organic chemical vapor deposition (MOCVD) method. The second mirror layer 212 and the first mirror layer 211 are entirely composed of semiconductors. Furthermore, the optical film thickness of each mirror layer is formed in a superlattice pattern such that it is 1 / 4λ of the oscillation wavelength λ.

[0039] Next, as shown in Figure 3, an insulating region 270 is formed by implanting ions from the top surface of the laminate 200A using the photoresist 300 as a mask. The photoresist 300 is patterned on the second contact layer 250 so as to shield the non-ion implanted region. The ions implanted from the top surface of the second contact layer 250 reach the top surface of the first AlAs layer 221A. The ion species are, for example, H + He + Li + Be + B + , C + , N + , O + Ne + Ar + It is one of the following. Also, the dose of ions injected is 1 × 10⁻⁶. 14 atoms / cm 2 That's all.

[0040] Next, as shown in Figure 4, the insulating region 270 and the first mirror layer 211 are etched using the RIE (Reactive Ion Etching) method, with the photoresist 310 acting as a mask. This removes a portion of the laminate 200A, forming the mesa structure 200. The photoresist 310 is patterned on the second contact layer 250 and the insulating region 270 so as to shield the non-etched areas.

[0041] Next, as shown in Figure 5, the first AlAs layer 221A and the second AlAs layer 222A are oxidized from the sidewalls of the mesa structure 200, for example, using steam oxidation. As a result, the first oxidized AlAs layer 221 and the second oxidized AlAs layer 222 are completed. Note that in Figure 5, the unoxidized portions of the first AlAs layer 221A and the second AlAs layer 222A are not shown. In addition, the ion-implanted portion of the second AlAs layer 222A is also oxidized.

[0042] Finally, returning to Figure 1, a second electrode 260 is formed on the second contact layer 250, and a first electrode 130 is formed on the first contact layer 120. For example, each contact layer is formed by depositing a metal layer using vacuum deposition or sputtering, followed by removing the unwanted metal portion using a lift-off method.

[0043] Here, we will explain the technical effects obtained by forming the insulating region 270. In this embodiment, the upper end of the insulating region 270 is located on the upper surface of the mesa structure 200, specifically on the upper surface of the second contact layer 250. The lower end of the insulating region 270 is located on the upper surface of the first AlAs oxide layer 221, which is the lowest layer in the AlAs oxide layer.

[0044] Figure 6A is a graph showing an example of aging test results. In Figure 6A, the horizontal axis represents the aging test time, and the vertical axis represents the optical output of the VCSEL element. Figure 6A also shows optical output characteristics C11 and C12. Optical output characteristic C11 shows the aging test results when the oxidation length of the AlAs oxide layer in a VCSEL element without an insulating region 270 is 5.0 μm or less. On the other hand, optical output characteristic C12 shows the aging test results when the oxidation length of the AlAs oxide layer in a VCSEL element without an insulating region 270 is longer than 5.0 μm.

[0045] As shown in Figure 6A, when the insulating region 270 is not formed, if the oxidation length of the AlAs oxide layer becomes 5.0 μm or less, a tendency for the optical output to decrease with the passage of aging test time can be observed.

[0046] Figure 6B is a graph showing an example of aging test results. In Figure 6B, the horizontal axis represents the aging test time, and the vertical axis represents the optical output of the VCSEL element. Figure 6B shows the optical output characteristics C21 when the insulating region 270 is not formed, and the optical output characteristics C22 when the insulating region 270 is formed, with the oxidation length being 5.0 μm or less in both cases. In the optical output characteristics C2, the width w of the insulating region 270 (see Figure 1) is 0.2 μm.

[0047] If the insulating region 270 is not formed, the optical output decreases as the aging test time progresses, as shown in the optical output characteristic C21. On the other hand, if the insulating region 270 is formed as in this embodiment, even if the width w of the insulating region 270 is 5.0 μm or less, the optical output remains stable without decreasing even after the aging test time has elapsed, as shown in the optical output characteristic C22. This is because the insulating region 270 suppresses the diffusion of carriers to the mesa sidewall. In particular, in this embodiment, the insulating region 270 is formed by ion implantation reaching the first active layer 231, the second active layer 232, and the first tunnel junction layer 241, insulating the sidewall of the mesa structure 200. This improves reliability.

[0048] Figure 6C is a graph showing an example of the test results of the optical output characteristics of a VCSEL element according to the distance D from the leading edge of the AlAs oxide layer to the insulating region 270. In Figure 6C, the horizontal axis represents the current flowing through the non-oxidized portion of the AlAs layer, and the vertical axis represents the optical output of the VCSEL element. Figure 6C also shows optical output characteristics C31-C33. Optical output characteristic C31 shows the optical output when the distance D is 0 μm. Optical output characteristic C32 shows the optical output when the distance D is 0.5 μm. Optical output characteristic C33 shows the optical output when the distance D is 1.0 μm.

[0049] As shown in Figure 6C, in a VCSEL element where the distance D is 0 μm, laser oscillation does not occur due to light absorption loss. On the other hand, if the distance D is 0.5 μm, it becomes possible to prevent a decrease in optical output characteristics caused by light absorption.

[0050] For example, if the length L1 (see Figure 1) of the first AlAs oxide layer 221 from the side wall of the mesa structure 200 is 0.5 μm or more and 5.0 μm or less, preferably 1.0 μm or more and 3.5 μm or less, then reliability can be sufficiently improved if the width w of the insulating region 270, i.e., the ion implantation width, is within the range of 0.2 μm to 0.5 μm. In this case, since the distance D from the leading edge of each of the first AlAs oxide layer 221 and the second AlAs oxide layer 222 to the insulating region 270 is 0.5 μm or more, a technical effect of reducing light absorption loss can also be obtained.

[0051] Of the first active layer 231 and the second active layer 232, the portions insulated by the insulating region 270 are converted into light absorption sources rather than gain sources. When these overlap with the optical field, light absorption loss occurs, which can degrade the laser characteristics. Each AlAs oxide layer confines lateral light inside itself (the unoxidized first AlAs layer 221A and second AlAs layer 222A) to form an optical field. In this case, if the above distance D is secured to be 0.5 μm or more, degradation of laser characteristics due to light absorption loss can be avoided.

[0052] As described above, this embodiment makes it possible to improve reliability. In addition, in this embodiment, since the width w of the insulating region 270, i.e., the ion implantation width, is narrow, a sufficient contact area is secured between the second electrode 260 and the second contact layer 250 that has not been ion implanted. This makes it possible to reduce the resistance increase caused by contact resistance between the second electrode 260 and the second contact layer 250.

[0053] (Second Embodiment) Figure 7 is a cross-sectional view showing the structure of the main part of the VCSEL element according to the second embodiment. In the following description, the same reference numerals are used for components similar to those of the VCSEL element 1 according to the first embodiment, and redundant explanations are omitted.

[0054] In the VCSEL element 2 shown in Figure 7, the number of multi-stacks is greater than that of the VCSEL element 1 according to the first embodiment. Specifically, the second tunnel junction layer 242, the third AlAs oxide layer 223, and the third active layer 233 are provided on the second active layer 232 in this order.

[0055] As the number of multi-stacks increases, it becomes necessary to implant ions to a deeper location than in the first embodiment in order to perform ion implantation that reaches all of the active layer and tunnel junction layer from the surface of the mesa structure 200. However, depending on the thickness of the semiconductor layer within the mesa structure 200, it may be difficult to reach all of the active layer and tunnel junction layer.

[0056] Therefore, in this embodiment, a regrowth interface 280 is provided in the semiconductor layer located above the third active layer 233, and ion implantation is performed from the regrowth interface 280 before regrowth. That is, the upper end of the insulating region 270 is located between the third active layer 233 and the second mirror layer. Also, the lower end of the insulating region 270 is located on the upper surface of the first AlAs oxide layer 221, which is the lowest layer in the AlAs oxide layer. This allows ions to reach a deeper position than in the first embodiment. Current diffusion to the sidewalls of the mesa structure 200 is likely to occur in the active layer and the tunnel junction layer. Therefore, if these layers are insulated by ion implantation, reliability is improved even if the sidewalls of the regrowth layer are not insulated.

[0057] The manufacturing process of the VCSEL element 2 according to this embodiment will be described below with reference to Figures 8 to 12.

[0058] First, as shown in Figure 8, a laminate 200B is formed on a semiconductor substrate 110 by sequentially stacking a first contact layer 120, a first mirror layer 211, a first AlAs layer 221A, a first active layer 231, a first tunnel junction layer 241, a second AlAs layer 222A, a second active layer 232, a second tunnel junction layer 242, a third AlAs layer 223A, and a third active layer 233. Each layer is formed by epitaxial growth. However, this epitaxial growth is temporarily stopped before the formation of the second mirror layer 212. As a result, the upper surface of the laminate 200B corresponds to the regrowth interface 280.

[0059] Next, as shown in Figure 9, an insulating region 270 is formed by implanting ions from the regrowth interface 280 using the photoresist 300 as a mask. The ion species and dose amount used in this ion implantation process are the same as in the first embodiment.

[0060] Next, as shown in Figure 10, the second mirror layer 212 and the second contact layer 250 are formed on the laminate 200B. The second mirror layer 212 and the second contact layer 250 are formed in the same manner as in the first embodiment.

[0061] Next, as shown in Figure 11, the second mirror layer 212, the second contact layer 250, the insulating region 270, and the first mirror layer 211 are etched using the RIE method, with the photoresist 310 acting as a mask. This removes a portion of the laminate 200B, forming the mesa structure 200. The photoresist 310 is patterned on the second contact layer 250 so as to shield the non-etched regions.

[0062] Next, as shown in Figure 12, the first AlAs layer 221A, the second AlAs layer 222A, and the third AlAs layer 223A are oxidized from the sidewall portion of the mesa structure 200, for example, using steam oxidation. As a result, the first oxidized AlAs layer 221, the second oxidized AlAs layer 222, and the third oxidized AlAs layer 223 are completed. Note that in Figure 12, the unoxidized portions of each AlAs layer are omitted from the illustration. In addition, the ion-implanted portions of the second AlAs layer 222A and the third AlAs layer 223A are also oxidized.

[0063] Finally, returning to Figure 7, the second electrode 260 is formed on the second contact layer 250, and the first electrode 130 is formed on the first contact layer 120. Each electrode is formed in the same manner as in the first embodiment.

[0064] According to the embodiment described above, the insulating region 270 suppresses current diffusion to the sidewall portion of the mesa structure 200, thereby improving reliability. In addition, in this embodiment, by providing a regrowth interface 280, ions can reach deeper positions. This makes it possible to improve design flexibility, such as increasing the number of multi-stacks.

[0065] (Third embodiment) Figure 13 is a cross-sectional view showing the structure of the main part of the VCSEL element according to the third embodiment. In the following description, the same reference numerals are used for components similar to those of the VCSEL element 2 according to the second embodiment, and redundant explanations are omitted.

[0066] In the VCSEL element 3 shown in Figure 13, the number of multi-stacks is greater than that of the VCSEL element 1 according to the first embodiment, similar to the second embodiment. However, in this embodiment, instead of providing the regrowth interface 280 described in the second embodiment, the second mirror layer 212 is divided into a semiconductor mirror layer 2121 and a dielectric mirror layer 2122. As a result, the upper end of the insulating region 270 is located between the semiconductor mirror layer 2121 and the dielectric mirror layer 2122.

[0067] The semiconductor mirror layer 2121 is provided between the third active layer 233 and the second contact layer 250. In the semiconductor mirror layer 2121, two semiconductor layers with different optical refractions are alternately stacked in the z direction.

[0068] On the other hand, the dielectric mirror layer 2122 is provided on the second contact layer 250 and covered by the second electrode 260. In the dielectric mirror layer 2122, two dielectric layers with different optical refractions are alternately stacked in the z direction.

[0069] Furthermore, in the VCSEL element 3 shown in Figure 13, the dielectric film 140 is provided on the back side of the semiconductor substrate 110. In the VCSEL element 3 according to this embodiment, the dielectric mirror layer 2122 is formed on the front side of the mesa structure 200. Therefore, this VCSEL element 3 is configured as a back-side emission type VCSEL element that emits light from the back side of the semiconductor substrate 110. Thus, the dielectric film 140 formed on the back side of the semiconductor substrate 110 functions as an AR (Anti-Reflect) coating. However, if the reflectivity of the dielectric mirror layer 2122 is kept low and an opening is formed in the center of the second electrode 260, this VCSEL element 3 can also be applied to a front-side emission type VCSEL element that emits light from the front side of the semiconductor substrate 110.

[0070] The manufacturing process of the VCSEL element 2 according to this embodiment will be described below with reference to Figures 14 to 19.

[0071] First, as shown in Figure 14, a laminate 200C is formed on a semiconductor substrate 110 by sequentially stacking a first contact layer 120, a first mirror layer 211, a first AlAs layer 221A, a first active layer 231, a first tunnel junction layer 241, a second AlAs layer 222A, a second active layer 232, a second tunnel junction layer 242, a third AlAs layer 223A, a third active layer 233, a semiconductor mirror layer 2121, and a second contact layer 250. Each layer is formed by epitaxial growth. In this embodiment, the number of pairs of semiconductor mirror layers 2121 is less than the number of pairs of first mirror layers 211 or second mirror layers 212. As a result, the thickness of the semiconductor mirror layer 2121 is thinner than the thickness of the first mirror layer 211 or second mirror layer 212.

[0072] Next, as shown in Figure 15, an insulating region 270 is formed by implanting ions from the surface of the second contact layer 250 using the photoresist 300 as a mask. The ion species and dose amount used in this ion implantation process are the same as in the first embodiment.

[0073] Next, as shown in Figure 16, a dielectric mirror layer 2122 is formed on the insulating region 270 and the second contact layer 250. The dielectric mirror layer 2122 is deposited using, for example, chemical vapor deposition (CVD) or sputtering. At this time, the optical thickness of each of the two dielectric layers provided in the dielectric mirror layer 2122 is deposited in a superlattice pattern such that it is 1 / 4λ of the oscillation wavelength λ. Examples of materials for the two dielectric layers include a combination of SiO2 and Si, or a combination of SiO2 and SiN.

[0074] Next, as shown in Figure 17, the dielectric mirror layer 2122 is etched using the photoresist 320 as a mask, for example, by the RIE method. The photoresist 320 is patterned so that the non-etched areas are shielded.

[0075] Next, as shown in Figure 18, the insulating region 270 and the first mirror layer 211 are etched using the RIE method, with the photoresist 330 acting as a mask. This removes a portion of the laminate 200C, forming the mesa structure 200. The photoresist 330 is patterned to cover the dielectric mirror layer 2122 so as to shield the non-etched regions.

[0076] Next, as shown in Figure 19, the first AlAs layer 221A, the second AlAs layer 222A, and the third AlAs layer 223A are oxidized from the sidewall portion of the mesa structure 200, for example, using steam oxidation. As a result, the first oxidized AlAs layer 221, the second oxidized AlAs layer 222, and the third oxidized AlAs layer 223 are completed. Note that in Figure 19, the unoxidized portions of each AlAs layer are omitted from the illustration. In addition, the ion-implanted portions of the second AlAs layer 222A and the third AlAs layer 223A are also oxidized.

[0077] Finally, returning to Figure 13, a second electrode 260 is formed to cover the dielectric mirror layer 2122, and a first electrode 130 is formed on the first contact layer 120. Each electrode is formed in the same manner as in the first embodiment. Furthermore, a dielectric film 140 is deposited on the back surface of the semiconductor substrate 110. The dielectric film 140 is, for example, a SiN film, and can be deposited using chemical vapor deposition (CVD) or sputtering.

[0078] According to the embodiment described above, the insulating region 270 suppresses current diffusion to the sidewalls of the mesa structure 200, thereby improving reliability. In addition, in this embodiment, by dividing the mirror layer placed on top of the mesa structure 200 into a semiconductor mirror layer 2121 and a dielectric mirror layer 2122, ions can reach deeper locations. This makes it possible to improve design flexibility, such as increasing the number of multi-stacks.

[0079] (Fourth Embodiment) Figure 20 is a cross-sectional view showing the structure of the main part of the VCSEL element according to the fourth embodiment. In the following description, the same reference numerals are used for components similar to those in the VCSEL element 3 according to the third embodiment, and redundant explanations are omitted. In the VCSEL element 3 according to the third embodiment, for each mesa structure 200, a first electrode 130 is connected to a first contact layer 120, and a second electrode 260 is connected to a second contact layer 250. In other words, one second electrode 260 is provided for each first electrode 130.

[0080] In contrast, in the VCSEL element 4 shown in Figure 20, the second electrode 260 is connected to the second contact layer 250 for each mesa structure 200, while the first electrode 130 is connected to multiple mesa structures 200 in common via the first contact layer 120. In other words, the first electrode 130 is shared by multiple second electrodes 260. This simplifies the wiring pattern of the first electrode 130, thereby improving mass production efficiency.

[0081] According to the embodiment described above, similar to the third embodiment, the insulating region 270 suppresses current diffusion to the sidewall portion of the mesa structure 200, thereby improving reliability. In addition, since ions can reach deeper locations, it is possible to improve design flexibility, such as increasing the number of multi-stacks.

[0082] (Fifth embodiment) Figure 21 is a cross-sectional view showing the structure of the main part of the VCSEL element according to the fifth embodiment. In the following description, the same reference numerals are used for components similar to those of the VCSEL element 4 according to the fourth embodiment, and redundant explanations are omitted.

[0083] The VCSEL element 5 shown in Figure 21 differs from the VCSEL element 4 according to the third embodiment in that the first mirror layer 211 is divided into an upper mirror layer 2111 and a lower mirror layer 2112. A first contact layer 120 is placed between the upper mirror layer 2111 and the lower mirror layer 2112. That is, the upper mirror layer 2111 and the lower mirror layer 2112 face each other in the z direction with the first contact layer 120 in between. As a result, the number of pairs of first mirror layers 211 in the mesa structure 200, which is a high-resistance region, is reduced, and the series resistance of the mesa structure 200 is reduced.

[0084] According to the embodiment described above, similar to the fourth embodiment, the insulating region 270 suppresses current diffusion to the sidewall portion of the mesa structure 200, thereby improving reliability. In addition, since ions can reach deeper locations, it is possible to improve design flexibility, such as increasing the number of multi-stacks.

[0085] (Sixth Embodiment) Figure 22 is a cross-sectional view showing the structure of the main part of the VCSEL element according to the sixth embodiment. In the following description, a dielectric film 140 is formed on the same components as in the VCSEL element 1 according to the first embodiment.

[0086] In the VCSEL element 6 shown in Figure 22, the insulating region 270 is formed so as not to overlap with the second electrode 260 in the in-plane direction (x and y directions). Specifically, the upper inner edge of the insulating region 270 is in contact with the lower outer edge of the second electrode 260, forming the boundary between them (see the area enclosed by the dotted circle in Figure 22). Furthermore, no opening is formed in the central region of the second electrode 260. In addition, a dielectric film 140 is deposited on the back surface of the semiconductor substrate 110. Since the dielectric film 140 functions as an AR coating, this VCSEL element 6 is a back-side injection type VCSEL element. However, if an opening is formed in the central part of the second electrode 260 by wet etching with aqua regia or the like, this VCSEL element 6 can also be applied to a front-side injection type VCSEL.

[0087] The manufacturing process of the VCSEL element 6 according to this embodiment will be described below with reference to Figures 23 to 27.

[0088] First, as shown in Figure 23, a laminate 200A is formed on a semiconductor substrate 110 by sequentially stacking a first contact layer 120, a first mirror layer 211, a first AlAs layer 221A, a first active layer 231, a first tunnel junction layer 241, a second AlAs layer 222A, a second active layer 232, a second mirror layer 212, and a second contact layer 250. This laminate 200A is formed in the same manner as in the first embodiment.

[0089] Next, as shown in Figure 24, a second electrode 260 is formed on the second contact layer 250. The method for forming the second electrode 260 is the same as in the first embodiment.

[0090] Next, as shown in Figure 25, an insulating region 270 is formed by implanting ions from the top surface of the laminate 200A, using the second electrode instead of photoresist as a mask. The ion species and dose are the same as in the first embodiment.

[0091] Next, as shown in Figure 26, the insulating region 270 and the first mirror layer 211 are etched using the RIE method, with the photoresist 340 acting as a mask. This removes a portion of the laminate 200A, forming the mesa structure 200. The photoresist 340 is patterned to cover the second electrode 260 so as to shield the non-etched region.

[0092] Next, as shown in Figure 27, the first AlAs layer 221A and the second AlAs layer 222A are oxidized from the sidewalls of the mesa structure 200, for example, using steam oxidation. As a result, the first oxidized AlAs layer 221 and the second oxidized AlAs layer 222 are completed. Note that in Figure 27, the unoxidized portions of each AlAs layer are omitted from the illustration. In addition, the ion-implanted portion of the second AlAs layer 222A is also oxidized.

[0093] Finally, returning to Figure 22, the first electrode 130 is formed on the first contact layer 120, and a dielectric film 140 is deposited on the back surface of the semiconductor substrate 110. The first electrode 130 is formed in the same manner as in the first embodiment. The dielectric film 140 is deposited in the same manner as in the third embodiment.

[0094] According to the embodiment described above, the insulating region 270 suppresses current diffusion to the sidewall portion of the mesa structure 200, thereby improving reliability. In addition, by using the second electrode 260 as a mask during ion implantation, it is possible to prevent the ion implantation region and the second electrode 260 from overlapping in the in-plane direction.

[0095] When a VCSEL element is driven with a structure in which the insulating region 270 and the second electrode 260 overlap each other, the crystallinity of the insulating region 270 near the second electrode 260 may recover due to current stress, resulting in a weakening of the insulating properties. In this case, voltage fluctuations occur during the operation of the VCSEL element, which can lead to a deterioration in the stability of the laser characteristics. As a fundamental and simple means of preventing this, it is conceivable to perform ion implantation using the second electrode 260 as a mask, as described above.

[0096] As described above, ion implantation allows the second electrode 260 and the insulating region 270 to be brought into extremely close proximity in plane. Therefore, during device design, a sufficient contact area can be secured between the second electrode 260 and the second contact layer 250 that has not been ion-implanted. As a result, the resistance increase caused by the contact resistance between the second electrode 260 and the second contact layer 250 can be reduced.

[0097] Furthermore, this technology can take the following configuration.

[0098] (1) Semiconductor substrate and A first contact layer of a first conductivity type is provided on the semiconductor substrate, A mesa structure provided on the first contact layer, The system comprises a first electrode electrically connected to the mesa structure via the first contact layer, The aforementioned mesa structure is The first mirror layer, A first mirror layer is provided with at least one AlAs oxide layer, At least one active layer provided above or below the AlAs oxide layer, A second mirror layer provided on the active layer, A second contact layer of second conductivity type provided on the second mirror layer, A second electrode provided on the second contact layer, The mesa structure includes an insulating region provided on the side wall, A vertical-cavity surface-emitting laser element in which the length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more.

[0099] (2) The vertical cavity type surface-emitting laser element according to (1), further comprising at least one tunnel junction layer provided between the active layer and the first mirror layer, or between the active layer and the second mirror layer.

[0100] (3) The upper end of the insulating region is located on the upper surface of the mesa structure, The vertical resonator type surface-emitting laser element according to (1) or (2), wherein the lower end of the insulating region is located on the upper surface of the AlAs oxide layer, which is the lowest layer in the mesa structure among the at least one AlAs oxide layer.

[0101] (4) The upper end of the insulating region is located between the active layer and the second mirror layer, A vertical-cavity surface-emitting laser element according to any one of (1) to (3), wherein the lower end of the insulating region is located on the upper surface of the AlAs oxide layer, which is the lowest layer in the mesa structure among the at least one AlAs oxide layer.

[0102] (5) The second mirror layer is divided into a semiconductor mirror layer that is thinner than the first mirror layer and a dielectric mirror layer provided on the semiconductor mirror layer. A vertical resonator type surface-emitting laser element according to any one of (1) to (4), wherein the upper end of the insulating region is located between the semiconductor mirror layer and the dielectric mirror layer.

[0103] (6) The first electrode is connected in common to a plurality of mesa structures via the first contact layer, A vertical-cavity surface-emitting laser element according to any one of (1) to (4), wherein the second contact layer and the second electrode are provided for each of the plurality of mesa structures.

[0104] (7) The vertical-cavity surface-emitting laser element according to (6), wherein the first mirror layer is divided into an upper mirror layer and a lower mirror layer that face each other with the first contact layer in between.

[0105] (8) The ion species included in the insulating region is H + He + Li + Be + B + , C + , N + , O + Ne + Ar + A vertical-cavity surface-emitting laser element as described in any of (1) to (7), which is one of the following:

[0106] (9) A vertical resonator type surface-emitting laser element according to any one of (1) to (8), wherein the insulating region does not overlap with the second electrode in the in-plane direction.

[0107] (10) A step of forming a laminate on a semiconductor substrate in which a first contact layer of a first conductivity type, a first mirror layer, at least one AlAs layer, and at least one active layer are stacked, A step of forming an insulating region in the laminate by implanting ions from the upper surface of the laminate using a first photoresist patterned to mask non-ion implanted regions, A step of forming a mesa structure in which the insulating region is formed on the side wall by etching a part of the laminate using a second photoresist patterned to mask the non-etched region, The process includes oxidizing at least one AlAs layer to form an AlAs oxide layer, A method for manufacturing a vertical cavity type surface-emitting laser element, wherein the length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more. [Explanation of Symbols]

[0108] 1-6: VCSEL element 110: Semiconductor substrate 120: First Contact Layer 130: 1st electrode 200: Mesa Structures 200A, 200B, 200C: Laminate 211: First Mirror Layer 212: Second Mirror Layer 221: Primary AlAs oxide layer 221A: 1st AlAs layer 222: Second AlAs oxide layer 222A: 2nd AlAs layer 223: Third AlAs oxide layer 223A: 3rd AlAs layer 231: 1st active layer 232: 2nd active layer 233: 3rd active layer 241: First Tunnel Junction Layer 242: Second Tunnel Junction Layer 250: Second Contact Layer 260: 2nd electrode 2111: Upper mirror layer 2112: Lower mirror layer 2121: Semiconductor mirror layer 2122: Dielectric mirror layer

Claims

1. Semiconductor substrate and A first contact layer of a first conductivity type is provided on the semiconductor substrate, A mesa structure provided on the first contact layer, The system comprises a first electrode electrically connected to the mesa structure via the first contact layer, The aforementioned mesa structure is The first mirror layer and At least one AlAs oxide layer provided on the first mirror layer, At least one active layer provided above or below the AlAs oxide layer, A second mirror layer provided on the active layer, A second contact layer of second conductivity type provided on the second mirror layer, The second electrode provided on the second contact layer, The mesa structure includes an insulating region provided on the side wall, A vertical-cavity surface-emitting laser element in which the length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more.

2. The vertical-cavity surface-emitting laser element according to claim 1, further comprising at least one tunnel junction layer provided between the active layer and the first mirror layer, or between the active layer and the second mirror layer.

3. The upper end of the insulating region is located on the upper surface of the mesa structure, The vertical resonator type surface-emitting laser element according to claim 1, wherein the lower end of the insulating region is located on the upper surface of the AlAs oxide layer, which is the lowest layer in the mesa structure among the at least one AlAs oxide layer.

4. The upper end of the insulating region is located between the active layer and the second mirror layer. The vertical resonator type surface-emitting laser element according to claim 1, wherein the lower end of the insulating region is located on the upper surface of the AlAs oxide layer, which is the lowest layer in the mesa structure among the at least one AlAs oxide layer.

5. The second mirror layer is divided into a semiconductor mirror layer that is thinner than the first mirror layer and a dielectric mirror layer provided on the semiconductor mirror layer. The vertical resonator type surface-emitting laser element according to claim 3, wherein the upper end of the insulating region is located between the semiconductor mirror layer and the dielectric mirror layer.

6. The first electrode is commonly connected to a plurality of mesa structures via the first contact layer. The vertical-cavity surface-emitting laser element according to claim 3, wherein the second contact layer and the second electrode are provided for each of the plurality of mesa structures.

7. The vertical resonator type surface-emitting laser element according to claim 6, wherein the first mirror layer is divided into an upper mirror layer and a lower mirror layer that face each other with the first contact layer in between.

8. The ion species contained in the insulating region is H ＋ , He ＋ , Li ＋ , Be ＋ , B ＋ , C ＋ , N ＋ , O ＋ , Ne ＋ , Ar ＋ The vertical cavity surface emitting laser device according to claim 3, wherein the ion species is any one of the above.

9. The vertical resonator type surface-emitting laser element according to claim 3, wherein the insulating region does not overlap with the second electrode in the in-plane direction.

10. A step of forming a laminate on a semiconductor substrate in which a first contact layer of a first conductivity type, a first mirror layer, at least one AlAs layer, and at least one active layer are stacked. A step of forming an insulating region in the laminate by implanting ions from the upper surface of the laminate using a first photoresist patterned to mask non-ion implanted regions, A step of forming a mesa structure in which the insulating region is formed on the side wall by etching a part of the laminate using a second photoresist patterned to mask the non-etched region, The process includes a step of oxidizing the at least one AlAs layer to form an AlAs oxide layer, A method for manufacturing a vertical cavity type surface-emitting laser element, wherein the length of the AlAs oxide layer from the side wall portion is 0.5 μm or more and 5.0 μm or less, and the distance from the leading edge of the AlAs oxide layer to the insulating region is 0.5 μm or more.

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