Semiconductor equipment and electronic control systems

Abstract

The present invention provides a semiconductor device that can turn on an output transistor even during a period when a reverse current is generated from the load toward the output transistor. [Solution] The discharge transistor 12 is formed on a semiconductor substrate and, when controlled to be ON, short-circuits the gate of the power transistor 7 with the reference node N9, thereby controlling the power transistor 7 to be OFF. The reverse current detection circuit 63 detects the generation of a reverse current Iinv from the power output terminal 2 toward the power supply terminal 1 and asserts a reverse current detection signal INVD during the period in which the reverse current Iinv is generated. The switch control circuit 75 controls switch SW1 to be ON and switch SW2 to be OFF during the negate period of the reverse current detection signal INVD, and controls switch SW1 to be OFF and switch SW2 to be ON during the assertion period of the reverse current detection signal INVD.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and electronic control systems, and more particularly to a semiconductor device that supplies power to an externally connected load, and an electronic control system equipped therewith. [Background technology]

[0002] Patent Document 1 describes a semiconductor device that can prevent malfunction of a protection transistor when a reverse current occurs. This semiconductor device comprises a power transistor and a protection circuit that short-circuits the gate-source of the power transistor using a protection transistor when a load short-circuit occurs. The protection circuit detects a load short-circuit by a combination of determining the output voltage of the power transistor and determining the time using a timer. The protection transistor has a parasitic bipolar transistor that turns on when a reverse current flows through the power transistor. Here, the protection circuit is configured to prevent false detection of a load short-circuit when the reverse current is eliminated by controlling the timer based on the output voltage determination result. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-11117 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] For example, as shown in Patent Document 1, a semiconductor device is known that includes a power transistor and a protection transistor that short-circuits the gate-source of the power transistor when controlled to be in the ON state. In a power transistor that supplies power to a load, a reverse current is generated from the load to the power supply terminal when the output voltage is higher than the power supply voltage. This reverse current occurs, for example, when driving a capacitive load or an inductive load. Another example is the ripple current generated by rectification when the load is a generator, which can also be a reverse current. When the power transistor is in the OFF state, such a reverse current flows through the body diode of the power transistor.

[0005] Here, a parasitic bipolar transistor may be formed in the protection transistor, which turns on when a reverse current occurs. When the parasitic bipolar transistor is in the ON state, it connects the gate of the power transistor to the power supply voltage. On the other hand, in order to turn on the power transistor, which is in the OFF state, it is necessary to apply a boost voltage higher than the power supply voltage to the gate. However, when the parasitic bipolar transistor is in the ON state, it may be difficult to apply a boost voltage to the gate of the power transistor due to the aforementioned connection to the power supply voltage. In other words, there was a risk that the power transistor could not be turned on during the period when a reverse current was present.

[0006] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes an output transistor, a first switch, a second switch, a first control transistor, a reverse current detection circuit, and a switch control circuit. The output transistor is formed on a semiconductor substrate and connected between a power supply terminal and a power output terminal, supplying power to a load connected to the power output terminal when controlled to the ON state. The first switch connects the power output terminal to a reference node. The second switch connects the power supply terminal to a reference node. The first control transistor is formed on a semiconductor substrate and, when controlled to the ON state, controls the output transistor to the OFF state by short-circuiting the gate of the output transistor to the reference node. The reverse current detection circuit detects the generation of a reverse current from the power output terminal to the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is generated. The switch control circuit controls the first switch to the ON state and the second switch to the OFF state during the negate period of the reverse current detection signal, and controls the first switch to the OFF state and the second switch to the ON state during the assert period of the reverse current detection signal. [Effects of the Invention]

[0008] According to the above embodiment, the output transistor can be turned on even during the period when a reverse current is generated from the load toward the output transistor. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a circuit diagram showing an example of the configuration of the main parts of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic diagram showing an example of the layout configuration of the semiconductor device in Figure 1. [Figure 3] Figure 3 is a cross-sectional view showing an example of the configuration between A and A' in Figure 2. [Figure 4A] Figure 4A is a timing chart showing an example of operation in the semiconductor device shown in Figure 1 when no reverse current is flowing. [Figure 4B] Figure 4B is a timing chart showing an example of operation when a reverse current is flowing in the semiconductor device shown in Figure 1. [Figure 5] FIG. 5 is a circuit block diagram showing a configuration example of an electronic control system (ECU) to which the semiconductor device shown in FIG. 1 is applied. [Figure 6] FIG. 6 is a schematic diagram showing a configuration example of a vehicle equipped with the electronic control system (ECU) shown in FIG. 5. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to a second embodiment. [Figure 8] FIG. 8 is a diagram showing an example of an operation mode provided in the on-off control circuit in FIG. 7. [Figure 9] FIG. 9 is a timing chart showing a detailed operation example in each operation mode of the on-off control circuit in FIGS. 7 and 8. [Figure 10] FIG. 10 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to a fourth embodiment. [Figure 12A] FIG. 12A is a circuit diagram showing a detailed configuration example including parasitic elements in the voltage switching switch shown in FIG. 1l. [Figure 12B] FIG. 12B is a comparative example with respect to FIG. 12A, and is a circuit diagram showing a detailed configuration example including parasitic elements in the voltage switching switch shown in FIG. 10. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device as a comparative example. [Figure 14] FIG. 14 is a timing chart showing an operation example when a reverse current is flowing in the semiconductor device shown in FIG. 13.

BEST MODE FOR CARRYING OUT THE INVENTION

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number.

[0011] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., it shall include those that substantially approximate or resemble such shapes, etc., unless specifically stated or considered to be not in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0012] Furthermore, in the following embodiments, p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and n-channel MOSFETs will be referred to as pMOS transistors and nMOS transistors, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all figures used to explain the embodiments, the same reference numerals will be used for identical components, and repeated explanations will be omitted.

[0013] (First Embodiment) <Circuit configuration of semiconductor device> Figure 1 is a circuit diagram showing an example of the main components of a semiconductor device 101 according to the first embodiment. The semiconductor device 101 shown in Figure 1 includes a power terminal 1, a power output terminal 2, a control input terminal 4, a power transistor (PT) 7, a gate resistor element 11, and various control circuits for controlling the power transistor (PT) 7.

[0014] The various control circuits include an on / off control circuit 60, a charge pump (CP) circuit 61, a discharge transistor (control transistor) 12, a charging transistor 14, a protection transistor (control transistor) 22, and a protection circuit 62. In addition, the various control circuits include a voltage switching switch 66A, a reverse current detection circuit 63, and a switch control circuit 75, although these will be described in detail later.

[0015] Power terminal 1 receives a battery voltage Vbat, such as 12V, from an external battery 6. This supplies the power supply voltage VCC to power terminal 1, i.e., power node N7. A load 8 is connected to power output terminal 2, i.e., power output node N8. Load 8 has a parallel-connected load 8a and a resistive load 8b. One end of load 8 is supplied with the ground power supply voltage PGND. Power output terminal 2 also generates an output voltage VOUT and an output current IOUT.

[0016] The power transistor (PT) 7 is also an output transistor connected between the power supply terminal 1 and the power output terminal 2. When controlled to the ON state, the power transistor (PT) 7 supplies power to the load 8 connected to the power output terminal 2. In this example, the power transistor (PT) 7 is an nMOS transistor. The source and drain of the power transistor (PT) 7 are connected to the power output terminal 2 and the power supply terminal 1, respectively. The power transistor (PT) also has a body diode 7B with a commonly connected source and back gate as the anode and the drain as the cathode.

[0017] The control input terminal 4 receives an external on / off control signal IN. The on / off control signal IN is a signal for externally instructing the on / off status of the power transistor (PT) 7. The on / off control circuit 60 exclusively controls the on / off status of the charging transistor 14 and the discharging transistor 12 in response to the on / off control signal IN. In this process, the on / off control circuit 60 controls the charging transistor 14 using the charging control signal CG and controls the discharging transistor 12 using the discharging control signal DCG.

[0018] Furthermore, the on / off control circuit 60 controls the active and inactive states of the charge pump (CP) circuit 61 using a boost control signal ENcp. When the charge pump (CP) circuit 61 is active, it generates a boost voltage Vcp that is higher than the power supply voltage VCC. The charging transistor 14 is, for example, a pMOS transistor. The discharging transistor 12 is, for example, an nMOS transistor.

[0019] For example, when the ON / OFF control signal IN instructs the circuit to turn ON, the ON / OFF control circuit 60 uses the charging control signal CG to control the charging transistor 14 to the ON state. The ON state of the charging transistor 14 applies the boosted voltage Vcp from the charge pump (CP) circuit 61 to the gate node N4 of the power transistor (PT) 7. This controls the power transistor (PT) 7 to the ON state. More specifically, the charging transistor 14 applies the boosted voltage Vcp to node N3, which is the drain node, and then applies it to the gate node N4 of the power transistor (PT) 7 via the gate resistor element 11.

[0020] On the other hand, if the ON / OFF control signal IN instructs the circuit to be OFF, the ON / OFF control circuit 60 uses the discharge control signal DCG to control the discharge transistor (control transistor) 12 to the ON state. The ON state of the discharge transistor 12 short-circuits the gate node N4 of the power transistor (PT) 7 and the power output node N8, which is the source of the power transistor (PT) 7. As a result, the power transistor (PT) 7 is controlled to the OFF state. More specifically, the power output node N8 is connected to the reference node N9 via the voltage switching switch 66A, which will be described later. The discharge transistor 12 short-circuits the node N3, which is connected to the gate node N4 via the gate resistor element 11, and the reference node N9.

[0021] The protection transistor (control transistor) 22 is, for example, an nMOS transistor. Similar to the discharge transistor 12, when controlled to the ON state, the protection transistor 22 short-circuits the gate node N4 and the power output node N8 of the power transistor (PT) 7. More specifically, the protection transistor 22 short-circuits node N3 and the reference node N9. The protection circuit 62 detects a predetermined abnormality and, upon detecting the abnormality, controls the protection transistor 22 to the ON state via, for example, a level shift circuit (not shown).

[0022] In this example, protection circuit 62 is an overcurrent protection circuit that detects that an overcurrent (OC) has flowed through the power transistor (PT) 7 due to a load short circuit and controls the protection transistor 22 to the ON state. However, protection circuit 62 is not limited to this and may be any other circuit, including, for example, an overtemperature protection circuit that detects that the power transistor (PT) 7 has become overheated and controls the protection transistor 22 to the ON state. In response to such a predetermined abnormality detection, the protection transistor 22 turns off the power transistor (PT) 7 by short-circuiting the gate of the power transistor (PT) 7 with the reference node N9.

[0023] <Device configuration of semiconductor device> Figure 2 is a schematic diagram showing an example of the layout configuration of the semiconductor device 101 in Figure 1. The semiconductor device 101 shown in Figure 2 comprises a power transistor (PT) 7 formation region ARp and various control circuit formation regions ARc. The various control circuits are circuits for controlling the power transistor (PT) 7, as described in Figure 1. In this example, a guard ring (GR) 40 for isolation is provided between the formation regions ARp and ARc. However, the semiconductor device 101 does not necessarily need to have a guard ring (GR) 40.

[0024] The power transistor (PT) 7, or output transistor, is more specifically composed of multiple unit output transistors PTu connected in parallel to each other. In this example, a temperature sensing diode formation region ARd is provided near the center of the power transistor (PT) 7 formation region ARp. The temperature sensing diode is used when the protection circuit 62 is an over-temperature protection circuit.

[0025] Figure 3 is a cross-sectional view showing an example of the configuration between A and A' in Figure 2. In Figure 3, an N-type epitaxial layer 502 is formed on an N-type semiconductor substrate 501. Various elements are formed using a diffusion layer or oxide film placed on the surface of the epitaxial layer 502. Here, the various elements shown are a unit output transistor PTu constituting a power transistor (PT) 7, low-voltage pMOS transistors MP-L and nMOS transistors MN-L, high-voltage pMOS transistors MP-H and nMOS transistors MN-H, and a guard ring GR. The various elements are arranged adjacent to each other and separated by a thick oxide film 503 (LOCOS).

[0026] The pMOS transistors MP-L, MP-H and nMOS transistors MN-L, MN-H are included in the various control circuits described above. The high-voltage pMOS transistor MP-H and nMOS transistor MN-H have a withstand voltage of approximately 40V, for example. On the other hand, the low-voltage pMOS transistor MP-L and nMOS transistor MN-L have a withstand voltage of approximately 6V, for example.

[0027] The unit output transistor PTu is composed of a vertical nMOS transistor with the back surface of the semiconductor substrate 501 as the drain. Specifically, in the unit output transistor PTu, a Pbase diffusion layer 505, which serves as the back gate (BG), is formed on the surface of the epitaxial layer 502. Within the Pbase diffusion layer 505, N + A source (S) diffusion layer 510 and a P for supplying power to the back gate (BG) +A power supply diffusion layer 511 of a certain type is formed. The epitaxial layer 502 and the semiconductor substrate 501 serve as the drain (D). A power supply voltage VCC is supplied to the back surface of the drain (D), that is, the semiconductor substrate 501.

[0028] Also, a trench 509 extending in the depth direction is formed in the epitaxial layer 502. A thin gate oxide film 506 and polysilicon 508 serving as the gate (G) are embedded in the trench 509. The source (S) diffusion layer 510 is formed at a position contacting the side wall of the trench 509. When a predetermined voltage is applied between the gate (G) and the source (S), a channel is formed at a position on the side wall of the trench 509 in the Pbase diffusion layer 505. Thereby, a drive current flows from the back surface of the semiconductor substrate 501 toward the source (S) diffusion layer 510.

[0029] In the pMOS transistor MP-L with a low-voltage specification, a deep diffusion layer 504 of the P - type, that is, a p-well, is formed on the surface of the epitaxial layer 502. In the P - type diffusion layer 504, a shallow diffusion layer 513 of the N - type, that is, an n-well, is formed. In the N - type diffusion layer 513, a source (S) diffusion layer 511 and a drain (D) diffusion layer 511 of the P + type, and a power supply diffusion layer 510 of the N + type for the back gate are formed. On the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, polysilicon 508 serving as the gate (G) is formed via a thin gate oxide film 506.

[0030] In the nMOS transistor MN-L with a low-voltage specification, a deep diffusion layer 504 of the P - type, that is, a p-well, is formed from the surface of the epitaxial layer - 502. In the P + type diffusion layer 504, a source (S) diffusion layer 510 and a drain (D) diffusion layer 510 of the N +A power supply diffusion layer 511 of the type is formed. On the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, a polysilicon 508 that will serve as the gate (G) is formed via a thin gate oxide film 506.

[0031] In the high-voltage pMOS transistor MP-H, the surface of the epitaxial layer 502 is P + The source (S) diffusion layer 511 of type and N for the back gate + A power supply diffusion layer 510 of the type is formed. On the other hand, on the drain (D) side, from the surface of the epitaxial layer 502, P - A deep diffusion layer 512 of the type is formed. - In the type diffusion layer 512, P + A drain (D) diffusion layer 511 of type 511 is formed.

[0032] Furthermore, polysilicon 508, which forms the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, via a thin gate oxide film 506. However, unlike the low-voltage pMOS transistor MP-L, the gate oxide film 506 and polysilicon 508 near the drain (D) are superimposed on a thick oxide film 503 to achieve high breakdown voltage.

[0033] In the high-voltage nMOS transistor MN-H, P is present on the surface of the epitaxial layer 502. - A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the diffuse layer 504 of type N + The source (S) diffusion layer 510 of the type and P for the back gate (BG) + A power supply diffusion layer 511 of the type is formed. On the other hand, on the drain (D) side, N is released from the surface of the epitaxial layer 502. - A shallow diffusion layer 513 of the type is formed. - In the diffuse layer 513 of type N + A drain (D) diffusion layer 510 of type 510 is formed.

[0034] Furthermore, polysilicon 508, which will serve as the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, via a thin gate oxide film 506. However, unlike the low-voltage nMOS transistor MN-L, the gate oxide film 506 and polysilicon 508 near the drain (D) are superimposed on a thick oxide film 503 to achieve high breakdown voltage.

[0035] In Guard Ring GR, from the surface of the epitaxial layer 502, P - A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the type diffusion layer 504, P + A power supply diffusion layer 511 of type P is formed. + For example, the ground power supply voltage is applied to the power supply diffusion layer 511 of this type.

[0036] In Figure 1, when power is supplied to the load 8, for example, a drop in the power supply voltage VCC may cause the output voltage VOUT to become higher than the power supply voltage VCC. In this case, a reverse current Iinv flows from the power output terminal 2 to the power supply terminal 1. When the power transistor (PT) 7 is in the off state, this reverse current Iinv flows through the body diode 7B formed between the source (S) and back gate (BG) and drain (D) of the power transistor (PT) 7. Figure 3 illustrates this reverse current Iinv in a unit output transistor PTu.

[0037] Furthermore, the discharge transistor 12 and protection transistor 22 shown in Figure 1 are composed of high-voltage nMOS transistors MN-H shown in Figure 3. An NPN-type parasitic bipolar transistor 51a may be formed in the discharge transistor 12. Similarly, an NPN-type parasitic bipolar transistor 51b may be formed in the protection transistor 22. The parasitic bipolar transistors 51a and 51b are formed as vertical parasitic bipolar transistors 51, as shown in Figure 3.

[0038] As shown in Figures 3 and 1, the parasitic bipolar transistor 51 operates with the back gate (BG) of the nMOS transistor MN-H and the source (S) connected to the back gate (BG) as its base. The parasitic bipolar transistor 51 also operates with the drain (D) of the nMOS transistor MN-H and one side of the back surface of the semiconductor substrate 501 as the emitter and the other as the collector. In this example, the back surface of the semiconductor substrate 501 is used as the emitter, assuming that a high voltage is applied to the drain (D) of the nMOS transistor MN-H.

[0039] With the formation of these vertical parasitic bipolar transistors 51, as shown in Figure 1, the bases of the parasitic bipolar transistors 51a and 51b are connected to the power output terminal 2 via the voltage selector switch 66A. In addition, the emitters of the parasitic bipolar transistors 51a and 51b are connected to the power supply terminal 1, which is on the back surface of the semiconductor substrate 501.

[0040] Here, when a reverse current Iinv flows through the body diode 7B of the power transistor (PT), the forward voltage of the body diode 7B clamps the output voltage VOUT generated at the power output terminal 2 to a state approximately 0.6V higher than the power supply voltage VCC supplied to the power supply terminal 1. As a result, the parasitic bipolar transistors 51a and 51b are subjected to a forward bias of approximately 0.6V between their base and emitter, allowing them to turn on. The on-state parasitic bipolar transistors 51a and 51b connect the gate node N4 of the power transistor (PT) 7 to the power supply terminal 1.

[0041] On the other hand, in order to turn on the power transistor (PT) 7, it is necessary to apply a boost voltage Vcp higher than the power supply voltage VCC to the gate of the power transistor (PT) 7. However, when the parasitic bipolar transistors 51a and 51b are in the ON state, it may be difficult to apply the boost voltage Vcp to the gate of the power transistor (PT) 7 due to the connection to the power supply terminal 1 mentioned above. In other words, during the period when a reverse current Iinv is generated, there was a risk that the power transistor (PT) 7 could not be turned on. Therefore, in Figure 1, a voltage switching switch 66A, a reverse current detection circuit 63, and a switch control circuit 75 are provided.

[0042] <Details related to voltage selector switches> In Figure 1, the voltage selector switch 66A includes two switches, SW1 and SW2. When the switch (first switch) SW1 is controlled to the ON state, it connects the power output terminal 2, i.e., the power output node N8, to the reference node N9. When the switch (second switch) SW2 is controlled to the ON state, it connects the power supply terminal 1, i.e., the power supply node N7, to the reference node N9.

[0043] The reverse current detection circuit 63 detects the occurrence of a reverse current Iinv from the power output terminal 2 toward the power supply terminal 1. The reverse current detection circuit 63 then asserts a reverse current detection signal INVD during the period in which the reverse current Iinv is occurring. Specifically, the reverse current detection circuit 63 includes, for example, pMOS transistors 23, 24 and nMOS transistors 25, 26 that constitute a source-input type differential amplifier circuit.

[0044] The gate of pMOS transistor 24 is connected to the drain and also to the gate of pMOS transistor 23. pMOS transistors 23 and 24 receive output voltage VOUT and power supply voltage VCC as sources, respectively. The two nMOS transistors 25 and 26 are supplied with an internal power supply voltage VSS as a source. The internal power supply voltage VSS is lower than the power supply voltage VCC, for example, "VCC-6V". The two nMOS transistors 25 and 26 each supply a common bias current from their drains to the two pMOS transistors 23 and 24, based on the bias voltage Vbs.

[0045] With this configuration, the reverse current detection circuit 63 functions as a comparator that compares the magnitudes of the output voltage VOUT and the power supply voltage VCC, and thereby detects the presence or absence of a reverse current Iinv. When a reverse current Iinv is flowing, "VOUT > VCC", so the gate-source voltage of the pMOS transistor 23 becomes larger than that of the pMOS transistor 24. As a result, the reverse current detection circuit 63 outputs an assert level, in this case a "H" level reverse current detection signal INVD, to the output node N10. On the other hand, when no reverse current Iinv is flowing, the reverse current detection circuit 63 outputs a negate level, in this case a "L" level reverse current detection signal INVD.

[0046] The switch control circuit 75 controls switch SW1 to the ON state and switch SW2 to the OFF state during the negate period of the reverse current detection signal INVD. Furthermore, the switch control circuit 75 controls switch SW1 to the OFF state and switch SW2 to the ON state during the assertion period of the reverse current detection signal. In detail, the switch control circuit 75 comprises an inverter circuit 64 and a level shift circuit 65. In this example, it is assumed that switches SW1 and SW2 are controlled to the ON state by signals with opposite polarities.

[0047] The inverter circuit 64 is supplied with, for example, the power supply voltage VCC and the internal power supply voltage VSS. The inverter circuit 64 controls the on / off state of switch SW2 based on the reverse current detection signal INVD. More specifically, the inverter circuit 64 controls switch SW2 with a voltage switching signal Ssw2, which is the inverse signal of the reverse current detection signal INVD. Switch SW2 is controlled to be ON when the voltage switching signal Ssw2 is at the "L" level, and consequently when the reverse current detection signal INVD is at the assert level. The "L" and "H" levels of the voltage switching signal Ssw2 are the "VSS" level and the "VCC" level, respectively.

[0048] The level shift (LS) circuit 65 is supplied with, for example, the boosted voltage Vcp generated at the output node N15 of the charge pump (CP) circuit 61 and the reference output voltage VOUTR generated at the reference node N9. The level shift circuit 65 controls the on / off state of switch SW1 based on the reverse current detection signal INVD.

[0049] In detail, the level shift circuit 65 generates a voltage switching signal Ssw1 for switch SW1 by level shifting the voltage switching signal Ssw2 for switch SW2. The level shift circuit 65 then controls switch SW1 with this voltage switching signal Ssw1. Unlike switch SW2, switch SW1 is controlled to be ON when the voltage switching signal Ssw1 is at the "H" level, and consequently when the reverse current detection signal INVD is at the negate level. The "L" level and "H" level of the voltage switching signal Ssw1 are the "VOUTR" level and the "Vcp" level, respectively.

[0050] With the above configuration, when the reverse current detection signal INVD is at the assert level, i.e., when a reverse current Iinv is present, the power supply voltage VCC can be applied to the bases of the parasitic bipolar transistors 51a and 51b. As a result, the base-emitter voltage of the parasitic bipolar transistors 51a and 51b becomes 0V, and the parasitic bipolar transistors 51a and 51b can be controlled to the off state. Consequently, even during the period when a reverse current Iinv is present, a boost voltage Vcp can be applied to the gate of the power transistor (PT) 7, making it possible to turn on the power transistor (PT) 7.

[0051] More specifically, even when the power transistor (PT) 7 is in the off state and a reverse current Iinv is flowing through the body diode 7B, it is still possible to turn on the power transistor (PT) 7. That is, when the power transistor (PT) 7 is in the on state, the reverse current Iinv flows through the channel of the power transistor (PT) 7. In this case, the output voltage VOUT is clamped to approximately the power supply voltage VCC, resulting in the parasitic bipolar transistors 51a and 51b being in the off state. Therefore, the parasitic bipolar transistors 51a and 51b do not pose any particular problem when the power transistor (PT) 7 is in the on state.

[0052] <Semiconductor device operation> Figure 4A is a timing chart showing an example of operation in the semiconductor device 101 shown in Figure 1 when no reverse current Iinv is flowing. For example, when supplying power to a load 8 as shown in Figure 1, an inrush current flows when charging the load 8a by controlling the power transistor (PT) 7 to the ON state. To suppress the inrush current, as shown in Figure 4A, an on / off control signal IN is usually used to periodically switch the device on and off. As a result, the semiconductor device 101 charges the load 8a in stages.

[0053] When the on / off control signal IN is at the "H" level, the charging transistor 14 is controlled to be in the on state, and the discharging transistor 12 is controlled to be in the off state. As a result, a boosted voltage Vcp higher than the power supply voltage VCC is applied to the gate node N4 of the power transistor (PT) 7. Consequently, the power transistor (PT) 7 is controlled to be in the on state to charge the load 8a.

[0054] On the other hand, when the on / off control signal IN is at the "L" level, the charging transistor 14 is controlled to be in the off state, and the discharging transistor 12 is controlled to be in the on state. As a result, the voltage of the gate node N4 of the power transistor (PT) 7 is pulled down to the voltage of the power output node N8 which is the source node. Consequently, the power transistor (PT) 7 is controlled to be in the off state, and the charging of the load 8a is stopped. By repeating these operations, the load 8a is charged step by step while limiting the maximum value of the inrush current. And in this example, at time t4, the step-by-step charging of the load 8a is completed.

[0055] Note that in this example, the power supply voltage VCC and the output voltage VOUT maintain the relationship of "VOUT < VCC". Accordingly, no reverse current Iinv flows. For this reason, in the reverse current detection circuit 63, through the differential amplification operation corresponding to "VOUT < VCC", the pMOS transistor 23 is controlled to be in the off state. As a result, the reverse current detection signal INVD is maintained at the "L" level, that is, the negative level.

[0056] The voltage switching signal Ssw2 becomes the "H" level, here the off level, in response to the "L" level of the reverse current detection signal INVD. As a result, the switch SW2 maintains the off state. On the other hand, the voltage switching signal Ssw1 becomes the "H" level, here the on level, in response to the "H" level of the voltage switching signal Ssw2. As a result, the switch SW1 maintains the on state. Also, by the switch SW1 maintaining the on state, the reference output voltage VOUTR at the reference node N9 becomes equal to the output voltage VOUT.

[0057] Furthermore, if no reverse current Iinv is flowing, the base-emitter voltage VBE of the two parasitic bipolar transistors 51a and 51b will be at least reverse-biased. As a result, the two parasitic currents InpnA and InpnB flowing through the two parasitic bipolar transistors 51a and 51b, respectively, are 0A. For the sake of simplicity, the reverse-biased base-emitter voltage VBE is shown as 0V in this diagram.

[0058] The above describes the operation when the output current IOUT flowing through the power transistor (PT) 7 is less than the threshold current. In this case, the protection circuit 62, more specifically the overcurrent protection circuit, outputs a "L" level signal to keep the protection transistor 22 in the off state. On the other hand, when the output current IOUT becomes greater than the threshold current due to a load short circuit, the protection circuit 62 outputs a "H" level signal to turn on the protection transistor 22. As a result, the power transistor (PT) 7 is protected by turning off, and charging to the load 8a is stopped.

[0059] Figure 4B is a timing chart showing an example of operation in the semiconductor device 101 shown in Figure 1 when a reverse current Iinv is flowing. In Figure 4B, unlike in Figure 4A, at time t1, a decrease in the power supply voltage VCC occurs during the off period of the power transistor (PT) 7, resulting in the condition "VOUT>VCC". When the power transistor (PT) 7 is in the off state, no channel is formed, and therefore a reverse current Iinv flows through the body diode 7B. More specifically, the reverse current Iinv begins to flow from time t2, for example, when "VOUT-VCC" exceeds the forward voltage of the body diode 7B, for example, about 0.6V.

[0060] Here, the reverse current detection circuit 63 detects the occurrence of the reverse current Iinv and asserts the reverse current detection signal INVD to the "H" level. That is, the reverse current detection circuit 63 controls the pMOS transistor 23 to the ON state through differential amplification operation in response to "VOUT>VCC". As a result, the reverse current detection signal INVD becomes the "H" level. In reality, the reverse current detection signal INVD can become the "H" level from time t1 when "VOUT>VCC" occurs.

[0061] The voltage switching signal Ssw2 becomes "L" level, in this case the ON level, depending on the "H" level of the reverse current detection signal INVD. As a result, switch SW2 turns ON. On the other hand, the voltage switching signal Ssw1 becomes "L" level, in this case the OFF level, depending on the "L" level of the voltage switching signal Ssw2. As a result, switch SW1 turns OFF.

[0062] When switch SW2 is controlled to the ON state, the reference output voltage VOUTR generated at reference node N9 becomes equal to the power supply voltage VCC. As a result, the parasitic bipolar transistors 51a and 51b can remain OFF because their base-emitter voltage VBE becomes 0V. Consequently, the parasitic currents InpnA and InpnB can also remain at 0A.

[0063] Subsequently, at time t3, the on / off control signal IN transitions to the "H" level. At this time, the parasitic bipolar transistors 51a and 51b are in the off state, allowing the boosted voltage Vcp to be applied to the gate node N4 of the power transistor (PT) 7. As a result, the power transistor (PT) 7 turns on. In response, the reverse current Iinv that was flowing through the body diode 7B flows into the channel of the power transistor (PT) 7, which has a low channel resistance.

[0064] When the reverse current Iinv flows through the channel of the power transistor (PT) 7, the output voltage VOUT approaches the power supply voltage VCC. Along with this, the reverse current Iinv also decreases. When the reverse current Iinv stops flowing, and actually when "VOUT < VCC", the reverse current detection circuit 63 negates the reverse current detection signal INVD to the "L" level. In response to this, the switch SW2 turns off as the voltage switching signal Ssw2 transitions to the "H" level, that is, the off level. On the other hand, the switch SW1 turns on as the voltage switching signal Ssw1 transitions to the "H" level, that is, the on level.

[0065] When the switch SW1 turns on, the reference output voltage VOUTR generated at the reference node N9 becomes equal to the output voltage VOUT. Also, since the charge of the load 8a is discharged through the resistive load 8b, the output voltage VOUT will eventually be lower than the power supply voltage VCC. As a result, the reverse current Iinv becomes zero and returns to the normal state. Note that in FIG. 4B, for simplicity of explanation, the reverse current detection signal INVD is negated at time t3.

[0066] <Differences from the semiconductor device (comparative example)> FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device 301 as a comparative example. FIG. 14 is a timing chart showing an operation example when the reverse current Iinv is flowing in the semiconductor device 301 shown in FIG. 13. The semiconductor device 301 as the comparative example shown in FIG. 13 is different from the configuration example shown in FIG. 1 in the following points. As the first difference, the voltage switching switch 66A, the reverse current detection circuit 63, and the switch control circuit 75 are not provided. As the second difference, along with the deletion of the voltage switching switch 66A, the sources of the discharge transistor 12 and the protection transistor 22 are connected to the power output node N8.

[0067] When using this configuration, as shown in Figure 14, the parasitic bipolar transistors 51a and 51b turn on at time t2 when the reverse current Iinv occurs. As a result, even if the on / off control signal IN switches to the "H" level at the subsequent time t3, the power transistor (PT) 7 cannot be turned on. In other words, the power transistor (PT) 7 cannot be turned on until the reverse current Iinv stops flowing.

[0068] Furthermore, the period during which the reverse current Iinv flows can be prolonged because the power transistor (PT) 7 cannot be turned on. Consequently, the period during which the power transistor (PT) 7 cannot be turned on can also be prolonged. On the other hand, using the configuration example in Figure 1, the power transistor (PT) 7 can be turned on at time t3, and as a result, the period during which the reverse current Iinv flows can be shortened.

[0069] <Examples of application to electronic control units (ECUs)> Figure 5 is a circuit block diagram showing an example configuration of an electronic control unit (ECU) 401 to which the semiconductor device 101 shown in Figure 1 is applied. The electronic control unit (ECU) 401 shown in Figure 5 includes, in addition to the semiconductor device 101 shown in Figure 1, a power regulator 404 and a diode 403, and an ECU control device 402, in this case a microcontroller unit (MCU). The electronic control unit (ECU) 401 may be composed of a wiring board or the like on which these components are mounted.

[0070] Furthermore, the electronic control unit (ECU) 401 has a power terminal 1A, a ground power terminal 5A, and a power output terminal 2A. A battery 6 is connected between power terminal 1A and ground power terminal 5A. A load 8 is connected to power output terminal 2A. In this example, load 8 is another electronic control unit (ECU). The electronic control unit that is load 8 is equipped with load 8a, a resistive load 8b, and a power switch 8c, etc. Another load 80 is connected between the power output terminal of the electronic control unit, which is also the power output terminal of the power switch 8c, and the ground power voltage PGND.

[0071] Power terminal 1A receives the battery voltage Vbat. Power regulator 404 receives the power voltage VCC obtained from power terminal 1A and generates a low-voltage power supply voltage for the ECU control device 402. The generated power supply voltage is supplied to the ECU control device 402 via diode 403. In addition, the ground power supply voltage SGND of the battery 6 is supplied to one end of the ECU control device 402 via ground power terminal 5A. Diode 403 is responsible for protecting the ECU control device 402, for example, preventing reverse current from flowing to the ECU control device 402 when the battery 6 is reverse-connected.

[0072] The output port of the ECU control device 402 is connected to the control input terminal 4 of the semiconductor device 101. The ECU control device 402 outputs an on / off control signal IN to the semiconductor device 101 to instruct the power transistor (PT) 7 to be turned on or off. The semiconductor device 101 controls the power supply to the load 8 based on the on / off control signal IN from the control input terminal 4. In this case, for example, even if a reverse current Iinv occurs due to a decrease in the battery voltage Vbat as described above, the power supply to the semiconductor device 101, and consequently to the load 8, can be controlled by the on / off control signal IN from the ECU control device 402.

[0073] The power supply terminal 1 of the semiconductor device 101 is supplied with a power supply voltage VCC from the power supply terminal 1A of the electronic control unit (ECU) 401. The power output terminal 2 of the semiconductor device 101 is connected to the power output terminal 2A of the electronic control unit (ECU) 401. The semiconductor device 101 also has a ground power supply terminal 5. The ground power supply voltage SGND is supplied to the ground power supply terminal 5 via the ground power supply terminal 5A of the electronic control unit (ECU) 401.

[0074] Figure 6 is a schematic diagram showing an example configuration of a vehicle 111 equipped with the electronic control unit (ECU) 401 shown in Figure 5. The vehicle 111 is, for example, an automobile. The vehicle 111 shown in Figure 6 is equipped with a battery 6, the electronic control unit 401, and loads 8 and 80, as shown in Figure 5. The electronic control unit 401 and load 8, and loads 8 and 80 are connected by wire harnesses. In addition, the ground power supply voltage PGND shown in Figure 5 is connected to the housing of the vehicle 111, for example.

[0075] <Regarding supplementary information> For example, Figure 4B illustrates the case where a reverse current Iinv occurs during the period when load 8a is being charged in stages, i.e., before time t4. Here, we consider the case where a reverse current Iinv occurs after the staged charging of load 8a is complete, i.e., after time t4.

[0076] First, when the power transistor (PT) 7 is controlled to the ON state based on the "H" level ON / OFF control signal IN, the reverse current Iinv flows into the channel of the power transistor (PT) 7, not the body diode 7B. As a result, the output voltage VOUT is clamped to approximately the power supply voltage VCC, and the parasitic bipolar transistor 51 remains in the OFF state. In other words, in this case, no particular problems arise due to the parasitic bipolar transistor 51.

[0077] On the other hand, when the power transistor (PT) 7 is controlled to the off state based on the "L" level on / off control signal IN, a reverse current Iinv flows through the body diode 7B. As a result, the parasitic bipolar transistor 51 can be turned on. When the parasitic bipolar transistor 51 is on, it can fix the voltage at node N3 connected to the gate of the power transistor (PT) 7 to the power supply voltage VCC.

[0078] However, in this case, an output voltage VOUT, which is higher than the power supply voltage VCC, is applied to the source of the power transistor (PT) 7 due to the reverse current Iinv. Therefore, the power transistor (PT) 7 can maintain the off state as commanded by the on / off control signal IN. In other words, in this case, even if the parasitic bipolar transistor 51 were to turn on, no particular problem would occur.

[0079] Furthermore, when the on / off control signal IN transitions from the "L" level to the "H" level while a reverse current Iinv is flowing, the reverse current detection circuit 63 and the switch control circuit 75 control switch SW1 to the off state and switch SW2 to the on state. As a result, the parasitic bipolar transistor 51 is controlled to the off state. Consequently, a boosted voltage Vcp can be applied to the gate of the power transistor (PT) 7 via the charging transistor 14, which is controlled to the on state. In other words, the power transistor (PT) 7 can be turned on according to the command based on the on / off control signal IN.

[0080] <Main effects of the first embodiment> As described above, the semiconductor device 101 according to the first embodiment includes, in addition to an output transistor and a control transistor that controls the output transistor to be in the off state, a reverse current detection circuit 63, a voltage selector switch 66A, and a switch control circuit 75. The switch control circuit 75 connects the source and back gate of the control transistor to the power terminal 1 using the voltage selector switch 66A during the period when a reverse current Iinv is generated from the load 8 toward the output transistor. This allows the parasitic bipolar transistor 51 formed on the control transistor to be in the off state, and enables the output transistor to be turned on even during the period when a reverse current is generated.

[0081] (Second Embodiment) <Circuit configuration and operation of semiconductor devices> Figure 7 is a circuit diagram showing an example of the main configuration of the semiconductor device 102 according to the second embodiment. The semiconductor device 102 shown in Figure 7 differs from the configuration example shown in Figure 1 in the following ways. The first difference is that the voltage switching switch 66B includes a switch SW3 in addition to switches SW1 and SW2. Switch (third switch) SW3 is connected in parallel with switch (first switch) SW1. The second difference is that an on / off control circuit 60A different from the one in Figure 1 is provided. The on / off control circuit 60A controls the discharge transistor 12 and the charging transistor 14, the active and inactive states of the charge pump (CP) circuit 61, and the on / off state of switch SW3.

[0082] Figure 8 shows an example of the operating modes provided in the on / off control circuit 60A in Figure 7. The on / off control circuit 60A operates in a capacitive load startup mode or in a normal switching mode. The on / off control circuit 60A operates in the capacitive load startup mode during the period when the load 8a is being charged in stages, i.e., before time t4 in Figures 4A and 4B. On the other hand, the on / off control circuit 60A operates in a normal switching mode during the period after the staged charging of the load 8a is completed, i.e., after time t4.

[0083] In the startup mode of a capacitive load, the on / off control circuit 60A receives an on / off control signal IN that varies with frequency Fin, and controls the on / off state of the power transistor (PT) 7 based on the on / off control signal IN. The on / off control circuit 60A also uses a boost control signal ENcp to keep the charge pump (CP) circuit 61 in an active state at all times. Furthermore, the on / off control circuit 60A uses a voltage switching signal Ssw3 to keep the switch SW3 in an off state at all times.

[0084] The charge pump (CP) circuit 61 is primarily provided to generate the boost voltage Vcp necessary to control the power transistor (PT) 7 to the ON state. On the other hand, the semiconductor device 102 is also required to reduce power consumption. For this reason, it is desirable to control the charge pump (CP) circuit 61 to an inactive state during the period when the ON / OFF control signal IN is at the "L" level. However, if the active and inactive states of the charge pump (CP) circuit 61 are frequently switched during the period when the load 8a is charged in stages, the switching speed of the power transistor (PT) 7 may decrease.

[0085] In detail, at node N15 where the boosted voltage Vcp is generated, discharge may occur in response to the transition of the on / off control signal IN to the "L" level. In this case, when the on / off control signal IN subsequently transitions to the "H" level, a certain amount of time is required to charge node N15 to the desired boosted voltage Vcp. As a result, the effective switching speed of the power transistor (PT) 7 may decrease. For this reason, in the startup mode of the capacitive load, the charge pump (CP) circuit 61 is controlled to be active at all times.

[0086] On the other hand, in normal switching mode, the on / off control circuit 60A receives an on / off control signal IN at an "H" level or an "L" level and controls the power transistor (PT) 7 to be on or off. Here, it is desirable that the on / off control circuit 60A uses a boost control signal ENcp to control the charge pump (CP) circuit 61 to an inactive state during the period when an "L" level on / off control signal IN is input.

[0087] However, in the configuration examples shown in Figures 1 and 7, switch SW1 is controlled to the ON state by the boosted voltage Vcp generated at node N15. When the charge pump (CP) circuit 61 is deactivated, the voltage at node N15 may drop to the level of the power supply voltage VCC supplied to power supply node N7, for example, by the leakage current of the charging transistor 14. This allows switch SW1 to be controlled to the OFF state in response to the transition of the ON / OFF control signal IN to the "L" level.

[0088] When switch SW1 is in the off state, the reference node N9, which is the source of the discharge transistor 12, is disconnected from the power output node N8, which is the source of the power transistor (PT) 7. As a result, a situation may arise where the charge at the gate node N4 of the power transistor (PT) 7 cannot be extracted by the discharge transistor 12, i.e., the power transistor (PT) 7 cannot be turned off.

[0089] Therefore, in normal switching mode, when the on / off control circuit 60A is instructed to turn off the power transistor (PT) 7 by the on / off control signal IN, it controls the active charge pump (CP) circuit 61 to an inactive state after a predetermined delay time (Td). In addition, the on / off control circuit 60A controls the charge pump (CP) circuit 61 to an inactive state and also controls the switch SW3 to be turned on using the power supply voltage VCC.

[0090] Figure 9 is a timing chart showing detailed operation examples of the on / off control circuit 60A in each operating mode in Figures 7 and 8. First, in the start-up mode of the capacitive load, the on / off control circuit 60A maintains the boost control signal ENcp at the active level, in this case the "H" level, even when the on / off control signal IN transitions to the "L" level. As a result, the switch SW1 remains in the ON state by applying the desired boost voltage Vcp, as long as no reverse current Iinv is generated.

[0091] Furthermore, the on / off control circuit 60A controls the discharge transistor 12 to the ON state by outputting an ON level, in this case an H level, discharge control signal DCG, in response to the transition of the ON / OFF control signal IN to the "L" level. Since the switch SW1 remains ON, the discharge transistor 12, which is in the ON state, can turn off the power transistor (PT) 7. The on / off control circuit 60A also maintains the OFF state of switch SW3 by outputting a voltage switching signal Ssw3 at the "L" level, in this case the level of the reference output voltage VOUTR. However, switch SW3 may also be in the ON state.

[0092] On the other hand, in normal switching mode, when the on / off control circuit 60A transitions the on / off control signal IN to the "L" level, it transitions the boost control signal ENcp from the active level to the inactive level, in this case the "L" level, after a predetermined delay time Td. During this delay time Td, the switch SW1 remains in the ON state. Therefore, when the discharge transistor 12 turns on in response to the "H" level discharge control signal DCG, it can draw the charge from the gate of the power transistor (PT) 7 to the source of the power transistor (PT) 7.

[0093] The power transistor (PT) 7 turns off in response to the turn-on of the discharge transistor 12. Consequently, the output voltage VOUT drops to, for example, the level of the ground power supply voltage PGND. The length of the delay time Td is determined based on the time required for the power transistor (PT) 7 to turn off, or the rate at which the output voltage VOUT drops. On the other hand, the switch SW1 may not remain in the ON state during the period after the delay time Td has elapsed, i.e., after the charge pump (CP) circuit 61 has been controlled to an inactive state.

[0094] Therefore, the on / off control circuit 60A turns on the switch SW3 using the "H" level voltage switching signal Ssw3 after a predetermined delay time Td. At this time, the output voltage VOUT and the reference output voltage VOUTR are approximately at the level of the ground power supply voltage PGND. For this reason, the "H" level of the voltage switching signal Ssw3 may be at the level of the power supply voltage VCC. After the switch SW3 is turned on, the off state of the power transistor (PT) 7 can be maintained by the low-impedance discharge path through the discharge transistor 12 and the switch SW3.

[0095] <Main effects of the second embodiment> As described above, by using the method of the second embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, since the charge pump (CP) circuit 61 can be controlled to an inactive state for unnecessary periods, for example, during periods when it is not necessary to operate the load 8, the power consumption of the semiconductor device 102 can be reduced.

[0096] (Third embodiment) <Specific examples of voltage selector switches> Figure 10 is a circuit diagram showing an example of the main configuration of the semiconductor device 103 according to the third embodiment. The semiconductor device 103 shown in Figure 10 has the same configuration as shown in Figure 7. However, unlike Figure 7, Figure 10 shows a more detailed example of the configuration of the voltage selector switch 66C. The voltage selector switch 66C has three switches SW1-SW3, as in Figure 7.

[0097] Switch SW1 consists of an nMOS transistor (first FET) 68. Switch SW2 consists of a pMOS transistor (second FET) 67. Switch SW3 consists of an nMOS transistor (third FET) 71. In each of the two nMOS transistors 68 and 71, the source and back gate are connected to the reference node N9, and the drain is connected to the power output node N8. In the pMOS transistor 67, the source and back gate are connected to the power supply node N7, and the drain is connected to the reference node N9.

[0098] In this case, nMOS transistor 68 is controlled to the ON state when a boost voltage Vcp is applied to its gate, and controlled to the OFF state when a reference output voltage VOUTR is applied to its gate. nMOS transistor 71 is controlled to the OFF state when a reference output voltage VOUTR is applied to its gate. Furthermore, nMOS transistor 71 is controlled to the ON state when a power supply voltage VCC is applied to its gate, assuming that the reference output voltage VOUTR is approximately at the level of the ground power supply voltage PGND. pMOS transistor 67 is controlled to the ON state when an internal power supply voltage VSS is applied to its gate, and controlled to the OFF state when a power supply voltage VCC is applied to its gate.

[0099] <Main effects of the third embodiment> As described above, by using the method of the third embodiment, the same effects as those described in the second embodiment can be obtained. Furthermore, each of the three switches SW1-SW3 can be implemented with a single MOS transistor. This reduces the circuit area overhead.

[0100] (Fourth embodiment) <Variation of a voltage selector switch> Figure 11 is a circuit diagram showing an example of the main configuration of a semiconductor device 104 according to the fourth embodiment. The semiconductor device 104 shown in Figure 11 has a configuration similar to that shown in Figure 10, except for the voltage selector switch 66D. The voltage selector switch 66D includes two nMOS transistors 68, 71 and one pMOS transistor 67, which are almost the same as in Figure 10, in addition to two nMOS transistors 69, 70. However, unlike in Figure 10, the sources of the two nMOS transistors 68, 71 are not connected to the back gate.

[0101] Two nMOS transistors 69 and 70 are connected in series between the power output terminal 2 and the reference node N9, and in parallel with nMOS transistor 68. One of the sources and drains of nMOS transistor (fourth FET) 69 is connected to the reference node N9, the other to the intermediate node N13, and the gate is connected to the intermediate node N13. One of the sources and drains of nMOS transistor (fifth FET) 70 is connected to the intermediate node N13, the other to the power output terminal 2.

[0102] The nMOS transistors (first FET) 68 and (fifth FET) 70 are commonly controlled on and off by the switch control circuit 75. Furthermore, the back gates of the four nMOS transistors 68, 69, 70, and 71 are all connected to the intermediate node N13. This configuration prevents current from flowing through the back gates of either the nMOS transistor 68 (switch SW1) or the nMOS transistor 71 (switch SW3). In other words, parasitic bipolar transistors that may form in the four nMOS transistors 68, 69, 70, and 71 can be controlled to the off state.

[0103] Figure 12A is a circuit diagram showing a detailed configuration example, including parasitic elements, of the voltage selector switch 66D shown in Figure 11. Figure 12B is a comparative example with Figure 12A, and is a circuit diagram showing a detailed configuration example, including parasitic elements, of the voltage selector switch 66C shown in Figure 10. First, in Figure 12B, the nMOS transistor 68 has, more specifically, a body diode 68B between the back gate and the drain. Also, since the back gate-source is short-circuited, the body diode between the back gate and the source is ignored. Similarly, the nMOS transistor 71 also has a body diode 71B between the back gate and the drain.

[0104] Here, for example, let's consider a case where the voltage at power output node N8 drops rapidly due to a load short circuit or surge, while pMOS transistor 67 is ON and the two nMOS transistors 68 and 71 are OFF. In this case, current flows from power node N7 to power output terminal 2 via the body diodes 68B and 71B of the two nMOS transistors 68 and 71.

[0105] As a result, the two nMOS transistors 68 and 71 may be destroyed by the parasitic bipolar transistors formed around them turning on. In other words, just like the discharge transistor 12 and protection transistor 22 shown in Figure 10, parasitic NPN type bipolar transistors that operate with reference node N9 as the base are formed around the two nMOS transistors 68 and 71. When current flows through the body diodes 68B and 71B of the two nMOS transistors 68 and 71, rather than the channels, the parasitic bipolar transistors can turn on due to forward biasing of the base-emitter junction.

[0106] On the other hand, in Figure 12A, the back gates of the four nMOS transistors 68, 69, 70, and 71 are connected to the intermediate node N13. Therefore, nMOS transistor 68 has two body diodes 68B and 68C, both with the back gate as the anode. Similarly, the remaining three nMOS transistors 69, 70, and 71 have a total of six body diodes 69B, 69C, 70B, 70C, 71B, and 71C. However, two of these body diodes, 69B and 70C, are short-circuited due to the wiring and are therefore ignored.

[0107] The two body diodes 68C and 71C, whose cathodes are connected to the reference node N9, block the current flowing from the reference node N9 to the power output terminal 2 via the two body diodes 68B and 71B when the two nMOS transistors 68 and 71 are in the off state. In addition, the body diode 69C of the nMOS transistor 69, whose cathode is connected to the reference node N9, blocks the current flowing to the three body diodes 68B, 70B, and 71B via the back gate intermediate node N13.

[0108] Furthermore, the on / off state of nMOS transistor 70 is controlled by the same voltage switching signal Ssw1 as that of nMOS transistor 68. When nMOS transistor 70 is in the ON state, the voltage at intermediate node N13, that is, the back gate voltages of the four nMOS transistors 68, 69, 70, and 71, is set as the output voltage VOUT.

[0109] With this configuration, for example, even if the voltage at power output node N8 drops rapidly due to a load short circuit or surge when the three nMOS transistors 68, 70, and 71 are in the off state, no current flows from power node N7 through the three body diodes 68B, 70B, and 71B. As a result, the three nMOS transistors 68, 70, and 71 can maintain the off state of parasitic bipolar transistors, thus preventing damage that could occur due to on-state parasitic bipolar transistors.

[0110] The operation of the semiconductor device 104 shown in Figure 11 is the same as that shown in Figures 4A and 4B, except for the operation of the voltage selector switch 66D. To briefly explain the differences, first, as shown in Figure 4A, when the load 8a is charged in stages with no reverse current Iinv flowing, the pMOS transistor 67, which is switch SW2, is controlled to the off state. On the other hand, the nMOS transistor 68, which is switch SW1, and the nMOS transistor 70, which shares a gate with the nMOS transistor 68, are controlled to the on state. As a result, the voltages at the reference node N9 and the intermediate node N13 become approximately equal to the output voltage VOUT.

[0111] The nMOS transistor 69 has the voltage of the intermediate node N13, i.e., approximately the output voltage VOUT, applied to its gate and back gate, and the reference output voltage VOUTR, i.e., approximately the output voltage VOUT, applied to its source. This controls the nMOS transistor 69 to the off state. As a result, the voltage of the intermediate node N13 is set to approximately the level of the output voltage VOUT by the on-state nMOS transistor 70.

[0112] Furthermore, as described in Figures 8 and 9, the nMOS transistor 71 is fixed in the off state, for example, during the period when the load 8a is charged in stages. The parasitic bipolar transistors 51a and 51b of the discharge transistor 12 and the protection transistor 22 remain in the off state, similar to the case in Figure 4A, because no reverse current Iinv flows through them.

[0113] On the other hand, as shown in Figure 4B, if a reverse current Iinv flows during the stepwise charging of load 8a, at time t2, the pMOS transistor 67, which is switch SW2, is controlled to the ON state. Meanwhile, the nMOS transistor 68, which is switch SW1, and the nMOS transistor 70, which shares a gate with nMOS transistor 68, are controlled to the OFF state. As a result, the reference output voltage VOUTR generated at reference node N9 becomes equal to the power supply voltage VCC. Also, reference node N9 is disconnected from power output node N8.

[0114] Furthermore, the voltage at intermediate node N13, i.e., the back gate voltages of the four nMOS transistors 68, 69, 70, and 71, is the voltage between the reference output voltage VOUTR, i.e., the power supply voltage VCC, and a higher output voltage VOUT. The nMOS transistor 70 is controlled to the off state because the voltage at intermediate node N13 is applied to its source, and a voltage switching signal Ssw1 at the level of the reference output voltage VOUTR is applied to its gate. As a result, the series circuit consisting of the two nMOS transistors 69 and 70, together with the nMOS transistor 68, can isolate the reference node N9 from the power output node N8.

[0115] As a result, similar to the case in Figure 4B, the parasitic bipolar transistors 51a and 51b are controlled to the off state because their base-emitter voltage VBE becomes 0V. Consequently, the parasitic currents InpnA and InpnB also do not flow. As a result, the power transistor (PT) 7 can be turned on by applying a boost voltage Vcp to its gate. In other words, the power transistor (PT) 7 can be controlled on and off based on the on / off control signal IN.

[0116] <Main effects of the fourth embodiment> As described above, by using the method of the fourth embodiment, the same effects as those described in the second embodiment can be obtained. Furthermore, unlike the method of the third embodiment, the voltage switching switch 66D can keep the parasitic bipolar transistors formed on each nMOS transistor in the off state. As a result, it is possible to prevent the destruction of each nMOS transistor that may occur due to the on state of the parasitic bipolar transistors. In other words, the reliability of the semiconductor device 104 can be improved.

[0117] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0118] 1 Power terminal 2 Power output terminals 7. Power Transistors (Output Transistors) 8 loads 12. Discharge transistor (control transistor) 14 Charging Transistors 22. Protection transistor (control transistor) 51a, 51b Parasitic bipolar transistors 61 Charge Pump (CP) Circuit 63 Reverse current detection circuit 66A-66D Voltage Selector Switch 67 pMOS transistors 68-71 nMOS transistors 75 Switch control circuit 101-104 Semiconductor Equipment 401 Electronic Control Unit (ECU) 402 ECU Control Unit IN On / Off Control Signal INVD Reverse Current Detection Signal Iinv reverse current N9 Reference Node N13 Intermediate Node SW1-SW3 Switch VCC power supply voltage Vcp Boost Voltage

Claims

1. An output transistor formed on a semiconductor substrate, connected between a power supply terminal and a power output terminal, and which supplies power to a load connected to the power output terminal when controlled to the ON state, A first switch that connects the aforementioned power output terminal to a reference node, A second switch that connects the power terminal to the reference node, A first control transistor, formed on the semiconductor substrate, controls the output transistor to an off state by short-circuiting the gate of the output transistor and the reference node when controlled to an ON state, A reverse current detection circuit that detects the occurrence of a reverse current from the power output terminal toward the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is occurring, A switch control circuit controls the first switch to the ON state and the second switch to the OFF state during the negate period of the reverse current detection signal, and controls the first switch to the OFF state and the second switch to the ON state during the assert period of the reverse current detection signal. Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The output transistor is composed of an n-channel MOSFET with the power output terminal and the power supply terminal as the source and drain, respectively. The first switch is composed of a first FET which is an n-channel MOSFET. The second switch is composed of a second FET, which is a p-channel MOSFET. Semiconductor equipment.

3. In the semiconductor device described in claim 2, Furthermore, the system includes a fourth FET and a fifth FET, both of which are n-channel MOSFETs, connected in series between the power output terminal and the reference node and connected in parallel with the first FET. The fourth FET has one of its source and drain connected to the reference node, the other connected to the intermediate node, and its gate connected to the intermediate node. The fifth FET has one of its source and drain connected to the intermediate node and the other connected to the power output terminal. The first FET and the fifth FET are commonly controlled on and off by the switch control circuit. The back gates of the first FET, the fourth FET, and the fifth FET are all connected to the intermediate node. Semiconductor equipment.

4. In the semiconductor device according to claim 1, An on / off control circuit controls the on / off state of the first control transistor based on an on / off control signal for instructing the on / off state of the output transistor from an external source, A charge pump circuit that generates a boosted voltage higher than the power supply voltage applied to the power supply terminal when in the active state, Equipped with, Semiconductor equipment.

5. In the semiconductor device according to claim 4, Furthermore, it includes a third switch connected in parallel with the first switch, The on / off control circuit further controls the active and inactive states of the charge pump circuit and the on / off state of the third switch. The switch control circuit uses the boosted voltage to control the first switch to the ON state. The on / off control circuit, when the on / off control signal instructs the output transistor to be turned off, controls the active charge pump circuit to an inactive state after a predetermined delay time, and controls the third switch to an on state using the power supply voltage. Semiconductor equipment.

6. In the semiconductor device described in claim 5, The output transistor is composed of an n-channel MOSFET with the power output terminal and the power supply terminal as the source and drain, respectively. The first switch is composed of a first FET which is an n-channel MOSFET. The second switch is composed of a second FET which is a p-channel MOSFET. The third switch is composed of a third FET, which is an n-channel MOSFET. Semiconductor equipment.

7. In the semiconductor device according to claim 4, Furthermore, the semiconductor substrate is formed with a second control transistor that controls the output transistor to an off state by short-circuiting the gate of the output transistor and the reference node in response to a predetermined anomaly detection. Semiconductor equipment.

8. In the semiconductor device described in claim 1, The output transistor is a vertical n-channel MOSFET with the back surface of the semiconductor substrate as the drain and the power output terminal and the power supply terminal as the source and drain, respectively. The first control transistor is composed of a lateral n-channel MOSFET with the gates of the reference node and the output transistor as the source and drain, respectively. An NPN-type parasitic bipolar transistor is formed in the first control transistor. The parasitic bipolar transistor is based on the back gate of the first control transistor and the source connected to the back gate, and operates with the drain of the first control transistor and one of the back surfaces of the semiconductor substrate as the emitter and the other as the collector. Semiconductor equipment.

9. In the semiconductor device described in claim 1, The reverse current detection circuit includes a comparator that compares the magnitude of the power supply voltage applied to the power supply terminal with the output voltage generated at the power output terminal. Semiconductor equipment.

10. Power terminals to which power voltage is supplied, The power output terminal to which the load is connected, A semiconductor device that supplies power to the aforementioned load, A control device for controlling the aforementioned semiconductor device, An electronic control system having, The aforementioned semiconductor device is An output transistor formed on a semiconductor substrate, connected between the power supply terminal and the power output terminal, and which supplies power to the load when controlled to the ON state, A first switch that connects the aforementioned power output terminal to a reference node, A second switch that connects the power terminal to the reference node, A first control transistor, formed on the semiconductor substrate, controls the output transistor to an off state by short-circuiting the gate of the output transistor and the reference node when controlled to an ON state, A reverse current detection circuit that detects the occurrence of a reverse current from the power output terminal toward the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is occurring, A switch control circuit controls the first switch to the ON state and the second switch to the OFF state during the negate period of the reverse current detection signal, and controls the first switch to the OFF state and the second switch to the ON state during the assert period of the reverse current detection signal. Equipped with, The control device outputs an on / off control signal to the semiconductor device for instructing the output transistor to be turned on or off. Electronic control system.

11. In the electronic control system according to claim 10, The output transistor is composed of an n-channel MOSFET with the power output terminal and the power supply terminal as the source and drain, respectively. The first switch is composed of a first FET which is an n-channel MOSFET. The second switch is composed of a second FET, which is a p-channel MOSFET. Electronic control system.

12. In the electronic control system according to claim 11, The semiconductor device further includes a fourth FET and a fifth FET, both of which are n-channel MOSFETs, connected in series between the power output terminal and the reference node and connected in parallel with the first FET. The fourth FET has one of its source and drain connected to the reference node, the other connected to the intermediate node, and its gate connected to the intermediate node. The fifth FET has one of its source and drain connected to the intermediate node and the other connected to the power output terminal. The first FET and the fifth FET are commonly controlled on and off by the switch control circuit. The back gates of the first FET, the fourth FET, and the fifth FET are all connected to the intermediate node. Electronic control system.

13. In the electronic control system according to claim 10, The aforementioned semiconductor device further, An on / off control circuit controls the on / off state of the first control transistor based on an on / off control signal for instructing the on / off state of the output transistor from an external source, A charge pump circuit that generates a boosted voltage higher than the power supply voltage applied to the power supply terminal when in the active state, Equipped with, Electronic control system.

14. In the electronic control system according to claim 13, The semiconductor device further includes a third switch connected in parallel with the first switch, The on / off control circuit further controls the active and inactive states of the charge pump circuit and the on / off state of the third switch. The switch control circuit uses the boosted voltage to control the first switch to the ON state. The on / off control circuit, when the on / off control signal instructs the output transistor to be turned off, controls the active charge pump circuit to an inactive state after a predetermined delay time, and controls the third switch to an on state using the power supply voltage. Electronic control system.

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