Filter circuit device

Abstract

To provide a filter circuit device that can perform impedance adjustment and phase adjustment while suppressing increases in insertion loss and chip size. [Solution] In the filter circuit device 1, the piezoelectric substrate 100 has filter circuits 2 and 3 composed of filter IDT electrodes 20, 30a and 30b, and a capacitor IDT electrode 5 used as a capacitor for impedance adjustment and phase adjustment, which is provided on the input side of the filter circuit 2. Furthermore, the input side of the filter circuit 2 is provided with a connection port 104 for connecting an external impedance adjustment inductor 41.

Description

Technical Field

[0001] The present invention relates to a filter circuit device mounted on a communication device.

Background Art

[0002] For example, in a communication device such as a mobile phone, a number of filter circuits are provided, and impedance matching with other circuits is achieved using inductors and capacitors. For example, Patent Document 1 describes a configuration in which a grounded inductor is connected between a switch for connecting to an antenna and a reception filter in a high-frequency module used in a communication device.

[0003] In addition, in a communication device, there may be a need to support carrier aggregation (CA) that simultaneously uses multiple frequency bands. In a communication device that supports CA, there may be a need for unique measures in impedance adjustment and phase adjustment of the filter circuit. On the other hand, for the entire filter circuit device including elements for adjusting impedance and phase, it is preferable to minimize insertion loss and mounting area as much as possible.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made based on such circumstances, and an object thereof is to provide a filter circuit device capable of performing impedance adjustment and phase adjustment while suppressing an increase in insertion loss and an increase in chip size.

Means for Solving the Problems

[0006] The filter circuit device of the present invention is Piezoelectric substrate and One or more filter circuits formed on the piezoelectric substrate and composed of filter IDT electrodes, Used as a capacitor for impedance adjustment and phase adjustment, the capacitor IDT electrode is provided on the input side of the filter circuit on the piezoelectric substrate, The filter circuit is characterized by having a connection port on the input side for connecting an external impedance adjustment inductor.

[0007] The filter circuit device may have the following features. (a) The multiple electrode fingers constituting the capacitor IDT electrode and the multiple electrode fingers constituting the filter IDT electrode of the filter circuit connected to the capacitor IDT electrode are all spaced apart from each other. (b) The connection port is provided at the end of a branch line that branches off from the connection line connecting the filter circuit and the capacitor IDT. (c) The capacitance of the capacitor IDT electrode is adjusted by the electrode index that constitutes the capacitor IDT electrode. (d) One or more of the filter circuits include a ladder-type filter circuit comprising one or more of the filter IDT electrodes that are in series and one or more of the filter IDT electrodes that are in parallel. The one or more of the filter circuits also include a dual-mode filter circuit in which the multiple filter IDT electrodes are acoustically coupled and excite multiple resonant modes. [Effects of the Invention]

[0008] According to the filter circuit device of the present invention, a capacitor IDT electrode, used as a capacitor for impedance adjustment and phase adjustment, is provided on a piezoelectric substrate on which a filter circuit consisting of filter IDT electrodes is provided, and a connection port for connecting an external impedance adjustment inductor is also provided. With this configuration, impedance adjustment and phase adjustment can be performed while suppressing an increase in chip size. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram showing the configuration of a filter circuit device relating to the first comparative configuration. [Figure 2] This shows the insertion loss characteristics of the filter circuit device according to the first comparison configuration. [Figure 3] This is a Smith chart showing the reflection characteristics of the filter circuit device relating to the first comparative configuration. [Figure 4] This is a diagram showing the configuration of a filter circuit device relating to the second comparative configuration. [Figure 5] This shows the insertion loss characteristics of the filter circuit device according to the second comparative configuration. [Figure 6] This is a Smith chart showing the reflection characteristics of the filter circuit device relating to the second comparative configuration. [Figure 7] This is a configuration diagram of a filter circuit device according to an embodiment. [Figure 8] This shows the insertion loss characteristics of the filter circuit device according to the embodiment. [Figure 9] This is a Smith chart showing the reflection characteristics of the filter circuit device according to the embodiment. [Figure 10] This graph shows the phase characteristics of the filter circuit device according to the embodiment. [Figure 11] This graph shows the reflection characteristics of the filter circuit device according to the embodiment. [Figure 12] This is a configuration diagram of the filter circuit device according to the first modified example. [Figure 13] This is a diagram showing the configuration of a filter circuit device according to a second modified example. [Modes for carrying out the invention]

[0010] The filter circuit device 1 according to an embodiment of the present invention is configured as a chip with a side length of about 1 mm, for example. The chip configuration of the filter circuit device 1 can be exemplified by the case of adopting a WLP (Wafer Level Package). The carrier frequency of the frequency signal processed by the filter circuit device 1 varies depending on the country or communication carrier using the mobile communication device, but frequencies within the range of approximately 0.8 to 3 GHz can be exemplified.

[0011] Before explaining a specific configuration example of the filter circuit device 1 according to an embodiment of the present invention, the functions required for the filter circuit device 1 mounted on a communication device having a carrier aggregation (CA) function will be explained while referring to two comparative forms. Hereinafter, in the filter circuit devices 1, 1a, 1b, 10a, 10b according to the comparative forms and embodiments shown in FIGS. 1, 4, 7, 12, and 13, the same reference numerals are given to common components.

[0012] FIG. 1 shows a configuration example of a filter circuit device 10a according to a first comparative form. This filter circuit device 10a forms a ladder-type filter circuit 2 and a dual-mode SAW (DMS: Double Mode SAW) filter circuit 3 on a piezoelectric substrate 100 made of, for example, lithium tantalate (LiTaO3), and these filter circuits 2 and 3 are connected in series.

[0013] The ladder-type filter circuit 2 is a band filter provided with series arms 21 connected in series to each other and parallel arms 22 connected to the subsequent stage of each series arm 21 and grounded via a ground port 103. In the ladder-type filter circuit 2 of this example, two sets of combinations of series arms 21 and parallel arms 22 are provided. The input side of the ladder-type filter circuit 2 is connected to an input port 101, and the output side is connected to the subsequent-stage DMS filter circuit 3.

[0014] In the ladder-type filter circuit 2, the series arm 21 and the parallel arm 22 are composed of known IDT (Interdigital Transducer) electrodes 20 and 20a. Each IDT electrode 20 and 20a has multiple electrode fingers connected to each other via busbars, and is configured such that an intersection region of the electrode fingers is formed between the pairs of electrode fingers and busbars. To distinguish them from the IDT electrode 5, which will be described later and used as a capacitor, the IDT electrodes provided in the filter circuits 2 and 3 are also referred to in this application as "filter IDT electrodes 20, 20a, and 30".

[0015] When viewed along the propagation direction (also called the "longitudinal direction") of the SAW (Surface Acoustic Wave) excited on the piezoelectric substrate 100 by the filter IDT electrodes 20 and 20a, reflectors with multiple electrode fingers short-circuited are provided on both sides of each filter IDT electrode 20 and 20a, but the symbols in the figure are omitted. In the following explanation, these reflectors may also be collectively referred to as "filter IDT electrodes 20a, 20a".

[0016] The DMS filter circuit 3 is a bandpass filter that excites multiple vibration modes by arranging a filter IDT electrode 30a connected to the output side of the ladder-type filter circuit 2 and a filter IDT electrode 30b connected to the output port 102 in a vertical direction, acoustically coupling SAW between these filter IDT electrodes 30a and 30b. The DMS filter circuit 3 shown in Figure 1 has a configuration in which, for example, three filter IDT electrodes 30a and four filter IDT electrodes 30b are arranged alternately. In the DMS filter circuit 3, a reflector is placed outside the arrangement of these filter IDT electrodes 30a and 30b (not shown in numerals). In addition, for each filter IDT electrode 30a and 30b, the electrode fingers not connected to the ladder-type filter circuit 2 or the output port 102 are connected to the ground port 103. Furthermore, if the filter circuit device 10a is configured with WLP, each port 101 to 103 corresponds to a solder bump connected to a connecting wire formed on the piezoelectric substrate 100.

[0017] The filter circuit device 10a, having the configuration described above, is implemented in communication equipment by connecting an impedance adjusting element such as an inductor 41 between it and the input-side switch and the output-side signal processing device (neither the switch nor the signal processing device is shown in the diagram). On the other hand, as explained in the background art, the filter circuit device 10a is required to have the smallest possible insertion loss in the operating bandwidth, and may also require special phase adjustment to accommodate CA.

[0018] Figure 2 shows the frequency characteristics of the insertion loss of the entire circuit, including the filter circuit device 10a and inductor 41, as explained using Figure 1. The horizontal axis of Figure 2 represents the normalized frequency based on a predetermined frequency within the frequency range (0.8 to 3 GHz) described above, and the vertical axis represents the attenuation [dB] (the same applies to Figures 5 and 8 described later). Figure 3 is a Smith chart showing the reflection characteristics of the entire circuit, and it shows the reflectance characteristics in the frequency range of other frequency bands used simultaneously in CA (hereinafter also referred to as "CA partners").

[0019] Here, the filter circuit 10a corresponding to CA is required to exhibit a response close to that of an open circuit when a frequency signal within the frequency range of the CA partner is input. In this case, the filter circuit 10a appears not to be connected to the input terminal of the frequency signal within the frequency range of the CA partner. As a result, the entire CA-compatible communication equipment can achieve a state where, for frequency signals within the frequency range of the CA partner, only the filter circuit (not shown) of the other CA partner is functioning.

[0020] In this example, we consider a case where a filter circuit device 10a exhibits a response close to an open circuit in the CA frequency range by adjusting the characteristics of the filter IDT electrode 20a that constitutes the first-stage series arm 21 on the input side of the ladder-type filter circuit 2. In this case, the design is made so that the capacitance of the IDT electrode 20a is small in the CA frequency range. Design variables for reducing the capacitance of the filter IDT electrode 20a include, for example, reducing the number of electrode fingers or shortening the electrode fingers. For ease of illustration, in Figure 1, the IDT electrode 20a (first-stage series arm 21) that has been designed to reduce capacitance in the CA frequency range is shown as smaller than the other filter IDT electrodes 20. In the filter circuit device 10a, the electrode finger spacing of the filter IDT electrodes 20 and 20a provided on the series arm 21 is the same.

[0021] Figure 2 shows the overall insertion loss characteristics including the filter circuit 10a and inductor 41 shown in Figure 1, including the filter circuit 10a with adjusted capacitance of the filter IDT electrode 20a of the series arm 21 on the input side. In this example, insertion loss characteristics were obtained in which the attenuation in the passband was approximately -2 to -3.5 dB. However, it is desirable to have this insertion loss as small as possible.

[0022] Furthermore, in CA (Computer Adapter), the phase of the frequency signal to which the CA is applied rotates clockwise due to the influence of the capacitance of the switch or the wiring itself. In such cases, it is understood that impedance adjustment is easier if the filter circuit 10a is configured so that the phase of the reflection coefficient rotates counterclockwise.

[0023] Looking at the Smith chart in Figure 3 from this perspective, the reflection characteristics of the circuit including the filter circuit device 10a shown in Figure 1 show that the phase of the reflection coefficient in the frequency range of the CA target is in the range of approximately -70° to -40°. If the circuit including the filter circuit device 10a has such reflection characteristics, it becomes difficult to achieve impedance matching with the switch side. Thus, from the perspective of application to CA, the filter circuit device 10a in the first comparison form shown in Figure 1 needs improvement in terms of reflection characteristics as well.

[0024] Based on these challenges, the circuit shown in the second comparative configuration of Figure 4 has a configuration in which a capacitor 42 is connected in series with the input inductor 41 at the connection point outside the filter circuit device 10b. In the ladder-type filter circuit 2 of this filter circuit device 10b, the configuration of the filter IDT electrodes 20 of the first and second stage series arms 21 is the same (the first stage series arm 21 does not have a filter IDT electrode 20a designed to have a small capacitance).

[0025] Furthermore, examining the insertion loss of the circuit shown in Figure 4 (the entire circuit including the filter circuit device 10b, inductor 41, and capacitor 42), we see that, as shown in Figure 5, the insertion loss characteristics in the passband are approximately -1.5 to -2 dB. This can be evaluated as an improvement in insertion loss compared to the first comparison configuration shown in Figure 2. In addition, according to the Smith chart shown in Figure 6, the phase of the reflection coefficient is in the range of approximately -25° to +20°, indicating a significant improvement in the reflection characteristics as well. As will be described later in Figure 10, the goal of this invention is to keep the phase of the reflection coefficient of the CA counterpart within ±30°. As confirmed above, the filter circuit device 10b according to the second comparison configuration shown in Figure 4 can be evaluated as having better insertion loss characteristics and reflection characteristics compared to the filter circuit device 10a according to the first comparison configuration shown in Figure 1.

[0026] On the other hand, looking at the overall circuit configuration of the second comparison configuration in Figure 4, as mentioned above, a capacitor 42 is provided outside the filter circuit device 10b, which means that the number of elements mounted on the communication equipment has increased by one compared to the first comparison configuration shown in Figure 1. In particular, adding a separate capacitor 42 outside the filter circuit device 10b has a relatively large impact in terms of mounting area. Especially in communication equipment, since the circuit including the filter circuit device 10b is connected to the switch in multiple systems, the impact of adding the capacitor 42 becomes even greater.

[0027] Furthermore, adding a capacitor 42 as an external element to the filter circuit device 10b and performing impedance matching while adjusting the characteristics of the inductor 41 and capacitor 42 increases the design burden on communication equipment using the filter circuit device 10b. In this respect, if a filter circuit device 1 with the function of capacitor 42 already incorporated can be provided, it will contribute to reducing the design burden on communication equipment.

[0028] As discussed above, the first comparative form of the filter circuit device 10a has the problem of improving insertion loss and reflection characteristics, while the second comparative form of the filter circuit device 10b has the problem of increased mounting area and increased design burden due to the addition of the capacitor 42. To solve these problems, the inventors of the present application have found a configuration in which a capacitor is provided on a piezoelectric substrate 100 common to the filter circuits 2 and 3. Figure 7 shows an example of the configuration of the filter circuit device 1 according to the embodiment.

[0029] In the filter circuit device 1 shown in Figure 7, an IDT electrode 5 is connected in series to the input side of the first series arm 21 of the ladder-type filter circuit 2 on the piezoelectric substrate 100. This IDT electrode 5 corresponds to the capacitor 42 in the circuit shown in Figure 4. That is, this IDT electrode 5 has the function of adjusting the impedance and phase of the entire circuit shown in Figure 7. From this perspective, this IDT electrode is also called the "capacitor IDT electrode 5".

[0030] The following describes the features of the capacitor IDT electrode 5. The first feature is that the multiple electrode fingers constituting the capacitor IDT electrode 5 and the multiple electrode fingers constituting the filter IDT electrode 20 of the series arm 21 of the ladder-type filter circuit 2 connected to the capacitor IDT electrode 5 have the same spacing between them. This makes it possible to avoid the effect of the capacitor IDT electrode 5 on the filter characteristics of the filter circuit device 1. In a typical ladder-type filter circuit 2, the spacing between the electrode fingers of the filter IDT electrode 20 differs between the series arm 21 and the parallel arm 22 in order to create different resonant frequencies. Therefore, the spacing between the electrode fingers of the capacitor IDT electrode 5 and the electrode fingers of the filter IDT electrode 20 of the parallel arm 22 differs from each other.

[0031] A second feature is that the capacitance of the capacitor IDT electrode 5 can be adjusted, for example, by the electrode index that constitutes the capacitor IDT electrode 5. Therefore, the electrode index provided on the capacitor IDT electrode 5 may differ from the electrode index of the filter IDT electrode 20 of the series arm 21. For example, the capacitance of the capacitor IDT electrode 5 is set to a capacitance that exhibits reflection characteristics equivalent to the second comparison configuration described in Figure 6 when an inductor 41 having a predetermined self-inductance is connected to the input side of the ladder-type filter circuit 2 and the output side of the DMS filter circuit 3.

[0032] Furthermore, the filter circuit device 1 of this embodiment is provided with a connection port 104 on the input side of the ladder-type filter circuit 2 for connecting an external impedance adjustment inductor 41. In the example shown in Figure 7, the connection port 104 is provided at the end of a branch line that branches off from the connection line connecting the ladder-type filter circuit 2 (first-stage series arm 21) and the capacitor IDT electrode 5. When the filter circuit device 1 is configured with WLP, the connection port 104 is configured by a solder bump connected to the branch line, similar to the other ports 101 to 103.

[0033] Looking at the insertion loss of the circuit (the entire circuit including the filter circuit device 1 and inductor 41) according to the embodiment of the configuration described above, as shown in Figure 8, the insertion loss characteristics in the passband are approximately -1.5 to -2 dB. Furthermore, according to the Smith chart shown in Figure 9, the phase of the reflection coefficient is in the range of approximately -30° to +20°, satisfying the target reflection characteristics (±30°). Based on these results, the circuit including the filter circuit device 1 according to the embodiment shown in Figure 7 can be evaluated as having characteristics equivalent to the circuit in the second comparative configuration shown in Figure 4, in which an external capacitor 42 is provided.

[0034] Furthermore, the characteristics of the circuit including the filter circuit device 1 will be examined in detail with reference to Figures 10 and 11. Figure 10 shows the phase characteristics of S(1,1) of the filter circuit device 1, and Figure 11 shows the reflection characteristics of S(1,1). In both figures, the horizontal axis is the normalized frequency, the vertical axis in Figure 10 is the phase [°], and the vertical axis in Figure 11 is the attenuation of the reflected wave [dB]. Furthermore, in both figures, the range indicated by the hatched area represents the frequency band of the CA counterpart. According to Figure 10, in the frequency band of the CA counterpart, the phase of the reflected wave is within ±30°. Also, looking at the reflection characteristics in Figure 11, the attenuation in the frequency band of the CA counterpart is less than -0.5dB. In this application, the goal is to keep this attenuation within -1.0dB, and the reflection characteristics shown in Figure 11 satisfy this goal.

[0035] On the other hand, as a result of manufacturing a filter circuit device 1 with the above characteristics using WLP, the chip size of the filter circuit device 1 could be made 0.85 mm × 0.6 mm. If a filter circuit device 10b and capacitor 42 according to the comparative configuration shown in Figure 4 were to be provided, the mounting area would need to be about 1.3 to 1.5 times that of the filter circuit device 1 of the embodiment, including the area for arranging the connecting wires between them. In this respect, the filter circuit device 1, in which the capacitor IDT electrode 5, ladder-type filter circuit 2, and DMS filter circuit 3 are integrated and formed on a common piezoelectric substrate 100 by photolithography or the like, has a small increase in mounting area when adding the capacitor IDT electrode 5.

[0036] According to the filter circuit device 1 of this embodiment, a ladder-type filter circuit 2 consisting of filter IDT electrodes 20 and a DMS filter circuit 3 consisting of filter IDT electrodes 30a and 30b are provided on a piezoelectric substrate 100. Capacitor IDT electrodes 5, used as capacitors for impedance adjustment and phase adjustment, are provided on the substrate 100, and a connection port 104 for connecting an external impedance adjustment inductor 41 is also provided. This configuration allows for impedance adjustment and phase adjustment while suppressing an increase in the chip size of the filter circuit device 1.

[0037] Here, the configuration of the filter circuit device 1 is not limited to the case where it comprises multiple filter circuits (ladder-type filter circuit 2, DMS filter circuit 3) as shown in the embodiment in Figure 7. For example, as shown in the filter circuit device 1a in Figure 12, capacitor IDT electrodes 5 and connection ports 104 may be provided on a piezoelectric substrate 100 on which a set of ladder-type filter circuits 2 are formed. Alternatively, as shown in the filter circuit device 1b in Figure 13, capacitor IDT electrodes 5 and connection ports 104 may be provided on a piezoelectric substrate 100 on which a single DMS filter circuit 3 is formed. In this case, the electrode spacing of the capacitor IDT electrodes 5 is matched to the electrode spacing of the filter IDT electrodes 30a and 30b of the DMS filter circuit 3.

[0038] Furthermore, the DMS filter circuit 3 is not limited to using a longitudinally coupled dual-mode filter that excites vibrational modes between filter IDT electrodes 30a and 30b arranged along the vertical direction. It may also be a transversely coupled dual-mode filter in which filter IDT electrodes 30a and 30b are arranged side by side in the horizontal direction, and a SAW is acoustically coupled between these filter IDT electrodes 30a and 30b to excite multiple vibrational modes. [Explanation of Symbols]

[0039] 1, 1a, 1b Filter circuit device 100 Piezoelectric substrates 104 connection ports 2. Ladder filter circuit 20 Filter IDT electrodes 3. Dual-mode SAW (DMS) filter circuit 30a, 30b Filter IDT electrode 5 Capacitor IDT electrode

Claims

1. A filter circuit device, Piezoelectric substrate and One or more filter circuits formed on the piezoelectric substrate and composed of filter IDT electrodes, A capacitor used for impedance adjustment and phase adjustment, and a capacitor IDT electrode provided on the input side of the filter circuit on the piezoelectric substrate, A filter circuit device characterized by having a connection port on the input side of the filter circuit for connecting an external impedance adjustment inductor.

2. The filter circuit device according to claim 1, characterized in that the plurality of electrode fingers constituting the capacitor IDT electrode and the plurality of electrode fingers constituting the filter IDT electrode of the filter circuit connected to the capacitor IDT electrode are spaced evenly apart from each other.

3. The filter circuit device according to claim 1, characterized in that the connection port is provided at the end of a branch line that branches off from the connection line connecting the filter circuit and the capacitor IDT.

4. The filter circuit device according to claim 1, characterized in that the capacitance of the capacitor IDT electrode is adjusted by the electrode index constituting the capacitor IDT electrode.

5. The filter circuit device according to claim 1, characterized in that one or more of the filter circuits include a ladder-type filter circuit comprising one or more of the filter IDT electrodes which are in series and one or more of the filter IDT electrodes which are in parallel.

6. The filter circuit device according to claim 1, characterized in that one or more of the filter circuits include a dual-mode filter circuit in which a plurality of the filter IDT electrodes are acoustically coupled and a plurality of resonance modes are excited.

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