Semiconductor packages

Abstract

We provide semiconductor packages with improved reliability. [Solution] The semiconductor package of the present invention comprises a base substrate, a base chip including an upper connection terminal disposed on the upper part of the base substrate, a semiconductor chip stack including a plurality of semiconductor chips having through vias electrically connecting the lower pad and the upper pad, a dummy chip on the semiconductor chip stack, and a plurality of adhesive layers including a first adhesive layer on the uppermost semiconductor chip and a second adhesive layer on the first adhesive layer, wherein the plurality of semiconductor chips include the lowest semiconductor chip and the uppermost semiconductor chip, and the lower pad of the lowest semiconductor chip is in contact with the upper connection terminal.

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] Semiconductor devices mounted on electronic devices are required to be miniaturized, have higher performance, and larger capacity. To achieve this, semiconductor packages have been developed that connect semiconductor chips stacked vertically using through electrodes (for example, Through Silicon Via).

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package with improved reliability.

Means for Solving the Problems

[0004] A semiconductor package according to one aspect of the present invention made to achieve the above objective comprises: a base chip including opposite lower and upper connection terminals and through electrodes electrically connecting the lower and upper connection terminals; a semiconductor chip stack including a plurality of semiconductor chips sequentially stacked in a first direction on the base chip; a plurality of connecting bumps disposed below the base chip and electrically connected to the lower connection terminals; a dummy chip on the semiconductor chip stack; and a plurality of adhesive layers between the semiconductor chip stack and the dummy chip, wherein the plurality of semiconductor chips of the semiconductor chip stack include a first semiconductor chip disposed on the base chip and including opposite first lower pads and first upper pads, and a first through via electrically connecting the first lower pad and the first upper pad; and the first semiconductor chip The semiconductor chip includes at least one second semiconductor chip positioned on top of the first semiconductor chip and including a second lower pad and a second upper pad opposite to each other, and a second through-via electrically connecting the second lower pad and the second upper pad; and a third semiconductor chip positioned on the at least one second semiconductor chip and including a front pad positioned on the front, wherein the first lower pad of the first semiconductor chip contacts the upper connection terminal of the base chip adjacent in the first direction; the first upper pad of the first semiconductor chip contacts the second lower pad of the at least one second semiconductor chip adjacent in the first direction; and the front pad of the third semiconductor chip contacts the second upper pad of the at least one second semiconductor chip adjacent in the first direction; and the plurality of adhesive layers include a first adhesive layer on the semiconductor chip stack and a second adhesive layer on the first adhesive layer.

[0005] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising: a base chip; a semiconductor chip stack including a plurality of semiconductor chips sequentially stacked in a first direction on the base chip; a dummy chip on the semiconductor chip stack; an adhesive layer between the semiconductor chip stack and the dummy chip; and a sealing material covering the sides of the semiconductor chip stack, the dummy chip, and the adhesive layer on the base chip, wherein the adhesive layer includes an extension portion extending in a second direction perpendicular to the first direction between the semiconductor chip stack and the dummy chip, and a plurality of fillet portions connected to the extension portion and extending into the sealing material, the plurality of fillet portions including a first fillet portion extending into the sealing material from the lower region of the extension portion and a second fillet portion extending into the sealing material from the upper region of the extension portion.

[0006] A semiconductor package according to one embodiment comprises a base substrate, a base chip including an upper connection terminal disposed on the upper part of the base substrate, a semiconductor chip stack including a plurality of semiconductor chips having through vias electrically connecting the lower pad and the upper pad, a dummy chip on the semiconductor chip stack, and a plurality of adhesive layers including a first adhesive layer on the uppermost semiconductor chip and a second adhesive layer on the first adhesive layer, wherein the plurality of semiconductor chips include the lowest semiconductor chip and the uppermost semiconductor chip, and the lower pad of the lowest semiconductor chip contacts the upper connection terminal. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor package with improved reliability and a method for manufacturing the same.

[0008] Specifically, according to the present invention, by arranging multiple adhesive layers between the semiconductor chip stack and the dummy chip, the bonding strength between the base chip and the encapsulating material is improved, thereby providing a semiconductor package with enhanced reliability.

[0009] The diverse yet significant advantages and effects of the present invention are not limited to those described above and will be more readily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view showing an example of a semiconductor package according to one embodiment. [Figure 2a] This is a cross-sectional view of an example of a semiconductor package, showing the cross-section along the line I-I' in Figure 1. [Figure 2b] This is a magnified view of area "A" in Figure 2a. [Figure 2c] This is a magnified view of area "B" in Figure 2a. [Figure 3a] This is an enlarged view of a part of the first modified example of a semiconductor package according to one embodiment, and is a partial enlarged view showing area "B" in Figure 2a. [Figure 3b] This is an enlarged view of a part of a second modified example of a semiconductor package according to one embodiment, and is a partial enlarged view showing area "B" in Figure 2a. [Figure 3c] This is an enlarged view of a part of a third modified example of a semiconductor package according to one embodiment, and is a partial enlarged view showing area "B" in Figure 2a. [Figure 3d] This is an enlarged view of a part of a fourth modified example of a semiconductor package according to one embodiment, and is a partial enlarged view showing area "B" in Figure 2a. [Figure 4] This is a cross-sectional view of another example of a semiconductor package, showing the cross-section along the line I-I' in Figure 1. [Figure 5] This is a plan view showing another example of a semiconductor package according to one embodiment. [Figure 6a] Figure 5 shows a cross-sectional view of a semiconductor package along the line I-I'. [Figure 6b] This is a magnified view of area "C" in Figure 6a. [Figure 7] This is a partially enlarged view of a modified semiconductor package according to one embodiment, and is a partially enlarged view showing region "C" in Figure 6a. [Figure 8a] It is a plan view showing an example of a semiconductor package according to an embodiment. [Figure 8b] It is a cross-sectional view of a semiconductor package showing a cross-section along the line II-II' in FIG. 8a. [Figure 9] It is a cross-sectional view shown according to the process procedure for explaining a manufacturing method of an example of a semiconductor package according to an embodiment. [Figure 10] It is a cross-sectional view shown according to the process procedure for explaining a manufacturing method of an example of a semiconductor package according to an embodiment. [Figure 11] It is a cross-sectional view shown according to the process procedure for explaining a manufacturing method of an example of a semiconductor package according to an embodiment. [Figure 12] It is a cross-sectional view shown according to the process procedure for explaining a manufacturing method of an example of a semiconductor package according to an embodiment. [Figure 13] It is a cross-sectional view shown according to the process procedure for explaining a manufacturing method of another example of a semiconductor package according to an embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0011] In the following, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface", "upper end", "lower end", etc. are denoted by reference numerals in the drawings, and are understood to be referred to based on the drawings unless otherwise specified. Terms such as "upper part", "middle", and "lower part" are replaced with other terms, for example, terms such as "first", "second", and "third", and are used to describe the components of the specification. Terms such as "first", "second", and "third" are used to describe various components, but the above components are not limited by the above terms, and the "first component" can be named the "second component".

[0012] Hereinafter, specific examples of the embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0013] FIG. 1 is a plan view showing an example of a semiconductor package according to an embodiment, FIG. 2a is a cross-sectional view of an example of the semiconductor package showing a cross-section along line I-I' of FIG. 1, FIG. 2b is a partial enlarged view showing region "A" of FIG. 2a, and FIG. 2c is a partial enlarged view showing region "B" of FIG. 2a.

[0014] Referring to FIGS. 1 to 2c, the semiconductor package 10 of the present embodiment includes a semiconductor chip stack CS on a base chip BC, a dummy chip DC on the semiconductor chip stack CS, and a plurality of adhesive layers 400 between the semiconductor chip stack CS and the dummy chip DC. The semiconductor chip stack CS includes a plurality of semiconductor chips (C1, C2, C3) sequentially stacked on the base chip BC. According to an embodiment, the semiconductor package 10 further includes a sealing material ML and / or a plurality of connection bumps BP.

[0015] The plurality of semiconductor chips (C1, C2, C3) are composed of memory chips or memory elements that store and output data based on address commands and control commands received from the base chip BC. For example, the plurality of semiconductor chips (C1, C2, C3) include volatile memory elements such as DRAM and SRAM, and non-volatile memory elements such as PRAM, MRAM, FeRAM, or ReRAM. The uppermost third semiconductor chip C3 (hereinafter, "the third semiconductor chip") of the plurality of semiconductor chips does not include through electrodes, but is not limited thereto. The uppermost semiconductor chip (C3' in FIG. 4) of the plurality of semiconductor chips includes, for example, through electrodes (see FIG. 4).

[0016] The plurality of semiconductor chips (C1, C2, C3) include a first semiconductor chip C1, at least one second semiconductor chip C2, and a third semiconductor chip C3 sequentially stacked in a first direction (e.g., the Z direction) on the base chip BC.

[0017] The base chip BC includes a substrate SB, opposite lower connectors LT and upper connectors UT, an element layer CL, and through-vias TV electrically connecting the lower connector LT and the upper connector UT. The base chip BC further includes an upper protective layer DL surrounding the upper connector UT. The upper surface DL_US of the upper protective layer DL is coplane with the upper surface of the upper connector UT.

[0018] The base chip BC is a buffer chip that includes, for example, a large number of logic elements and / or memory elements in the element layer CL. Therefore, the base chip BC transmits signals from multiple semiconductor chips (C1, C2, C3) stacked on top of it to the outside, and also transmits external signals and power to the multiple semiconductor chips (C1, C2, C3). The base chip BC performs logic and memory functions together via logic elements and memory elements, but depending on the embodiment, the base chip BC may also include only logic elements and perform only logic functions.

[0019] The substrate SB contains semiconductor elements such as silicon or germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate SB has a Silicon On Insulator (SOI) structure. The substrate SB includes conductive regions, such as impurity-doped wells or impurity-doped structures. The substrate SB includes various device isolation structures, such as Shallow Trench Isolation (STI) structures.

[0020] The upper connector terminal UT is located on the upper surface of the substrate SB (or on the top of the base chip BC). The upper connector terminal UT contains a conductive material. For example, the upper connector terminal UT contains copper (Cu). The lower connector terminal LT is located on the lower surface of the element layer CL (or on the bottom of the base chip BC). The lower connector terminal LT contains, but is not limited to, the same material as the upper connector terminal UT. For example, the lower connector terminal LT contains at least one of aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0021] The upper protective layer DL is formed on the upper surface of the substrate SB to protect the substrate SB. The upper protective layer DL is formed of an insulating layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but the material of the upper protective layer DL is not limited to the above substances. For example, the upper protective layer DL is formed of a polymer such as PI (Polyimide) or PSPI (Photosensitive polyimide). Although not shown in the figures, a lower protective layer may be further formed on the lower surface of the device layer CL.

[0022] The element layer CL is located on the underside of the substrate SB and contains various types of elements. For example, the element layer CL includes FETs such as planar FETs (Field Effect Transistors) and FinFETs, memory elements such as flash memory, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and ReRAM (Resistive Random Access Memory), logic elements such as AND, OR, and NOT, and various active and / or passive elements such as system LSIs (Large Scale Integration), CIS (CMOS Imaging Sensor), and MEMS (Micro-Electro-Mechanical System).

[0023] The element layer CL includes an interlayer insulating layer (not shown) and a multilayer wiring layer (not shown) on the elements described above. The interlayer insulating layer (not shown) contains silicon oxide or silicon nitride. The multilayer wiring layer (not shown) contains multilayer wiring and / or vertical contacts. The multilayer wiring layer (not shown) connects the elements of the element layer CL to each other, connects the elements to the conductive region of the substrate SB, and connects the elements to the lower connection terminal LT.

[0024] A through-via TV penetrates the substrate SB vertically (Z-direction) and provides an electrical path connecting the lower connection terminal LT and the upper connection terminal UT. The through-via TV is electrically connected to multiple semiconductor chips (C1, C2, C3). The through-via TV includes a conductive plug and a barrier film surrounding it. The conductive plug includes a metallic material, such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The conductive plug is formed by a plating process, PVD process, or CVD process. The barrier film includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and is formed by a plating process, PVD process, or CVD process. A side insulating film (not shown) containing an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP (High Aspect Ratio Process) oxide) is formed between the side of the through-via TV and the substrate SB.

[0025] A connecting bump BP is positioned beneath the base chip BC. The connecting bump BP is electrically connected to multiple semiconductor chips (C1, C2, C3) via through-vias TV. The connecting bump BP includes, for example, tin (Sn) or an alloy containing tin (e.g., Sn-Ag-Cu). Depending on the embodiment, the connecting bump BP may also have a configuration in which a metal pillar and a solder ball are combined. The connecting bump BP is electrically connected to an external device such as a module substrate or system board. The base chip BC has a width greater than the width of each of the multiple semiconductor chips (C1, C2, C3) in the horizontal direction (e.g., X and / or Y direction). Although not shown, at least a portion of the connecting bump BP and at least a portion of the lower connection terminal LT may be positioned so as not to overlap the multiple semiconductor chips (C1, C2, C3) in the vertical direction (Z direction).

[0026] The first semiconductor chip C1 is disposed on a base chip BC and includes a first substrate 110, a first circuit layer 120, a first lower pad LP1 and a first upper pad UP1 opposite to each other, and a first through-electrode TSV1 that electrically connects the first lower pad LP1 and the first upper pad UP1. In some embodiments, the first semiconductor chip C1 further includes a first lower insulating layer LI1 surrounding the first lower pad LP1 and a first upper insulating layer UI1 surrounding the first upper pad UP1.

[0027] The first substrate 110 contains semiconductor elements such as silicon or germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first substrate 110 has a Silicon On Insulator (SOI) structure. The first substrate 110 includes conductive regions, such as impurity-doped wells or impurity-doped structures. The first substrate 110 includes various element isolation structures, such as Shallow Trench Isolation (STI) structures. In one embodiment, the first substrate 110 is referred to as the first semiconductor substrate.

[0028] The first upper pad UP1 is located on the upper surface of the first substrate 110 (or on the upper part of the first semiconductor chip C1). The first upper pad UP1 contains a conductive material. For example, the first upper pad UP1 contains copper (Cu). The first lower pad LP1 is located on the lower surface of the first lower insulating layer LI1 (or on the lower part of the first semiconductor chip C1). The first lower pad LP1 contains the same or a similar material as the first upper pad UP1.

[0029] The first upper insulating layer UI1 is formed on the upper surface of the first substrate 110 to protect the first substrate 110. The first upper insulating layer UI1 surrounds the sides of the first upper pad UP1. The first upper insulating layer UI1 is formed of an insulating layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but the material of the first upper insulating layer UI1 is not limited to the above substances. For example, the first upper insulating layer UI1 is formed of a polymer such as PI (Polyimide) or PSPI (Photosensitive polyimide).

[0030] The first lower insulating layer LI1 is formed on the lower surface of the first substrate 110 to protect the element layer 120. The first lower insulating layer LI1 surrounds the sides of the first lower pad LP1. The first lower insulating layer LI1 includes, for example, silicon oxide (SiO) or silicon carbonitride (SiCN).

[0031] A first circuit layer 120 is formed between the first substrate 110 and the first lower insulating layer LI1. The first circuit layer 120 is substantially the same as or similar to the second circuit layer 220, which will be described with reference to Figure 2b.

[0032] The first through-electrode TSV1 penetrates the first substrate 110 vertically (Z direction) and provides an electrical path connecting the first lower pad LP1 and the first upper pad UP1. The first through-electrode TSV1 includes a via plug 145 and a side barrier layer 141 surrounding its side. The via plug 145 includes, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu) and is formed by a plating process, PVD process, or CVD process. The side barrier layer 141 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and is formed by a plating process, PVD process, or CVD process. Between the side barrier layer 141 and the first substrate 110, a side insulating film 143 is formed, which includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP oxide).

[0033] The first through-electrode TSV1 penetrates an insulating protective layer 113 formed on the rear (upper) surface of the first substrate 110. The insulating protective layer 113 includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 114, such as an abrasion-blocking layer or barrier, is placed on the insulating protective layer 113. For example, the buffer film includes silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride (see Figure 2b).

[0034] The first semiconductor chip C1 and the base chip BC are joined and bonded to each other by bonding between metals and bonding between dielectrics.

[0035] For example, each of the first lower pads LP1 of the first semiconductor chip C1 and each of the upper connection terminals UT of the base chip BC are in contact with each other. The first lower insulating layer LI1 of the first semiconductor chip C1 and the upper protective layer DL of the base chip BC are in contact with each other.

[0036] At least one second semiconductor chip C2 is placed on the first semiconductor chip C1. The at least one second semiconductor chip C2 includes a plurality of second semiconductor chips that are sequentially stacked on the first semiconductor chip C1 in a first direction (e.g., the Z direction). The plurality of second semiconductor chips C2 include the bottommost second semiconductor chip (hereinafter referred to as the 2-1 semiconductor chip C2_1) and the topmost second semiconductor chip (hereinafter referred to as the 2-2 semiconductor chip C2_2).

[0037] Each of the plurality of second semiconductor chips C2 includes a second substrate 210, a second circuit layer 220, a second lower pad LP2 and a second upper pad UP2 opposite to each other, and a second through-electrode TSV2 that electrically connects the second lower pad LP2 and the second upper pad UP2. In some embodiments, each of the plurality of second semiconductor chips C2 further includes a second lower insulating layer UI2 surrounding the second lower pad LP2 and a second upper insulating layer UI2 surrounding the second upper pad UP2. In some embodiments, each of the plurality of second semiconductor chips C2 further includes an insulating protective layer 213.

[0038] The second substrate 210 is substantially the same as or similar to the first substrate 110. In one embodiment, the second substrate 210 is referred to as the second semiconductor substrate.

[0039] The second upper pad UP2 is located on the upper surface of the second substrate 210 (or on the upper surface of each of the multiple second semiconductor chips C2). The second upper pad UP2 contains a conductive material, such as copper (Cu). The second lower pad LP2 is located on the lower surface of the second lower insulating layer LI2 (or on the lower surface of each of the multiple second semiconductor chips C2). The second lower pad LP2 contains the same or a similar material as the second upper pad UP2.

[0040] The second upper insulating layer UI2 is formed on the upper surface of the second substrate 210 to protect the second substrate 210. The second upper insulating layer UI2 surrounds the sides of the second upper pad UP2. The second upper insulating layer UI2 is formed of an insulating layer such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but the material of the second upper insulating layer UI2 is not limited to the above substances. For example, the second upper insulating layer UI2 is formed of a polymer such as PI (Polyimide) or PSPI (Photosensitive polyimide).

[0041] The insulating protective layer 213 and the second lower insulating layer LI2 are formed on the lower part of the second substrate 210 to protect the element layer 220. The insulating protective layer 213 is located on the lower surface of the second substrate 210, surrounding the side of the lowest wiring structure of the wiring structure 225 and covering a portion of the lower surface of the lowest wiring structure. The insulating protective layer 213 is in contact with the side of the second lower pad LP2. The insulating protective layer 213 contains an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The second lower insulating layer LI2 surrounds the side of the second lower pad LP2. The second lower insulating layer LI2 contains, for example, silicon oxide (SiO) or silicon carbonitride (SiCN).

[0042] The second circuit layer 220 is located on the front (bottom) surface of the second substrate 210, on which the conductive region 212 is formed. The conductive region 212 includes, for example, impurity-doped wells or impurity-doped structures. The second substrate 210 further includes isolation regions 211. The isolation regions 211 are element isolation structures having an STI (shallow trench isolation) structure and contain silicon oxide. The second circuit layer 220 includes individual element IDs, an interlayer insulating layer 221, and a wiring structure 225.

[0043] The individual element IDs are arranged on the front surface of the second substrate 210. The individual element IDs include, for example, FETs such as planar FETs and FinFETs, memory elements such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and ReRAM, logic elements such as AND, OR, and NOT, and various active and / or passive elements such as system LSIs, CIS, and MEMS.

[0044] The interlayer insulating layer 221 is formed to cover the individual element ID and the wiring structure 225, electrically isolating the individual element ID placed on the second substrate 210. The interlayer insulating layer 221 includes FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilaca Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer 221 surrounding the wiring structure 225 is composed of a low dielectric layer. The interlayer insulating layer 221 is formed using chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process. Depending on the process, the boundary between the interlayer insulating layer 221 and the second lower insulating layer LI2 may not be clearly defined.

[0045] The wiring structure 225 is formed as a multilayer structure including multiple wiring patterns and multiple vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or combinations thereof. A barrier film (not shown) containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be placed between the wiring patterns and / or vias and the interlayer insulating layer 221. The wiring structure 225 is electrically connected to the conductive region 212 and / or individual element ID by interconnecting parts 223 (e.g., contact plugs).

[0046] The second through-electrode TSV2 penetrates the second substrate 210 vertically (Z direction) and provides an electrical path connecting the second lower pad LP2 and the second upper pad UP2. The second through-electrode TSV2 includes a via plug 245 and a side barrier layer 241 surrounding its side. The via plug 245 includes, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu) and is formed by a plating process, PVD process, or CVD process. The side barrier layer 241 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and is formed by a plating process, PVD process, or CVD process. Between the side barrier layer 241 and the second substrate 210, a side insulating film 243 is formed, which includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP oxide).

[0047] The bottommost semiconductor chip C2_1 and the first semiconductor chip C1 are joined and bonded to each other by bonding between metals and bonding between dielectrics.

[0048] For example, each of the second lower pads LP2 of the second-first semiconductor chip C2_1 and each of the first upper pads UP1 of the first semiconductor chip C1 are in contact with each other. The second lower insulating layer LI2 of the second-first semiconductor chip C2_1 and the first upper insulating layer UI1 of the first semiconductor chip C1 are in contact with each other.

[0049] Among multiple second semiconductor chips C2, adjacent second semiconductor chips in a first direction (e.g., Z direction) are joined and bonded to each other by bonding between metals and bonding between dielectrics. The second upper pad UP2 of each of the multiple second semiconductor chips C2 contacts the second lower pad LP2 of each of the multiple second semiconductor chips C2 adjacent in the first direction. The second insulating layer (LI2, UI2) of each of the multiple second semiconductor chips C2 contacts the second insulating layer (LI2, UI2) of each of the multiple second semiconductor chips C2 adjacent in the first direction.

[0050] The third semiconductor chip C3 is placed on the second-second semiconductor chip C2_2 and includes a third substrate 310, a third circuit layer 320, a third lower insulating layer LI3, and a front pad LP3 located on the front (bottom) side. The third substrate 301, the third circuit layer 320, and the front pad LP3 have the same or similar characteristics as the corresponding elements of the base chip BC described above, the first substrate 110, the first circuit layer CL, and the lower connection terminal LT, so redundant explanations are omitted.

[0051] Each of the front pads LP3 of the third semiconductor chip 300 contacts each of the second lower pads LP2 of the adjacent second-2 semiconductor chip C2 in the first direction. The third lower insulating layer LI3 of the third semiconductor chip 300 contacts the second upper insulating layer LI2 of the adjacent second-2 semiconductor chip C2 in the first direction.

[0052] The dummy chip DC is placed on the third semiconductor chip C3. The dummy chip DC is a dummy configuration placed on the semiconductor chip stack CS when the height of the semiconductor chip stack CS is smaller than the height of the target semiconductor package. From another point of view, the dummy chip DC is electrically isolated from the semiconductor chip stack CS.

[0053] The side DC_S of the dummy chip DC aligns with the side CS_S of the semiconductor chip stack CS. For example, the side DC_S of the dummy chip DC aligns with the side C3_S of the third semiconductor chip C3. From another perspective, the horizontal width (e.g., X and / or Y direction) of the dummy chip DC is substantially the same as the horizontal width of each of the multiple semiconductor chips (C1, C2, C3). The rear (top) surface of the dummy chip DC is exposed and not covered by the encapsulant ML. The rear surface of the dummy chip DC is substantially coplane with the top surface of the encapsulant ML.

[0054] Multiple adhesive layers 400 are placed between the semiconductor chip stack CS and the dummy chip DC. From another perspective, the dummy chip DC is fixed by the multiple adhesive layers 400 without directly contacting the uppermost semiconductor chip (e.g., the third semiconductor C3).

[0055] The multiple adhesive layers 400 include first and second adhesive layers (401, 402). The first adhesive layer 401 is provided bonded to the rear surface (top) of the third semiconductor chip C3 ("C3_BS" in Figure 11). The second adhesive layer 402 is provided bonded to the front surface (bottom) of the dummy chip DC ("DC_FS" in Figure 12). In one embodiment, each of the multiple adhesive layers 400 is, but is not limited to, an NCF (Non-Conductive Film). The multiple adhesive layers 400 can include any type of polymer film that can be subjected to a thermocompression bonding process.

[0056] Each side of the first and second adhesive layers (401, 402) aligns with the respective sides of the semiconductor chip stack CS and the dummy chip DC. For example, the side of the first adhesive layer 401 aligns with the side C3_S of the third semiconductor chip C3 (or the side CS_S of the semiconductor chip stack CS), and the side of the second adhesive layer 402 aligns with the side DC_S of the dummy chip DC. From another point of view, the first and second adhesive layers (401, 402) have the same width relative to each other in the horizontal direction (e.g., X and / or Y direction). From yet another point of view, the first and second adhesive layers (401, 402) do not contain any protrusions (or fillet portions) extending into the encapsulant ML.

[0057] By placing multiple adhesive layers 400 between the semiconductor chip stack CS and the dummy chip DC, the residue detaching from the multiple adhesive layers 400 can be minimized or prevented. The residue refers to impurities (e.g., fumes) resulting from a predetermined thermocompression bonding process to strengthen the adhesion of the multiple adhesive layers 400.

[0058] For example, compared to directly placing the adhesive layer formed on the front surface of the dummy chip DC onto the rear surface of the third semiconductor chip C3, by placing the second adhesive layer 402 formed on the front surface of the dummy chip DC onto the first adhesive layer 401 formed on the rear surface of the third semiconductor chip C3, the adhesive force of the first and second adhesive layers (401, 402) can be sufficiently activated even by a thermocompression bonding process under relatively low pressure and low temperature conditions.

[0059] This minimizes or prevents the unnecessary formation of residue on the upper surface BC_US of the base chip BC, and therefore minimizes or prevents a decrease in the bonding strength between the base chip BC and the sealing material ML.

[0060] The encapsulant ML encapsulates the semiconductor chip stack CS on the base chip BC. The encapsulant ML is formed to expose the rear surface of the dummy chip DC. In some embodiments, the encapsulant ML may be formed to cover the rear surface of the dummy chip DC. The encapsulant ML is formed of an insulating material such as EMC (Epoxy Mold Compound), but the material of the encapsulant ML is not particularly limited. The encapsulant ML surrounds the sides CS_S of the multiple semiconductor chips (C1, C2, C3), the sides of the multiple adhesive layers 400, and the side DC_S of the dummy chip DC. In some embodiments, a heat dissipation structure (not shown) can be placed on top of the encapsulant ML. The heat dissipation structure (not shown) controls the warpage of the semiconductor package 10 and releases heat generated by the multiple semiconductor chips (C1, C2, C3) to the outside.

[0061] Figures 3a to 3d are enlarged views of parts of the first to fourth modified examples of a semiconductor package according to one embodiment. Figures 3a to 3d are enlarged views of a portion of area "B" in Figure 2a.

[0062] Referring to Figures 3a to 3c, the configuration is the same as or similar to that described with reference to Figures 1 to 2c, except that a portion of at least one of the multiple adhesive layers 400 extends into the sealant ML.

[0063] Referring to Figure 3a, the semiconductor package 10a is the same as or similar to that described with reference to Figures 1 to 2c, except that it includes first and second adhesive layers (401, 402) each having protrusions (401p, 402p).

[0064] The first adhesive layer 401 includes a first extension 401e extending onto the rear surface of the third semiconductor chip C3, and a first protrusion 401p protruding beyond the side surface C3_S of the third semiconductor chip C3. The first protrusion 401p is connected to the first extension 401e and is a fillet portion extending into the encapsulant ML. In this case, the first protrusion 401p is referred to as the first fillet portion.

[0065] The second adhesive layer 402 includes a second extension 402e extending over the front surface of the dummy chip DC, and a second projection 402p protruding beyond the side surface DC_S of the dummy chip DC. The second projection 402p is connected to the second extension 402e and is a fillet portion extending into the sealant ML. In this case, the second projection 402p is referred to as the second fillet portion.

[0066] The upper surface of the first extension 401e and the lower surface of the second extension 402e are in contact. A boundary region BR is defined between the first projection 401p and the second projection 402p. The boundary region BR is a concave region between the respective ends of the first and second projections (401p, 402p). From another viewpoint, the boundary region BR is a groove or recessed portion between the ends.

[0067] Referring to Figure 3b, the semiconductor package 10b is the same as or similar to that described with reference to Figures 1 to 3a, except that it includes first and second adhesive layers (401, 402) each having protrusions (401p, 402p).

[0068] The first adhesive layer 401 includes a first extension 401e extending onto the rear surface of the third semiconductor chip C3, and a first protrusion 401p protruding beyond the side surface C3_S of the third semiconductor chip C3. The first protrusion 401p is connected to the first extension 401e and is a fillet portion extending into the encapsulant ML. In this case, the first protrusion 401p is referred to as the first fillet portion.

[0069] The second adhesive layer 402 includes a second extension 402e extending over the front surface of the dummy chip DC, and a second projection 402p protruding beyond the side surface DC_S of the dummy chip DC. The second projection 402p is connected to the second extension 402e and is a fillet portion extending into the sealant ML. In this case, the second projection 402p is referred to as the second fillet portion.

[0070] The upper surface of the first extension 401e and the lower surface of the second extension 402e are in contact.

[0071] A boundary region BR is defined between the first projection 401p and the second projection 402p. The boundary region BR is a concave region between the respective ends of the first and second projections (401p, 402p). From another viewpoint, the boundary region BR is a stepped portion between the ends.

[0072] In this embodiment, at least a portion of the first protrusion 401p extends toward the upper surface of the base chip BC (BC_US in Figure 2a) and contacts the side surface C3_S of the third semiconductor chip C3. At least a portion of the second protrusion 402p extends away from the upper surface of the base chip BC (BC_US in Figure 2a) (e.g., in the Z direction) and contacts the side surface DC_S of the dummy chip DC. The area of ​​contact between the first protrusion 401p and the side surface C3_S is greater than the area of ​​contact between the second protrusion 402p and the side surface DC_S. The upper portion of the first protrusion 401p and the lower portion of the second protrusion 402p are in contact.

[0073] In this embodiment, the maximum horizontal width (e.g., X and / or Y direction) of the first protrusion 401p is greater than the maximum horizontal width of the second protrusion 402p.

[0074] Referring to Figure 3c, the semiconductor package 10c is the same as or similar to that described with reference to Figures 1 to 3b, except that it includes a first adhesive layer 401 having a width smaller than the width of the third semiconductor chip C3.

[0075] The first adhesive layer 401 extends over the rear surface of the third semiconductor chip C3 and has a width smaller than the width of the third semiconductor chip C3. The edges of the first adhesive layer 401 have a rounded shape. For example, the thickness of the first adhesive layer 401 in the vertical direction (e.g., Z direction) decreases towards the edges. In this embodiment, the first adhesive layer 401 is referred to as the first portion.

[0076] The second adhesive layer 402 includes a second extension 402e extending over the front surface of the dummy chip DC, and a second protrusion 402p that protrudes beyond the side surface C3_S of the third semiconductor chip C3 and the side surface DC_S of the dummy chip DC.

[0077] The second extension 402e includes a second-first portion 402e_1 that covers the upper part of the first adhesive layer 401, and a second-second portion 402e_2 that is connected to the second-first portion 402e_1 and covers the side of the first adhesive layer 401.

[0078] The second protrusion 402p is connected to the second-second portion 402e_2 and is a fillet portion that extends into the sealing material ML. The second protrusion 402p contacts the side surface C3_S of the third semiconductor chip C3 and the side surface DC_S of the dummy chip DC.

[0079] According to the present invention, by arranging multiple adhesive layers 400 between the semiconductor chip stack CS and the dummy chip DC, relatively small protrusions (e.g., 401p, 402p) are formed compared to the arrangement of a single adhesive layer. Here, size refers to the width, thickness, and / or volume of the protrusions. This minimizes or prevents the unnecessary formation of residue detached from the adhesive layer on the upper surface BC_US of the base chip BC, thereby minimizing or preventing a decrease in the bonding strength between the base chip BC and the encapsulant ML.

[0080] Referring to Figure 3d, the semiconductor package 10d is the same as or similar to that described with reference to Figures 1 to 3c, except that it includes a plurality of adhesive layers 400, further comprising a third adhesive layer 403 between the first and second adhesive layers (401, 402).

[0081] The third adhesive layer 403 is provided bonded together with the first adhesive layer 401 to the rear surface of the third semiconductor chip C3, but is not limited thereto. For example, the third adhesive layer 403 may be provided bonded together with the second adhesive layer 402 to the front surface of the dummy chip DC.

[0082] Figure 4 is a cross-sectional view of another example of a semiconductor package, showing a cross-section along the line I-I' in Figure 1.

[0083] Referring to Figure 4, the third semiconductor chip C3' of the semiconductor package 10e is the same as or similar to that described with reference to Figures 1 to 3d, except that it includes a third through-electrode TSV3.

[0084] The third semiconductor chip C3' is positioned on the uppermost second semiconductor chip C2_2 and includes a third substrate 310, a third circuit layer 320, a third lower pad LP3 and a third upper pad UP3 opposite to each other, and a third through-electrode TSV3 that electrically connects the third lower pad LP3 and the third upper pad UP3. The third semiconductor chip C3' further includes a third lower insulating layer LI3 surrounding the third lower pad LP3 and a third upper insulating layer UI3 surrounding the third upper pad UP3. The third substrate 310, third circuit layer 320, third lower and upper pads (LP3, UP3), third through-electrode TSV3, and third lower and upper insulating layers (LI3, UI3) of the third semiconductor chip C3' in this embodiment are substantially the same as the second substrate 210, second circuit layer 220, second lower and upper pads (LP2, UP2), second through-electrode TSV2, and second lower and upper insulating layers (LI2, UI2) of the second-2 semiconductor chip C2_1 described with reference to Figure 2a. Therefore, a detailed explanation is omitted.

[0085] The third semiconductor chip C3' and the uppermost second-second semiconductor chip C2_2 are joined and bonded to each other by bonding between metals and bonding between dielectrics.

[0086] For example, each of the third lower pads LP3 of the third semiconductor chip C3' and each of the third upper pads UP3 of the second-second semiconductor chip C2_2 are in contact with each other. The third lower insulating layer LI3 of the third semiconductor chip C3' and the second upper insulating layers LI2 and UI2 of the second-second semiconductor chip C2_2 are in contact with each other.

[0087] In this embodiment, the first adhesive layer 401 covers the third upper pad UP3 and the third upper insulating layer UI3.

[0088] Figure 5 is a plan view showing another example of a semiconductor package according to one embodiment, Figure 6a is a cross-sectional view of the semiconductor package showing a cross-section along the line I-I' in Figure 5, and Figure 6b is a partially enlarged view showing region "C" in Figure 6a.

[0089] Referring to Figures 5 to 6b, the semiconductor package 10f is the same as or similar to that described with reference to Figures 1 to 4, except that the horizontal width (e.g., X and / or Y direction) W1 of the dummy chip DC is greater than the horizontal width W2 of the semiconductor chip stack CS. From another point of view, unlike the semiconductor package 10 described with reference to Figures 1 to 2c, in the semiconductor package 10f, the side DC_S of the dummy chip DC is not aligned with the side C3_S of the third semiconductor chip C3.

[0090] The horizontal width W1 of the dummy chip DC is greater than the horizontal width W2 of the semiconductor chip stack CS (or the width of the third semiconductor chip C3). From another point of view, the horizontal width of the second adhesive layer 402 is greater than the horizontal width of the first adhesive layer 401. As a result, the encapsulant ML covers at least a portion of the lower surface of the second adhesive layer 402.

[0091] Figure 7 is a partially enlarged view of a modified semiconductor package according to one embodiment. Figure 7 is a partially enlarged view showing region "C" in Figure 6a.

[0092] Referring to Figure 7, the semiconductor package 10g is the same as or similar to that described with reference to Figures 1 to 6b, except that it includes first and second adhesive layers (401, 402) each having protrusions (401p, 402p).

[0093] The first adhesive layer 401 includes a first extension 401e extending onto the rear surface of the third semiconductor chip C3, and a first protrusion 401p protruding beyond the side surface C3_S of the third semiconductor chip C3. The first protrusion 401p is connected to the first extension 401e and is a fillet portion extending into the encapsulant ML. In this case, the first protrusion 401p is referred to as the first fillet portion.

[0094] The second adhesive layer 402 includes a second extension 402e extending over the front surface of the dummy chip DC, and a second projection 402p protruding from the second extension 402e.

[0095] The second projection 402p includes a second-first projection 402pa that protrudes from the lower surface of the second extension 402e and contacts the first projection 401p. This defines a boundary region BR between the first projection 401p and the second-first projection 402pa.

[0096] The second projection 402p further includes a second-second projection 402pb extending into the sealing material ML from the end of the second extension 402e. The second-second projection 402pb is defined as including a first portion 402pb1 projecting from the lower surface of the end of the second extension 402e toward the upper surface of the base chip BC (BC_US in Figure 6a), and a second portion 402bp2 projecting from the side surface of the end of the second extension 402e and contacting the side surface DC_S of the dummy chip DC. The second-second projection 402pb of the second projection 402p is referred to as the second fillet portion.

[0097] Although not shown in the figures, the second projection 402p may further include a plurality of projections other than the second-first and second-second projections (402pa, 402pb).

[0098] Figure 8a is a plan view showing an example of a semiconductor package according to one embodiment, and Figure 8b is a cross-sectional view of the semiconductor package showing a cross-section along the line II-II' in Figure 8a.

[0099] Referring to Figures 8a and 8b, the semiconductor package 10h includes a package substrate 900, an interposer substrate 700, at least one chip structure PS, and a processor chip 800. The chip structure PS has the same or similar features as the semiconductor packages (10, 10a, 10b, 10c, 10d, 10e, 10f, 10g) described with reference to Figures 1-7.

[0100] The package substrate 900 is a support substrate on which the interposer substrate 700, processor chip 800, and chip structure PS are mounted, and is a semiconductor package substrate including printed circuit boards (PCBs), ceramic substrates, glass substrates, tape wiring substrates, etc. The main body of the package substrate 900 contains other materials depending on the type of substrate. For example, if the package substrate 900 is a printed circuit board, it is in the form of a main body copper foil laminate or a copper foil laminate with wiring layers further laminated on the cross section or both sides.

[0101] The package substrate 900 includes a lower terminal 912, an upper terminal 911, and a rewiring circuit 913. The upper terminal 911, the lower terminal 912, and the rewiring circuit 913 form an electrical path connecting the lower and upper surfaces of the package substrate 900. The upper terminal 911, the lower terminal 912, and the rewiring circuit 913 include a metallic material, such as an alloy containing at least one metal or two or more metals from among copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). An external connection terminal 920 connected to the lower terminal 912 is located on the lower surface of the package substrate 900. The external connecting terminal 920 includes tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof.

[0102] The interposer substrate 700 includes a substrate 701, a lower protective layer 703, a lower pad 705, an interconnecting structure 710, metal bumps 720, and through vias 730. The chip structure PS and the processor chip 800 are electrically connected to each other via the interposer substrate 700.

[0103] The substrate 701 is formed from one of the following materials: silicon, organic material, plastic, and glass. When the substrate 701 is a silicon substrate, the interposer substrate 700 is referred to as a silicon interposer. When the substrate 701 is an organic material substrate, as is not shown in the figures, the interposer substrate 700 is referred to as a panel interposer.

[0104] A lower protective layer 703 is placed on the underside of the substrate 701, and a lower pad 705 is placed beneath the lower protective layer 703. The lower pad 705 is connected to a through via 730. The chip structure PS and the processor chip 800 are electrically connected to the package substrate 900 via a metal bump 720 located beneath the lower pad 705.

[0105] The interconnecting structure 710 is positioned on the upper surface of the substrate 701 and includes an interlayer insulating layer 711 and a single-layer or multilayer wiring structure 712. If the interconnecting structure 710 consists of a multilayer wiring structure, the wiring patterns of different layers are connected to each other via contact vias.

[0106] The through-via 730 extends from the top to the bottom of the substrate 701 and penetrates the substrate 701. The through-via 730 also extends into the interconnecting structure 710 and is electrically connected to the wiring of the interconnecting structure 710. If the substrate 701 is silicon, the through-via 730 is referred to as a TV. In some embodiments, the interposer substrate 700 contains only the interconnecting structure internally and does not contain the through-via.

[0107] The interposer substrate 700 is used to convert or transmit input electrical signals between the package substrate 900 and the chip structure PS or processor chip 800. Therefore, the interposer substrate 700 does not contain any elements such as active or passive elements. Depending on the embodiment, the interconnecting structure 710 may be located below the through via 730. For example, the positional relationship between the interconnecting structure 710 and the through via 730 is relative.

[0108] The metal bump 720 electrically connects the interposer substrate 700 and the package substrate 900. The chip structure PS is electrically connected to the metal bump 720 via wiring and through vias 730 of the interconnecting structure 710. Depending on the embodiment, the number of lower pads 705 used for power or ground may be greater than the number of metal bumps 720, as they are integrated and connected together with the metal bump 720.

[0109] The processor chip 800 includes, for example, a central processor (CPU), graphics processor (GPU), field-programmable gate array (FPGA), digital signal processor (DSP), cryptographic processor, microprocessor, microcontroller, analog-to-digital converter, and on-demand semiconductor (ASIC). Below the processor chip 800 is a linkage bump 850.

[0110] Depending on the embodiment, the semiconductor package 10h may further include an internal encapsulant covering the chip structure PS and the processor chip 800 on the interposer substrate 700. The semiconductor package 10h may further include an external encapsulant covering the interposer substrate 700 and the internal encapsulant on the package substrate 900. The external and internal encapsulants may be formed together and indistinguishable. Depending on the embodiment, the semiconductor package 10h may further include a heat dissipation structure covering the chip structure PS and the processor chip 800.

[0111] Figures 9 to 12 are cross-sectional views illustrating a process procedure for explaining an example of a semiconductor package 10 according to one embodiment.

[0112] Referring to Figure 9, the first semiconductor chip C1 is formed on the base chip BC.

[0113] A base chip BC is provided, comprising a substrate SB, a circuit layer CL, opposite lower connectors LT and upper connectors UT, an upper protective layer DL surrounding each side of the upper connector UT on the substrate SB, and through-vias TV electrically connecting the lower connector LT and the upper connector UT. Multiple connecting bumps BP are attached to the underside of the base chip BC. The base chip BC is temporarily attached to a carrier (not shown) by an adhesive layer (not shown).

[0114] A planarization process is applied to the base chip BC. This creates a flat surface BC_US that is provided for "direct bonding".

[0115] A first semiconductor chip C1 is formed on a base chip BC. The first semiconductor chip C1 is understood to include the components described with reference to Figures 1 to 2c. The first semiconductor chip C1 is directly bonded to the base chip BC by metal-to-metal bonding and dielectric-to-dielectric bonding (hereinafter referred to as "direct bonding") without conductive members for electrical connection (e.g., solder bumps, copper pillars, etc.).

[0116] Similarly, a planarization process is applied to the first semiconductor chip C1 to provide a flat surface for "direct bonding".

[0117] Referring to Figure 10, at least one second semiconductor chip C2 is formed on the first semiconductor chip C1.

[0118] At least one second semiconductor chip C2 is formed on the first semiconductor chip C1. The at least one second semiconductor chip C2 is understood to include the components described with reference to Figures 1 to 2c. The at least one second semiconductor chip C2 is directly bonded to the first semiconductor chip C1 by metal-to-metal bonding and dielectric-to-dielectric bonding (hereinafter referred to as "direct bonding") without conductive members for electrical coupling (e.g., solder bumps, copper pillars, etc.).

[0119] If there are multiple instances of at least one second semiconductor chip C2, it is understood that the lowest 2-1 semiconductor chip C2_1 and the uppermost 2-2 semiconductor chip C2_2 are formed on the first semiconductor chip C1.

[0120] As described with reference to Figure 9, a planarization process is applied to each of the multiple second semiconductor chips C2 to provide a flat surface for "direct bonding".

[0121] Referring to Figure 11, a third semiconductor chip C3 is formed on the second semiconductor chip C2.

[0122] A third semiconductor chip C3, with a first adhesive layer 401 attached to its rear (upper) surface C3_BS, is formed on the second semiconductor chip C2. The third semiconductor chip C3 is understood to include the components described with reference to Figures 1 to 2c. Alternatively, the third semiconductor chip C3 is understood to include the components described with reference to Figure 4.

[0123] The third semiconductor chip C3 is directly bonded to the second semiconductor chip C2 (or the second-second semiconductor chip C2_2) by metal-to-metal bonding and dielectric-to-dielectric bonding (hereinafter referred to as "direct bonding") without conductive members for electrical connection (e.g., solder bumps, copper pillars, etc.).

[0124] Referring to Figure 12, a dummy chip DC is formed on the third semiconductor chip C3.

[0125] A dummy chip DC, with a second adhesive layer 402 attached to its front (lower) DC_FS, is formed on the third semiconductor chip C3. The dummy chip DC is formed on the third semiconductor chip C3 such that the second adhesive layer 402 is formed on the first adhesive layer 401.

[0126] Next, the adhesive strength of the first and second adhesive layers (401, 402) is formed by a thermocompression bonding process.

[0127] The thermocompression bonding process of the present invention is performed under relatively low pressure and low temperature conditions compared to a conventional thermocompression bonding process that is performed after directly forming an adhesive layer on the rear surface of a semiconductor chip, which is formed on the front surface of a dummy chip. According to the present invention, sufficient adhesive strength is formed on the first and second adhesive layers (401, 402) even by a thermocompression bonding process under relatively low pressure and low temperature conditions.

[0128] Next, a sealing material ML is formed on the base chip BC to cover each side of multiple chip stacks CS, multiple adhesive layers (401, 402), and dummy chip DC.

[0129] Figure 13 is a cross-sectional view illustrating a process procedure for manufacturing another example of a semiconductor package 10g according to one embodiment. Figure 13 is a process diagram following Figure 11.

[0130] Referring to Figure 13, a dummy chip DC is formed on the third semiconductor chip C3.

[0131] A second adhesive layer 402 is attached to the front (lower) DC_FS, and a dummy chip DC having a first width W1 is formed on a third semiconductor chip C3 having a second width W2 that is smaller than the first width W1. As a result, at least a portion of the lower surface of the second adhesive layer 402 is exposed.

[0132] Next, a sealant ML is formed on the base chip BC, covering the sides of multiple chip stacks CS, multiple adhesive layers (401, 402), and dummy chip DC. The sealant ML covers the lower surface of the second adhesive layer 402, where at least a portion is exposed.

[0133] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0134] 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h semiconductor packages 110, 210, 310 First to third substrates (first to third semiconductor substrates) 113 Insulating protective layer 114 Buffer membrane 141, 241 Side barrier layer 143, 243 Side insulating film 145, 245 via plugs 120, 220, 320 1st to 3rd circuit layer 211 Separation area 212 Conductive area 213 Insulating protective layer 221 Interlayer insulating layer 223 Interconnections 225 Wiring structures 400 adhesive layer 401, 402, 403 1st to 3rd adhesive layer 401e, 402e First and Second Extensions Pages 401 and 402: First and second protrusions (first and second fillet portions) 402e_1 Part 2-1 402e_2 Part 2-2 402pa No. 2-1 protrusion 402pb 2nd-2nd protrusion 402pb1 Part 1 402pb2 2nd part 700 Interposer board 701 circuit board 703 Lower protective layer 705 Lower pad 710 Interconnected Structures 711 Interlayer insulating layer 712 Wiring structure 720 Metal Bump 730 Through via 800 processor chips 850 Linked Bumps 900 Package Substrates 911, 912 Upper and lower terminals 913 Rewiring circuit 920 External connection terminal BC base chip Top surface (flat surface) of the BC_US base chip GF Linked Bump BR boundary area C1, C2, C3: First to third semiconductor chips C2_1 Second-to-first semiconductor chip (the second semiconductor chip at the bottom) C2_2 Second-to-second semiconductor chip (the uppermost second semiconductor chip) C3' Third Semiconductor Chip C3_BS Rear (top) of the third semiconductor chip C3_S Side view of the third semiconductor chip CL element layer (circuit layer) CS Chip Stack CS_S side DC dummy chip DC_FS dummy chip front (bottom) DC_S Dummy Chip Side View DL top protective layer DL_US Upper protective layer top surface ID Individual element LI1, LI2, LI3: First to third lower insulating layers LP1, LP2, LP3 1st to 3rd lower pads LP3 Front Pad LT, UT lower and upper connection terminals ML encapsulant PS chip structure SB board TSV1, TSV2, TSV3: First to third through electrodes TV Penetrating Via UI1, UI2, UI3: First to third upper insulating layers UP1, UP2, UP3 1st to 3rd upper pads

Claims

1. A base chip including a lower connection terminal and an upper connection terminal opposite to each other, and a through electrode that electrically connects the lower connection terminal and the upper connection terminal, A semiconductor chip stack including a plurality of semiconductor chips sequentially stacked in a first direction on the base chip, A plurality of connecting bumps are positioned below the base chip and electrically connected to the lower connection terminal, A dummy chip on the aforementioned semiconductor chip stack, The semiconductor chip stack comprises a plurality of adhesive layers between the semiconductor chip stack and the dummy chip, The plurality of semiconductor chips in the semiconductor chip stack are A first semiconductor chip disposed on the base chip, including a first lower pad and a first upper pad opposite to each other, and a first through-via electrically connecting the first lower pad and the first upper pad, A second semiconductor chip disposed on the first semiconductor chip, including a second lower pad and a second upper pad opposite to each other, and a second through-via electrically connecting the second lower pad and the second upper pad, A third semiconductor chip is disposed on at least one of the second semiconductor chips and includes a front pad located on the front surface, The first lower pad of the first semiconductor chip contacts the upper connection terminal of the base chip adjacent in the first direction. The first upper pad of the first semiconductor chip contacts the second lower pad of the at least one second semiconductor chip adjacent in the first direction. The front pad of the third semiconductor contacts the second upper pad of the at least one second semiconductor chip adjacent in the first direction. The semiconductor package is characterized in that the plurality of adhesive layers include a first adhesive layer on the semiconductor chip stack and a second adhesive layer on the first adhesive layer.

2. The first adhesive layer includes a first protrusion that protrudes beyond the side surface of the third semiconductor chip, The semiconductor package according to claim 1, characterized in that the second adhesive layer includes a second protrusion that protrudes beyond the side surface of the dummy chip.

3. The semiconductor package according to claim 2, characterized in that the lower region of the second protrusion and the upper region of the first protrusion are in contact with each other.

4. The semiconductor package according to claim 2, characterized in that a boundary region is defined between the first protrusion and the second protrusion.

5. The semiconductor package according to claim 4, characterized in that the boundary region is a concave region formed between the end of the first protrusion and the end of the second protrusion.

6. At least a portion of the first projection extends toward the upper surface of the base chip, The semiconductor package according to claim 2, characterized in that at least a portion of the first protrusion is in contact with the side surface of the third semiconductor chip.

7. At least a portion of the second projection extends in the first direction, The semiconductor package according to claim 2, characterized in that at least a portion of the second protrusion contacts the side surface of the dummy chip.

8. Base chip and, A semiconductor chip stack including a plurality of semiconductor chips sequentially stacked in a first direction on the base chip, A dummy chip on the aforementioned semiconductor chip stack, The adhesive layer between the semiconductor chip stack and the dummy chip, The base chip comprises a sealing material that covers the sides of the semiconductor chip stack, the dummy chip, and the adhesive layer, The adhesive layer includes an extension portion extending in a second direction perpendicular to the first direction between the semiconductor chip stack and the dummy chip, and a plurality of fillet portions connected to the extension portion and extending to the sealing material. The aforementioned multiple fillet portions are A first fillet portion extending from the lower region of the extension into the sealing material, A semiconductor package characterized by including a second fillet portion extending from the upper region of the extension into the sealing material.

9. The first fillet portion and the second fillet portion are in contact with each other. The semiconductor package according to claim 8, characterized in that a boundary region is defined between the end of the first fillet portion and the end of the second fillet portion.

10. The first fillet portion contacts the side surface of the semiconductor chip stack, The semiconductor package according to claim 8, characterized in that the second fillet portion is in contact with the side surface of the dummy chip.

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