Laminated structure and method for manufacturing a laminated structure

Abstract

This invention provides a method for manufacturing a laminated structure that can stably bond metal electrodes together. [Solution] The disclosed method for manufacturing a laminated structure includes the steps of: (i) preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface; (ii) forming a protrusion on the surface of the first metal electrode made of the oxide of the first metal electrode; (iii) bonding the first substrate and the second substrate so that the first insulating layer and the second insulating layer are in contact; and (iv) joining the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together. At least one of the first substrate and the second substrate includes a semiconductor element.

Description

Technical Field

[0001] The present disclosure relates to a laminated structure and a method for manufacturing the laminated structure.

Background Art

[0002] Conventionally, the density of semiconductor chips has been increasing. Also, as a technology related to semiconductor chips, chiplet technology has been attracting attention. Claim 1 of Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2020-170740) states, "A method for manufacturing a laminated device chip including a first device formed in each region on the surface of a first wafer partitioned by a plurality of planned division lines and a second device formed in each region on the surface of a second wafer partitioned by a plurality of planned division lines, a first wafer dividing step of forming a plurality of first chips by dividing the first wafer of a work set including a ring frame, an adhesive tape adhered to the ring frame so as to close the opening of the ring frame, and the first wafer having the back surface adhered to the adhesive tape, along the planned division lines, a polishing step of removing processing debris from the first surface by polishing the first surface including the first device that becomes the bonding surface in the plurality of first chips with a polishing pad after the first wafer dividing step, a cleaning step of cleaning the first chip by supplying cleaning water to the first surface side of the first chip after the polishing step, a pickup step of separating the first chip from the adhesive tape after the cleaning step, a preparation step of performing preparations for making the first surface of the first chip and the second surface which is the bonding surface of the second device in the second wafer bondable, a bonding step of facing the first surface of the first chip to the second surface of the second device and bonding the second surface and the first surface, A stacked device chip manufacturing process for manufacturing individual stacked device chips by dividing the second wafer along the planned division line of the second wafer after the bonding process, The document discloses a method for manufacturing a stacked device chip, including [the specified component].

[0003] Claim 1 of Patent Document 2 (Japanese Patent Publication No. 2021-197430) is "a step of preparing a first semiconductor substrate having a first substrate body, a first insulating film and a first electrode provided on one surface of the first substrate body, A step of preparing a second semiconductor substrate having a second substrate body, a second insulating film provided on one surface of the second substrate body, and a plurality of second electrodes, A step of polishing at least one of the one side of the first semiconductor substrate and the one side of the second semiconductor substrate, A step of separating the second semiconductor substrate into individual pieces to obtain a plurality of semiconductor chips, each of which is provided with an insulating film portion corresponding to the second insulating film and at least one of the second electrodes, A step of aligning the second electrode of at least one semiconductor chip among the plurality of semiconductor chips with respect to the first electrode of the first semiconductor substrate, A step of bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip to each other, The process includes a step of joining the first electrode of the first semiconductor substrate to the second electrode of the semiconductor chip, At least one of the first insulating film and the second insulating film contains an organic material. The document discloses "a method for manufacturing a semiconductor device."

[0004] Chiplet technology requires bonding the substrate and the semiconductor chip. Currently, hybrid bonding and other methods are attracting attention as ways to bond the substrate and the semiconductor chip. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-170740 [Patent Document 2] Japanese Patent Publication No. 2021-197430 [Overview of the project] [Problems that the invention aims to solve]

[0006] In hybrid bonding, copper electrodes on a substrate and copper electrodes on a semiconductor chip are joined together. However, the bond between copper electrodes can sometimes be unstable. In such situations, one of the objectives of this disclosure is to provide a method for manufacturing a laminated structure that can stably bond metal electrodes together. [Means for solving the problem]

[0007] One aspect of this disclosure is a method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a protrusion made of the oxide of the first metal electrode on the surface of the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, The present invention relates to a method for manufacturing a stacked structure in which at least one of the first substrate and the second substrate includes a semiconductor element.

[0008] Another aspect of this disclosure is a laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a part of the first insulating layer and at least a part of the second insulating layer are in close contact with each other. The laminated structure relates to a laminated structure in which the first metal electrode and the second metal electrode are joined by a metal protruding from a flat portion of the first metal electrode and a flat portion of the second metal electrode.

Advantages of the Invention

[0009] According to the present disclosure, a laminated structure in which metal electrodes are stably joined to each other can be obtained.

Brief Description of the Drawings

[0010] [ [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of the manufacturing method according to the present embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically showing an example of the laminated structure manufactured in the present embodiment. [Figure 3] FIG. 3 is a cross-sectional view schematically showing an example of one step of the manufacturing method according to the present embodiment. [Figure 4] FIG. 4 is a side view schematically showing an example of the apparatus used in the manufacturing method according to the present embodiment. [Figure 5] FIG. 5 is a cross-sectional view schematically showing an example of one step of the manufacturing method according to the present embodiment. [Figure 6] FIG. 6 is a diagram schematically showing the flow of an example of the manufacturing method according to the present embodiment. { [Figure 7] FIG. 7 is a cross-sectional view schematically showing an example of one step of the manufacturing method according to the present embodiment. [Figure 8] FIG. 8 is a cross-sectional view schematically showing an example of one step of the manufacturing method according to the present embodiment. [[ID=4I]]

Embodiments for Carrying Out the Invention

[0011] The embodiments of this disclosure will be described below with examples, but this disclosure is not limited to the examples described below. In the following description, specific numerical values ​​and materials may be given as examples, but other numerical values ​​and other materials may be applied as long as they allow the invention of this disclosure to be carried out. In this specification, the description "numerical value A to numerical value B" includes numerical value A and numerical value B, and can be read as "greater than or equal to numerical value A and less than or equal to numerical value B". In the following description, when lower and upper limits of numerical values ​​relating to specific physical properties or conditions are given as examples, either the given lower limit and either the given upper limit may be arbitrarily combined, as long as the lower limit does not exceed the upper limit. In the following description, when examples of components or methods are listed, unless otherwise specified, only one of the listed examples may be used, or multiple of the listed examples may be used in combination.

[0012] (Method of manufacturing a laminated structure) The manufacturing method according to this embodiment is a method for manufacturing a laminated structure. The manufacturing method according to this embodiment may be referred to as "manufacturing method (M)" below. Manufacturing method (M) includes steps (i), (ii), (iii), and (iv) in that order. These steps are described below.

[0013] (Step (i)) Step (i) is a step of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface (one main surface of the first substrate), and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface (one main surface of the second substrate). The first insulating layer and the first metal electrode are exposed at the bonding surface of the first substrate. The second insulating layer and the second metal electrode are exposed at the bonding surface of the second substrate.

[0014] The preparation step may be the process of procuring the first and / or second substrates manufactured by a third party. Alternatively, the preparation step may be the process of manufacturing the first and / or second substrates. The method of manufacturing these substrates is not limited and may be done by known methods.

[0015] At least one of the first substrate and the second substrate includes semiconductor elements. The first substrate alone may include semiconductor elements. The second substrate alone may include semiconductor elements. Alternatively, the first substrate and the second substrate may each include semiconductor elements. In a typical example, the first substrate and the second substrate each include multiple semiconductor elements. In a typical example, the first substrate includes multiple first metal electrodes, and the second substrate includes multiple second metal electrodes. The first substrate and / or the second substrate may include elements other than semiconductor elements, and may include electrodes disposed within the substrate.

[0016] Each of the first and second substrates may contain multiple semiconductor chips that have not been individually packaged. For example, both the first and second substrates may contain semiconductor wafers, or only one of them may contain a semiconductor wafer. One of the first and second substrates may contain individually packaged semiconductor chips. In one example of manufacturing method (M), one of the first and second substrates contains a semiconductor wafer, and the other of the first and second substrates contains individually packaged semiconductor chips. This configuration makes it possible to improve the yield of semiconductor chips formed using a stacked structure. In this configuration, typically in step (iii), semiconductor chips are placed on a substrate containing a semiconductor wafer.

[0017] The first substrate may include a first base substrate. If the first substrate includes a first base substrate, the first insulating layer and the first metal electrode may be laminated directly or indirectly on the first base substrate. The second substrate may include a second base substrate. If the second substrate includes a second base substrate, the second insulating layer and the second metal electrode may be laminated directly or indirectly on the second base substrate. The first base substrate and the second base substrate can be semiconductor substrates, glass substrates, etc. Examples of semiconductor substrates include silicon substrates, etc. The first insulating layer and the second insulating layer may be inorganic insulating layers or organic insulating layers. Examples of inorganic insulating layers include silicon oxide layers and SiCN layers, etc. The insulating layer may be made of a compound containing the elements of the semiconductor that constitute the substrate.

[0018] The first and second metal electrodes may each be made of copper or a copper alloy. A first insulating layer is present around the first metal electrode, and a second insulating layer is present around the second metal electrode.

[0019] To ensure reliable bonding between the first and second metal electrodes, it is preferable that the bonding surfaces of the first and second substrates be generally flat. Therefore, the bonding surface of the first substrate may be polished, or the bonding surface of the second substrate may be polished. The difference in height between the surface of the first metal electrode and the surface of the first insulating layer is preferably 10 nm or less. The difference in height between the surface of the second metal electrode and the surface of the second insulating layer is preferably 10 nm or less. Considering the difference in thermal expansion coefficients, in a preferred example, the surface of the first metal electrode is lower than the surface of the first insulating layer, and the surface of the second metal electrode is lower than the surface of the second insulating layer. The manufacturing method (M) for forming the protrusions is particularly effective when the surface of the metal electrode is lower than the surface of the insulating layer. For example, the manufacturing method (M) is particularly effective when the surface of the metal electrode is 10 nm or more lower than the surface of the insulating layer.

[0020] Step (i) may include polishing the surface of the first insulating layer and the surface of the first metal electrode, or it may include polishing the surface of the second insulating layer and the surface of the second metal electrode. Step (i) may also include polishing the surface of the first insulating layer and the surface of the first metal electrode, and polishing the surface of the second insulating layer and the surface of the second metal electrode. These polishing steps can facilitate the bonding of the first metal electrode and the second metal electrode, and can also increase the bonding strength between them. The polishing method is not limited. Examples of polishing methods include chemical mechanical polishing (CMP).

[0021] Step (i) may include removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, or removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode. That is, step (i) may include removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, and / or removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode.

[0022] Generally, the thermal expansion coefficient (volume expansion coefficient) of a metal electrode (e.g., a copper electrode) is greater than that of an insulating layer (e.g., silicon oxide). Therefore, if the surface height of the metal electrode and the surface height of the insulating layer are the same, the expansion of the metal electrode generates a force that separates the first and second substrates. If all metal electrodes are at the same height, uniform bonding is possible, but it is difficult to make all metal electrodes the same height. If some metal electrodes are higher than others, the bonding of the other metal electrodes will be hindered. By removing at least a portion of the insulating layer adjacent to the metal electrode, a gap can be created in that portion. Even if there is a metal electrode that is higher than others, the expanded metal electrode can move into the gap, suppressing defects in the bonding of the metal electrodes.

[0023] The removal of a portion of the adjacent portion of the insulating layer may be performed by forming a resist mask with an opening in the portion to be removed and then etching. These steps can be performed using methods commonly used in semiconductor device manufacturing processes. Alternatively, the removal of a portion of the adjacent portion of the insulating layer may be performed by chemical mechanical polishing. In one example of this method, first, the substrates (first substrate, second substrate) are pressed toward a polishing pad at a first pressure that planarizes the surface of the metal electrode and the surface of the insulating layer, respectively, and the metal electrode and insulating layer are chemically mechanically polished. Next, the adjacent portion of the insulating layer is chamfered by chemically mechanically polishing the metal electrode and insulating layer by pressing the substrate toward the polishing pad at a pressure higher than the first pressure. In this way, it is possible to remove a portion of the adjacent portion. The method using chemical mechanical polishing is particularly effective when the insulating layer is more difficult to polish than the metal electrode. For example, it is particularly effective when the insulating layer is a silicon-containing insulating layer (silicon oxide, SiCN, etc.) and the metal electrode is copper or a copper alloy.

[0024] The pressure for chemical mechanical polishing is selected according to the materials of the metal electrode and insulating layer, the type of abrasive, etc. The first pressure may be 8 Pa or more and 18 Pa or less. The second pressure may be 15 Pa or more and 25 Pa or less. The ratio of the second pressure P2 (Pa) to the first pressure P1 (Pa), P2 / P1, may be 1.1 or more and 2.0 or less. The pressures described herein are particularly preferable when the metal electrode is a copper electrode or a copper alloy electrode and the insulating layer is a silicon-containing insulating layer (silicon oxide, SiCN, etc.).

[0025] (Step (ii)) Step (ii) is a step of forming protrusions made of the oxide of the first metal electrode on the surface of the first metal electrode. The protrusions protrude from the flat surface of the first metal electrode. Typically, multiple protrusions are formed in step (ii). The average height of the multiple protrusions may be in the range of 1 nm to 10 nm. The multiple protrusions formed in step (ii) may include protrusions with heights of 3 nm or more, 5 nm or more, or 8 nm or more. The maximum height of the protrusions may be 30 nm or less, or 20 nm or less.

[0026] The protrusions may be formed in a dot-like (or island-like) shape. A high level of effectiveness can be achieved by forming the protrusions in a dot-like shape.

[0027] The first substrate prepared in step (i) may include an antioxidant film disposed to cover the first metal electrode. In that case, step (ii) may include a step of removing a portion of the antioxidant film on the first metal electrode (removal step) and a step of forming a protrusion by oxidizing the first metal electrode exposed after the antioxidant film has been removed (oxidation step). The antioxidant film is not particularly limited, and known antioxidant films may be used. Examples of antioxidant films include films containing benzotriazole.

[0028] In the removal process, a portion of the antioxidant film is removed so that a portion of the first metal electrode is exposed. For example, a portion of the antioxidant film may be removed so that the first metal electrode is exposed in a dot pattern. The method for removing a portion of the antioxidant film is not limited. In one example, plasma treatment may be performed so that a portion of the antioxidant film is removed. If the plasma treatment is insufficient, the first metal electrode will not be exposed. On the other hand, if the plasma treatment is excessive, the entire surface of the first metal electrode will be exposed. By performing plasma treatment under appropriate conditions, a portion of the first metal electrode can be exposed.

[0029] The method for oxidizing the first metal electrode is not limited. For example, the exposed portion of the first metal electrode can be oxidized by heating or plasma treatment of the first substrate (or first metal electrode) in an oxygen atmosphere. As a result, a convex portion made of metal oxide (e.g., copper oxide) can be formed.

[0030] Step (ii) may include the steps of forming a resist mask on the first metal electrode such that a portion of the first metal electrode of the first substrate is exposed, and forming protrusions by oxidizing the first metal electrode exposed at the openings of the resist mask (oxidation step). The resist mask can be formed by known methods. The resist mask may be formed such that the first metal electrode is exposed in a dot pattern. The oxidation step has been described above, so a redundant explanation will be omitted.

[0031] Step (ii) may further include the step of forming a protrusion on the surface of the second metal electrode, which is made of the oxide of the second metal electrode. That is, step (ii) may include the steps of forming a first protrusion on the surface of the first metal electrode, which is made of the oxide of the first metal electrode, and forming a second protrusion on the surface of the second metal electrode, which is made of the oxide of the second metal electrode. The second protrusion can be formed by the method described for forming the first protrusion. The height and area of ​​the second protrusion may be within the range described for the height and area of ​​the first protrusion.

[0032] (Step (iii)) Step (iii) is a step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact. Step (iii) can be performed by adjusting the relative positions of the first substrate and the second substrate and bringing the bonding surface of the first substrate into contact with the bonding surface of the second substrate. The first insulating layer and the second insulating layer are bonded together by contact.

[0033] Prior to step (iii), the bonding surfaces of the first substrate and the second substrate may be plasma-treated to bond hydroxyl groups to the surfaces of the first and second insulating layers. For example, the surfaces of the insulating layers may be hydrophilized (or activated) by plasma treatment. If the first and second insulating layers are silicon oxide films, hydroxyl groups can be bonded to the surface of the silicon oxide films by performing plasma treatment (hydrophilization treatment). In that case, the first and second insulating layers can be bonded more strongly via hydrogen bonds in step (iii). The conditions for plasma treatment are not particularly limited, and known conditions may be applied.

[0034] (Step (iv)) Step (iv) is a step in which the first metal electrode and the second metal electrode are joined together while the first substrate and the second substrate are bonded together. Step (iv) electrically connects the first metal electrode of the first substrate and the second metal electrode of the second substrate. Step (iv) can be performed by heating the first substrate and the second substrate while they are bonded together. For example, both substrates may be heated while applying pressure to them so that the bonding surface of the first substrate and the second substrate are in contact.

[0035] The heating method is not limited; the bonded first and second substrates may be heated in a heating chamber. The heating conditions can be selected according to the material of the metal electrodes, etc. The heating temperature may be between 180°C and 500°C. The heating time may be 60 minutes or more.

[0036] In conventional hybrid bonding, the bonding surface of a planarized first substrate is bonded to the bonding surface of a planarized second substrate. However, due to the difference in materials, after planarization, the surface of the metal electrode tends to be lower than the surface of the insulating layer. When the surface of the metal electrode is lower than the surface of the insulating layer, contact between the first and second metal electrodes becomes insufficient, and a proper bond may not be formed between them. However, in manufacturing method (M), a protrusion is formed that extends from the surface of the metal electrode, so that the protrusion reliably reaches the opposing metal electrode, and the bond is formed starting from the protrusion. As a result, a good bond is formed.

[0037] Furthermore, an oxide layer (e.g., a native oxide layer) exists on the surface of the metal electrode. When joining two electrodes, the presence of the oxide layer may prevent proper bonding. In manufacturing method (M), a first metal electrode with a protrusion formed on its surface is joined to a second metal electrode. In this case, the protrusion penetrates the oxide layer on the surface of the second metal electrode. Therefore, bonding between the heated first metal electrode and the second metal electrode is promoted at the protrusion. As a result, a good bond is formed.

[0038] According to manufacturing method (M), a substrate containing multiple semiconductor chips can be manufactured. By dividing the substrate manufactured by manufacturing method (M), multiple semiconductor chips can be obtained. Furthermore, manufacturing method (M) can be applied to chiplet technology.

[0039] (Laminated structure) The stacked structure according to this embodiment may be referred to as "stacked structure (S)" below. The stacked structure (S) can be manufactured by the manufacturing method (M). Matters described regarding the manufacturing method (M) can be applied to the stacked structure (S), so redundant explanations may be omitted. Matters described regarding the stacked structure (S) may also be applied to the manufacturing method (M). From one perspective, the stacked structure (S) includes multiple semiconductor chips. Multiple semiconductor chips can be obtained by dividing the stacked structure (S). From one perspective, the stacked structure (S) can be considered to include at least one semiconductor device. Therefore, from one perspective, the manufacturing method (M) is a method for manufacturing a semiconductor device.

[0040] The laminated structure (S) includes a first substrate having a first insulating layer and a first metal electrode arranged on one main surface (one main surface of the first substrate), and a second substrate having a second insulating layer and a second metal electrode arranged on one main surface (one main surface of the second substrate). At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. The first metal electrode and the second metal electrode are joined by metal protruding from the flat portion of the first metal electrode and the flat portion of the second metal electrode.

[0041] Let S0 be the area of ​​the portion where the first metal electrode and the second metal electrode face each other. Let Sb be the area of ​​the joint (the portion where the joint between the first metal electrode and the second metal electrode is formed). Preferably, the ratio of Sb to S0, Sb / S0, is 0.1 or greater.

[0042] As described above, in manufacturing method (M), the first metal electrode and the second metal electrode are joined starting from a protrusion protruding from the flat portion (flat surface) of the first metal electrode. Therefore, in the laminated structure (S), the first metal electrode and the second metal electrode are joined by the metal protruding from the flat portion of the first metal electrode and the flat portion of the second metal electrode. In other words, there may be a portion in the region where the surface of the first metal electrode and the surface of the second metal electrode face each other that is not joined. The first metal electrode and the second metal electrode may also be joined by a columnar joint. Furthermore, in the laminated structure (S) manufactured by manufacturing method (M), the joint may be formed over almost the entire region where the first metal electrode and the second metal electrode face each other.

[0043] One of the first and second substrates may include a semiconductor wafer, and the other of the first and second substrates may be a flaked semiconductor chip.

[0044] Examples of embodiments relating to this disclosure will be specifically described below with reference to the drawings. The above description can be applied to the examples described below. Furthermore, the examples described below can be modified based on the above description. In addition, the matters described below may be applied to the embodiments described above. Furthermore, in the embodiments described below, matters that are not essential to the laminated structure and manufacturing method relating to this disclosure may be omitted. Note that the following figures are schematic and may differ from the actual configuration. In the following figures, only the surface portion of the substrate may be shown. Semiconductor elements are formed inside the actual substrate. A native oxide layer is formed on the surface of the metal electrode, but since it is a very thin layer, it is omitted from the following figures.

[0045] (Embodiment 1) Embodiment 1 describes an example of a manufacturing method (M) and an example of a laminated structure. First, a first substrate 10 and a second substrate 20 are prepared. A part of the first substrate 10 is shown in Figure 1(a). The first substrate 10 includes a first base substrate (not shown), a first insulating layer 11 laminated on one surface of the first base substrate, and a plurality of first metal electrodes 12. The first insulating layer 11 and the plurality of first metal electrodes 12 are exposed at the bonding surface 10a of the first substrate 10. The surface of the first insulating layer 11 and the surface of the first metal electrodes 12 are at approximately the same height, but Embodiment 1 describes an example in which the surface of the first metal electrodes 12 is slightly lower than the surface of the first insulating layer 11. When the bonding surface 10a is flattened by conventional chemical mechanical polishing, the metal electrodes are often slightly lower than the insulating layer.

[0046] Next, as shown in Figure 1(b), a resist mask 31 is formed on the first metal electrode 12 such that a portion of the first metal electrode 12 is exposed. The resist mask 31 has openings 31a at multiple locations where protrusions are formed. As described above, the resist mask 31 may be replaced with an anti-oxidation film.

[0047] Next, as shown in Figure 1(c), the first metal electrode 12 exposed at the opening of the resist mask 31 is oxidized to form a plurality of protrusions 12a made of the oxide of the metal constituting the first metal electrode 12. Then, the resist mask 31 is removed.

[0048] Next, as shown in Figure 1(d), the first substrate 10 and the second substrate 20 are bonded together so that the first insulating layer 11 and the second insulating layer 21 are in contact. In the example shown in Figure 1(d), the second substrate 20 may be a sectional semiconductor chip. As described above, the second substrate 20 may be an unsectional semiconductor chip, or it may include a semiconductor wafer.

[0049] The second substrate 20 includes a second base substrate (not shown), a second insulating layer 21 laminated on one surface of the second base substrate, and a plurality of second metal electrodes 22. The second insulating layer 21 and the plurality of second metal electrodes 22 are exposed at the bonding surface of the second substrate 20. The surface of the second insulating layer 21 and the surface of the second metal electrodes 22 are at approximately the same height. The first insulating layer 11 and the second insulating layer 21 are bonded together by applying pressure to the second substrate 20 toward the first substrate 10 while the first insulating layer 11 and the second insulating layer 21 are in contact. At this time, at least a portion of the plurality of protrusions 12a are in contact with the second metal electrodes 22. At least a portion of the plurality of protrusions 12a may penetrate into the second metal electrodes 22.

[0050] Next, the first metal electrode 12 and the second metal electrode 22 are joined together by heating the first substrate 10 and the second substrate 20 while they are bonded together. In this way, a laminated structure is obtained in which the insulating layers and the metal electrodes are joined together. The obtained laminated structure may be divided as needed. As described above, in manufacturing method (M), the joining of the metal electrodes is reliably performed starting from the protrusion 12a. Therefore, the reliability of the joining of the metal electrodes can be increased.

[0051] Figure 2 shows a partial example of a laminated structure manufactured by the above manufacturing method. The laminated structure 100 in Figure 2 includes a first substrate 10 and a second substrate 20. The first substrate 10 includes a first insulating layer 11, a first metal electrode 12, a first base substrate 13, and an internal electrode 14. The second substrate 20 includes a second insulating layer 21, a second metal electrode 22, a second base substrate 23, and an internal electrode 24. At least one of the first substrate 10 and the second substrate 20 includes a semiconductor element (not shown). The first insulating layer 11 and the second insulating layer 21 are joined together. The first metal electrode 12 and the second metal electrode 22 are joined by a joint 100a. The joint 100a consists of metal protruding from the flat portion of the first metal electrode 12 and the flat portion of the second metal electrode 22. The shape of the joint 100a varies depending on the shape (and arrangement pattern) of the convex portion 12a. For example, if the protrusion 12a is formed in a dot shape, the joint 100a may be columnar.

[0052] The manufacturing method of Embodiment 1 may include a step of removing a portion of the adjacent portion of the first insulating layer 11 of the first substrate 10 that is adjacent to the first metal electrode 12. This step is performed before the step of forming the protrusion 12a. An example of removing a portion of the adjacent portion by forming a resist mask and etching is shown in Figure 3. First, as shown in Figure 3(a), a resist mask 201 having an opening 201a above the adjacent portion is formed. Next, as shown in Figure 3(b), at least a portion of the first insulating layer 11 exposed at the opening 201a is removed. As a result, a recess 11c is formed in the adjacent portion of the first insulating layer 11. After removing a portion of the adjacent portion of the first insulating layer 11, the resist mask 201 is removed.

[0053] An example of a method for removing a portion of the adjacent part of the first insulating layer 11 adjacent to the first metal electrode 12 by chemical mechanical polishing is described below. A side view of an example of a chemical mechanical polishing apparatus is shown in Figure 4. The apparatus 300 in Figure 4 includes a rotating stage 301, a polishing pad 302, a substrate holding head 303, a conditioner 304, and a slurry supply unit 305. The polishing pad 302 is fixed on the rotating stage 301 and rotates together with the rotating stage 301. A substrate (first substrate 10 in Figure 4) is fixed to the substrate holding head 303. The substrate holding head 303 rotates while applying pressure to the substrate toward the polishing pad 302. The conditioner 304 is a component for refreshing the surface of the polishing pad 302. The slurry supply unit 305 supplies a slurry containing abrasive material onto the polishing pad 302. By rotating the polishing pad 302 and the substrate and pressing the substrate against the polishing pad, the surface of the substrate is flattened.

[0054] In one example of a method using chemical mechanical polishing, first, the bonding surface 10a (first insulating layer 11 and first metal electrode 12) of the first substrate 10 is chemically polished. At this time, as shown in Figure 5(a), chemical mechanical polishing is performed while applying pressure to the substrate holding head 303 with a first pressure so that the surface of the first insulating layer 11 and the surface of the first metal electrode 12 are flattened.

[0055] Next, the substrate holding head 303 is pressurized with a pressure higher than the first pressure to chemically and mechanically polish the bonding surface 10a (the first insulating layer 11 and the first metal electrode 12). This allows the adjacent portion 11a (the portion adjacent to the first metal electrode 12) of the first insulating layer 11 to be chamfered, as shown in Figure 5(b). In this way, a portion of the adjacent portion 11a can be removed. Note that a portion of the adjacent portion of the second insulating layer 21 of the second substrate 20 can also be removed by the method described above.

[0056] An example of the manufacturing process flow for producing a stacked structure (S) will be explained with reference to Figure 6. Figure 6 shows an example of an embodiment in which a fragmented semiconductor chip is used as the second substrate. However, an unfragmented first substrate and an unfragmented second substrate may be bonded together. Alternatively, a fragmented semiconductor chip may be used as the first substrate, and a substrate containing a semiconductor wafer may be used as the second substrate. In that case, the fragmented first substrate is bonded to the second substrate placed on the substrate stage.

[0057] First, a first substrate and a second substrate (more precisely, the substrate that will become the second substrate) are prepared. As shown in Figure 6, the bonding surfaces of the first substrate and the second substrate may be flattened. Next, the aforementioned protrusions are formed on the first metal electrode of the first substrate. The second substrate is also separated into individual pieces to obtain multiple semiconductor chips (second substrates). Next, the bonding surfaces of the first substrate and the bonding surfaces of the second substrate (semiconductor chips) are subjected to a hydrophilic treatment. Next, the bonding surfaces of the first substrate and the bonding surfaces of the second substrate are brought into contact to bond the first insulating layer and the second insulating layer (preliminary bonding step). Next, the first metal electrode and the second metal electrode are bonded (final bonding step). In this way, a laminated structure is obtained.

[0058] As described above, the protrusions may be formed only on the second metal electrode. Alternatively, the protrusions may be formed on both the first and second metal electrodes. Between the planarization step and the protrusion formation step, and / or between the planarization step and the framing step, a step of removing a portion of the adjacent part of the insulating layer may be performed.

[0059] Examples of the temporary bonding process and the permanent bonding process are shown in Figures 7 and 8. In the temporary bonding process, as shown in Figure 7, a plurality of individualized second substrates 20 are sequentially placed at predetermined positions on the first substrate 10, which is placed on the substrate stage 401. Specifically, the second substrates 20 are attracted to the bonding head 402, transported, and pressed onto the predetermined positions on the first substrate 10. Temporary bonding is performed by this pressing. This transport and alignment can be carried out by known methods. For example, alignment can be performed using an alignment optical unit 403. Note that the parts shown in Figures 1(d) and 2 are part of region A in Figure 7.

[0060] As shown in Figure 8, the first substrate 10, to which multiple second substrates 20 are temporarily bonded, is heated in a heating chamber 410. This heating bonds the first metal electrode and the second metal electrode (main bonding step). In this way, a laminated structure (S) is obtained. The obtained laminated structure (S) is divided as needed.

[0061] (Note) The following technologies are disclosed based on the above description. (Technology 1) A method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a protrusion made of the oxide of the first metal electrode on the surface of the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, A method for manufacturing a stacked structure, wherein at least one of the first substrate and the second substrate includes a semiconductor element. (Technology 2) The first substrate prepared in step (i) includes an anti-oxidation film disposed to cover the first metal electrode, The above step (ii) is, A step of removing a portion of the antioxidant film on the first metal electrode, The manufacturing method according to Art 1, comprising the step of forming the protrusion by oxidizing the first metal electrode that has been exposed after the oxidation-preventive film has been removed. (Technology 3) The above step (ii) is, A step of forming a resist mask on the first metal electrode such that a portion of the first metal electrode of the first substrate is exposed, The manufacturing method according to Art 1, comprising the step of forming the protrusion by oxidizing the first metal electrode exposed at the opening of the resist mask. (Technology 4) The manufacturing method according to any one of the technologies 1 to 3, further comprising the step (ii) of forming a protrusion on the surface of the second metal electrode made of the oxide of the second metal electrode. (Technology 5) The manufacturing method according to any one of the technologies 1 to 4, wherein step (i) includes polishing the surface of the first insulating layer and the surface of the first metal electrode, and polishing the surface of the second insulating layer and the surface of the second metal electrode. (Technology 6) The manufacturing method according to any one of the technologies 1 to 5, wherein step (i) includes a step of removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, or a step of removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode. (Technology 7) A manufacturing method according to any one of the technologies 1 to 6, wherein one of the first substrate and the second substrate comprises a semiconductor wafer, and the other of the first substrate and the second substrate comprises a flaked semiconductor chip. (Technology 8) A manufacturing method according to any one of the technologies 1 to 7, wherein the first metal electrode and the second metal electrode are each made of copper or a copper alloy. (Technology 9) A laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. A laminated structure in which the first metal electrode and the second metal electrode are joined together by a metal protruding from the flat portion of the first metal electrode and the flat portion of the second metal electrode. (Technology 10) The stacked structure according to Technical Reference 9, wherein one of the first substrate and the second substrate includes a semiconductor wafer, and the other of the first substrate and the second substrate is a flaked semiconductor chip. [Industrial applicability]

[0062] This disclosure can be used for multilayer structures (such as semiconductor devices or semiconductor device precursors) and methods for manufacturing multilayer structures. [Explanation of symbols]

[0063] 10: First board 11: First insulating layer 11a: Adjacent area 12:First metal electrode 12a: Convex part 13: First base board 20: Second board 21: Second insulating layer 22:Second metal electrode 23: Second base board 100: Laminated structure

Claims

1. A method for manufacturing a laminated structure, Step (i) of preparing a first substrate including a first insulating layer and a first metal electrode arranged on one main surface, and a second substrate including a second insulating layer and a second metal electrode arranged on one main surface, (ii) A step of forming a protrusion made of the oxide of the first metal electrode on the surface of the first metal electrode, (iii) A step of bonding the first substrate and the second substrate together such that the first insulating layer and the second insulating layer are in contact, The process includes (iv) a step of bonding the first metal electrode and the second metal electrode while the first substrate and the second substrate are bonded together, A method for manufacturing a stacked structure, wherein at least one of the first substrate and the second substrate includes a semiconductor element.

2. The first substrate prepared in step (i) includes an anti-oxidation film disposed to cover the first metal electrode, The above step (ii) is, A step of removing a portion of the antioxidant film on the first metal electrode, The manufacturing method according to claim 1, comprising the step of forming the protrusion by oxidizing the first metal electrode that has been exposed after the oxidation-preventive film has been removed.

3. The above step (ii) is, A step of forming a resist mask on the first metal electrode such that a portion of the first metal electrode of the first substrate is exposed, The manufacturing method according to claim 1, comprising the step of forming the protrusion by oxidizing the first metal electrode exposed at the opening of the resist mask.

4. The manufacturing method according to any one of claims 1 to 3, wherein step (ii) further comprises the step of forming a protrusion on the surface of the second metal electrode made of the oxide of the second metal electrode.

5. The manufacturing method according to any one of claims 1 to 3, wherein step (i) includes polishing the surface of the first insulating layer and the surface of the first metal electrode, and polishing the surface of the second insulating layer and the surface of the second metal electrode.

6. The manufacturing method according to any one of claims 1 to 3, wherein step (i) includes a step of removing at least a portion of the adjacent portion of the first insulating layer adjacent to the first metal electrode, or a step of removing at least a portion of the adjacent portion of the second insulating layer adjacent to the second metal electrode.

7. The manufacturing method according to any one of claims 1 to 3, wherein one of the first substrate and the second substrate includes a semiconductor wafer, and the other of the first substrate and the second substrate is a flammable semiconductor chip.

8. The manufacturing method according to any one of claims 1 to 3, wherein the first metal electrode and the second metal electrode are each made of copper or a copper alloy.

9. A laminated structure, A first substrate including a first insulating layer and a first metal electrode arranged on one main surface, It includes a second substrate having a second insulating layer and a second metal electrode arranged on one main surface, At least one of the first substrate and the second substrate includes a semiconductor element. At least a portion of the first insulating layer and at least a portion of the second insulating layer are in close contact. A laminated structure in which the first metal electrode and the second metal electrode are joined together by metal protruding from the flat portion of the first metal electrode and the flat portion of the second metal electrode.

10. The laminated structure according to claim 9, wherein one of the first substrate and the second substrate includes a semiconductor wafer, and the other of the first substrate and the second substrate is a flaked semiconductor chip.

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