Memory system

Abstract

To provide a highly reliable memory system. [Solution] The memory system comprises a non-volatile memory and a controller. The non-volatile memory includes a plurality of first memory cells, first word lines connected thereto, a plurality of second memory cells, and second word lines connected thereto. The controller is configured to hold first write data used for writing to the plurality of first memory cells and second write data used for writing to the plurality of second memory cells. The controller is also configured to calculate rewrite data based on the first write data and the second write data. The non-volatile memory is also configured to perform a first write operation, which writes to the plurality of first memory cells based on the first write data input from the controller, and a rewrite operation, which writes to a portion of the plurality of first memory cells based on rewrite data input from the controller.

Description

Technical Field

[0001] This embodiment relates to a memory system.

Background Art

[0002] A memory system including a non-volatile memory and a controller connected to the non-volatile memory and connectable to a host device is known. Also, various writing methods to the non-volatile memory are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a highly reliable memory system.

Means for Solving the Problems

[0005] A memory system according to one embodiment includes a non-volatile memory and a controller connected to the non-volatile memory. The non-volatile memory includes a plurality of first memory cells, a first word line connected to the plurality of first memory cells, a plurality of second memory cells, and a second word line connected to the plurality of second memory cells. The controller is configured to hold first write data used for writing to the plurality of first memory cells, and second write data used for writing to the plurality of second memory cells after writing to the plurality of first memory cells. The controller is also configured to calculate rewrite data based on the first write data and the second write data. The non-volatile memory is also configured to perform a first write operation, which writes to the plurality of first memory cells based on the first write data input from the controller, and a rewrite operation, which writes to a portion of the plurality of first memory cells based on the rewrite data input from the controller. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram of a non-volatile semiconductor device showing an example configuration of the first embodiment. [Figure 2] This is a block diagram of memory system 10. [Figure 3] This is a circuit diagram showing an example of a 3D NAND flash memory cell array (MCA). [Figure 4A] This is a cross-sectional view of a portion of a three-dimensional NAND flash memory cell array (MCA). [Figure 4B] This is an enlarged cross-sectional view of region R1 shown in Figure 4A. [Figure 5] This figure shows an example of the threshold voltage range. [Figure 6] This diagram shows the data coding for 3 bits / cell. [Figure 7] This is a flowchart showing the page loading process. [Figure 8] This figure shows the transition of the read voltage on the word line during page readout. [Figure 9]This figure shows the threshold distribution when all bits are programmed simultaneously. [Figure 10] This flowchart shows an example of the write order within a block BLK when all bits are programmed simultaneously. [Figure 11] This figure shows an example of the order in which to select word lines WL when programming all bits simultaneously. [Figure 12] This figure shows the threshold distribution after programming in the Foggy-Fine program. [Figure 13] This diagram shows the program sequence for the Foggy-Fine program. [Figure 14] This flowchart shows an example of the program sequence for the entire BLK (Block) in the first embodiment. [Figure 15] This figure shows an example of the order in which word lines WL are selected when programming in the first embodiment. [Figure 16] This figure shows the threshold distribution after programming in the first embodiment. [Figure 17] In the first embodiment, this is an example of a combination of threshold regions between a target cell and an adjacent cell that will be used to write the program in the third stage. [Figure 18] This is a control flow diagram of the written data in the first embodiment. [Figure 19] This figure shows the threshold distribution after programming in the second embodiment. [Figure 20] This is an example of a combination of threshold regions between a target cell and an adjacent cell, which is the target of the program writing in the 3rd stage in the second embodiment. [Figure 21] This is a control flow diagram of the write data in the second embodiment. [Figure 22] This figure shows the threshold distribution after programming in the third embodiment. [Figure 23] This is an example of a combination of threshold regions between a target cell and an adjacent cell, which is the target of the program writing in the 3rd stage in the third embodiment. [Figure 24] This is a control flow diagram of write data in the third embodiment. [Figure 25] This is a diagram showing an example of the order of selecting word lines WL in the program in the third embodiment. **Embodiments for Carrying Out the Invention**

[0007] Next, the memory system according to the embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Also, the following drawings are schematic, and for convenience of explanation, some configurations may be omitted. In addition, the same reference numerals are assigned to common parts in a plurality of embodiments, and the description may be omitted.

[0008] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0009] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper", and the direction approaching the substrate along the Z direction is called "lower". Also, when referring to the lower surface or lower end of a certain configuration, it means the surface or end on the substrate side of this configuration, and when referring to the upper surface or upper end, it means the surface or end on the side opposite to the substrate of this configuration. Also, a surface intersecting the X direction or Y direction is called a side surface or the like.

[0010] [First Embodiment] [Configuration] FIG. 1 is a block diagram of a non-volatile semiconductor device (non-volatile memory) showing a configuration example of the first embodiment. FIG. 2 is a block diagram of the memory system 10. FIG. 3 is a circuit diagram showing an example of a three-dimensional structure NAND flash memory cell array MCA.

[0011] A non-volatile semiconductor memory device (non-volatile memory) is a memory that stores data in a non-volatile manner, such as a NAND flash memory 40. In this embodiment, the non-volatile semiconductor memory device is described as a NAND flash memory 40 having memory cells MC capable of storing 3 bits per memory cell MC, that is, a 3-bit / Cell (TLC: Triple Level Cell) NAND flash memory 40.

[0012] Non-volatile semiconductor memory devices are constructed and arrayed in three dimensions using memory cells MC. In this specification, a physical memory cell group MG is defined as a group of multiple memory cells MC that are commonly connected to a single word line WL and simultaneously selected by a single select gate line SGD (Figure 3). In this embodiment, the non-volatile semiconductor memory device is, for example, a 3-bit / Cell NAND flash memory 40, and one physical memory cell group MG corresponds to 3 pages. Each of the 3 bits in each memory cell MC corresponds to one of these 3 pages. In this specification, these 3 pages are referred to as the Lower page, Middle page, and Upper page.

[0013] The non-volatile semiconductor memory device shown in Figure 1, for example, a NAND flash memory 40, comprises a NANDI / O interface NIF, a control unit CTU, a NAND flash memory cell array MCA (memory cell MC section), and a data latch section DL. The non-volatile semiconductor memory device is formed on a semiconductor substrate (for example, a silicon substrate) to form a chip.

[0014] The control unit CTU controls the operation of the NAND flash memory 40 based on commands from the memory controller 30 via the NANDI / O interface NIF. Specifically, when a write request is received, the control unit CTU controls the writing of the requested data to a specified address on the NAND flash memory cell array MCA. When a read request is received, the control unit CTU controls the reading of the requested data from the NAND flash memory cell array MCA and outputs it to the memory controller 30 via the NANDI / O interface NIF.

[0015] The data latch section DL is a buffer that temporarily stores data input from the memory controller 30 during writing to the NAND flash memory cell array MCA, and temporarily stores data read from the NAND flash memory cell array MCA. Generally, the data latch section DL requires a number of data latches equal to the number of bits that can be held in one cell plus one. In this embodiment, since there are 3 bits / cell, there are 4 rows of data latches. A data latch is a circuit composed of, for example, a latch circuit with two inverter circuits connected together. These 4 rows of data latches will be called data latches XDL, ADL, BDL, and CDL, respectively. Data latches XDL, ADL, BDL, and CDL can transfer data to each other. Of these, only data latch XDL is directly connected to the serial access controller SAC and can directly input / output data. Data latch XDL constitutes a page buffer.

[0016] The control unit CTU comprises an oscillator OC, a sequencer SQC, a command user interface CUIF, a voltage supply unit VG, a column counter CCT, and a serial access controller SAC.

[0017] Furthermore, the NAND flash memory cell array MCA has a low decoder RD and a sense amplifier SA.

[0018] The NANDI / O interface NIF is a circuit for sending and receiving I / O signals and control signals to and from the memory controller 30.

[0019] The command user interface (CUIF) acquires the command and address from the command, address, and data received from the memory controller (30) via the I / O signal lines, based on the control signal. The command user interface (CUIF) is a circuit that passes the acquired command and address to the sequencer (SQC).

[0020] The oscillator (OC) is a circuit that generates a clock signal. The clock signal generated by the oscillator (OC) is supplied to each component, including the sequencer (SQC).

[0021] The Sequencer SQC is a state machine driven by a clock supplied by the Oscillator OC. The Sequencer SQC performs control such as accessing the NAND flash memory cell array MCA. For example, the Sequencer SQC issues commands to control various internal voltages and operating timings in response to commands received from the Command User Interface CUIF. The Sequencer SQC also supplies the block address and page address included in the address received from the Command User Interface CUIF to the Raw Decoder RD. Furthermore, the Sequencer SQC supplies the column address included in the address received from the Command User Interface CUIF to the Column Counter CCT.

[0022] The voltage supply unit VG is a circuit that generates various internal voltages supplied to the word line and various internal voltages supplied to the bit line BL, and supplies them to the low decoder RD and sense amplifier SA. The column counter CCT, during program operation or read operation, starts with the column address supplied from the sequencer SQC and sequentially advances the column addresses according to the control signals supplied from the serial access controller SAC.

[0023] The page buffer is a circuit that, during program operation, sequentially stores data received from the serial access controller SAC in the column address area specified by the column counter CCT. During read operations, the page buffer sequentially sends data from the stored data at the column addresses specified by the column counter to the serial access controller SAC.

[0024] The serial access controller (SAC) is a circuit that, during program operation, stores data received serially from the NANDI / O interface (NIF) bit by bit of the I / O signal line into a page buffer. During read operation, the serial access controller (SAC) sends the data received serially from the page buffer bit by bit of the I / O signal line to the NANDI / O interface (NIF).

[0025] The raw decoder RD is a circuit that decodes the block address and page address during program and read operations, and selects the word line WL corresponding to the page to be accessed within the block BLK. Each raw decoder RD then applies an appropriate voltage to the selected word line WL and the unselected word line WL.

[0026] The sense amplifier SA is a circuit that, during programmed operation, transfers the corresponding data stored in the page buffer to the memory cell transistor MT, and during read operation, senses the data read from the selected word line to the bit line BL and stores the obtained data in the page buffer. The data stored in the page buffer is sent to the memory controller 30 via the serial access controller SAC and the NANDI / O interface NIF.

[0027] Figure 2 shows a memory system 10 utilizing NAND flash memory 40. The memory controller 30 controls the writing of data to the NAND flash memory 40 according to write commands from the host 20. The memory controller 30 also controls the reading of data from the NAND flash memory 40 according to read commands from the host 20. The memory controller 30 includes RAM 31 (Random Access Memory), ROM 32 (Read Only Memory), a processor 33, a host interface 34, an ECC circuit 35 (Error Check and Correct), and a memory interface 36. The RAM 31, ROM 32, processor 33, host interface 34, ECC circuit 35, and memory interface 36 are connected to each other by an internal bus.

[0028] The host interface 34 outputs commands, user data (written data), etc., received from the host 20 to the internal bus. The host interface 34 is also a circuit that transmits user data read from the NAND flash memory 40, responses from the processor 33, etc., to the host 20.

[0029] The memory interface 36 is a circuit that controls the process of writing user data, etc., to the NAND flash memory 40 and the process of reading data from the NAND flash memory 40, based on instructions from the processor 33.

[0030] The processor 33 comprehensively controls the memory controller 30. The processor 33 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), etc. When the processor 33 receives a command from the host 20 via the host interface 34, it performs control according to that command. For example, the processor 33 instructs the memory interface 36 to write user data and parity to the NAND flash memory 40 according to a command from the host 20. The processor 33 also instructs the memory interface 36 to read user data and parity from the NAND flash memory 40 according to a command from the host 20. The processor 33 determines the storage area (memory area) on the NAND flash memory 40 for the user data to be stored in the RAM 31. The user data is stored in the RAM 31 via the internal bus.

[0031] The processor 33 determines the memory area for data in page units (page data), which are the writing units. In this specification, user data stored in one page of the NAND flash memory 40 is defined as unit data.

[0032] Unit data is generally encoded and stored in the NAND flash memory 40 as a codeword. In this embodiment, encoding is not mandatory. The memory controller 30 may store the unit data in the NAND flash memory 40 without encoding, but in this embodiment, a configuration in which encoding is performed is shown as an example. If the memory controller 30 does not perform encoding, the page data matches the unit data. Furthermore, one codeword may be generated based on one unit data, or one codeword may be generated based on segmented data obtained by dividing the unit data. Alternatively, one codeword may be generated using multiple unit data.

[0033] The processor 33 determines the memory area of ​​the NAND flash memory 40 to write to for each unit data. A physical address is assigned to the memory area of ​​the NAND flash memory 40. The processor 33 manages the memory area to which the unit data is written using the physical address. The processor 33 instructs the memory interface 36 to write the user data to the NAND flash memory 40 by specifying the determined memory area (physical address). The processor 33 manages the correspondence between the logical address (logical address managed by the host 20) and the physical address of the user data. When the processor 33 receives a read command from the host 20 that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 36 to read the user data by specifying the physical address.

[0034] The ECC circuit 35 is a circuit that encodes user data stored in the RAM 31 and generates codewords. The ECC circuit 35 also decodes codewords read from the NAND flash memory 40. Figure 2 shows an example configuration in which the memory controller 30 is equipped with both the ECC circuit 35 and the memory interface 36, but the ECC circuit 35 may be built into the memory interface 36 or into the NAND flash memory 40.

[0035] RAM31 temporarily stores user data received from the host 20 before storing it in the NAND flash memory 40, and also temporarily stores data read from the NAND flash memory 40 before sending it to the host 20. RAM31 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0036] When the memory system 10 receives a write request from the host 20, it operates as follows: The processor 33 temporarily stores the write data in the RAM 31. The processor 33 reads the data stored in the RAM 31 and inputs it to the ECC circuit 35. The ECC circuit 35 encodes the input data and inputs the codeword to the memory interface 36. The memory interface 36 writes the input codeword to the NAND flash memory 40.

[0037] When the memory system 10 receives a read request from the host 20, it operates as follows: The memory interface 36 inputs the codeword read from the NAND flash memory 40 to the ECC circuit 35. The ECC circuit 35 decodes the input codeword and stores the decoded data in the RAM 31. The processor 33 transmits the data stored in the RAM 31 to the host 20 via the host interface 34. Note that the NAND flash memory 40 may consist of multiple chips, and the NAND flash memory 40 and the memory interface 36 can also be connected via an interface chip that relays data and control signals.

[0038] Note that the configuration of the memory controller 30 shown in Figure 2 is just one example, and it can take on various other derivative forms, such as having a segmented or hierarchical internal bus, or having additional functional blocks connected.

[0039] Figure 3 shows the circuit configuration of one of several block blocks within a three-dimensional NAND flash memory cell array (MCA). The other block blocks in the NAND flash memory cell array (MCA) have a similar circuit configuration to that shown in Figure 3.

[0040] As shown in Figure 3, block BLK has, for example, four finger FNGs (FNG0 to FNG3). Each finger FNG contains multiple NAND strings NS. Each NAND string NS has, for example, eight cascaded memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. In this specification, each finger FNG may be referred to as string St. Note that the number of memory cell transistors MT in a NAND string NS is not limited to eight.

[0041] The memory cell transistors MT are positioned so that their current paths are connected in series between the selection transistors ST1 and ST2. The current path of memory cell transistor MT7 on one end of this series connection is connected to one end of the current path of selection transistor ST1, and the current path of memory cell transistor MT0 on the other end is connected to one end of the current path of selection transistor ST2.

[0042] The gates of the selection transistors ST1 of each of the finger FNG0 to FNG3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same select gate line SGS across multiple finger FNGs. Furthermore, the control gates of the memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. In other words, the word lines WL0 to WL7 and the select gate line SGS are commonly connected across multiple finger FNG0 to FNG3 within the same block BLK, while the select gate line SGD is independent for each of the finger FNG0 to FNG3, even within the same block BLK.

[0043] The control gate electrodes of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. In each NAND string NS within the same finger FNG, the i-th memory cell transistor MTi (where i is an integer from 0 to 7) from one side is similarly connected by the i-th word line WLi. That is, the control gate electrodes of memory cell transistors MTi in the same row within block BLK are connected to the same word line WLi. Each NAND string NS is connected to both the word line WLi and the bit line BL. Each memory cell MC within each NAND string NS can be identified by an address that identifies the word line WLi and select gate lines SGD0 to SGD3, and an address that identifies the bit line BL.

[0044] As described above, data in memory cells MC (memory cell transistors MT) within the same block BLK is erased collectively. On the other hand, data reading and writing are performed in units of physical memory cell groups MG. One physical memory cell group MG is connected to one word line WLi and includes multiple memory cells MC belonging to one finger FNG. The memory controller 30 writes (programs) to all memory cells MC connected to one word line WL within one finger FNG. Therefore, the unit of data that the memory controller 30 programs is 3 bits × (number of bit lines BL). The unit that identifies these 3 bits is called a page.

[0045] During read and program operations, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical memory cell group MG is selected. In this specification, writing data to the memory cell MC is referred to as programming, as needed.

[0046] Figure 4A is a cross-sectional view of a portion of the three-dimensional NAND flash memory cell array (MCA). Figure 4B is an enlarged cross-sectional view of region R1 shown in Figure 4A. As shown in Figure 4A, multiple NAND strings NS are formed on the p-type well region (P-well). Specifically, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WL), and multiple wiring layers 331 functioning as select gate lines (SGD) are formed on the p-type well region (P-well). Memory holes are formed that penetrate these wiring layers 331, 332, and 333 and reach the p-type well region (P-well).

[0047] As shown in Figure 4B, a block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side of the memory hole, and a conductive film 338 is embedded within the memory hole. The conductive film 338 functions as the current path of the NAND string NS and is the region where a channel is formed when the memory cell transistor MT and the selection transistors ST1 and ST2 are operating. As shown in Figure 4B, an insulating layer 101, such as silicon oxide (SiO2), may be provided between the wiring layers 331, 332, and 333.

[0048] In each NAND string NS, a selection transistor ST2, multiple memory cell transistors MT, and a selection transistor ST1 are sequentially stacked on the p-type well region P-well. A wiring layer that functions as a bit line BL is formed on the upper edge of the conductive film 338.

[0049] Furthermore, an n+-type impurity diffusion layer 350 and a p+-type impurity diffusion layer 351 are formed within the surface of the p-type well region (P-well). A contact plug 340 is formed on the n+-type impurity diffusion layer, and a wiring layer that functions as a source line SL is formed on the contact plug 340. A contact plug 339 is formed on the p+-type impurity diffusion layer 351, and a wiring layer that functions as a well wiring CPWELL is formed on the contact plug 339.

[0050] The configuration shown in Figure 4A is arranged in multiple locations in the depth direction of the page in Figure 4A, and one finger FNG is formed by a collection of multiple NAND strings NS arranged in a line in the depth direction. Other finger FNGs are formed, for example, in the left-right direction of Figure 4A. Figure 3 shows four finger FNGs FNG0 to FNG3, but Figure 4A shows an example in which three finger FNGs are arranged between contact plugs 339 and 340.

[0051] Furthermore, this embodiment can be applied not only to three-dimensional memory cell MCs but also to two-dimensional memory cell MCs.

[0052] [Threshold distribution of non-volatile memory] Figure 5 shows an example of a threshold voltage range. In Figure 5, the horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. Figure 5 shows an example of the threshold distribution for a 3-bit / cell non-volatile memory. In non-volatile memory, information is stored by the amount of charge stored in the charge storage layer 336 of the memory cell MC. Each memory cell MC has a threshold voltage corresponding to the amount of charge. Multiple data values ​​to be stored in the memory cell MC are then associated with multiple regions (threshold regions) of the threshold voltage.

[0053] The bell-shaped distributions DS0, DS1, DS2, DS3, DS4, DS5, DS6, and DS7 in Figure 5 represent the threshold voltage distributions within the eight threshold voltage regions S0 to S7. Thus, each memory cell MC has a threshold voltage distribution separated by seven boundaries. In this embodiment, the region where the threshold voltage is less than or equal to voltage Vr1 is called region S0, the region where the threshold voltage is greater than voltage Vr1 and less than or equal to voltage Vr2 is called region S1, the region where the threshold voltage is greater than voltage Vr2 and less than or equal to voltage Vr3 is called region S2, and the region where the threshold voltage is greater than voltage Vr3 and less than or equal to voltage Vr4 is called region S3. In this embodiment, the region where the threshold voltage is greater than voltage Vr4 and less than or equal to voltage Vr5 is called region S4, the region where the threshold voltage is greater than voltage Vr5 and less than or equal to voltage Vr6 is called region S5, the region where the threshold voltage is greater than voltage Vr6 and less than or equal to voltage Vr7 is called region S6, and the region where the threshold voltage is greater than voltage Vr7 is called region S7. The threshold distributions corresponding to regions S0, S1, S2, S3, S4, S5, S6, and S7 are called distributions DS0, DS1, DS2, DS3, DS4, DS5, DS6, and DS7, respectively. Voltages Vr1 to Vr7 are the threshold voltages that mark the boundaries of each region.

[0054] In non-volatile memory, multiple data values ​​are associated with multiple threshold regions (i.e., threshold distributions) of a memory cell MC. This association is called data coding. This data coding is predetermined, and when writing data (programming), charge is injected into the memory cell MC according to the data coding so that it falls within the threshold region corresponding to the data value to be stored. When reading, a read voltage is applied to the memory cell MC, and the data is determined by whether the threshold voltage of the memory cell MC is lower or higher than the read voltage. If the threshold voltage is lower than the read voltage, it is in an "erased" state, and the data value is defined as "1". If the threshold voltage is equal to or greater than the read voltage, it is in a "programmed" state, and the data is defined as "0".

[0055] Figure 6 shows the data coding for 3-bit / Cell. In this embodiment, the eight threshold distributions (threshold regions) shown in Figure 5 are each associated with eight 3-bit data values. The relationship between the threshold voltage and the data values ​​of the bits corresponding to the Upper, Middle, and Lower pages is as follows. • Memory cells MC whose threshold voltage is within region S0 are storing "111". • Memory cells MC whose threshold voltage is within region S1 are storing "110". • Memory cells MC whose threshold voltage is within region S2 are storing the value "100". • Memory cells MC whose threshold voltage is within region S3 are in a state where they are storing "000". • Memory cells MC whose threshold voltage is within region S4 are storing "010". • Memory cells MC whose threshold voltage is within region S5 are storing "011". • Memory cells MC whose threshold voltage is within region S6 are storing "001". • Memory cells MC whose threshold voltage is within region S7 are storing the value "101".

[0056] In this way, the state of the 3-bit data of each memory cell MC can be represented for each threshold voltage region. Note that when the memory cell MC is in an unwritten state ("erased" state), the threshold voltage of the memory cell MC is within region S0. Furthermore, in the data coding shown here, only one bit of data changes between any two adjacent states, such as storing the data "111" in region S0 and storing the data "101" in region S1. Thus, the coding shown in Figure 6 is a Gray code in which only one bit of data changes between any two adjacent regions.

[0057] In the coding of this embodiment shown in Figure 6, the threshold voltages that serve as boundaries for determining the bit values ​​of each page are as follows: The threshold voltages used to determine the bit values ​​on the upper page are voltages Vr3 and Vr7. The threshold voltages used to determine the bit values ​​of the Middle page are voltages Vr2, Vr4, and Vr6. The threshold voltages used to determine the bit values ​​of the lower page are voltages Vr1 and Vr5.

[0058] Thus, the number of threshold voltages that serve as boundaries for determining bit values ​​(hereinafter referred to as the boundary number) is 2, 3, and 2 for the Lower page, Middle page, and Upper page, respectively. This type of coding, using the respective boundary numbers for the Lower, Middle, and Upper pages, is called 2-3-2 coding.

[0059] In this embodiment, the 2-3-2 coding will be used as an example. The correspondence between multiple threshold regions and data values ​​of the memory cell MC can also be expressed with other data coding, but all examples will not be shown. In this embodiment, the type of data coding is not important, but generally, data coding is selected that minimizes the bias in the number of boundaries distributed to each page. In that case, because the bias in the number of boundaries between pages is small, the resulting bias in the bit error rate between pages is also small. This is because most bit errors are caused by changes in threshold values ​​in adjacent threshold regions, and pages with more boundaries tend to have more bit errors. This means that even if the error rate of the memory cell MC is the same, the correction capability of the ECC required to correct errors in page data must be strengthened, which is effective in suppressing deterioration of the response performance, cost, and power consumption of the memory system 10 to write or read requests from the host 20. In addition, the bias in read speed caused by the bias in the number of boundaries is also reduced.

[0060] [Read operation] Next, the page read process will be explained. According to the 2-3-2 data coding shown in Figure 6, there are two boundaries between threshold states where the lower page data changes. Therefore, the control unit CTU (Figure 1) determines the data based on which of the three ranges separated by these boundaries the threshold falls into. For example, if the threshold voltage is less than voltage Vr1, the control unit CTU outputs "1" as the data for the memory cell MC. Also, if the threshold voltage is greater than voltage Vr5, the control unit CTU outputs "1" as the data for the memory cell MC. Furthermore, if the threshold voltage is less than voltage Vr5 and greater than voltage Vr1, the control unit CTU outputs "0" as the data for the memory cell MC. Since there are three boundaries between threshold states where the physical middle page data changes, the control unit CTU determines the value of the read data to be either "0" or "1" based on which of the four ranges separated by these boundaries the threshold falls into. Since there are two boundaries between threshold states where the data on the upper page changes, the control unit (CTU) determines whether the value of the read data is "0" or "1" depending on which of the three ranges separated by those boundaries the threshold falls into.

[0061] The following describes the specific procedure for page retrieval. Figure 7 is a flowchart showing the page retrieval procedure.

[0062] As shown in Figure 7, the control unit (CTU) selects a read page (step S101).

[0063] If the page to be read is the Lower page, the control unit CTU first reads at voltage Vr1 (step S102). Next, the control unit CTU reads at voltage Vr5 (step S103). Then, based on the reading results at voltage Vr1 and voltage Vr5, the control unit CTU determines whether the value of the read data is "0" or "1" (step S104). The control unit CTU then transfers this one page of data from the S / A to the data latch XDL (step S105).

[0064] In the above explanation, when reading the lower page, we described the process as being performed in order of increasing voltage, Vr1 followed by Vr5. However, the reverse order, with increasing voltage, is also acceptable: Vr5 followed by Vr1. This is illustrated in Figures 8(a) and 8(b), respectively.

[0065] If the page to be read is the Middle page, the control unit (CTU) performs the read operation using three read voltages. These voltages are the Middle page read voltages Vr2, Vr4, and Vr6. Based on the results of the read operation at the threshold voltage of voltage Vr2 (step S112), the read operation at the threshold voltage of voltage Vr4 (step S113), and the read operation at the threshold voltage of voltage Vr6 (step S114), the control unit (CTU) determines the value of the read data to be either "0" or "1" (step S115). The control unit (CTU) then transfers this one page of data from the S / A to the data latch XDL (step S116).

[0066] Although the above explanation states that the Middle page is read in ascending order of voltage Vr2, Vr4, and Vr6, it is also acceptable to read in the reverse order of ascending voltage Vr6, Vr4, and Vr2. This is shown in Figures 8(c) and 8(d), respectively.

[0067] If the page to be read is an Upper page, the control unit CTU performs a read using two read voltages. These voltages are the Upper page read voltages, Vr3 and Vr7. The control unit CTU then determines the value of the read data to be "0" or "1" based on the result of reading at the threshold voltage of voltage Vr3 (step S122) and the result of reading at the threshold voltage of voltage Vr7 (step S123) (step S124). The control unit CTU then transfers this one page of data from the S / A to the data latch XDL (step S125).

[0068] In addition, while the above explanation states that the reading of the upper page is performed in order of increasing voltage (Vr3, then Vr7), it is also acceptable to read in the reverse order (Vr7, then Vr3, with increasing voltage). This is shown in Figures 8(e) and 8(f), respectively.

[0069] Another example of a read sequence is a sequential read as shown in Figure 8(g) or Figure 8(h). This read method assumes that the Lower, Middle, and Upper pages are output to the external network in succession, and the internal read is performed for all read voltages. In this case, the internal read is controlled by sequentially increasing the read voltage from the lowest voltage (Figure 8(g)) or sequentially decreasing it from the highest voltage (Figure 8(h)), which reduces the voltage change range of the word line WL, shortens the time required for voltage transitions, and consequently has the advantage of speeding up the read. External output becomes possible after the read at voltage Vr5, which is the read of the physical Lower page, is completed. Also, since it becomes necessary to simultaneously hold the data for three pages, three data latches ADL, BDL, and XDL are used to save the page read data.

[0070] [Write operation] Next, the program will be explained. The non-volatile memory control unit (CTU) controls the programming of the NAND flash memory cell array (MCA) based on the data coding shown in Figure 6.

[0071] In the case of 3D memory cells, if the size of the memory cells (MCs) is still in a generation where miniaturization has not yet progressed and the spacing between adjacent memory cells (MCs) is wide, then interference between adjacent memory cells is small. In this case, a method is generally used to program all bits simultaneously (all pages simultaneously if each bit is assigned to a different page). Based on the data of all bits, it is determined where in the eight threshold distributions the memory cell is located, and the memory is programmed from the erased region S0 to the determined region. Interference between adjacent memory cells will be described in detail later.

[0072] [A technique for programming all bits simultaneously] Figure 9 shows the threshold distribution when all bits are programmed simultaneously. Figure 9(T1) shows the threshold distribution in the erased state, which is the initial state before programming, and Figure 9(T2) shows the threshold distribution after programming.

[0073] As shown in Figure 9 (T1), all memory cells MC in the NAND flash memory cell array MCA are in a state where their distribution is in region S0 when they are unwritten ("erased"). As shown in Figure 9 (T2), the control unit CTU of the non-volatile memory, according to the program, either keeps the distribution of each memory cell MC in region S0 or injects charge to move the distribution to regions S1 to S7 above region S0, depending on the bit values ​​to be written (stored) in the Lower page, Middle page, and Upper page.

[0074] Specifically, the control unit (CTU) does not inject charge if the bit values ​​to be written to the Lower, Middle, and Upper pages are all "1". The control unit (CTU) is programmed to inject charge and move the threshold voltage to a higher value if any one of the bit values ​​to be written to the Lower, Middle, and Upper pages is "0".

[0075] In other words, the threshold voltage distribution is moved as follows: to area S1 if the bit value written to the Lower, Middle, and Upper pages is "110"; to area S2 if the bit value written to the Lower, Middle, and Upper pages is "100"; to area S3 if the bit value written to the Lower, Middle, and Upper pages is "000"; to area S4 if the bit value written to the Lower, Middle, and Upper pages is "010"; to area S5 if the bit value written to the Lower, Middle, and Upper pages is "011"; to area S6 if the bit value written to the Lower, Middle, and Upper pages is "001"; and to area S7 if the bit value written to the Lower, Middle, and Upper pages is "101".

[0076] Typically, programming is performed by applying one or more program voltage pulses to the word line WL. When applying multiple program voltage pulses, the voltage value is increased in steps. After each program voltage pulse, a read operation called verification is performed to confirm whether the memory cell MC has moved beyond the threshold boundary level. By repeating this application and read operation, it is possible to move the threshold of the memory cell MC within a predetermined threshold distribution range.

[0077] Figure 10(a) is a flowchart showing an example of the program order for an entire block BLK when all bits are programmed simultaneously. This flowchart shows an example of the program order when there are four strings St in the block BLK. Hereafter, these four strings St will be referred to as strings Stj, using string number j (where j is an integer from 0 to 3). Also, hereafter, one block BLK is assumed to have n+1 word lines WLi, represented as word lines WL0 to WLn (where n is a natural number), using word line number i (where i is an integer from 0 to n). The memory controller 30 proceeds with the programming of the word lines WLi in a continuous order, and executes the program as a unit of program sequence for a given group of word lines WLi (in this case, a block BLK).

[0078] When writing begins, the control unit CTU (Figure 1), based on instructions from the processor 33 (Figure 2), sequentially selects word lines WLi and strings St in a predetermined order as shown in Figure 10(a) and executes the program continuously. Word lines WL are selected in order from the smallest word line number i, as shown in Figure 11. Multiple physical memory cell groups MG corresponding to the same word line number i are selected in order from the smallest string number j. Once the programming of all strings St0 to St3 (all physical memory cell groups MG) corresponding to one word line WLi is complete, the word line WLi+1 corresponding to the next word line number i+1 is selected. In the following explanation, although the operation of the control unit CTU's program is based on instructions from the processor 33, for the sake of simplicity, this statement will be omitted.

[0079] In the example shown in Figure 10(a), the control unit CTU first executes the program for string St0 of word line WL0 (step S201). Next, the control unit CTU executes the program for string St1 of word line WL0 (step S202). Next, the control unit CTU executes the program for string St2 of word line WL0 (step S203). Next, the control unit CTU executes the program for string St3 of word line WL0 (step S204). Next, the control unit CTU executes the program for string St0 of word line WL1 (step S205). Next, the control unit CTU executes the program for string St1 of word line WL1 (step S206). Similarly, the control unit CTU continues processing in the order of the arrows in Figure 10(a) until it reaches the last word line in block BLK (steps S207 to S212).

[0080] Note that while Figures 10(a) and 11 illustrate the case where there are four strings St within block BLK, there may be three or fewer strings St within block BLK, or five or more strings St.

[0081] Figure 10(b) is a subflowchart showing the procedure for writing a single word line WL when all bits are programmed simultaneously. In this program, first, a command to start inputting lower page data is input from the memory controller 30 (Figure 2) to the NAND flash memory 40. Then, the lower page data is input from the memory controller 30 to the data latch XDL of the NAND flash memory 40 (step S301). When the control unit CTU (Figure 1) detects that the input of data from the outside has finished, it transfers the data in the data latch XDL to the data latch ADL (step S302).

[0082] Next, a command to start inputting Middle page data is input from the memory controller 30 to the NAND flash memory 40. Then, Middle page data is input from the memory controller 30 to the data latch XDL of the NAND flash memory 40 (step S303). When the control unit CTU detects that the input of data from the outside has finished, it transfers the data in the data latch XDL to the data latch BDL (step S304).

[0083] Next, the memory controller 30 inputs a command to start inputting upper page data to the NAND flash memory 40. Then, the memory controller 30 inputs upper page data to the XDL of the NAND flash memory 40 (step S305). When the control unit CTU detects that the input of data from the outside has finished, it transfers the data in the XDL to the CDL (step S306).

[0084] Up to this point, the data for the Lower, Middle, and Upper pages necessary for programming the word line WL has been transferred to the data latches ADL, BDL, and CDL, respectively, and the data preparation is complete. Furthermore, a program execution command is input from the memory controller 30 to the NAND flash memory 40, which makes the chip busy. Then, based on the combination of the previously input Lower, Middle, and Upper page data, the Vth (threshold voltage) of the programming destination for each memory cell MC is determined (step S307). After this, the data for the three pages is written using the determined Vth.

[0085] During data writing, one or more program voltage pulses are applied (step S308). For the first program voltage, an initial voltage is applied. For subsequent program voltages, the voltage may be increased by a predetermined voltage range from the initial voltage. Then, data is read (verified) to confirm whether the memory cell MC has moved beyond the threshold boundary level (step S309). The read level at this time is a predetermined level.

[0086] Furthermore, it is checked whether the number of fail bits in the data in each memory threshold region is smaller than the criterion (judgment standard) (step S310). If the number of fail bits in the data is greater than or equal to the criterion, the process from program pulse application to criterion determination (steps S308 to S310) is repeated. When the number of fail bits in the data becomes smaller than the criterion, the chip becomes ready. In this way, by repeating the application, reading, and check, it is possible to move the threshold of the memory cell MC within a predetermined threshold distribution range.

[0087] Note that the predetermined read level after applying the program voltage pulse during writing may differ slightly from the read level after writing, and is preferably higher than the read level after writing. This is to create a margin for threshold determination during reading after writing. When the number of fail bits in all threshold areas of data becomes smaller than the criteria, the chip becomes ready.

[0088] [Interference between adjacent cells] Here, we will explain interference between adjacent memory cells. The first type of interference between adjacent memory cells occurs when the charge accumulated in the charge storage layer 336 (Figure 4B) of one memory cell MC disturbs the electric field of an adjacent memory cell MC, resulting in noise that fluctuates the threshold voltage when reading the adjacent memory cell MC. When programming and verification are performed under certain electric field conditions, and after the program is completed, if an adjacent memory cell MC is programmed with a different charge, the threshold voltage will fluctuate to a higher value due to the influence of the electric field, which will degrade the read accuracy. Typically, if a memory cell MC adjacent to a memory cell MC located in a low threshold voltage distribution is programmed to a high threshold voltage distribution after the program is completed on the adjacent memory cell MC, the threshold voltage will rise after the program is completed on the adjacent memory cell MC. This interference between adjacent memory cells becomes more pronounced as memory device manufacturing technology is miniaturized and the spacing between memory cells decreases. This interference between adjacent memory cells mainly occurs between adjacent memory cell MCs connected to different word lines on the same bit line BL.

[0089] Another type of interference between adjacent memory cells, stemming from a different physical phenomenon, is charge coupling between adjacent cells. If there is a difference in the amount of charge stored in the charge storage layer 336 of one memory cell MC and the amount of charge stored in the charge storage layer 336 of an adjacent memory cell MC, i.e., a difference in threshold voltage, then the charges will gradually couple and neutralize in the boundary region between adjacent cells over time after programming. This becomes noise that fluctuates the threshold voltage, leading to a deterioration in read accuracy. Typically, when a memory cell MC located in a high threshold voltage distribution is adjacent to a memory cell MC located in a low threshold voltage distribution, the threshold voltage of the memory cell MC in the high threshold voltage distribution decreases, while the threshold voltage of the memory cell MC in the low threshold voltage distribution increases. The memory cell MC in the high threshold voltage distribution experiences a particularly large decrease in threshold voltage, partly due to the time-dependent leakage of the programmed charge. This interference between adjacent memory cells also becomes more pronounced as memory device manufacturing technology becomes more miniaturized and the spacing between memory cells decreases. Similarly, this interference between adjacent memory cells also occurs primarily between adjacent memory cells (MCs) connected to different word lines on the same bit line (BL).

[0090] [Foggy-Fine Program] The first type of interference between adjacent memory cells can be mitigated by reducing the difference in the electric field conditions of the memory cells MC during programming and verification, and during reading after the adjacent memory cell MC has been programmed. One method to reduce interference between adjacent memory cells MC connected to different word lines WL on the same bit line BL is to employ a programming method (Foggy-Fine program) that uses multiple programming stages, for example, two programming stages (hereinafter sometimes simply referred to as stages), to gradually inject charge into the charge storage layer 336 of the memory cell MC. In this Foggy-Fine program, after writing to the memory cell MC in the first stage (Foggy stage), writing to the adjacent cell is performed, and then the process returns to the first memory cell MC to perform the writing in the second stage (Fine stage). In this case, each stage is a program execution unit, and the programming of a memory cell MC corresponding to one word line WLi is completed by executing two programming stages.

[0091] In both the first and second stage programs, the program is executed using eight threshold regions. The threshold distribution of the threshold regions at the end of the first stage program has a wider range than the threshold distribution of the threshold regions in the final data coding. In other words, in the Foggy stage, a Foggy (rough) write is performed. In this Foggy stage program, all three pages of input data are required. The threshold distribution after the Foggy stage program is an intermediate state where adjacent distributions overlap, so data cannot be read. In the second stage, the Fine stage program, the threshold regions after the Foggy stage program are moved to the threshold regions in the final data coding. In other words, a Fine write is performed in the Fine stage. In this Fine stage program, all three pages of input data are also required. The threshold distribution after the Fine stage program is the final state where adjacent distributions are separated, so data can be read after the Fine stage program.

[0092] When significant interference between adjacent memory cells is anticipated, the program sequence is programmed using a Foggy-Fine program. Figure 12 shows the threshold distribution after programming in the Foggy-Fine program. (T1) in Figure 12 shows the threshold distribution in the erased state, which is the initial state before programming. (T2) in Figure 12 shows the threshold distribution after the 1st stage program (Foggy program). (T3) in Figure 12 shows the threshold distribution after the 2nd stage program (Fine program).

[0093] As shown in Figure 12 (T1), the threshold voltage of all memory cells MC in the NAND flash memory cell array MCA is in region S0 when the cell is unwritten ("erase" state).

[0094] As shown in (T2) of Figure 12, the control unit CTU of the NAND flash memory 40, in the first stage program, either keeps the threshold distribution in region S0 for each memory cell MC, or injects charge to move it to regions S1 to S7 above region S0, depending on the bit values ​​to be written (stored) in the Lower page, Middle page, and Upper page. The correspondence between the bit values ​​to be written and the threshold regions is as described above. Here, in regions S1 to S7, the threshold distribution is programmed coarsely by widening its width so that the threshold voltage is somewhat lower.

[0095] As a result, the memory cell MC is programmed into an 8-level threshold distribution using data from the Lower, Middle, and Upper pages. However, because the threshold distribution is wide and overlaps with other adjacent threshold distributions, data reading is impossible. Nevertheless, since the threshold distribution after this first stage of programming does not need to be narrowed down, high-speed programming is possible.

[0096] Furthermore, as shown in (T3) of Figure 12, the 2nd stage program also requires data from all pages—Lower, Middle, and Upper—for data writing. The control unit CTU of the NAND flash memory 40 then programs the threshold distribution to be separated into eight threshold regions after the 2nd stage program. This makes it possible to read all page data. In the 2nd stage program, the larger the change in the threshold voltage of the memory cell MC from the end of the 1st stage program, the greater the interference between the first adjacent cells. Therefore, it is preferable that the change in threshold voltage from the 1st stage to the 2nd stage threshold voltage is small.

[0097] Typically, writing (programming) to a memory cell MC is performed by applying one or more program voltage pulses to the corresponding word line WL. After each program voltage pulse is applied, a read operation is performed to confirm whether the memory cell MC has moved beyond the threshold boundary level. By repeating this application and read operation, it becomes possible to move the threshold voltage of the memory cell MC within a predetermined region S1 to S7. The threshold voltage of the corresponding memory cell MC is determined from the data of all pages to be written, and the voltage values ​​of multiple program pulses are gradually increased and written until the determined threshold voltage is reached. Memory cell MCs that have reached the target threshold voltage are excluded from writing.

[0098] Furthermore, the control unit CTU, instead of executing the 1st stage program and the 2nd stage program consecutively for multiple physical memory cell groups MG corresponding to a single word line WLi, executes the program in a discontinuous order across multiple word lines WLi in order to reduce the effects of interference between adjacent memory cells.

[0099] Figure 13 shows the program sequence of a Foggy-Fine program. The example shown in Figure 13 illustrates an example of the program sequence in a NAND flash memory 40 in which four strings St0 to St3 are connected to each word line WLi within each block BLK. In the example shown in Figure 13, programming is performed in two programming stages to minimize the effects of interference between the first adjacent memory cells.

[0100] When writing begins, the control unit CTU (Figure 1) proceeds through each program stage, traversing word lines WLi in a predetermined discontinuous order. That is, the 1st and 2nd stages for the same word line WL are not executed consecutively. After programming the 1st stage for all physical memory cell groups MG corresponding to a certain word line WLi, the 2nd stage program is executed for all physical memory cell groups MG corresponding to the previous word line WLi-1. If the 1st and 2nd stage programs are executed consecutively for the adjacent word line WLi+1 after completing the 2nd stage program for a certain word line WLi, the threshold voltage fluctuation will become large in multiple memory cells MC corresponding to the word line WLi. And if the threshold voltage fluctuation of the adjacent word line WLi+1 is large, the interference between adjacent memory cells between word lines WLi and word lines WLi+1 will increase.

[0101] To minimize interference between adjacent memory cells between word lines WL, it is effective to suppress the fluctuation of the threshold voltages of multiple memory cells MC corresponding to a word line WLi, caused by the program corresponding to the adjacent word line WLi+1 after the word line WLi has completed programming up to the 2nd stage. In the order shown in Figure 13, after a word line WLi has completed programming up to the 2nd stage, the programming stage of the adjacent word line WLi+1 is only the 2nd stage, thus effectively suppressing fluctuations in the threshold voltages of multiple memory cells MC corresponding to the word line WLi.

[0102] Note that while Figure 13 illustrates the case where there are four strings St within block BLK, there may be three or fewer strings St within block BLK, or five or more strings.

[0103] For example, in the example shown in Figure 4A, among the multiple word lines WL arranged in the Z direction, the adjacent word line WL to the k-th word line WL (where k is a natural number) from one side is either the (k-1)th word line WL or the (k+1)th word line WL from the other side.

[0104] [Rewrite operation] Next, the rewrite operation will be explained. In the first embodiment, the Foggy-Fine program is used to counter the first interference between adjacent memory cells, and the rewrite operation is used to counter the second interference between adjacent memory cells.

[0105] Figure 14 is a flowchart showing an example of the program sequence for the entire block BLK in the first embodiment. Figures 15(a) and 15(b) show examples of the order in which word lines WL are selected during programming in the first embodiment.

[0106] When writing begins, the control unit CTU (Figure 1), based on instructions from the processor 33 (Figure 2), sequentially selects word lines WL0 to WLn and strings St0 to St3 in a predetermined order as shown in Figure 14, and executes the program continuously. The word lines WL are selected in order from the smallest word line number i, as shown in Figures 15(a) and 15(b). In addition, multiple physical memory cell groups MG corresponding to the same word line number i are selected in order from the smallest string number j.

[0107] In the example in Figure 15(a), the 1st stage programming is performed for all strings St0 to St3 (all physical memory cell groups MG) corresponding to one word line WLi, then the 2nd stage programming is performed for all physical memory cell groups MG corresponding to the previous word line WLi-1, and finally, the 3rd stage programming is performed for all physical memory cell groups MG corresponding to word line WLi-1.

[0108] In the example in Figure 15(b), the 1st stage program is performed for all strings St0 to St3 (all physical memory cell groups MG) corresponding to one word line WLi, and then the 2nd stage program and the 3rd stage program are performed sequentially for all physical memory cell groups MG corresponding to the previous word line WLi-1.

[0109] There are three programming stages. The programs for the 1st and 2nd stages are the same as the conventional Foggy-Fine program, with the addition of a 3rd stage program (rewrite). The 3rd stage program is executed after the 2nd stage program has completed for all strings St0 to St3 within word line number i, returning to the first string number 0 within the same word line number i, and proceeding in ascending order of string number j.

[0110] Note that while Figures 14 and 15(a) describe the case where there are four strings St in block BLK, there may be three or fewer strings St in block BLK, or five or more strings. The procedure for writing a single word line WLi is basically the same as the explanation in Figure 10(b), so it will be omitted.

[0111] Figure 15(b) is a variation of Figure 15(a), showing an example where the 3rd stage program of word line WLi is executed immediately after the 2nd stage program of word line WLi. The example shown in Figure 15(b) has the advantage of simplifying the program sequence compared to the example shown in Figure 15(a) because the 3rd stage program is executed without changing the word line address. However, because it is immediately after the 2nd stage program, the initial charge leakage is not yet sufficient, and the rewrite is performed before the 2nd stage program of the next adjacent word line WLi+1, so the word line WLi in question has not been affected by the interference between adjacent cells until its final state. In other words, there is a disadvantage that the threshold voltage increase may not be as desired because the rewrite is performed before the threshold distribution has settled into its final form. Specifically, for example, by rewriting a memory cell MC that has not yet had sufficient initial charge leakage, the threshold voltage after the rewrite may become higher than expected and reach the region of the distribution adjacent to the high voltage side. This is called overwriting (overprogramming) and is one of the causes of data errors in NAND flash memory 40.

[0112] Figure 16 shows the threshold distribution after programming in the first embodiment. (T1) in Figure 16 shows the threshold distribution in the erase state, which is the initial state before programming. (T2) in Figure 16 shows the threshold distribution after the 1st stage programming (Foggy program). (T3) in Figure 16 shows the threshold distribution after the 2nd stage programming (Fine program). (T4) in Figure 16 shows the threshold distribution after the 3rd stage programming (reprogramming).

[0113] As shown in Figure 16 (T1), the threshold voltage of all memory cells MC in the NAND memory cell array is in region S0 when it is in an unwritten state ("erase" state).

[0114] As shown in (T2) of Figure 16, the control unit CTU of the NAND flash memory 40, in the first stage program, either keeps the threshold distribution in region S0 for each memory cell MC, or injects charge to move it to regions S1 to S7 with a threshold higher than region S0, depending on the bit value to be written (stored) in the Lower page, Middle page, and Upper page. The correspondence between the bit value to be written and the threshold region is as described above. Here, in regions S1 to S7, the threshold distribution is programmed coarsely by widening the width so that the threshold voltage is somewhat lower.

[0115] As a result, the memory cell MC is programmed into an 8-level threshold distribution using data from the Lower, Middle, and Upper pages. However, because the threshold distribution is wide and overlaps with other adjacent threshold distributions, data reading is impossible. Nevertheless, since the threshold distribution after this first stage of programming does not need to be narrowed down, high-speed programming is possible.

[0116] Furthermore, as shown in (T3) of Figure 16, the 2nd stage program also requires data from all pages—Lower, Middle, and Upper—for data writing. The control unit CTU of the NAND flash memory 40 is programmed after the 2nd stage program so that the threshold distribution is ultimately separated into eight threshold regions. This makes it possible to read all page data. In the 2nd stage program, the larger the change in the threshold voltage of the memory cell MC from the end of the 1st stage program, the greater the interference between the first adjacent cells. Therefore, it is preferable that the change in threshold voltage from the 1st stage to the 2nd stage threshold voltage is small.

[0117] For example, writing (programming) to a memory cell MC is performed by applying one or more program voltage pulses to the corresponding word line WL. After applying each program voltage pulse, a read operation is performed to confirm whether the memory cell MC has moved beyond the threshold boundary level. By repeating this application and read operation, it is possible to move the threshold distribution of the memory cell MC within a predetermined region S1 to S7. The threshold voltage of the corresponding memory cell MC is determined from the data of all pages to be written, and the voltage values ​​of multiple program pulses are gradually increased and written until the determined threshold voltage is reached. Memory cell MCs that have reached the target threshold voltage are excluded from the writing process.

[0118] As shown in (T4) of Figure 16, the control unit CTU of the NAND flash memory 40 performs a "weak" write in the 3rd stage program by adjusting the magnitude of the program voltage (set lower than the threshold voltage increase of the 2nd stage program) so that the threshold voltage increase caused by the application of a single program voltage pulse is small, targeting only the memory cells MC in areas S5 to S7, according to the bit values ​​to be written (stored) in the Lower page, Middle page, and Upper page. This prevents the threshold voltage of memory cells MC located on the higher side of the distribution from increasing, while only increasing the threshold voltage of those located on the lower side of the distribution.

[0119] In the 3rd stage program, verification may be performed, or it may be omitted. If verification is performed, the verification voltages Vr5', Vr6', Vr7' should be the same as or higher than the verification voltages (Vr5, Vr6, Vr7) in the 2nd stage program.

[0120] In the rewrite from area S5 to area S7 (3rd stage program), the memory cell MC to be written to is determined according to the written data of the adjacent cell.

[0121] Figure 17 shows an example of a combination of threshold regions between a target cell and an adjacent cell that is the target of program writing in the 3rd stage in the first embodiment. In Figure 17, the parts marked with "○" are the memory cells MC to be written to. The memory cells MC to be written to are memory cells MC in which the 3rd stage program of word line WLi is written to regions S5 to S7, and word line WLi+1 is written to regions S0 to S2.

[0122] Memory cell MCs in combinations other than those marked in Figure 17 are not targeted for writing in the 3rd stage program. Note that the combinations shown in Figure 17 are examples, and the combinations targeted for writing may be expanded or reduced depending on the strength of interference between adjacent cells, etc. In addition, for memory cell MCs corresponding to each region S5 to S7, at least one of the magnitude of the 3rd stage program voltage and the pulse width (application time) may be set individually. For example, the 3rd stage program voltage (initial voltage if verification is performed) may be greater than the 1st stage program voltage (initial voltage if verification is performed). For example, the 3rd stage program voltage (initial voltage if verification is performed) may be lower than the 2nd stage program voltage (initial voltage if verification is performed). For example, the application time of the 3rd stage program voltage may be longer than the application time of the 1st stage program voltage. For example, the application time of the 3rd stage program voltage may be shorter than the application time of the 2nd stage program voltage.

[0123] The advantages of limiting the memory cells (MCs) targeted for rewriting to those with significant inter-cell interference are as follows: Writing to a NAND flash memory cell involves applying a program voltage to the word line WLi and injecting charge into the charge storage layer 336 (Figure 4B). The amount of charge injected is typically determined by the program voltage. However, because each memory cell (MC) has individual differences in shape and characteristics, variations occur in the amount of charge injected among memory cells (MCs) connected to the same word line WLi and written to simultaneously. As a result, the threshold voltage range that rises with a single program pulse varies. Therefore, when writing to many memory cells (MCs) simultaneously, a small number of memory cells (MCs) will, with a certain probability, experience an unexpectedly large threshold voltage increase, and some of these may even reach the distribution region adjacent to the high-voltage side. This is called overwriting (overprogramming) and is one of the causes of data errors in the NAND flash memory 40. Limiting the memory cells (MCs) targeted for rewriting to only those necessary and reducing the number of memories has the effect of suppressing the occurrence of overwriting.

[0124] The determination of the combination of distributions of adjacent cells to be written to in the 3rd stage program shown in Figure 17 is performed, for example, by using the written data held in the data buffer (RAM 31) of the memory controller 30. For example, determining that the write distribution of word line WLi is in area S5 and the write distribution of word line WLi+1 is in area S0 is done by determining that the bit value written to each page of word line WLi is "011" and the bit value written to each page of the adjacent word line WLi+1 is "111".

[0125] When the memory controller 30 executes programs in the order shown in Figure 15(a) or Figure 15(b), it moves back and forth through word line number i, including cases where one word line i is skipped. Therefore, the data buffer (RAM 31) must always hold page data for three consecutive word lines WL. In other words, when the program in the 3rd stage of word line WLi is executed, it is immediately after the execution of the program in the 2nd stage of word line WLi, and between the program in the 1st stage and the program in the 2nd stage of word line WLi+1. As a result, the page data for both word line WLi and word line WLi+1 exists in the data buffer (RAM 31) of the memory controller 30, and calculations using this data are easy.

[0126] Figure 18 shows the control flow of write data in the first embodiment. Here, it is assumed that the memory interface 36 in the memory controller 30 performs the determination calculation of the memory cell MC to be written by the 3rd stage program. The 3rd stage program performs write control for each threshold region.

[0127] First, the write data for word line WL0 is sent from the host interface 34 to the data buffer (RAM 31) (flow F10), and then sent from the data buffer (RAM 31) to the memory interface 36 (flow F11). The memory interface 36 then sends this write data for word line WL0 to the NAND flash memory 40 (flow F12), and the first stage program for word line WL0 is executed in the NAND flash memory 40.

[0128] Next, the write data for word line WL1 is sent from the host interface 34 to the data buffer (RAM 31) (flow F13), and then sent from the data buffer (RAM 31) to the memory interface 36 (flow F14). The memory interface 36 sends this write data for word line WL1 to the NAND flash memory 40 (flow F15), and the first stage program for word line WL1 is executed in the NAND flash memory 40.

[0129] Next, the write data for word line WL0 is sent from the data buffer (RAM 31) to the memory interface 36 (flow F16). The memory interface 36 sends this write data for word line WL0 to the NAND flash memory 40 (flow F17), and the 2nd stage program for word line WL0 is executed in the NAND flash memory 40.

[0130] Next, the write data for word lines WL0 and WL1 is sent from the data buffer (RAM 31) to the memory interface 36 (flow F18).

[0131] Next, for example, in the word line WL0, 3rd stage, area S5 program, according to the discrimination conditions shown in Figure 17, one page of data (rewrite data) is generated in which the bits where the write data for word line WL0 is in area S5 and the write data for word line WL1 is in areas S0 to S2 are write bits, and the other bits are non-write bits (step S501).

[0132] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F19), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0133] Next, the write data for word lines WL0 and WL1 is sent from the data buffer (RAM 31) to the memory interface 36 (flow F20).

[0134] Next, in the word line WL0, 3rd stage, area S6 program, according to the discrimination conditions shown in Figure 17, one page of data (rewrite data) is generated where the write data for word line WL0 is in area S6, the write data for word line WL1 is in areas S0 to S2, the bits are write bits, and the other bits are non-write bits (step S502).

[0135] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F21), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0136] Next, the write data for word lines WL0 and WL1 is sent from the data buffer (RAM 31) to the memory interface 36 (flow F22).

[0137] Next, in the word line WL0, 3rd stage, area S7 program, according to the discrimination conditions shown in Figure 17, one page of data (rewrite data) is generated in which the bits where the write data for word line WL0 is in area S7 and the write data for word line WL1 is in areas S0 to S2 are write bits, and the other bits are non-write bits (step S503).

[0138] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F23), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0139] Similarly, in the word lines WL2 and beyond (flows F24 to F28 and beyond), data is sent to the data buffer (RAM31), and one page of data for the 3rd stage program is generated in the memory interface 36.

[0140] In the example shown in Figure 18, the procedure for rewriting each cell in the rewrite target distribution with one page's worth of write data is shown, but all cells to be rewritten can also be treated as a single unit. For example, in the rewrite target conditions shown in Figure 17, it is possible to specify erase distribution data so that the cells corresponding to the threshold area S5 are treated as "011", the cells corresponding to area S6 are treated as "001", the cells corresponding to the threshold area S7 are treated as "101", and the remaining cells are treated as "111", i.e., cells that are not to be written. It is also possible to send such page data as rewrite data to the NAND flash memory 40 from the memory interface 36 and perform the write operation.

[0141] [effect] According to this embodiment, it is possible to increase the margin for data retention threshold downshift in memory cells (MCs) whose data retention deteriorates depending on the adjacent cell pattern, thereby providing a highly reliable memory system 10.

[0142] Furthermore, in this embodiment, since the selection of memory cells MC to be rewritten (generation of rewritten data) is performed by calculation from the written data, there is no need to perform a read operation from the memory cell MC corresponding to the word line WLi+1. Therefore, since the time required for read operations, data transfer between the memory chip and the memory controller 30, ECC decoding, etc., is unnecessary, the selection of memory cells MC to be rewritten can be performed at high speed.

[0143] Furthermore, the additional write operation according to this embodiment can be implemented without requiring an additional data buffer (RAM31) when a Foggy-Fine program is used as the program sequence. This is because the write data in the data buffer (RAM31) can be used to perform the determination calculation of the cells to be written in the 3rd stage program.

[0144] [Modified version of the first embodiment] Although this embodiment uses the 3-bit / Cell case as an example, it can be similarly applied to other multi-value numbers (2-bit / Cell, 4-bit / Cell, 5-bit / Cell, etc.).

[0145] Although the explanation used the Foggy-Fine program as an example, the same principles can be applied to other multi-stage programs. Furthermore, even program sequences that program all bits simultaneously can be similarly applied by holding the write data for multiple adjacent word lines (WL) in the controller's buffer.

[0146] In this embodiment, an example was shown in which the data buffer (RAM 31) of the memory controller 30 holds write data corresponding to three consecutive word lines WL in a specific writing order. However, such write data may also be held in a data buffer included in, for example, the NAND flash memory 40.

[0147] Furthermore, in this embodiment, the target cell for the rewrite operation is determined based on the data of multiple memory cells MC corresponding to the selected word line WLi and the data of multiple memory cells MC corresponding to the adjacent word line WLi+1. However, for example, the target cell for the rewrite operation may also be determined based on the data of multiple memory cells MC corresponding to the adjacent word line WLi-1 in addition to this data.

[0148] [Second Embodiment] The second embodiment adds a countermeasure against interference between adjacent memory cells using the Foggy-Fine program. However, since the means are largely the same as those in the first embodiment, they will be described with some omissions as appropriate.

[0149] Figure 19 shows the threshold distribution after programming in the second embodiment. (T1) in Figure 19 shows the threshold distribution in the erase state, which is the initial state before programming. (T2) in Figure 19 shows the threshold distribution after the 1st stage program (Foggy program). (T3) in Figure 19 shows the threshold distribution after the 2nd stage program (Fine program). (T1) to (T3) in Figure 19 are the same as explained in Figure 16, so they are omitted here.

[0150] Figure 19 (T3') shows the threshold voltage distribution after the first stage programming (Foggy program) to the next adjacent word line WL. Memory cells MC located in low threshold regions such as S0 to S3 experience a shift in threshold voltage towards the higher voltage side due to interference between the first adjacent cells, as the threshold voltage of the memory cell MC (adjacent cell) corresponding to the adjacent word line WL becomes higher after writing. As a result, the distribution of low threshold regions such as S0 to S3 widens upwards. Therefore, after the first stage programming to the next adjacent word line WL, the gap between the threshold voltage distributions of adjacent cells becomes narrower, especially in the low threshold regions, making data errors during reading more likely.

[0151] (T4) in Figure 19 shows the threshold region after the 3rd stage programming (reprogramming). As shown in (T4) in Figure 19, the control unit CTU of the NAND flash memory 40 performs "weak" writing in the 3rd stage programming by adjusting the magnitude of the program voltage (setting it lower than the threshold rise of the 2nd stage programming) so that the increase in the threshold voltage due to the application of a single program voltage pulse is small, targeting only the memory cells MC in threshold regions S1 to S3, according to the bit values ​​to be written (stored) in the Lower page, Middle page, and Upper page. As a result, the threshold voltage of memory cells MC located on the higher side of the distribution is not increased, and only the threshold voltage located on the lower side of the distribution is increased.

[0152] In this 3rd stage program, verification may be performed, or it may be omitted. If verification is performed, the verification voltage should be set to the same voltage as the verification voltage in the 2nd stage program, or a higher voltage.

[0153] During rewriting from threshold region S1 to region S3, the memory cell MC to be written to is determined according to the written data of the adjacent cell.

[0154] Figure 20 shows an example of a combination of threshold regions between a target cell and an adjacent cell that is the target of program writing in the 3rd stage in the second embodiment. In Figure 20, the 3rd stage program of the word line WLi, marked with a "○", is the memory cell MC to be written to, where the threshold voltage is in region S1 to region S3, and the threshold voltage of the adjacent memory cell MC on the word line WLi+1 is in region S0 to S2.

[0155] Memory cell MCs with combinations other than those marked in Figure 20 are not subject to writing. Note that the combinations shown in Figure 20 are examples, and the combinations subject to writing may be expanded or reduced depending on the strength of interference between adjacent cells, etc. In addition, for memory cell MCs corresponding to each region S5 to S7, at least one of the magnitude of the 3rd stage program voltage and the pulse width (application time) may be set individually. For example, the 3rd stage program voltage (initial voltage if verification is performed) may be greater than the 1st stage program voltage (initial voltage if verification is performed). For example, the 3rd stage program voltage (initial voltage if verification is performed) may be lower than the 2nd stage program voltage (initial voltage if verification is performed). For example, the application time of the 3rd stage program voltage may be longer than the application time of the 1st stage program voltage. For example, the application time of the 3rd stage program voltage may be shorter than the application time of the 2nd stage program voltage.

[0156] Figure 21 shows the control flow of the written data in the second embodiment. The program in the third stage performs write control for each threshold region.

[0157] The control flow shown in Figure 21 is basically the same as the control flow shown in Figure 18. However, in the control flow shown in Figure 21, steps S601, S602, and S603 are performed instead of steps S501, S502, and S503, and flows F61, F62, and F63 are performed instead of flows F19, F21, and F23.

[0158] For example, in the word line WL0, 3rd stage, area S1 program, according to the discrimination conditions shown in Figure 20, one page of data (rewrite data) is generated in which the bits where the write data for word line WL0 is in area S1 and the write data for word line WL1 is in areas S0 to S2 are write bits, and the other bits are non-write bits (step S601).

[0159] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F61), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0160] Next, in the word line WL0, 3rd stage, area S2 program, according to the discrimination conditions shown in Figure 20, one page of data (rewrite data) is generated where the write data for word line WL0 is in area S2, the bits where the write data for word line WL1 is in areas S0 to S2 are write bits, and the other bits are non-write bits (step S602).

[0161] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F62), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0162] Next, in the word line WL0, 3rd stage, area S3 program, according to the discrimination conditions shown in Figure 20, one page of data (rewrite data) is generated where the bits where the write data for word line WL0 is in area S3 and the write data for word line WL1 is in areas S0 to S2 are write bits, and the other bits are non-write bits (step S603).

[0163] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F63), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0164] In the example shown in Figure 21, the procedure for rewriting each cell in the rewrite target distribution with one page's worth of write data is shown, but all cells to be rewritten can also be treated as a single unit. For example, in the rewrite target conditions shown in Figure 20, it is possible to specify erase distribution data such that the bit value to write to the page is "110" for cells corresponding to threshold area S1, "100" for cells corresponding to area S2, "000" for cells corresponding to area S3, and "111" for all other cells, i.e., to treat them as non-write cells. It is also possible to send such page data as rewrite data to the NAND flash memory 40 from the memory interface 36 and perform the write operation.

[0165] [Third Embodiment] The third embodiment adds a countermeasure against interference between the first adjacent memory cells using a Foggy-Fine program, by means different from that of the first embodiment. Common parts with the first embodiment will be omitted from explanation as appropriate.

[0166] Figure 22 shows the threshold distribution after programming in the third embodiment. (T1) in Figure 22 shows the threshold distribution in the erase state, which is the initial state before programming. (T2) in Figure 22 shows the threshold distribution after the 1st stage program (Foggy program). (T3) in Figure 22 shows the threshold distribution after the 2nd stage program (Fine program). (T1) to (T3) in Figure 22 are the same as explained in Figure 16, so they are omitted here.

[0167] Figure 22 (T4) shows the threshold voltage distribution after the 3rd stage programming (reprogramming). As shown in Figure 22 (T4), the control unit CTU of the NAND flash memory 40 performs "weak" writing in the 3rd stage programming by adjusting the magnitude of the program voltage so that the increase in the threshold voltage due to the application of a single program voltage pulse is small, targeting only the memory cells MC in region S0, according to the bit values ​​to be written (stored) in the Lower page, Middle page, and Upper page. This prevents the threshold voltage of memory cells MC located on the higher side of the distribution from increasing, while only increasing the threshold voltage of those located on the lower side of the distribution. Verification may be performed in the 3rd stage programming, or it may be omitted. If verification is performed, the verification voltage Vr0' is set between the lower and upper limits of the original region S0.

[0168] During rewriting to area S0, the memory cell MC to be written to is determined according to the data written to the adjacent cell.

[0169] Figure 23 shows an example of threshold region combinations between a target cell and an adjacent cell that are targeted for writing the 3rd stage program in the third embodiment. In Figure 23, the memory cells MC marked with a "○" in the 3rd stage program for word line WLi are those whose threshold voltage is in region S0 and whose adjacent memory cell MC on word line WLi+1 has a threshold voltage in region S5~S7. Memory cells MCs in combinations other than those marked in Figure 23 are not targeted for writing. Note that the combinations shown in Figure 23 are examples, and the combinations targeted for writing may be expanded or contracted depending on the strength of interference between adjacent cells, etc.

[0170] Furthermore, when determining which memory cells MC to be rewritten, a verification operation may be performed. The verification operation may target only those exemplified in Figure 23, or it may include other memory cells MC. In addition, during the verification operation, the verification voltage Vr0' as described above may be supplied to the selected word line WL. Alternatively, memory cells with a threshold voltage equal to or greater than the verification voltage Vr0' may be excluded from rewriting, and only those with a threshold voltage less than the verification voltage Vr0' may be included in the rewriting process. The results of the verification operation may or may not be sent to the memory controller 30. If the results of the verification operation are sent to the memory controller 30, the results of the verification operation may be reflected in the rewrite data, thereby excluding memory cells with a threshold voltage equal to or greater than the verification voltage Vr0' from being rewritten. If the results of the verification operation are not sent to the memory controller 30, calculations may be performed internally in the NAND flash memory 40, thereby excluding memory cells with a threshold voltage equal to or greater than the verification voltage Vr0' from being rewritten.

[0171] Figure 24 shows the control flow of the written data in the third embodiment.

[0172] The control flow shown in Figure 24 is basically the same as the control flow shown in Figure 18. However, in the control flow shown in Figure 24, step S701 is performed instead of steps S501, S502, and S503, flow F71 is performed instead of flow F19, and steps S502, S503, and flows F20, F21, F22, and F23 are not performed.

[0173] In the word line WL0, 3rd stage, area S0 program, according to the discrimination conditions shown in Figure 23, one page of data (rewrite data) is generated where the bits where the write data for word line WL0 is in area S0 and the write data for word line WL1 is in areas S5 to S7 are write bits, and the other bits are non-write bits (step S701).

[0174] Next, the memory interface 36 sends this one page of data to the NAND flash memory 40 (flow F71), and the NAND flash memory 40 performs a rewrite of one page to the word line WL0.

[0175] The order in which word lines are selected during programming in the third embodiment is the same as in the first embodiment shown in Figure 15, but a modified example of the third embodiment is shown in Figure 25. This modified example shows the case where the third stage of word line WLi is programmed after the second stage of the next adjacent word line WLi+1. In this order, the number of word lines WL that are spanned when advancing the programming stages increases to four, which has the disadvantage of making the control more complex, but it has the advantage that the risk of overprogramming is reduced because the third stage of programming is performed after the final inter-cell interference from the adjacent word line WL has occurred.

[0176] In the program sequence shown in Figure 25, when the 3rd stage of the word line WLi program is executed, the data for word line WLi may already be discarded from the controller's data buffer (RAM 31). However, to identify the target memory cell MC, the only condition required is that the threshold of the adjacent memory cell MC of word line WLi+1 is in region S5 to region S7, and the condition that the threshold of the memory cell MC of word line WLi is in region S0 may be excluded. This is because, if the program voltage is adjusted to a voltage that causes only a weak write to the lower edge of region S0, even if all memory cell MCs of word line WLi are targeted for writing, only the memory cell MCs located at the lower edge of region S0 will actually be written to.

[0177] [Other embodiments] Figure 17 illustrates an example of a combination of memory cells (MCs) to be rewritten in the first embodiment. Figure 20 illustrates an example of a combination of memory cells (MCs) to be rewritten in the second embodiment. Figure 23 illustrates an example of a combination of memory cells (MCs) to be rewritten in the third embodiment. However, these are merely examples, and specific combinations can be adjusted as appropriate. For example, all 21 combinations of memory cells (MCs) illustrated in Figures 17, 20, and 23 may be targeted for rewriting, or only some of them may be targeted for rewriting.

[0178] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0179] MC...Memory cell, WL...Word line, 10...Memory system, 30...Memory controller, 31...RAM (Data buffer), 40...NAND flash memory.

Claims

1. Multiple first memory cells, A first word line connected to the plurality of first memory cells, Multiple second memory cells, The second word line connected to the plurality of second memory cells and Non-volatile memory including, A controller connected to the non-volatile memory and Equipped with, The aforementioned controller, First write data used for writing to the plurality of first memory cells, The second write data used for writing to the plurality of second memory cells, which is performed after writing to the plurality of first memory cells, It is configured to be able to hold, The system is configured to calculate rewrite data based on the first and second written data. The aforementioned non-volatile memory is A first write operation is performed to write to the plurality of first memory cells based on the first write data input from the controller, A rewrite operation is performed to write to a portion of the plurality of first memory cells based on the rewrite data input from the controller. Configured to be executable Memory system.

2. The rewrite operation is performed after the first write operation has been performed at least once. The memory system according to claim 1.

3. The non-volatile memory is configured to further perform a second write operation, which writes to the plurality of second memory cells based on the second write data input from the controller. After the first write operation is performed at least once, the second write operation is performed. The rewrite operation is performed after the second write operation has been performed at least once. The memory system according to claim 1.

4. The aforementioned non-volatile memory is Multiple third memory cells, The third word line connected to the plurality of third memory cells and It further includes, The first word line, the second word line, and the third word line are aligned in the first direction. The first word line is provided between the second word line and the third word line, The aforementioned controller, The device is configured to further hold third write data used for writing to the plurality of third memory cells, which is performed before writing to the plurality of first memory cells. The rewrite data is calculated based on the first write data, the second write data, and the third write data. The memory system according to claim 1.

5. In the rewrite operation, at least one of the magnitude of the first write voltage applied to the first word line and the duration for which the first write voltage is applied to the first word line can be set based on the first write data and the second write data. The memory system according to claim 1.

6. During the rewrite operation, a verification operation is performed, and a portion of the plurality of first memory cells that are the target of the rewrite operation is selected according to the result of the verification operation. The memory system according to claim 2.

7. During the rewrite operation, a verification operation is performed, and depending on the result of the verification operation, some of the multiple first memory cells are written to multiple times. The memory system according to claim 1.

8. The first write operation is performed in multiple stages. The memory system according to claim 1.

9. The controller includes a first memory area, The first written data and the second written data are stored in the first storage area. The memory system according to claim 1.

10. The non-volatile memory includes a second storage area, The first written data and the second written data are stored in the second storage area. The memory system according to claim 1.

11. The non-volatile memory includes a voltage supply unit, The voltage supply unit applies a first program voltage pulse to the first word line during the first write operation. The voltage supply unit applies a second program voltage pulse to the first word line during the rewrite operation. The magnitude of the second program voltage pulse is greater than the magnitude of the first program voltage pulse. The memory system according to claim 1.

12. The non-volatile memory includes a voltage supply unit, The voltage supply unit applies a first program voltage pulse to the first word line during the first write operation. The voltage supply unit applies a second program voltage pulse to the first word line during the rewrite operation. The application time of the second program voltage pulse is longer than the application time of the first program voltage pulse. The memory system according to claim 1.

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