Shielded connector assembly with temperature and alignment control

Abstract

The present invention provides a connector assembly configured to control temperature and / or alignment while reducing EMI. [Solution] A high-speed connector and connector assembly that can utilize various connector side plate designs and / or include temperature or alignment control. The side plate can be configured to receive and hold one or more wafer portions and to align the tail edges of the terminals of each wafer tail portion in the same geometric plane.

Description

[Technical Field]

[0001] Related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 010061, filed on 15 April 2020, and U.S. Provisional Patent Application No. 63 / 116648, filed on 20 November 2020, both of which are incorporated herein by reference in their entirety.

[0002] Field of Invention This disclosure relates to the field of connector assemblies, more specifically to connector assemblies and their components suitable for use in high-speed data rate applications (e.g., at least 100 gigabits per second (Gbps)). [Background technology]

[0003] This section presents embodiments that may help facilitate a better understanding of the present invention. Therefore, the descriptions in this section should be read from this perspective and should not be understood as acknowledgments of what constitutes prior art and what does not.

[0004] To date, high-speed data connector assemblies have faced challenges in controlling temperatures, for example, those generated by the electronic circuits within the plug module connected to the assembly, while simultaneously maintaining conductor alignment within the assembly and, above all, mitigating the effects of potentially harmful electromagnetic interference (EMI). Controlling temperatures reached within the receptacle cage of the assembly is particularly difficult.

[0005] Therefore, it is desirable to provide solutions to these challenges. [Overview of the project]

[0006] The inventors describe exemplary miniature, high-speed, multilevel, multiport connector assemblies and various configurations of their components. The assemblies and components of the present invention are configured, among other things, to control temperature and / or alignment while reducing EMI.

[0007] In one embodiment, the high-speed multi-level multi-port connector assembly of the present invention may include a shielded cage and a connector within the cage, the connector including an internal housing made of plastic configured to enclose one or more wafers, a first support side plate on one side of the housing and a second support side plate on the opposite side of the housing, each side plate configured to receive and hold the tail portions of one or more wafers and to align the tail edges of each tail portion in the same geometric plane. In the embodiment, the plastic may include a high-temperature liquid crystal polymer (LCP), and the one or more wafers may be, for example, equivalent to 1 to 8 wafers.

[0008] Several different internal housings are provided. In one embodiment, the internal housing of the present invention encloses portions of the upper and lower ports, while in another embodiment, the internal housing encloses portions of the upper ports but not portions of the lower ports. If the housing does not enclose portions of the lower ports, such a housing may still include, for example, one or more notches on both sides for contact with the lower ports to support the upper ports and the housing. Alternatively, an alternative housing may include an upper port support structure configured to be fixedly positioned between the upper and lower ports, the upper port support structure may include one or more apertures, each aperture configured to receive its respective upper port projection and to fixably position the upper port support structure.

[0009] The housing can be secured in several different ways. In one embodiment, the housing may include one or more substrate locks for securing the housing to the PCB, and one or more substrate locks may be made of deformable metal or plastic.

[0010] It should be understood that one or more wafers in the connector assembly of the present invention may include wafers of the upper port wafer assembly, while others may include, for example, wafers of the bottom port assembly.

[0011] Each wafer of the connector assembly of the present invention may include one or more wafer protrusions, and a first support side plate and a second support side plate may be configured to receive one or more wafer protrusions, and the side plates may be made of a metal such as stainless steel or a plastic such as LCP. More specifically, the first support side plate and the second support side plate may be configured to have one or more apertures for receiving one or more wafer protrusions, and each corresponding wafer protrusion and aperture may be configured such that each protrusion is structurally biased toward the corner of its respective aperture in order to control the tail portion of each wafer so that the tail portion of the wafer lies in the same geometric plane as, for example, a PCB also connected to the assembly.

[0012] The connector assembly of the present invention may further include an upper port tail alignment and support structure (for example, made from a non-conductive material) having one or more protrusions, wherein a first support side plate and a second support side plate may be configured to receive one or more protrusions of the upper port tail alignment and support structure. Such an upper port tail alignment and support structure of the present invention may further include one or more mounting structures for attaching the structure to a printed circuit board (PCB), for example, (i) some of the one or more mounting structures may be made of adhesive-covered non-conductive plastic and some of the mounting structures may be made of solderable plated non-conductive plastic or metal, or (ii) one or more of the mounting structures may be made of adhesive-covered non-conductive plastic, or (iii) one or more of the mounting structures may be made of solderable plated non-conductive plastic or metal.

[0013] In addition, the assembly of the present invention may further include a bottom port wafer assembly which can be configured to be connected to a PCB by, for example, surface mount technology, ball grid array, solder charge, press fit, or optical fiber technology. Furthermore, in embodiments, the assembly of the present invention may further include a conductive bottom port tail alignment and support structure configured to align the tail edges of one or more terminals of each tail portion of the bottom port wafer of the bottom port assembly, and may further be configured as a ground reference plane structure which surrounds the differential high-speed terminals of the bottom port wafer and electrically reflects an electrical ground plane structure formed on the surface of the PCB mated to the connector assembly. It should be understood that such a conductive bottom port tail alignment and support structure does not need to be connected to the PCB and may be configured to be isolated from the PCB surface by, for example, a non-limiting distance of 0.25 to 0.50 millimeters. In one embodiment, the conductive bottom port tail alignment and support structure may include plated plastic or stainless steel and may be configured, for example, as an integral part of the bottom port wafer assembly.

[0014] In one embodiment, a conductive grounding plastic shield element may be configured to cover the wafer of a bottom port wafer assembly, and such a conductive grounding plastic shield element may include plated plastic, plated ceramic, or a hybrid laminate having dielectric and conductive elements, or another conductive material having a dielectric coating.

[0015] Furthermore, such a conductive grounding plastic shield element may include multiple distinct elements.

[0016] In an embodiment, the connector assembly of the present invention may include, for example, a quad-small form-factor pluggable (QSFP) input / output (I / O) connector or a quad-double density small form-factor pluggable (QDD) I / O connector.

[0017] Each of the terminals of the connector assembly of the present invention may include a terminal overmolded with a plastic or plated plastic structure, the terminal including differential high-speed terminals, low-speed terminals, power terminals, and ground terminals, and each differential high-speed signal terminal may be configured to have, for example, another differential high-speed signal terminal on one side and a ground terminal on the other side.

[0018] In an embodiment, each differential high-speed signal terminal may transfer signals up to, for example, at least 100 gigabits per second (Gbps). Further, a portion of each wafer corresponding to the low-speed terminals and power terminals may electrically separate a set of differential high-speed terminals adjacent to the low-speed terminals and power terminals from another set of adjacent differential high-speed terminals within the same wafer, preventing mutual harmful electrical interference.

[0019] The connector assembly of the present invention provided by the inventors may also include a housing including one or more latches on both sides configured to fix or lock the upper portions of each wafer in place, and each latch may be configured as a part of the housing and be operable to deflect and fix one or more wafers.

[0020] In addition to the above alignment mechanism, the connector assembly of the present invention may include one or more conductive ground shield elements configured to cover some or all of the terminals of one or more wafers. Thus, in some embodiments where each of the one or more wafers supports one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals, and one or more ground terminals, the conductive ground shield of the present invention may be positioned between some of the one or more wafers.

[0021] For example, one or more conductive ground shields may include two or more separate shields having gaps between each shield, configured to cover differential high-speed transmission terminals, and two or more separate shields having gaps between each shield, configured to cover high-speed reception terminals, in order to enable temperature control (i.e., air passes through the gaps and flows over the uncovered low-speed terminals and power terminals). In another embodiment, a first conductive ground shield element of the one or more conductive ground shield elements may be configured to cover one or more differential high-speed terminals of one of the wafers, and a second conductive ground shield element of the one or more conductive ground shield elements may be configured to cover additional differential high-speed terminals of the same wafer. Further, the first and second conductive ground shields may be configured to have a gap therebetween, and the dimension of the gap corresponds to an area obtained by multiplying the total number of low-speed terminals and power terminals of a row of terminals with one terminal added by the required pitch of the terminals. In one embodiment, the gap may include, for example, 4.0 millimeters.

[0022] In one embodiment, the one or more conductive ground shield elements may be configured to extend along a vertical axis (regardless of the presence or absence of a gap therebetween), or may be configured to extend along an axis other than the vertical axis (regardless of the presence or absence of a gap therebetween). Regardless of the orientation of the shield or shields, in an embodiment, the ground shield elements may be configured to cover, for example, one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals, and one or more ground terminals of each wafer.

[0023] As described above and elsewhere in this specification, one or more differential high-speed terminals may be covered by a conductive ground shield element. If one set of differential high-speed terminals is a transmission element and another set is a reception element, for example, one conductive ground shield element (the "first" conductive ground shield element) may cover the transmission terminals and another conductive ground shield element (the "second" conductive ground shield element) may cover the reception terminals.

[0024] Furthermore, if each of one or more wafers supports one or more differential high-speed terminals, the connector assembly may be further configured to position a conductive ground shield at a first distance adjacent to one or more of the differential high-speed terminals of each of the wafers, thereby creating field affinity between each ground shield and each differential high-speed terminal.

[0025] The connector assembly of the present invention, provided by the inventors, may include additional temperature control in addition to the aforementioned gap in the shield. For example, low-speed terminals and power terminals in the same row on one wafer may be configured to be offset from low-speed terminals and power terminals in a different row on another wafer.

[0026] For example, the housings described above and elsewhere in this specification may include one or more gaps that allow airflow to pass through and remove heat generated by at least the low-speed terminals and power terminals of one or more wafers.

[0027] The inventors also provide a connector assembly comprising the present invention's combination of a grounding conductor and a plastic grounding shield. For example, in one embodiment, one or more insert-molded metal grounding conductors (e.g., made of copper, copper alloy, gold, or platinum) may be stitchably fitted to a grounding conductive portion which is, for example, part of a plastic grounding shield element, for example, the grounding conductive portion or a plurality of grounding conductive portions may include conductive plastic, conductive metal, conductive or plated plastic, or a hybrid laminate having dielectric and conductive elements.

[0028] Each of the stitched, one or more insert-molded metal grounding conductors may include, for example, a continuous conductive structure.

[0029] To reduce undesirable voltage gradients in a connector assembly, the inventors provide one or more wafers (of an upper and / or bottom wafer assembly), each of which may include a dual ground path, where a first path may be formed by individual ground conductors and a second ground path may be formed by conductive finger portions and a conductive plated plastic shield. The inventors believe that the dual ground path of the present invention substantially reduces the combined impedance shared along the length of each path, where the shared combined impedance may be smaller than the impedance of either of the individual paths.

[0030] With respect to the finger portions of the present invention as described above, each conductive finger portion may be electrically and galvanically connected to one contact portion of an individual grounding conductor, for example, and may include a finger portion of a conductive grounding plate. Alternatively, each conductive finger portion may include, for example, an insert-molded finger portion of a plastic grounding shield structure.

[0031] In addition to the connector assembly of the present invention, the inventors also provide a related method of the present invention for that purpose, in parallel with the connector assembly of the present invention.

[0032] In one embodiment, the connector assembly of the present invention may include an internal housing having a first side and a second side opposite the first side, and first and second support side plates connected to the first and second sides of the internal housing, respectively, the first and second support side plates being configured to fix the position of the tail portion of the wafer within the internal housing relative to each other and to align the tail edges of the terminals of each tail portion in the same geometric plane.

[0033] In one embodiment, both side plates may include metal side plates, and the internal housing may include a plastic such as liquid crystal polymer (LCP). Furthermore, each side plate may be configured to receive wafer protrusions within one or more apertures of each side plate to hold the tail portion of the terminal, and to align the tail edges of each tail portion in the same geometric plane.

[0034] It should be understood that the connector assembly of the present invention may also include multiple wafers (both upper port wafers and bottom port wafers) within an internal housing, and each of these multiple wafers may include terminals overmolded with plastic or plated plastic.

[0035] An exemplary connector assembly of the present invention may further include an upper port tail alignment and support structure including one or more tail alignment and support structure protrusions, and a bottom port tail alignment and support structure including one or more tail alignment and support structure protrusions.

[0036] In one embodiment, the upper port tail alignment and support structure may be made of a non-conductive material, while the lower port tail alignment and support structure may be made of a conductive material, for example.

[0037] Furthermore, the exemplary upper port tail alignment and support structure may include one or more mounting structures for attaching the upper port tail alignment and support structure to a printed circuit board (PCB), the one or more mounting structures may include (i) an adhesive-covered non-conductive plastic, or (ii) a solderable plated non-conductive plastic or metal that can be soldered to the PCB, or (iii) a combination of an adhesive-covered non-conductive plastic and a solderable plated non-conductive plastic or metal that is soldered to the PCB.

[0038] In alternative embodiments, each side panel may include one or more inwardly or outwardly bent or configured hook-shaped tabs connected to the PCB, and may also include, for example, one or more integrated solder nails for securing each side panel to the PCB.

[0039] Another embodiment of the present invention relates to components of a connector assembly, particularly a side plate. In one embodiment, the side plate of the present invention may be connected to the side of an internal housing and may be configured to receive projections of tail alignment and support structures and wafer projections, in particular to hold each tail portion of a plurality of wafers and to align the tail edges of the terminals of each tail portion in the same geometric plane. Such a side plate may also further include one or more inwardly or outwardly curved or configured hook-shaped tabs connected to a PCB or one or more integrated and / or solder nails for securing each side plate to the PCB.

[0040] In addition to the connector assemblies and components of the present invention, the inventors also provide methods of the present invention that are related in parallel with the connector assemblies and components of the present invention. For example, a method for fixing the position of a wafer within a connector assembly may include fixing the position of the wafer within the internal housing of the connector assembly relative to each other using first and second support side plates connected to first and second sides of the internal housing, and receiving the projections of a non-conductive upper port tail alignment and support structure, the projections of a conductive bottom port tail alignment and support structure, and the wafer projections within the apertures of the first and second side plates to hold each tail portion of the wafer and aligning the tail edges of the terminals of each tail portion in the same geometric plane. [Brief explanation of the drawing]

[0041] The present invention is illustrated as an example, but is not limited by the accompanying drawings, and similar reference numerals in the drawings refer to similar elements.

[0042] [Figure 1A] This is a diagram of an exemplary connector assembly of the present invention according to one embodiment of the present invention. [Figure 1B] This is a diagram of an exemplary connector assembly of the present invention according to one embodiment of the present invention. [Figure 2] This is an exploded view of an exemplary connector assembly of the present invention according to one embodiment of the present invention. [Figure 3A] This is a different diagram of an exemplary connector of the present invention according to an embodiment of the present invention. [Figure 3B] This is a different diagram of an exemplary connector of the present invention according to an embodiment of the present invention. [Figure 3C] This figure shows an exemplary wafer of the present invention according to an embodiment of the present invention. [Figure 3D] This figure shows an exemplary alignment control mechanism according to an embodiment of the present invention. [Figure 3E] This figure shows an exemplary alignment control mechanism according to an embodiment of the present invention. [Figure 3F] This figure shows an exemplary conductive earth shield according to an embodiment of the present invention. [Figure 3G] This is an enlarged view of an exemplary temperature control mechanism of the present invention, according to one embodiment of the present invention. [Figure 3H] This figure shows an exemplary wafer of the present invention according to an embodiment of the present invention. [Figure 3I] This figure shows an additional exemplary temperature control mechanism according to an embodiment of the present invention. [Figure 3J] This figure shows an exemplary conductive earth shield according to an embodiment of the present invention. [Figure 3K] This figure shows an exemplary conductive earth shield according to an embodiment of the present invention. [Figure 3L] This figure shows an exemplary stitching of a grounding terminal to a conductive grounding shield according to an embodiment of the present invention. [Figure 3M] This figure shows an exemplary stitching of a grounding terminal to a conductive grounding shield according to an embodiment of the present invention. [Figure 3N] This figure shows an exemplary stitching of a grounding terminal to a conductive grounding shield according to an embodiment of the present invention. [Figure 3P] This figure shows an exemplary grounding path configuration according to an embodiment of the present invention. [Figure 3Q]This figure shows an exemplary grounding path configuration according to an embodiment of the present invention. [Figure 3R] This figure shows an exemplary grounding path configuration according to an embodiment of the present invention. [Figure 3S] This figure shows an exemplary tail alignment and support structure according to an embodiment of the present invention. [Figure 3T] This figure shows an exemplary tail alignment and support structure according to an embodiment of the present invention. [Figure 3U] This is a different diagram of an exemplary connector of the present invention according to an embodiment of the present invention. [Figure 3V] This figure shows an exemplary alignment control mechanism according to an embodiment of the present invention. [Figure 3W] This figure shows an exemplary alignment control mechanism according to an embodiment of the present invention. [Figure 3X] This figure shows an exemplary alignment control mechanism and an exemplary tail alignment and support structure according to embodiments of the present invention. [Figure 4A] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4B] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4C] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4D] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4E] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4F] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4G] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4H] This figure shows an exemplary mechanism of the present invention, specifically a bottom port wafer assembly, according to an embodiment of the present invention. [Figure 4I] This figure shows an exemplary tail alignment and support structure for at least a bottom port wafer assembly according to an embodiment of the present invention. [Figure 5A] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5B] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5C] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5D] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5E] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5F] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5G] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5H] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5I] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 5J] This is a diagram illustrating the exemplary mechanism of an alternative exemplary connector according to an embodiment of the present invention. [Figure 6A] This figure shows an alternative upper port wafer assembly configuration according to one embodiment of the present invention. [Figure 6B] This figure shows an alternative upper port wafer assembly configuration according to one embodiment of the present invention.

[0043] Specific embodiments of the present invention are disclosed below with reference to various drawings and schematics. Both the description and the examples have been drafted with the intention of enhancing understanding. For example, some dimensions of elements in the figures may be exaggerated relative to others, and well-known elements that are beneficial or even necessary for a commercially successful implementation may not be depicted so as to allow the embodiments to be made clearer and with less ambiguity.

[0044] Conciseness and clarity in both the examples and descriptions are required to enable those skilled in the art to effectively manufacture, use, and best implement the invention, taking into account what is already known in the art. Those skilled in the art will understand that various modifications and changes can be made to the specific embodiments described below without departing from the spirit and scope of the invention. Accordingly, this specification and drawings should be considered descriptive and illustrative, rather than restrictive or comprehensive, and all such modifications to the specific embodiments described below are intended to be within the scope of the invention. [Modes for carrying out the invention]

[0045] The following detailed description illustrates exemplary embodiments and is not intended to limit you to the combinations expressly disclosed. Therefore, unless otherwise specified, the features disclosed herein may be combined to form additional combinations not shown otherwise for the sake of brevity.

[0046] The disclosure provided herein is characterized in terms of its preferred and exemplary embodiments. Those skilled in the art will be able to recall, by considering this disclosure, many other embodiments, modifications, and variations within the scope and spirit of the appended claims.

[0047] When used herein and in the appended claims, the terms “comprises,” “comprising,” or any other variation thereof, as well as “includes” or “including,” and any other variation thereof, are intended to refer to non-exclusive contents, such that a process, method, article, or apparatus containing a list of elements does not include only those elements on the list, but may also include other elements not expressly enumerated or that are not specific to such process, method, article, or apparatus.

[0048] As used herein, the terms "a" or "an" mean one or more. As used herein, the term "plural" means two or three or more. As used herein, the term "another" means at least one more.

[0049] Unless otherwise indicated herein, the use of relational terms such as “first” and “second,” “top” and “bottom,” “left” or “right,” where applicable, is used solely to distinguish one element, component, existence or action from another, without necessarily requiring or implying any actual relationship, order or importance between such elements, components, existence or action.

[0050] As used herein, the terms “including” and / or “having” are defined as “comprising” (i.e., open language). As used herein, the term “coupled” is defined as connected, but not necessarily direct or mechanical. As used herein, the use of “or” or “and / or” is defined as inclusive (A, B, or C means any one, any two, or all three letters) and not exclusive (unless explicitly indicated as exclusive). Therefore, in some cases, the use of “and / or” should not be interpreted as implying that the use of “or” elsewhere means that the use of “or” is exclusive. Terms derived from the term “indicating” (e.g., “indicates” and “indication”) are intended to encompass all the various techniques available for conveying or referring to the indicated object / information. Some, though not all, examples of techniques available for conveying or referencing the object / information being shown include the transport of the object / information being shown, the transport of an identifier for the object / information being shown, the transport of information used to generate the object / information being shown, the transport of any part or portion of the object / information being shown, the transport of any derivative of the object / information being shown, and the transport of any symbol representing the object / information being shown.

[0051] As used herein, the terms “high speed,” “high speed signal,” “high speed data,” and “high speed data signal” are synonymous unless otherwise interpreted in context or by the knowledge of those skilled in the art. An example of a high speed data signal may be a signal of at least 100 Gbps.

[0052] Similarly, terms such as “low speed,” “low speed signal,” “low speed data,” and “low speed data signal” are synonymous unless otherwise interpreted in context or by the knowledge of those skilled in the art. Generally, low speed signals can be considered signals associated with control and system maintenance, as opposed to signals associated with information transfer. Furthermore, non-restrictive low speed signals can be associated with data transmission speeds of less than 1 Gbps and typically do not require special signal carrier structures such as ground-supported waveguides. For brevity, a reference to “low speed terminal” may include power terminals depending on the context.

[0053] As used herein, the phrases “configured to” or “operable to” mean “function to” unless otherwise interpreted in the context or by the knowledge of those skilled in the art.

[0054] As used herein, the phrase "a~n" refers to the first element "a" and the last element "n". For example, in one or more apertures, "a" is the first aperture and "n" is the last aperture. Furthermore, the letters "n" or "nn" refer to one exemplary element among several similar elements, for example, aperture 11n.

[0055] As used herein, the terms “exemplary” and “embodiment” mean one or more non-limiting examples of the connector assembly, component or element of the present invention, process of the present invention, or part of the process of the present invention.

[0056] As used herein, the terms “terminal” and “conductor” may be used synonymously unless otherwise interpreted in context or by the knowledge of those skilled in the art.

[0057] As used herein, the terms “hold” and “secure” may be used synonymously unless otherwise interpreted in context or by the knowledge of those skilled in the art.

[0058] Referring here to Figure 1A, an exemplary shielded, high-speed, multi-level, multi-port connector assembly 1 of the present invention is shown. As shown, assembly 1 may include an electromagnetic shielding cage 2 which can be configured to protect several different connectors, each of which may have an upper port and a bottom port (both hidden from view) and may be connected to a main electronic printed circuit board 3 (PCB) according to one embodiment of the present invention. Pluggable module assemblies 4a, 4b which may include PCB subassemblies are also shown, one pluggable module assembly 4a which may be connected to the upper port via a card slot (not shown) in the upper port, and the other assembly 4b which may be connected to the bottom port via a card slot in the bottom port. Figure 1B shows the two assemblies 4a, 4b before being connected to the upper and bottom ports 8a, 8b.

[0059] More specifically, cage 2 is positioned above the upper and lower ports 8a, 8b of the connector to provide shielding from electromagnetic interference (EMI) for at least the connector and other components within cage 2.

[0060] Referring here to Figure 2, an exploded view of exemplary components that may be used to construct exemplary connector assembly 1 is shown. As shown, cage 2 may include a cage base 2b, a shielded backplate 2c, and a front-end shield 2d, along with a three-sided conductive cover 2a (e.g., top and two sides). Each of these components 2a, 2b, 2c, and 2d may be operable to shield the component it covers, such as connector 1a, from EMI. When positioned in this manner, cage 2 may be operable to shield connector 1a from a range of EMI (e.g., nominally covering 10 MHz to 50 GHz).

[0061] In one embodiment, components 2a, 2b, 2c, and 2d may consist of, for example, a sufficiently conductive metal or a sufficiently conductive plated plastic, but these are only two of the types of conductive materials that can be used. Furthermore, these shielded component structures may consist of one or more differently configured perforated and / or non-perforated apertures to allow airflow and contribute to temperature control of the components constituting assembly 1. Such apertures may also be configured to reduce the effects of EMI.

[0062] More specifically, the front-end shield 2d may include one or more associated openings, apertures, or vents 5a (collectively, “apertures”) that are operable to allow air to flow into and / or out of the cage 2 in order to reduce the temperature of components enclosed by the cage 2, such as the connector 1a. Furthermore, the front-end shield 2d may further include a plurality of conductive deformable structures or elements 6 that can be formed around part or substantially all of the periphery of the shield 2d. In one embodiment, another device (e.g., a paddle card, see component 7b) having a corresponding opposing deformable structure or element (not shown) may be pressed onto and positioned on the element 6, so that the other device can be so-called “plugged in” to port 8b of the connector 1a via a card slot in port 8b. The opposing forces of two opposing sets of deformable elements, along with one or more latches (e.g., one latch located on each side of the cage 2, closer to the front, as typically described elsewhere herein), secure the other device to port 8b of the connector 1a. Furthermore, in one embodiment, such a "plug-in" configuration forms a continuous EMI shielding seal. Moreover, since element 6 is conductive, an electrical grounding path can be established.

[0063] Next, assembly 1 may further include an upper heatsink 2g and a second fastening clip 2h, as well as an internal, integrated (e.g., one-piece) central housing 2j surrounding the bottom and upper ports 8a and 8b, with the paddle card 7b being exemplified as being inserted into the bottom port 8b.

[0064] Optionally, assembly 1 may further include a central cage portion containing an internal heatsink 2e and fastening clips 2f.

[0065] In one embodiment, the upper heatsink 2g may extend substantially along the entire length of the cage 2, while the internal central housing 2j is located within the cage 2.

[0066] Figure 2 shows Assembly 1 as including all of the components described above, but it should be understood that other embodiments of connector assemblies including only a subset of such components are conceivable. Furthermore, additional embodiments may include, for example, (i) additional components not shown in Figure 2, (ii) fewer components (i.e., a subset of the components shown in Figure 2), and / or (iii) a subset of the components shown in Figure 2 and additional components not shown in Figure 2.

[0067] Next, the first fastening clip 2f may include one or more deformable elements 2ff that are operable to apply a spring-like force to the internal heatsink 2e located on both sides of the cage 2. As a result of such a force, the heatsink 2e may come into contact with components within the cage 2, such as the upper port. Referring to the second fastening clip 2h, in one embodiment, the clip 2h may be operable to apply a force to the upper heatsink 2g such that the heatsink 2g comes into contact with components enclosed and located within the cage 2, such as, for example, an optical / electrical (O / E) and / or electric / optical (E / O) conversion circuit, an active device, and / or a retiming circuit (not shown).

[0068] In embodiments of the present invention, assembly 1 may include additional components other than the front-end shield 2d that are operable to reduce the temperature of the components of assembly 1. For example, the cage 2 and shielded backplate 2c may also include one or more correspondingly related apertures 5b, 5c, respectively, configured to allow air to flow into the cage 2 in order to reduce the temperature of the components enclosed by the cage 2 (see Figures 1A and 2). In one embodiment, when connected to assembly 1a, the plug-in paddle card 7b and PCB 3 form a fully functional connection that enables, for example, transfers of up to 100 Gbps.

[0069] Depending on the embodiment, one or more of each of the above-described apertures may be molded as hexagonal. Alternatively, to list only two of the many different types of aperture shapes that may be available, one or more of each of the above-described apertures may be molded as circular, still allowing the aperture to function as a temperature control for reducing the temperature of the components of the assembly of the present invention. Furthermore, a given set of relevant apertures may include, for example, a subset of hexagonal apertures and a subset of circular apertures. In embodiments, the surface area and / or structure of the components of the assembly of the present invention (e.g., components 2a, 2c, and 2d) may, due to the dimensions of the components and apertures, allow for the inclusion of more hexagonal apertures than circular apertures (i.e., more hexagonal apertures than circular apertures may be formed on the components).

[0070] Furthermore, each aperture may be configured to have a width to reduce the EMI impact on internal components of assembly 1, depending on the frequency or multiple frequencies to be attenuated, and to have an extrusion depth to reduce the EMI impact on internal components, depending on the desired attenuation amount (e.g., dB). For example, a smaller aperture width allows for a higher upper cutoff frequency that can be attenuated, while a deeper extrusion depth allows the aperture to attenuate more of a given signal at a given frequency (i.e., reduce the decibel level of the signal). In one embodiment, an aperture used as part of the assembly of the present invention may have a width and extrusion depth corresponding to a desired attenuation amount (i.e., it may be sized).

[0071] Furthermore, in some embodiments, apertures of a given size within a group of apertures can be repeated aperiodically to avoid aperture amplification or "gain" at a given frequency or frequency band. Also, exemplary apertures may each have the same width and therefore can attenuate signals over substantially the same frequency range. However, by changing the extrusion depth of a given aperture, such an aperture will attenuate a given signal more at a given frequency than an aperture with a smaller (shorter) extrusion depth (i.e., an aperture with a larger extrusion depth can reduce the signal's decibel level more than an aperture with a shorter extrusion depth).

[0072] In one embodiment, the thickness and composition of the cover 2a of the cage 2 can be set to achieve a desired EMI attenuation level. For example, a thin thickness of a given material may attenuate unwanted frequencies less than a thicker thickness of the same given material. Furthermore, the cover 2a of the cage 2 may consist of multiple layers of the same or different attenuating materials (for example, layers may consist of a metallic material, while others may consist of other conductive materials such as plated plastic).

[0073] Referring here to Figures 3A and 3U, a diagram of connector 1a is shown. In one embodiment, the connector includes a central internal housing 2j which is substantially located within a shielded cage 2 and may be made of a plastic such as high-temperature liquid crystal polymer (LCP), and the housing 2j may be configured to surround both portions of the upper and bottom ports 8a, 8b and each of one or more wafers (not shown) within connector 1a.

[0074] Figures 3A and 3U also show a first support side plate 9a located on one side of the internal housing 2j, which may be configured to have a mechanism for connecting to the position of the wafers within the internal housing 2j and fixing them relative to each other. For example, the side plate 9a (and a second side plate 9b on the opposite side of the housing 2j, hidden from view in Figure 3A) may be configured to receive and hold the "tail" portions of the terminals of each wafer in order to align the tail edges of each tail portion (see description in Figure 3C; for example, 1 to 8 wafers) in the same geometric plane (i.e., the geometric plane to which the tail edges terminate is in the same plane as PCB 3) by receiving, for example, one or more posts or protrusions 14a to 14n (collectively, "protrusions") of the upper port tail alignment and support structure 14 and wafer protrusions or posts 10a to 10n (collectively, "protrusions"), for example, by receiving the tail edges of each tail portion (see description in Figure 3C; for example, 1 to 8 wafers) in the same geometric plane (i.e., the geometric plane to which the tail edges terminate is in the same plane as PCB 3). In embodiments, the side plates 9a, 9b may be made of metal (e.g., stainless steel). Since the side plates 9a and 9b are connected to the housing 2j, it can be said that the housing 2j is configured to control the center-to-center positioning between each wafer.

[0075] As shown in the figure, in one embodiment, connector 1a may be configured as a shielded, high-speed, multi-level, multi-port connector having a temperature and alignment control mechanism. In one embodiment, connector 1a may include input / output (I / O) connectors, such as those that can be used for small form factor pluggable applications or double-density small form factor pluggable applications (e.g., QSFP, SFP, QSFP-DD, SFP-DD, OSFP, CDFP applications). As configured, assembly 1 including connector 1a may be referred to as a shielded, high-speed, multi-port, multi-level connector assembly 1 having temperature and alignment control, among many other features.

[0076] More specifically, referring here to Figure 3C, the connector 1a may contain a plurality of wafers 15a-15n (e.g., 4-8 wafers, although only 4 are shown) within an internal housing 2j, and these wafers are aligned with card slots of ports such as ports 8a, 8b at their tips or tops. In one embodiment, each wafer 15a-15n may support a set of terminals, such terminals including terminals overmolded in a plastic or plated plastic structure, which will be described in more detail elsewhere in this specification (e.g., differential high-speed terminals, low-speed terminals, power terminals, and ground terminals, which are not shown for clarity). More specifically, unless otherwise specified, the terminals of each wafer may include a high-speed portion, which includes differential high-speed signal terminals and ground terminals extending in parallel across the wafer, and each differential high-speed signal terminal is configured to have another differential high-speed signal terminal on one side of each differential high-speed signal terminal and a ground terminal on the other side (see, for example, Figure 3K).

[0077] Furthermore, each terminal may have three parts: a tip, top, or contact portion (collectively referred to as the "contact portion") that contacts a pluggable card such as cards 7a, 7b; a tail portion on the opposite side; and a central body portion between the contact portion and the tail portion. As shown in Figure 3C, each tail portion of the terminals of wafers 15a to 15n may include several tail edges 30a' to 30n' (ground conductor tail edges), 31a' to 31n' (low-speed or power terminal tail edges), and 32a' to 32n' (high-speed tail edges) aligned in the same geometric plane.

[0078] As can be seen throughout the drawings of this specification, the terminals of each wafer may be arranged in one or more rows to contact a pluggable card (see, for example, Figures 3Q and 3R).

[0079] In this embodiment, the contact portions of one or more terminals on the wafer may be arranged to form, for example, an upper row of terminals in contact with the card slot and a bottom row of terminals in contact with the card slot (see, for example, Figures 3Q and 3R).

[0080] Conductive terminals, which are part of wafers 15a to 15n, may be configured to conduct electrical signals. Additionally, in alternative embodiments, the terminals may also be configured to supply electrical signals to, for example, an E / O conversion circuit or to receive electrical signals from an O / E conversion circuit. In the latter case, such an O / E or E / O conversion circuit may be included in a mated plug-in module or card (e.g., component 7b) and then connected to each conductive wafer of connector 1a.

[0081] In many cases, signals conducted through wafer terminals or through additional O / E and E / O conversion circuits can generate a considerable amount of heat during operation. Therefore, as described herein, the inventors provide solutions for controlling such temperatures.

[0082] Referring to Figure 3B, a diagram illustrating the connector 1a and its components is shown separately, which may include the connector 1a removed from the housing 2j for ease of explanation. It is understood that the components shown in Figure 3B are typically connected to or located within the housing 2j. Such components include the first support side plate 9a, the second support side plate 9b, the tail alignment and support structure 14, and the upper port wafer assembly 10 (the bottom port wafer assembly is not shown but is actually located within the connector 1a). In one embodiment, the composition of the internal housing 2j, the upper side plates 9a and 9b, and the alignment and support structure 14 may consist of plastic (e.g., LCP material). In an embodiment, the structure 14 may be a non-conductive material that can be fully or partially plated.

[0083] In embodiments of the present invention, the side plates 9a, 9b may be configured to have one or more apertures 11a to 11n, one or more of the apertures may be configured to receive the aforementioned one or more wafer protrusions of each wafer 15a to 15n of the upper port wafer assembly 10 (see elements 10a to 10n in Figure 3C, which are configured to be the tail portions of the terminals of wafers 15a to 15n). As configured, the protrusions help to control the alignment and positioning of each wafer 15a to 15n in order to ensure that the tail portions of the terminals of each wafer 15a to 15n are held and that the corresponding tail edges are aligned in the same plane (i.e., the tail edges of each terminal are coplanar with the plane of PCB 3). Figures 3B and 3C show only the projections (e.g., 10a-10n) on one side of each wafer 15a-15n (i.e., into the side plate 9a), but it should be understood that both sides of each wafer may be configured to have projections extending into apertures 11a-11n within each side plate 9a, 9b. In one embodiment, the projections may be insert-molded projections.

[0084] Furthermore, the housing 2j may include one or more latches 12a-12n on both sides of the housing 2j (see Figures 3A and 3B). In one embodiment, each set of latches 12a-12n (e.g., at least one on each side) may be configured to substantially fix or lock the top of each wafer 15a-15n in place to prevent the upper port wafer assembly 10 from coming out of the housing 2j (i.e., moving away from the front of port 8a). Although only one latch on one side of the housing 2j is shown, it should be understood that both sides of the housing 2j may include such latches. In one embodiment, each latch 12a-12n may be configured as an integral part or separately connected part of the housing 2j that can operate to deflect outward as the upper port wafer assembly 10, including (e.g.) one or more wafers, is inserted into the housing 2j. Since the wafer assembly 10 is in contact with the latches 12a to 12n, the latches 12a to 12n may be deflected inward when (for example) wafers 15a to 15n pass through the latches 12a to 12n and reach a determined position within the housing 2j that secures one or more wafers 15a to 15n. Alternatively, housing posts that fit into an additional aperture of the enclosure 2j may be used instead of the latches 12a to 12n.

[0085] Figure 3D shows, for example, an enlarged view of wafer protrusions 10a to 10n inserted within apertures 11a to 11n of side plate 9a (this also applies to side plate 9b). Tail edges 30a' to 30n' (ground conductor tail edges), 31a' to 31n' (low-speed or power terminal tail edges), and 32a' to 32n' (high-speed tail edges), aligned in the same geometric plane, are also shown.

[0086] Figure 3E shows side view S A ~S D An enlarged view of an inserted single exemplary projection 10n having a side plate 9a having sides s1-s4 is shown together with an aperture 11n of the side plate 9a. In one embodiment, each projection 10a-10n and aperture 11a-11n has a side S at the upper left corner c1 A ~s1 and S BThe distance between ~s2 and the side surface S of the lower right corner c2 c ~s3 and S D It can be configured (i.e., in this case, it can be formed) to be smaller than the distances between ~s4 respectively.

[0087] More specifically, the side surface s2 and S B are line-to-line (i.e., do not overlap), and the side surface s1 and S A are also line-to-line. On the other hand, the side surfaces s3 and S C overlap each other, and the side surfaces s4 and S D also overlap each other. In one embodiment, the overlapping side surfaces generate an interference fit / compression fit force that acts on the protrusion 10n and directs the protrusion 10n towards the upper left corner c1. Thus, the surfaces close to c1 (e.g., s2 and S B and s1 and S A ) are pushed in the direction approaching the corner c1, and the surfaces (e.g., s3 and S C and s4 and S D ) are pushed in the direction moving further away from the corner c2. In an exemplary embodiment, the surfaces s3 and S C and s4 and S D can be, for example, 0.03 millimeters further away from the corner c2 than the surfaces s2 and S B and s1 and S A are from the corner c1.

[0088] Therefore, it can be said that the protrusions 10a~10n are, for example, "biased" towards the upper left corner c1. However, it should be understood that biasing towards the upper left corner is merely an example. In an alternative embodiment, the protrusion 10n can be biased towards any one of the four corners if the overlapping side surfaces are properly configured and the same or similar difference in distance is achieved.

[0089] Such exemplary biased protrusions are one of the alignment control mechanisms of the present invention discovered by the inventors, for example, when wafers are connected to the main PCB 3 using surface mount technology (SMT), and such biased protrusions control the planarity and position of the tail portions of wafers 15a-15n. More specifically, such biased protrusions help control the tail portions of terminals on each wafer 15a-15n so that the tail edges of each tail portion of the terminals are aligned in the same plane (i.e., in the same geometric plane as PCB 3). Without such biasing, the height of one or more tails of the terminals on wafers 15a-15n may vary, and therefore the tail edges may not be coplanar (i.e., may be misaligned).

[0090] Furthermore, Figures 3B and 3D illustrate additional alignment control mechanisms. Figure 3B shows a non-conductive tail alignment and support structure 14 of the present invention, which may include one or more tail alignment protrusions 14a to 14n. In Figure 3D, in one embodiment, one or more apertures 11a to 11n on each of the side plates 9a and 9b may be configured to receive one or more protrusions 14a to 14n, thereby further fixing the tail portions of each wafer 15a to 15n to a common datum (i.e., a fixed reference structure), and enabling the side plates 9a and 9b to be connected. Although only four wafers are shown connected to the side plates 9a and 9b in Figure 3D, it should be understood that more than four wafers can be connected to the side plates. For example, eight wafers can be connected to the side plates (see Figure 3X).

[0091] In short, each exemplary side plate 9a, 9b may be configured to receive the protrusions 14a to 14n and wafer protrusions 10a to 10n of the tail alignment and support structure 14 and hold each of the plurality of wafers 15a to 15n in order to align the tail edges 30a' to 30n', 31a' to 31n' and / or 32a' to 32n' of each tail portion in the same geometric plane as a PCB such as PCB 3.

[0092] Figures 3V, 3W, and 3X show alternative side panels 9aa, 9ab, and 9ac, respectively. While only one side and side panel may be shown, it should be understood that each side of the housing may include similar side panels 9aa, 9ab, and 9ac.

[0093] As shown in Figures 3V and 3W, the side panels 9aa and 9ab may include one or more inwardly or outwardly bent or configured hook-shaped tabs 19a to 19n. In one embodiment, the tabs 19a to 19n may be connected to a PCB such as PCB 3 by soldering. In these embodiments, the side panel 9ab in Figure 3W is shown connected to the housing 2j, and the side panel 9aa in Figure 3V is shown connected to the bottom port 88b (see Figures 5A to 5E for the bottom port 88b), but these are merely illustrative configurations.

[0094] In the series of diagrams comprising Figure 3X, the side plate 9ac is shown connected to the housing 2j using projections and apertures, as described elsewhere in this specification. In this embodiment, the side plate 9ac may be configured to have one or more integrated solder nails 29a-29n. As shown, each solder nail 29a-29n may be received within an opening in the PCB 3, for example, to secure the side plate 9ac and the housing 2j to the PCB 3. In addition, the solder nails 29a-29n may be configured to frictionally contact the tail alignment and support structures 14, 46 at location 3a, for example, to further hold the structures 14, 46 in a fixed position.

[0095] As before, each side plate 9aa, 9ab, and 9ac may be configured to receive the protrusions of the tail alignment and support structure and the wafer protrusions, to hold or secure each of the multiple wafers, and to help align the tail edges of each tail portion of the terminals of each wafer in the same geometric plane as PCB3.

[0096] For ease of understanding, the inventors hereby discuss the features of an upper port wafer assembly (e.g., assembly 10) that may be incorporated into the connector assembly of the present invention, such as assembly 1. Furthermore, the inventors hereby discuss a bottom port wafer assembly. It should be understood that one or more features of the upper port wafer assembly of the present invention may be utilized in the bottom port wafer assembly of the present invention, and vice versa.

[0097] In one embodiment, the upper port wafer assembly 10 may include one or more separate power, high-speed, and low-speed communication signal conductors and a ground conductor (sometimes called a “terminal”) that forms part of a separate ground, power, and communication signal path. In the embodiment, each high-speed conductor / terminal may be configured to transfer signals up to at least 100 gigabits per second (Gbps), and in an alternative embodiment, more than 100 Gbps may be transferred by the high-speed signal terminals of the assembly 10 (and the bottom port assembly). In an alternative embodiment, communication signals up to 160 Gbps may be transferred by the high-speed terminals of the assembly.

[0098] In one embodiment, the upper port wafer assembly 10 may include a differential high-speed terminal, a centrally located low-speed / power terminal, and a ground terminal. In other words, the differential high-speed terminals may be located on the left and right sides of each wafer in the upper port connector assembly 10, while the low-speed or power terminal may be located, for example, centrally between the high-speed terminals (i.e., "on-center"). In one embodiment, this "on-center" portion of each wafer in the assembly 10 corresponding to the positioning of the low-speed and power terminals may electrically isolate the differential high-speed terminals on either side of the low-speed and power terminals from harmful electrical interference. More specifically, this portion may function to isolate or "block" one set of high-speed terminals configured to conduct communication (data) signals, located on one side of the low-speed and power terminals, from harmful electrical interference caused by communication (data) signals conducted by a second set of high-speed terminals on the opposite side of the same low-speed and power terminals. This “block” or separation can reduce harmful electrical crosstalk between opposing differential high-speed terminals and improve the signal-to-noise performance of each high-speed data signal being transmitted by the high-speed terminals.

[0099] Referring here to Figure 3F, one or more separate conductive grounding shield elements 16a to 16n are shown. In one embodiment, one or more elements, in this case element 16a ("first element"), may be configured to cover one or more differential high-speed terminals of the wafer of the upper port wafer assembly 10 (terminals not shown are covered), while another element 16n ("second element") may be configured to cover different differential high-speed terminals of the same wafer. In one embodiment, elements 16a to 16n together may constitute a multi-piece conductive grounding shield. It should be understood that each wafer of the wafer assembly 10 may have its own conductive grounding shield element (see, for example, elements 16aa to 16an in Figure 3H).

[0100] Furthermore, as shown in the figure, there is no conductive earth shield covering the low-speed and power terminals 31a to 31n within the gap "g1". In other words, in one embodiment, the first and second conductive earth shields 16a and 16n may be configured to have a gap g1 between them, and the dimensions of the gap g1 correspond to the area (length × width) obtained by multiplying the total number of low-speed and power terminals 31a to 31n plus one terminal by the required pitch of the terminals (for example, if the area of ​​four terminals is "X", the dimensions of the gap g1 are equal to (area of ​​X + area of ​​1 / 4X) × terminal pitch. For the reader's benefit, if the exemplary terminal pitch is 0.8 millimeters and there are five exemplary low-speed and power terminals, the gap g1 may be, for example, 4.0 millimeters.

[0101] Since the exemplary conductive multi-piece grounding shield does not cover all terminals of the wafer, at least during the operation of the low-speed and power terminals 31a-31n, the heat generated and dissipated by the uncovered low-speed and power terminals 31a-31n can be cooled, for example, by air flowing over the terminals. In other words, air flowing over the terminals can remove, for example, the heat generated by such terminals. In addition, in embodiments in which one of the conductive grounding shields 16a is configured to cover the high-speed transmit / transmitter terminal and the other 16n is configured to cover the high-speed receive / receiver terminal, the separation of the grounding shields can function, for example, to electrically isolate the transmit terminal from the receive terminal to reduce the effects of harmful electrical interference and / or noise. The separated conductive grounding shields 16a-16n are just one of the temperature and electrical controls of the present invention discovered by the inventors. The use of multiple separated (e.g., two) elements 16a, 16n may be referred to herein as a “split conductive grounding shield,” or simply a “split shield.”

[0102] The shield in Figure 3F is separated into two elements 16a and 16n with a gap g1 between them, but it should be understood that alternative exemplary shields may include additional shielding (for example, two or more separated shields with gaps between them may be configured to cover a high-speed transmit terminal, and two or more separated shields with gaps between them may be configured to cover a high-speed receive terminal).

[0103] Furthermore, the two shields 16a and 16n may be combined into a single shield having an opening, vent, or aperture in its central portion to allow for airflow and temperature control. In other words, one (or more) conductive grounding shield elements may be configured to cover some or all of the differential high-speed terminals of the wafer.

[0104] Figures 3F and 3G also illustrate another feature of the assembly of the present invention. More specifically, one or more of the low-speed / power terminals 31a-31n in a row of wafers (i.e., the same row) of the upper port assembly 10 may be configured to be offset from the low-speed / power terminals of a different row of a different wafer (i.e., shifted from the vertical axis "Y"), as indicated by the circled portions 18a-18n.

[0105] Figure 3G shows a magnified view of offsets 18a–18n. As can be seen within gap g1, there may be multiple rows of terminals (e.g., terminals 31a–31n) within gap g1, with one row nested beneath the other (except for the top row). For ease of understanding, in Figure 3G, for example, the rows of terminals are labeled 1–4, representing four wafers in the exemplary upper port.

[0106] As shown, the low-speed / power terminals in rows 3 and 4 may be offset to the left by half a pitch, while the terminals in rows 1 and 2 may be offset to the right by half a pitch. In one embodiment, the offset allows terminals 1-4 in each row to be aligned in a straight line, allowing air to pass through. In one embodiment, the distance by which terminals (e.g., 31a-31n) can be offset from the vertical axis Y'' may be, for example, half a pitch.

[0107] In addition, by configuring a set of terminals in a column offset from the vertical axis "Y", the terminals (e.g., low-speed and power terminals) can be more easily aligned.

[0108] Referring here to Figure 3H, another diagram of exemplary wafers 15a-15n is shown (i.e., here the labeled lines in Figure 3H refer to the tail edges and contact points of wafers 15a-15n). In one embodiment of the present invention, it should be understood that each of the one or more wafers 15a-15n may support one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals, and one or more ground terminals. Furthermore, a conductive ground shield (e.g., a split shield or a single shield) described elsewhere in this specification may be configured between some of the one or more wafers, among other things, to reduce harmful crosstalk between the respective conductors constituting each wafer. However, in certain embodiments, a shield may not be configured between certain wafers. For example, Figure 3H shows wafers 15a to 15n where conductive ground shields 16aa to 16an may be configured between wafers 15a and 15b, between 15c and 15n, and on wafers 15a and 15d, but a shield does not need to be configured between wafers 15b and 15c due to the field affinity generated between shield 16ac and the terminals of wafer 15c.

[0109] More specifically, each of the one or more wafers 15a-15n supporting one or more differential high-speed terminals may have a conductive ground shield positioned at a first distance close to its respective differential high-speed terminal to generate field affinity between its respective ground shield and the differential high-speed terminal. In one embodiment, the differential high-speed terminals of each wafer 15a-15n may be configured to conduct communication data signals at a specific power level. Thus, each corresponding ground shield 16aa-16an may function as a conductive ground reference structure positioned very close to each terminal of a given wafer 15a-15n to generate field affinity. That is, the very close positioning of each ground shield 16aa-16an to its respective wafer 15a-15n and the terminals it contains functions to electrically couple signals conducted within the terminals (e.g., high-speed data signals) to each shield 16aa-16an (referred to as signal or field "affinity").

[0110] In order to create such field affinity in the connector assembly of the present invention, in one embodiment, each exemplary shield, for example, shield 16ac in Figure 3H, may be positioned at a first distance h1 from each signal terminal of a wafer, for example, wafer 15c, where this first distance is smaller than a second distance h2 from the same terminal of wafer 15c to a terminal of another wafer, for example, wafer 15b. In other words, shield 16ac may be positioned at a smaller distance, closer to the terminals of wafer 15c, compared to the positioning of the terminals of wafer 15b.

[0111] In this embodiment, this field affinity can be generated between each wafer 15a-15n and their respective positioned shields 16aa-16an. Due to this field affinity, shielding is not required between wafers 15b and 15c.

[0112] The exemplary non-limiting distances h1 and h2 may be 0.30 millimeters and 2.40 millimeters, respectively.

[0113] Furthermore, in one embodiment, the first distance h1 must be less than a third distance between any two differential signal terminals of a given wafer (for example, in Figure 3R, the third distance h3 represents the distance between adjacent high-speed differential signal l terminals of the same wafer, and therefore h1 must be less than h3). Furthermore, in embodiments that include a ground terminal between sets of differential signal terminals (for example, one of terminals 30a to 30n between sets of differential terminals 32a to 32n in Figure 3R), the distance h1 must be much smaller than the distance formed between one of the differential signal terminals 32a to 32n of one set of terminals and the nearest adjacent differential signal terminals 32a to 32n of an adjacent second set of differential signal terminals, as shown by h4 in Figure 3R.

[0114] Referring to Figure 3I, an alternative embodiment including a further temperature control mechanism is shown. This figure shows the rear of the housing 2j. As shown, the housing 2j has one or more gaps or openings g 2a-2n It may include a gap g. 2a-2n The dimensions (i.e., area) of the central gap may be at least equal to the dimensions of the gap g1 described elsewhere herein. In one embodiment, there is an opening g on the rear of the housing 2j. 2a-2n By including this, for example, air can flow and remove heat generated by at least the low-speed and power terminals 31a-31n of each wafer within the housing 2j. In Figures 3B, 3F, and 3I, the conductive segmented grounding shield is separated into multiple elements along the vertical axis "Y". Figure 3I also shows, for example, pegs 17a-17n for securing the housing to the PCB.

[0115] Referring here to Figure 3J, in an alternative embodiment, the exemplary conductive segmented grounding shield may include, for example, two or more distinct elements 20a to 20n separated along axes other than the vertical or Y axis, e.g., the "X" or "Z" axis, to cover a terminal portion of the wafer 15nn.

[0116] While the above description illustrates a segmented shield, it should be understood that this is merely an example. Alternatively, the conductive ground shield of the present invention for a wafer (e.g., an upper port wafer or a bottom port wafer) may comprise a single element (i.e., a single piece). Thus, in alternative embodiments, the conductive ground shield element may be configured to cover one or more differential high-speed terminals, one or more low-speed terminals, one or more power terminals, and one or more ground terminals of each wafer (e.g., one shield per wafer).

[0117] For example, referring here to Figure 3K, a single-element conductive ground shield 21 is shown, configured to cover all of one or more terminals on one or more wafers (e.g., low-speed and power terminals 31a-31n and high-speed terminals 32a-32n and ground conductor or terminals 30a-30n). As shown, each differential high-speed terminal 32a-32n may be configured such that another differential high-speed signal terminal 32a-32n is located on one side and the ground terminals 30a-30n are located on the other side.

[0118] In addition to temperature and alignment control mechanisms, the inventors also provide a method and structure of the present invention that combines a metal grounding conductor / terminal and a plastic conductive grounding shield.

[0119] Referring here to Figures 3L to 3N, stitched, insert-molded grounding conductors or terminals are shown. In one embodiment, “stitching” means that one or more insert-molded metal grounding conductors 22a to 22n in, for example, Figures 3L and 3M can be mated with their respective grounding conductive portions, which are part of the plastic grounding shield elements 16a”, 16n”, by applying an interference mating force that (typically) forces the elements together (referred to as “stitchable mated”).

[0120] In these embodiments, the grounding conductive portions 23a to 23n may include conductive plastic that can operate to function as grounding path segments, for example, connecting one conductive metal portion 22a to another metal portion 22n.

[0121] Figure 3L shows the metal conductive ground portions 22a-22n, which are illustrated separately from the respective ground conductor portions 23a-23n of each plastic conductive ground shield. However, it should be understood that all the components of Figure 3L, when combined as shown in Figure 3M, for example, can form a single stitchable-fit structure. In embodiments, the illustrated metal portions 22a-22n may consist of copper, a copper alloy, or another conductive metal (e.g., gold, platinum).

[0122] It should be noted that stitching wafer conductors / terminals is one method of connecting conductors. Alternatively, the conductors / terminals may include, for example, a support structure for connecting wafer terminals to the nosepiece of an upper port module.

[0123] The grounding conductive portions 23a to 23n of the grounding shield elements 16a'' and 16n'' can consist of metal, conductive or plated plastic, or a hybrid laminate having dielectric and conductive elements such as a PCB portion. For example, in Figure 3M, the grounding conductive portions 23a to 23n are made of plated plastic. Alternatively, in Figure 3N, the grounding conductive portions 24a to 24n may be metal. Therefore, the electrical grounding paths P1 to P N This can be formed as a continuous metal conductor (for example, as shown in Figure 3N) or as some combination of metal and plastic conductive parts (for example, as shown in Figure 3M).

[0124] Please note that sections 22a to 22n are not separate parts but may constitute a continuous conductive structure.

[0125] In addition to providing the temperature and alignment control mechanism of the present invention, the connection assemblies of the present invention provided by the inventors may also include a mechanism for reducing the impedance of each grounding path and a mechanism for reducing harmful electrical crosstalk. For example, in embodiments of the present invention, the inventors provide a connector assembly of the present invention that includes an electrical grounding structure that functions to maintain substantially the same voltage gradient (i.e., voltage difference) substantially along the length of the grounding structure. While zero voltage gradient along the entire grounding structure may not be actually achievable, in embodiments of the present invention, the grounding structure discovered and provided by the inventors minimizes such a gradient substantially along the entire structure at the operating temperature. The ability to minimize such a voltage gradient substantially along the entire grounding structure provides a connector assembly of the present invention having a high-quality grounding reference structure, which in turn can reduce conducted crosstalk and further reduce coupling crosstalk between terminals, providing a reduction in shared voltage and providing an effective ground drain against any induced or coupling voltages caused by electrical noise.

[0126] For example, the inventors provide a connector including a structure configured to form a double grounding path. Referring here to Figure 3P, a double grounding path configuration according to one embodiment of the present invention is shown. For ease of explanation, Figure 3P does not include the low-speed terminal and the power terminal.

[0127] As shown, the diagram of the upper port grounding path assembly 10” may include a dual grounding path, one of which may be formed by individual grounding conductors 30a-30n, and the other grounding path may be formed by conductive deflectable spring “finger parts” or tabs 28a-28n (collectively “finger parts”) of an insert-molded conductive grounding plate 28 and a conductive plated plastic shield 21a. More specifically, each of the finger parts 28a-28n may be inserted into channels 36a-36n formed in the shield 21a.

[0128] In one embodiment, each of the grounding conductors 30a to 30n may function as a first grounding path, which includes a structure in which one end is connected to a terminal of an input / output module (e.g., card 7b), positioned parallel and inline with the respective differential signal conductors, and the other end is connected to the surface of a PCB (e.g., PCB 3).

[0129] When assembled, each of the finger portions 28a to 28n can be electrically and galvanically connected (i.e., in contact with) the respective contact points of the grounding conductors 30a to 30n (i.e., the tips of the conductors 30a to 30n), thereby functioning to provide a portion of a second grounding path. The second grounding path can pass from such contact points through the respective finger portions 28a to 28n and the conductive plate 28, and then through the conductive plated plastic 21a.

[0130] The drawings and description herein describe a second grounding path formed for differential high-speed terminals 32a-32n, but it should be understood that similar additional grounding paths may be formed for low-speed terminals 31a-31n. In either case (high-speed and low-speed applications), the inventors have found that the formation of double or multiple grounding paths results in an overall improvement in the integrity of the grounding path structure of the assembly. This ensures that the electrical impedance and steady-state resistance of the grounding structure along the length of the grounding path are controlled. The ability to control impedance and resistance further enables control of the temperature of power terminals / conductors associated with grounding, for example, when such power conductors conduct higher currents, the double grounding paths share the current (i.e., the lower the resistance, the less power may be lost or dissipated).

[0131] As described herein, the shield 21a may be plated plastic. Alternatively, the shield 21a may consist of, for example, plated ceramic (i.e., ceramic with conductive flashing), plated metal, or another conductive material having a dielectric coating such as nickel, tin, gold, or copper coating. The conductive deflectable finger portions are shown as part of the whole plate, but it should be understood that this is merely illustrative. Alternatively, each of the finger portions may be insert-molded, for example, within the grounding shield structure of their respective plastics.

[0132] In embodiments including a separate finger-shaped structure, it should be noted that terminals that can be supported by redundant, isolated grounding paths may take advantage of the overall lower longitudinal resistance along the path to the end of the substrate, and thus share the benefit of reduced path resistance, resulting in lower heat generation in the power delivery function.

[0133] Other dual grounding path structures / configurations may also be included in the assembly of the present invention. For example, Figures 3Q and 3R show a configuration including conductive deflectable spring fingers or tabs 35a-35n (collectively, “fingers”) that may be insert-molded as part of a conductive plated plastic shield 21b but not as part of a conductive plate. In this embodiment, a first grounding path may be formed by each of the grounding conductors 30a-30n, while a second grounding path may be formed by each of the fingers 35a-35n in contact with each of the contact points of the grounding conductors 30a-30n (i.e., the tip or top of the conductors 30a-30n), thereby serving to provide a second grounding path through each of the fingers 35a-35n and the conductive plastic shield 21b from such contact points. Figure 3Q also shows an optional additional gap g in the intermediate shield (hidden from view) of the upper port wafer assembly 10 for temperature control. 3a-3n This indicates that.

[0134] In each of the dual grounding paths described herein, each path has a corresponding voltage difference that can be measured between opposing ends of the path (e.g., from the tip of each finger portion 28a-28n to PCB3 or from the tip of each conductor 30a-30n to PCB3) due to the impedance of each path. In embodiments, the presence of dual grounding paths substantially reduces the combined impedance shared along the length of each path. For example, if the first path has an impedance of Z1 and the second path has an impedance of Z2, the shared combined impedance Z3 is smaller than Z1 or Z2 and can be given by the relationship Z3 = 1 / [(1 / Z1)+(1 / Z2)].

[0135] Referring here to Figures 3S and 3T, exemplary tail alignment and support structures 14 and 46 according to embodiments of the present invention are shown. In one embodiment, for example, structure 14 is configured as a non-conductive upper port tail alignment and support structure that can be connected to the tail edges 30a' to 30n of the ground terminals 30a to 30n, the tail edges 32a' to 32n of the differential high-speed terminals 32a to 32n, and the tail edges 31a' to 31n of the low-speed and power terminals 31a to 31n at the bottom of the connector assembly, while structure 46 is configured as a conductive bottom port tail alignment and support structure that can be connected to the tail edges of the ground terminals 43a to 43n, the differential high-speed terminals 42a to 42n, and the low-speed and power terminals 49a to 49n at the bottom of the connector assembly.

[0136] Structure 14 may include tail alignment protrusions 14a to 14n, each of which may be inserted into or attached to the apertures of the side plates 9a and 9b (see Figure 3A or Figure 3D). In addition, such exemplary structure 14 may include one or more mounting structures 26a to 26n and 27a to 27n. In one embodiment, structures 26a to 26n may constitute nonconductive plastic that can be covered with an adhesive for attaching structure 14 to a PCB such as PCB 3 in Figure 1A, and may be combined with one or more structures 27a to 27n that can be soldered to further attach structure 14 to the PCB. Alternatively, all of structures 26a to 26n and 27a to 27n may constitute nonconductive plastic that can be covered with an adhesive, or all may constitute, for example, solderable plated nonconductive plastic or metal.

[0137] Now, the inventors turn their attention to the bottom port wafer assembly. It should be noted that assembly 1 in Figure 1B shows both the top port 8a and the bottom port 8b. Each port has a corresponding wafer assembly which may include multiple wafers, and therefore may include multiple terminals.

[0138] Figure 4A shows a magnified view of the bottom port 8b, while Figure 4B shows a magnified view of an exemplary bottom port wafer assembly 40 within port 8b. It should be understood that some features of the top port wafer assembly can be incorporated into the bottom port wafer assembly. For example, the bottom port wafer assembly may include a side plate for holding the tail portion of the wafer terminals to align the tail edge of the wafer terminals, but such a plate is not shown in Figures 4A and 4B.

[0139] In one embodiment, the bottom port wafer assembly 40 may be configured to connect to the PCB 3 using, for example, SMT. In an alternative embodiment, the bottom port wafer assembly 40 may be connected to the PCB 3 using, for example, a ball grid array, solder charge, press fit, SMT, fiber optic technology, or a combination of such technologies.

[0140] Similar to the upper port wafer assembly, each wafer of the bottom port wafer assembly 40 may include one or more separate power and low-speed communication signal conductors / terminals, one or more differential high-speed conductors / terminals, and one or more ground conductors. In embodiments, at least exemplary high-speed communication signals up to and exceeding 100 gigabits Gbps may be transmitted by the high-speed signal conductors of the assembly 40. In alternative embodiments, communication signals up to 160 Gbps may be transmitted by the high-speed conductors.

[0141] In one embodiment, the low-speed / power terminal may be located, for example, in the center of the wafer. Furthermore, each differential high-speed terminal may be configured such that another differential high-speed signal terminal is located on one side and a ground terminal is located on the other side.

[0142] In Figure 4B, the bottom port wafer assembly 40 may include a conductive grounded plastic shield element 41 configured to cover the lead frame and each of its wafers. Similar to the upper port wafer assembly described above, the shield 41 may include plated plastic. Alternatively, the shield 41 may consist of a hybrid laminate having dielectric and conductive elements such as plated ceramic (i.e., ceramic with conductive flashing), plated metal, or PCB portion, or another conductive material having a dielectric coating such as nickel, tin, gold, or copper coating. Although shown as a single, integrated piece, it should be understood that the shield 41 may include multiple separate elements (e.g., two elements) where duplicate or redundant paths can be created to take advantage of the overall lower longitudinal resistance, thereby sharing the benefits of reduced path resistance and having lower heat generation in the power delivery function.

[0143] The bottom port wafer assembly may also include a dual grounding path configuration similar to that described above. For example, one grounding path may be formed by individual grounding conductors 43a-43n, and the other grounding path may be formed by conductive deflectable “finger parts” 45a-45n. More specifically, each of the grounding conductors 43a-43n may function as a grounding path to a PCB such as PCB 3. In one embodiment, when assembled, each of the finger parts 45a-45n may be electrically and galvanically connected to the respective contact portion (i.e., tip or upper portion) of the grounding conductors 43a-43n, thereby functioning to provide a second grounding path from such contact point through each finger part 45a-45n and then through conductive plated plastic 41 to the PCB. High-speed terminals 42a-42n and low-speed and power terminals 49a-49n are also shown.

[0144] Other dual grounding path configurations may also be utilized. For example, instead of providing finger portions 45a-45n that are insert-molded within the shield 41, the finger portions may be part of a plate, similar to the plate 28 described above. In each embodiment of the dual grounding path, the dual grounding path configuration may provide the features previously described herein.

[0145] Referring to Figure 4C, an enlarged view of an exemplary wafer 40a of assembly 40 is shown. As shown, the wafer 40a exemplifies a double grounding path formed by individual grounding conductors 43a-43n, as well as by conductive deflectable “fingers” 45a-45n and the shield 41.

[0146] Figure 4D shows an exploded view of an exemplary wafer 40a. In one embodiment, deflectable metal "finger portions" 45a-45n may be welded to or otherwise electrically attached to dielectric lead frame support structures 44a-44n, which also support primary ground conductors 42a-42n (e.g., high-speed conductors / terminals).

[0147] Figure 4E shows an exploded view of the bottom port wafer assembly 40. As shown, the assembly 40 may include a plurality of dielectric lead frame support structures 47a to 47n, each for supporting and electrically isolating one or more wafers having one or more conductors (e.g., high-speed terminals, low-speed terminals, power terminals, and ground conductors). A conductive bottom port tail alignment structure 46 is also shown for holding the tail portions of the terminals of each wafer and for assisting in aligning the tail edges of each terminal of the bottom port wafer. In one embodiment, the structure 46 may include plated plastic or stainless steel (e.g., stainless steel SUS301, copper C70250, etc.).

[0148] Enlarged views of an exemplary wafer 40a are shown in Figures 4F and 4G, and a view of the bottom port wafer 40a from below is shown in Figure 4H. To illustrate one exemplary method of connecting conductive fingers 45a-45n to the lead frame 47a, green cones are shown in Figures 4F and 4G, and it is understood that such cones are merely illustrative of connection points and not physical structures. In one embodiment, at each connection point indicated by the green cones, the exemplary conductive fingers 45a-45n may be welded, for example, to connect to the lead frame 47a.

[0149] Referring here to Figure 4I, an enlarged view of an exemplary conductive bottom port tail alignment and support structure 46 according to an embodiment of the present invention, viewed from below port 8b. In one embodiment, unlike the tail alignment and support structure 14 of the upper port wafer assembly as described above, the structure 46 may consist of a conductive material (e.g., metal, plated plastic). To provide alignment control, the tail edges 42a'~42n' of one or more high-speed terminals 42a~42n, the tail edges 49a'~49n' of one or more low-speed and power terminals 49a~49n, and the tail edges 43a'~43n' of one or more ground conductors 43a~43n may be connected to the structure 46. Furthermore, the bottom port tail alignment and support structure may include a plurality of projections that can be inserted into the side plate (e.g., apertures similar to 11a~11n and projections similar to 14a~14n).

[0150] In addition to alignment control, structure 46 can provide control over undesirable electrical interference (e.g., noise). For example, structure 46 may be configured as a ground reference plane structure surrounding, for example, differential high-speed terminals 42a-42n and their tail edges 42a'-42n'. Such a ground reference plane structure may be configured to electrically "reflect" (i.e., be configured similarly to) an electrical ground plane structure formed on the surface of the mated PCB (e.g., PCB 3). In embodiments, it should be understood that the "reflected" conductive ground structure (e.g., the surface of structure 46 and PCB 3) and the conductive surface do not need to be in direct galvanic contact with each other to electrically isolate, for example, differential signals conducted within high-speed terminals 32a-32n from differential signals conducted by terminals / conductors on the surface of the PCB. In one embodiment, to provide such electrical isolation, structure 46 may be separated from the surface of the PCB by 0.25-0.50 mm, to give just one non-limiting distance. Although not in direct galvanic contact, two opposing reflected structures / surfaces can function as an electrical capacitor, i.e., two conductive structures / surfaces separated by a dielectric (in this case, generally air).

[0151] In one embodiment, the structure 46 may be an integral part of the bottom port wafer assembly.

[0152] In previous considerations, assembly 1 included a central housing 2j enclosing both the upper and lower ports 8a and 8b. In one embodiment, an alternative housing may enclose a single port.

[0153] Referring here to Figure 5A, a connector 1b is shown which may be part of an alternative high-speed shielded multi-level multi-port connector assembly 100. As shown, connector 1b may include a central housing 102. Similar to housing 2j, the central housing 102 may be within cage 2 and may be made of plastic (e.g., LCP). Unlike housing 2j, housing 102 may enclose a portion of the upper port 88a but may not enclose the bottom port 88b. Housing 102 may be configured to protect one or more conductive wafers (not shown) within housing 102.

[0154] In one embodiment, the housing 102, ports 88a and 88b, internal wafers and their respective terminals, and additional components within the housing 102 can form a high-speed, shielded, multi-level, multi-port connector with temperature and alignment control, among other features. In one embodiment, connector 1b may include an input / output (I / O) connector, such as one used for quad-small form factor pluggable applications or quad-double-density small form factor pluggable applications (e.g., QSFP, OSFP, CDFP applications). Thus, the assembly 100 including the housing 102 can be referred to as a high-speed, shielded, multi-port, multi-level connector assembly with temperature and alignment control, among other features.

[0155] A conductive terminal, which is part of the wafer within connector 1b, may be configured to conduct electrical signals. Additionally, in an alternative embodiment, the terminal may also be configured to supply electrical signals to, for example, an E / O conversion circuit or to receive electrical signals from an O / E conversion circuit. In the latter case, such an O / E or E / O conversion circuit may be included and connected to the respective conductive wafer, for example, a cage mated to an active electronic circuit.

[0156] In many cases, signals conducted through conductive wafers, O / E and E / O conversion circuits, active devices, and retiming circuits can generate a considerable amount of heat during operation. Therefore, as described herein, the inventors provide solutions for controlling such temperatures.

[0157] The housing 102 may be configured to have one or more notches 101a-101n on both sides to contact the bottom port 88b. Alternatively, pillars or trusses may also be used to support the housing above the bottom port 88b (see, for example, Figure 5D). Compared to housing 2j, housing 102 does not enclose a portion of the bottom port 88b, unlike housing 2j which encloses a portion of the bottom port 8b, thus providing additional degrees of freedom in the assembly process (i.e., the upper port 88a and the lower port 88b are independent of each other and can be operated freely without affecting each other).

[0158] Figure 5B shows an exploded view of connector 1b. As shown, the housing 102 may include a central structure 102a, a first support side plate 102b, and a second support side plate 102c (e.g., a metal side plate) opposite the first support side plate 102b. In embodiments of the present invention, each side plate 102b, 102c may be configured to connect to and fix to the position of the wafer within the internal housing 102 (i.e., between wafers). More specifically, the side plates 102b, 102c may be configured to have one or more apertures 104a-104n, each aperture 104a-104n configured to receive the respective first projections 105a-105n of the upper port wafer assembly to control the positioning of the wafer terminals within the upper port, so that the wafer can be held and the tail edges of the respective terminal tail portions can be aligned in the same plane. Furthermore, in order to fix the central structure 102a and each side plate 102b, 102c to the underlying PCB (for example, PCB3 in Figure 1A), the central structure 102a and each side plate 102b, 102c may be configured to have one or more integrated deformable substrate locks 103a to 103n, which may be made of, for example, deformable metal or plastic.

[0159] Figure 5B also shows a plurality of dielectric lead frame support structures or hangers 117a-117n (abbreviated as "hangers") which may be made of plastic such as LCP. In one embodiment, each hanger 117a-117n may be configured to provide physical support and alignment for each upper lead frame. Each hanger 117a-117n may be further configured to have heat stake posts 118a-118n (see Figure 5C), each post may be configured to be received by alignment openings in their respective side plates 102b, 102c.

[0160] Referring here to Figures 5D and 5E, an alternative upper port support structure 107 is shown, which is configured to be fixedly positioned between the upper port 88a and the bottom port 88b. In one embodiment, the structure 107 may include one or more apertures 108a-108n, each aperture configured to receive its respective upper port projections 109a-109n, thereby fixing the structure 107 in place. As configured, the structure 107 may be operable to support the upper port 88a and the wafer within the upper port 88a. Although shown as an open rectangle, it should be understood that this is merely one exemplary shape and structure for the upper port support structure 107. Other shapes and structures may be used, for example, an open or filled square structure.

[0161] In further embodiments, the upper port 88a may be connected separately to PCB 3 using, for example, SMT technology. Such an exemplary upper port assembly is shown in Figure 5F. In addition to SMT-type connections, as described above, the assembly may be connected to PCB 3 using one or more substrate locks 103a-103n that can be inserted, for example, into corresponding apertures in PCB 3 (e.g., pin-in-paste type holes or compliant pin (press-fit) type holes) to provide alignment control of the wafers constituting the upper port assembly substrate and their respective terminals during reflow operation.

[0162] Figures 5G to 5J show diagrams of connector 1b, including temperature control.

[0163] In Figure 5G, the back cover 102d of the internal upper port housing 102 may include one or more openings 110a to 110n, which allow air to flow over the terminals (e.g., low-speed signal and power terminals) inside the wafer of the connector 1b.

[0164] Referring here to Figures 5H and 5I, a diagram of the upper port lead frame grounding shield 111 is shown. The shield 111 may include a temperature control mechanism for controlling the temperature of the conductors / terminals. For example, one or more openings 112a-112n may be configured within the lead frame grounding shield 111 to allow, for example, air to flow over the slow signal and power terminals 116a-116n. Also shown are fast signal terminals 114a-114n (e.g., differential signal pairs) which may be nested between the grounding conductors 113a-113n. As configured, this configuration provides enhanced shielding. Note that the upper port wafer assembly configuration shown in Figures 5G and 5H may also be incorporated by the upper port wafer assembly 10 described herein.

[0165] Figures 5H and 5I also show, for example, exemplary dielectric lead frame support structures 115a-115n of the upper port assembly. The lead frame support structures 115a-115n may be configured to align and support, for example, a plurality of ground conductors 113a-113n, a plurality of high-speed conductors or terminals 114a-114n, and a plurality of low-speed and power conductors or terminals 116a-116n.

[0166] While the terminals of the grounding conductor, high-speed conductor, low-speed conductor, and power conductor are shown facing downwards, it should be understood that the assembly may also include lead frame structures with upward-facing terminals, which may be supported by similar lead frames and covered by similar grounding shields. In other words, the upper port assembly may include multiple lead frame structures.

[0167] In embodiments of the present invention, the signal-field affinity between the terminals of each lead frame structure 115a to 115n of the assembly and their respective ground shields may be sufficient to limit, for example, harmful coupling and crosstalk between lead frames, as previously described herein.

[0168] Figure 5J shows a diagram of connector 1b having the upper port 88a before the lower port 88b is connected. Board locks 103a-103n are also shown, for example, for securing the upper port assembly to the PCB (e.g., PCB3) during a reflow operation.

[0169] Referring here to Figures 6A and 6b, a diagram of the upper port wafer assembly 13 is shown. As shown, the assembly may include opposing metal side plates (only one is shown) of the internal housing 102. In one embodiment, the assembly may be aligned and connected to a PCB such as PCB 3 using, for example, SMT and substrate locks 103a-103n. The assembly 13 has one or more gaps g that allow airflow over the terminals. 4a-4n Each of the intermediate conductive shields (e.g., plated plastic shields) may further include this.

[0170] As described herein, the inventors have discovered connector assemblies and related methods of the present invention that include a plurality of alignment controls for both the mated device (e.g., a high-speed active plug module) and the alignment of both the internal conductor and the ground wafer. Furthermore, the temperature control included in the connector assemblies of the present invention enables such connectors to control the temperature (e.g., up to more than 20 watts) generated by the electronic circuitry in the connected plug-in module, enabling the effective transfer of communication (data) signals up to at least 100 Gbps.

[0171] While certain features and functions of the present invention have been described with reference to one embodiment of the present invention or illustrative drawings, it should be understood that these are merely illustrative. That is, several features and functions may be applicable and may be incorporated into many embodiments other than those specifically described or shown in the drawings.

[0172] The claims included below are incorporated herein by reference in an expanded form, i.e., hierarchically from the broadest to the narrowest, and each possible combination is indicated by reference to a number of dependent claims described as distinct, independent embodiments.

[0173] Benefits, other advantages, and solutions to problems have been described above in relation to specific embodiments of the present invention. However, benefits, advantages, solutions to problems, and any elements that cause, can bring about, or make more apparent such benefits, advantages, or solutions should not be construed as important, necessary, or essential features or elements of any or all of the patent claims.

Claims

1. A connector assembly, Housing including ports, The housing includes a wafer assembly having contacts located within the port of the housing, The wafer assembly includes a row of conductors, which comprises a row of communication signal conductors and a row of ground conductors arranged within it. A connector assembly in which each communication signal conductor is located next to one of several ground conductors in the row of conductors.

2. The connector assembly according to claim 1, wherein the communication signal conductor comprises a plurality of high-speed communication signal conductors and a plurality of low-speed communication signal conductors, the plurality of low-speed communication signal conductors being located in the center of a row of conductors, at least one pair of the plurality of high-speed communication signal conductors being on the first side of the low-speed communication signal conductors, and at least one pair of the plurality of high-speed communication signal conductors being on the second side of the low-speed communication signal conductors.

3. The connector assembly according to claim 1, wherein the row of conductors further includes power conductors, the first pair of communication signal conductors is on the first side of the power conductors, and the second pair of communication signal conductors is on the second side of the power conductors.

4. The connector assembly according to claim 1, wherein the wafer assembly further includes a grounding path assembly.

5. The connector assembly according to claim 4, wherein the grounding path assembly includes at least one of a metal grounding shield, a plated plastic grounding shield, or a laminate of a dielectric and a conductive metal.

6. The connector assembly according to claim 4, wherein the grounding path assembly includes a plated plastic grounding shield and a metal grounding shield insert stitched to the plated plastic grounding shield.

7. The connector assembly according to claim 1, wherein the wafer assembly further comprises a grounding path assembly, the grounding path assembly comprising a double grounding path for a grounding conductor.

8. The grounding conductor includes a contact tip portion and a tail portion. The connector assembly according to claim 7, wherein the grounding path assembly includes a grounding shield and a conductive spring finger inserted into a channel of the grounding shield, the finger contacting the upper surface of the grounding conductor.

9. The row of conductors includes a row of transmitting conductors, The connector assembly according to claim 1, wherein the wafer assembly further includes a second row of conductors, the second row of conductors including a row of receiving conductors.

10. The connector assembly according to claim 1, wherein the wafer assembly further includes a second row of conductors, the second row of conductors including a row of high-speed communication signal conductors, a row of low-speed communication signal conductors, and a row of ground conductors arranged therein.

11. The wafer assembly further includes a grounding shield between the row of conductors and a second row of conductors. The plurality of low-speed communication signal conductors in the second row of the conductor are located in the center of the second row of the conductor. The connector assembly according to claim 10, wherein a plurality of low-speed communication signal conductors in a second row of the conductors are offset from a plurality of low-speed communication signal conductors in a row of the conductors and form an air-permeable gap located in the center of the wafer assembly.

12. The connector assembly according to claim 1, wherein the wafer assembly further comprises a second row of conductors, a third row of conductors, and a fourth row of conductors.

13. The connector assembly according to claim 12, wherein the wafer assembly further comprises a first grounding shield between the row of conductors and a second row of conductors, and a second grounding shield between the third row of conductors and a fourth row of conductors.

14. The connector assembly according to claim 13, wherein there is no grounding shield between the second row of conductors and the third row of conductors, and the second row of conductors faces the third row of conductors.

15. The connector assembly according to claim 12, further comprising a plurality of dielectric lead frame support structures that support and electrically insulate the row of conductors, a second row of conductors, a third row of conductors, and a fourth row of conductors, respectively.

16. The connector assembly comprises a first side plate on one side of the housing, including an aperture and a first side plate extending along the first bottom edge of the housing, A second side plate on the other side of the housing, comprising an aperture and extending along the second bottom edge of the housing, further comprising: The wafer assembly is A first projection located at one end of the row of conductors, the first projection being inserted into the aperture of the first side plate to align the row of conductors, The connector assembly according to claim 1, further comprising a second projection at the other end of the row of conductors, the second projection being inserted into the aperture of the second side plate to align the row of conductors.

17. The connector assembly according to claim 1, wherein the housing includes a latch that contacts a wafer assembly located within a port of the housing and locks the upper part of the wafer assembly within the housing.

18. The port of the housing includes an upper port, The housing further includes a bottom port, The wafer assembly includes an upper port wafer assembly having contacts located within the upper port of the housing, The connector assembly according to claim 1, further comprising a bottom port wafer assembly having contacts located within the bottom port of the housing.

19. The wafer assembly further includes a grounding path assembly, The grounding path assembly includes a first grounding shield and a second grounding shield, The aforementioned communication signal conductor includes a plurality of high-speed communication signal conductors and a plurality of low-speed communication signal conductors. The connector assembly according to claim 1, wherein the plurality of low-speed communication signal conductors are located in the center of a row of conductors, a first pair of the plurality of high-speed communication signal conductors extends along a first ground shield on the first side of the low-speed communication signal conductors, and a second pair of the plurality of high-speed communication signal conductors extends along a second ground shield on the second side of the low-speed communication signal conductors.

20. The connector assembly according to claim 19, wherein the wafer assembly further includes a gap in the row of conductors between the first earth shield and the second earth shield, and the plurality of low-speed communication signal conductors extend between the gaps.

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