Method for manufacturing vapor deposition masks and electronic devices

Abstract

The objective is to provide a vapor deposition mask that suppresses the occurrence of damage, and a method for manufacturing an electronic device using the vapor deposition mask. [Solution] The present invention provides a vapor deposition mask for placing between a substrate to be vapor-deposited and a vapor deposition source, and for vapor-depositing a vapor deposition material from the vapor deposition source onto the surface of the substrate through an opening, comprising: a membrane having an opening region with a plurality of openings and a peripheral region located around the opening region; and a support substrate supporting the membrane in the peripheral region, wherein the side surface of the support substrate includes a tapered surface such that the taper angle between the support substrate and the opposing surface of the membrane facing the support substrate is less than 80°.

Description

Technical Field

[0001] The present invention relates to an evaporation mask and a method for manufacturing an electronic device.

Background Art

[0002] For example, an evaporation mask used for coating three colors of RGB in the production of an organic EL display is known.

[0003] Patent Documents 1 and 2 disclose an evaporation mask having a first layer (outer frame substrate) and a second layer (mask substrate). A plurality of openings are formed in the second layer (mask substrate). The first layer (outer frame substrate) is a substrate that supports the second layer (mask substrate).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In order to achieve high definition of the evaporation mask, it is required to make the mask thinner and process it with high precision. Therefore, problems such as easy breakage occur during handling and cleaning in the manufacturing process of the evaporation mask.

[0006] Patent Documents 1 and 2 do not solve the above problems by improving the shape of the first layer (outer frame substrate).

[0007] An object of the present invention is to provide an evaporation mask in which the occurrence of breakage is suppressed and a method for manufacturing an electronic device using the evaporation mask.

Means for Solving the Problems

[0008] The deposition mask of this embodiment is a deposition mask placed between a substrate to be deposited and a deposition source, for depositing a deposition material from the deposition source onto the surface of the substrate through an opening, and comprises a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region, and a support substrate that supports the membrane in the peripheral region, wherein the side surface of the support substrate includes a tapered surface in which the taper angle between the surface that supports the membrane and a surface parallel to it is less than 80°. [Effects of the Invention]

[0009] According to the present invention, damage caused by handling and cleaning during the manufacturing process of vapor deposition masks can be suppressed, thereby increasing the yield. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing an example of a vapor deposition mask according to this embodiment. [Figure 2] This is a cross-sectional view showing an example of a different deposition mask than the one shown in Figure 1. [Figure 3] This is a magnified section of the support substrate of the vapor deposition mask. [Figure 4] This is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask of this embodiment. [Figure 5] This is a process diagram showing an example of a method for manufacturing the vapor deposition mask of this embodiment. [Figure 6] This is a process diagram showing an example of a method for manufacturing the vapor deposition mask of this embodiment. [Figure 7] This is a cross-sectional view showing an example of a vapor deposition mask according to another embodiment. [Figure 8] This is a cross-sectional view showing an example of a vapor deposition mask according to another embodiment. [Figure 9] This is a cross-sectional view showing an example of a vapor deposition mask according to another embodiment. [Figure 10] This is a cross-sectional view showing an example of a vapor deposition mask according to another embodiment. [Figure 11]It is a plan view of the mask of the experimental example. [Figure 12] (a) is a SEM photograph showing the support substrate used in the experiment, and (b) is a schematic diagram of (a). [Figure 13] (a) is a SEM photograph showing the support substrate used in the experiment, and (b) is a schematic diagram of (a). [Figure 14] (a) is a partially enlarged plan view of the evaporation mask used in the experiment, (b) is a partial cross-sectional view of the evaporation mask, and (c) is a perspective schematic view showing an enlargement of the vicinity of the support substrate of the membrane.

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions, ratios, etc. of each drawing are not necessarily the same as the actual ones. Also, even when the same part is represented between the drawings, the dimensional relationships and ratios between them may be represented differently. In particular, the embodiments shown below are examples of the structures for embodying the technical idea of the present invention, and do not specify the technical idea of the present invention. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the lower limit value and the upper limit value of the numerical range shall include the error range.

[0012] <Background of the Present Invention> Virtual reality / augmented reality (VR / AR) technologies and the VR / AR-related markets are growing rapidly. Along with the progress of the growth, the miniaturization of display panels suitable for the VR / AR field, the high pixelization of the screen resolution (PPI: Pixels Per Inch), the high-speed response, and the high color gamut have been advancing. In order to advance the technology, the spread of silicon-based organic light-emitting diode (OLED) microdisplay panels has become remarkable.

[0013] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. In order to effectively prepare for AR and VR as high-value-added industries, for example, it is expected to embody a display with an ultra-high resolution of 1000 ppi or more. In response to this, the need for vapor deposition masks for RGB painting used in the manufacturing process of OLED microdisplays is increasing.

[0014] For high-definition of the vapor deposition mask, it was necessary to process the thickness of the membrane having a plurality of openings thinly and with high precision. However, when the membrane becomes thin, it is easily damaged due to bending or vibration, such as cracks entering from vulnerable parts. For this reason, for example, problems occurred such as being easily damaged during handling and cleaning in the manufacturing process of the vapor deposition mask, leading to a decrease in yield.

[0015] Therefore, as a result of intensive research by the present inventors, by optimizing the shape of the support substrate that supports the membrane, a vapor deposition mask capable of suppressing damage has been developed.

[0016] <Overview of the vapor deposition mask 1 in the present embodiment> FIG. 1 is a cross-sectional view of the vapor deposition mask 1 in the present embodiment. The vapor deposition mask 1 has a laminated structure of a membrane 2 and a support substrate 4. The vapor deposition mask 1 shown in FIG. 1 is preferably composed of a SOI (Silicon on Insulator) substrate 9 in which the support substrate 4 includes an insulating layer 3 and a silicon substrate 30. Alternatively, the vapor deposition mask 1 shown in FIG. 1 is composed of a SOI substrate 9 including a membrane 1, an insulating layer 3, and a support substrate 4 (in this case, the support substrate 4 does not include the insulating layer 3). The support substrate 4 is, for example, a silicon substrate, but is not limited thereto. The embodiments of FIGS. 8 to 10 described later are illustrated as the support substrate 4 / insulating layer 3 / membrane 2. The membrane 2 is preferably a single-crystalline silicon layer, and is also called a semiconductor layer or an active layer.

[0017] As shown in Figure 1, the deposition mask 1 has multiple aperture regions 15 and a peripheral region 16 located around the aperture regions 15. In the peripheral region 16, the membrane 2 and the support substrate 4 are stacked. On the other hand, only the membrane 2 is placed in the aperture regions 15, meaning the support substrate 4 is removed, and furthermore, multiple minute apertures 5 are formed in each aperture region 15.

[0018] As shown in Figure 1, the membrane 2 has a front surface 2a and a back surface 2b that face each other in the thickness direction. A support substrate 4 is provided on the back surface 2b side. As shown in Figure 4, surface 2a is the surface facing the substrate 10 to be vapor-deposited, and surface 2b is the surface facing the vapor deposition source 11.

[0019] As shown in Figure 4, the membrane 2 has multiple openings 5 ​​that penetrate between the surface 2a and the back surface 2b. As shown in Figure 4, the opening width of each opening 5 gradually narrows from the back surface 2b to the surface 2a. Therefore, the side wall surface 5a of the opening 5 is inclined. Also, in Figure 4, the opening width W1 is defined by the width dimension in the surface direction along the surface 2a. Thus, in Figure 4, the opening width W1 is shown at the point where the width dimension is narrowest. Note that in Figure 4, the symbols for the opening width W1 and the side wall surface 5a are shown only for one opening 5, but they apply similarly to the other openings 5. Also, the distance between adjacent openings 5 ​​is defined as the opening inter-opening dimension W2. Note that the opening inter-opening dimension W2 is defined by the dimension along the surface 2a.

[0020] While not limited to these, the aperture width W1 is approximately 1 μm to 20 μm, preferably 3 μm to 15 μm, and more preferably 5 μm to 10 μm.

[0021] Furthermore, although not limited thereto, the aperture dimension W2 is approximately 1 μm to 20 μm, preferably between 1 μm and 15 μm, and more preferably between 3 μm and 10 μm.

[0022] The planar pattern of the opening 5 (the shape viewed from directly above the membrane 2 toward the surface 2a) is not limited, but examples include rectangles (including squares), polygons other than rectangles, circles, and ellipses. Furthermore, all openings 5 ​​may have the same planar pattern, or some may differ. In addition, each opening 5 may be arranged regularly, irregularly, or a mixture of regular and irregular arrangements.

[0023] The outer shape of the membrane 2 is preferably a rectangular or disc-shaped wafer, and although the diameter (or the length of one side in the case of a rectangular shape) is not limited, it is preferably about 100 mm to 500 mm. In this way, even if the diameter of the membrane 2 is large, each opening 5 can be formed uniformly.

[0024] The insulating layer 3 can be an oxide layer or a nitride layer, but it is preferably an oxide layer, and specifically, a silicon oxide (SiO2) layer is preferred. The insulating layer 3 is also called the BOX layer (Buried Oxide Layer). There is no limit to the thickness of the insulating layer 3, but for example, it is about 100 nm to 20 μm.

[0025] The insulating layer 3 shown in Figure 1 is not provided in the opening region of the membrane 2 facing the opening 5 and has been removed, remaining only in the area surrounding the opening region on the back surface 2b of the membrane 2. The insulating layer 3 acts as an etching stopper for the membrane 2, and its presence enables stable processing.

[0026] As shown in Figure 1, the support substrate 4, which includes the insulating layer 3 and the silicon substrate 30, can function as a columnar portion 16a and an outer peripheral frame 16b that constitute the surrounding region 16 of the opening region 15 on the back surface 2b of the membrane 2. Therefore, the membrane 2 can maintain a taut state due to the support substrate 4, eliminating the need for tensioning, and the deposition mask 1 of this embodiment can be brought into close contact with the substrate 10 to be deposited using an electrostatic chuck that utilizes electrostatic force. As shown in Figure 1, the columnar portion 16a is located inside the outer peripheral frame 16b, and they are all at the same height, but for example, the height of the columnar portion 16a may be lower than the outer peripheral frame 16b. However, maintaining the same height allows for better strength.

[0027] Furthermore, although not shown in Figure 1, alignment marks can be formed on the outer peripheral region of the surface 2a side of the membrane 2. These alignment marks can be formed, for example, as concave shapes on the surface 2a and to a depth that extends to the insulating layer 3.

[0028] <Detailed description of the support substrate 4 in this embodiment> As shown in Figure 1, the support substrate 4 has a first surface 4a facing the membrane 2 and a second surface 4b opposite to the first surface 4a. The first surface 4a is the surface closer to the substrate 10 to be deposited, as shown in Figure 4, and the second surface 4b is the surface closer to the deposition source 11, as shown in Figure 4.

[0029] As shown in Figure 1, the support substrate 4 is provided with a side surface 4e that connects the edge 4c of the first surface 4a and the edge 4d of the second surface 4b. The opening region 15 of the membrane 2 is provided inside the area enclosed by this side surface 4e.

[0030] As shown in Figure 1, the side surface 4e is inclined such that the width of the support substrate 4 gradually increases from the second surface 4b to the first surface 4a of the support substrate 4.

[0031] In this embodiment, the taper angle θ of the side surface 4e is defined by the angle between the surface supporting the membrane 2 and a surface parallel to it. The "surface supporting the membrane 2" is the back surface 2b of the membrane 2 and the first surface 4a of the support substrate 4. In Figure 1, the interface between the silicon substrate 30 and the insulating layer 3 (referred to as the "third surface 4f") is used as the "parallel surface". The "parallel surface" may be other than the third surface 4f, for example, the first surface 4a, but it is preferable to use a surface that makes it easy to measure the taper angle θ. Here, since the insulating layer 3 constituting the support substrate 4 is extremely thin compared to the silicon substrate 30, it is desirable to use the side surface 4e of the silicon substrate 30, which can be clearly identified by SEM images, etc., to measure the taper angle θ. Therefore, defining the taper angle θ by the angle between the third surface 4f of the silicon substrate 30 and the side surface 4e of the silicon substrate 30, as shown in Figure 1, allows for the deriving of a more accurate angle.

[0032] In this embodiment, the taper angle θ of the side surface 4e is set to less than 80°. If the taper angle θ of the side surface 4e is 80° or more, when the mask is oscillated (three up-and-down movements) in the cleaning process described later, the area receiving water pressure during the oscillating motion is smaller compared to when the taper angle θ of the side surface 4e is less than 80°, resulting in a larger load per unit area. As a result, the load on the edge 4c of the first surface 4a of the support substrate 4 increases, making the membrane 2 more susceptible to damage. The taper angle θ is preferably 70° or less, more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less. There is no lower limit to the taper angle θ, but for example, it is preferably 5° or more, or 10° or more.

[0033] In the embodiment shown in Figure 1, it is preferable that the entire side surface 4e has a taper angle θ of less than 80°, but it may have a different angle in some parts. For example, in the portion of the insulating layer 3, the side surface may be a vertical surface or an inverse tapered surface.

[0034] By tilting the side surface 4e of the support substrate 4 that supports the membrane 2, the concentration of force applied to the membrane 2 can be mitigated (dispersed) when handling the support substrate 4 as a frame or during the cleaning process. As a result, damage such as cracks between the openings 5 ​​of the membrane 2 can be suppressed, and the yield can be increased.

[0035] Figure 2 is a cross-sectional view showing an example of a different deposition mask than the one in Figure 1. Figure 3 is a magnified partial cross-sectional view of the support substrate of the deposition mask.

[0036] In Figure 1, the side surface 4e of the support substrate 4 is inclined with a generally constant taper angle θ from the second surface 4b to the first surface 4a. However, in Figure 2, the side surface 4e is formed by a first tapered surface 6 and a second tapered surface 7. As shown in Figure 2, the first tapered surface 6 and the second tapered surface 7 have different taper angles relative to the first surface 4a. In Figure 2, the first taper angle of the first tapered surface 6 is shown as θ1, and the second taper angle of the second tapered surface 7 is shown as θ2. As shown in Figure 2, taper angle θ1 > taper angle θ2. The second tapered surface 7, with a smaller taper angle θ2, is formed closer to the membrane 2 (the side in contact with the insulating layer 3) than the first tapered surface 6.

[0037] As shown in Figure 2, the first taper angle θ1 is approximately 90°, and therefore the first tapered surface 6 is approximately a vertical surface. Hereafter, the first tapered surface 6 may be referred to as the "vertical surface 6". "Approximately" includes an error of 5% or less. The first taper angle θ1 does not have to be approximately 90°, but it is preferable that it be approximately 90° or close to it.

[0038] On the other hand, the second taper angle θ2 is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less, similar to the taper angle θ shown in Figure 1.

[0039] In this way, the taper angle of the side surface 4e of the support substrate 4 is formed in two or more stages, and by making the taper angle smaller closer to the membrane 2, the width between cells can be narrowed, and the panelization efficiency within the mask can be increased. Figure 14(a) shows a partially enlarged plan view of the deposition mask 1 used in the experiment described later, and Figure 14(a) shows cells 8 arranged in a matrix. Numerous openings 5 ​​are formed in the vertical and horizontal directions (XY directions) of the cells 8. Note that in Figure 14(a), only one cell 8 and one opening 5 are typically labeled. The columnar portion 16a of the support substrate 4 (see also Figures 1 and 2) is located on the back side between the cells 8. Figure 14(b) is a partial cross-sectional view showing one cell 8 extracted from Figure 14(a).

[0040] Narrowing the spacing between cells 8 means narrowing the width of the columnar portion 16a of the support substrate 4. To further improve the damage suppression effect, it is desirable to make the second taper angle θ2 of the second tapered surface 7 on the membrane 2 side as gentle as possible. However, if one attempts to construct it with a single-stage tapered surface (Figure 1), it is not possible to form it with a very gentle slope. Therefore, by forming the first tapered surface on the side away from the membrane 2 as a vertical surface 6 or a tapered surface with a high taper angle close to it, and making the second taper angle θ2 of the second tapered surface 7 on the side closer to the membrane 2 smaller, it is possible to narrow the spacing between cells 8 while improving the damage suppression effect.

[0041] Figure 3(a) is a partially enlarged schematic diagram showing an enlarged portion of the support substrate 4 in this embodiment. In Figure 3(a), similar to that shown in Figure 2, the side surface 4e of the support substrate 4 is composed of a first tapered surface 6 and a second tapered surface 7 with different taper angles. The first tapered surface (vertical surface) 6 with a high taper angle is located on the side away from the membrane 2, while the second tapered surface 7 with a low taper angle is formed on the side closer to the membrane 2. The vertical surface 6 and the second tapered surface 7 are formed continuously.

[0042] As shown in Figure 3(a), the height dimension from the second surface 4b to the first surface 4a, drawn perpendicularly from the second surface 4b to the first surface 4a (= height dimension of the support substrate 4) is defined as t1. The height dimension of the second tapered surface 7 is defined by the height dimension t2 of the vertical surface v, drawn perpendicularly from the inflection point p between the first tapered surface 6 and the second tapered surface 7 to the first surface 4a. Furthermore, the projection width of the second tapered surface from the vertical surface v is defined as w.

[0043] In this embodiment, it is preferable that t2 / t1 is 0.3 or more and less than 0.85. Also, it is preferable that w / t2 is 0.4 or more and 1.4 or less. This allows the strength of the support substrate 4 to be increased while also securing the contact area with the membrane 2, regardless of the height dimension t1 of the support substrate 4, thereby enhancing the damage suppression effect. Here, when the side surface 4e is composed of three or more tapered surfaces, the tapered surface to which t2 / t1 and w / t2 apply is the tapered surface closest to the membrane 2.

[0044] The side surface 4e of the support substrate 4 shown in Figure 3(b) is also formed by a first tapered surface (vertical surface) 6 and a second tapered surface 17, similar to Figure 3(a). However, unlike Figure 3(b), the second tapered surface 17 is formed in a concave shape rather than a straight line. By forming the second tapered surface 17 in a concave shape in this way, the second taper angle θ2 can be made smaller, that is, the second tapered surface 7 can be formed in a gentler shape.

[0045] In Figure 3(b), the second taper angle θ2 of the second tapered surface 17 can be determined by drawing a tangent line L from the edge 4c of the first surface 4a to the second tapered surface 17, and defining the second taper angle θ2 as the angle between the first surface 4a and the tangent line L. In this case, the second taper angle θ2 of the concave second tapered surface 17 is 50° or less, preferably 30° or less, and more preferably 10° or less.

[0046] In Figure 3, the first surface 4a was used as the reference surface for the height dimensions t1, t2, and protrusion width w. However, the height dimensions t1, t2, and protrusion width w can also be measured using the third surface 4f of the silicon substrate 30 (see Figure 2, etc.) as the reference surface. In particular, in the configuration of Figure 3(b), measuring the second taper angle θ2 can be done more clearly and easily by measuring it on the side surface of the silicon substrate 30, so it is preferable to measure it excluding the insulating layer 3. Since the thickness of the insulating layer 3 is extremely thin, measuring t2 / t1 and w / t2 using only the silicon substrate 30 excluding the insulating layer 3 does not change the above-mentioned numerical range.

[0047] Furthermore, in this embodiment, as shown in Figure 2, it is preferable that the distance D between the edge 4c of the first surface 4a on the membrane 2 side of the support substrate 4 and the nearest opening 5 of the membrane 2 from the edge 4c is 30 μm or more and 100 μm or less. This distance D is the distance in the horizontal direction (the plane direction parallel to the first surface 4a).

[0048] If the distance D is too small, the membrane 2 becomes more susceptible to damage, particularly due to the effects of cleaning during the manufacturing process, during the process of forming multiple openings 5. On the other hand, if the distance D is too large, the width dimensions of the columnar portion 16a and the outer peripheral frame 16b that constitute the support substrate 4 become smaller, resulting in a thinner shape and a loss of strength. Therefore, from the viewpoint of damage suppression effect and strength, the distance D was set to 30 μm or more and 100 μm or less. In this configuration, it is sufficient for the side surface 4e of the support substrate 4 to have an inclined tapered surface, and the taper angle is not limited, but as explained in Figures 1 and 2, it is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less.

[0049] According to the vapor deposition mask 1 of this embodiment described in detail above, the following inventions can exist independently. (1) The invention includes a tapered surface on the side surface 4e of the support substrate 4, where the taper angle θ between it and the surface parallel to the surface supporting the membrane 2 is less than 80° (see Figure 1).

[0050] (2) The side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7, the taper angles of which differ between the surface parallel to the surface supporting the membrane 2 and the surface parallel to the membrane 2, wherein the second tapered surface 7 has a smaller taper angle than the first tapered surface 6 and is formed on the side closer to the membrane 2, and the taper angle θ2 of the second tapered surface is less than 80° (see Figures 2 and 3).

[0051] (3) The side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7, each having a different taper angle with respect to the surface parallel to the surface supporting the membrane 2, the second tapered surface 7 being formed closer to the membrane 2 than the first tapered surface 6, and when the height dimension of the support substrate 4 is t1, the height dimension of the second tapered surface 7 is t2, and the protrusion width of the second tapered surface 7 is w, then t2 / t1 is 0.3 or more and less than 0.85, and w / t2 is 0.4 or more and 1.4 or less (see Figure 3).

[0052] (4) The invention is such that the side surface 4e of the support substrate 4 includes a tapered surface, and the distance D between the edge 4c of the surface of the support substrate 4 facing the membrane 2 and the opening 5 closest to the support substrate 4 is 30 μm or more and 100 μm or less (see Figures 2 and 14).

[0053] In this embodiment, multiple inventions (1) to (4) described above may be combined. For example, invention (2) and invention (3) may be combined, or invention (1) and invention (4) may be combined.

[0054] <Regarding the relationship between membrane 2 and support substrate 4> As shown in Figure 1, the sidewall surfaces 5a of the multiple openings 5 ​​formed in the membrane 2 are inclined, and the taper angle of these sidewall surfaces 5a is defined as θ3. As shown in Figure 1, the taper angle θ3 of the opening 5 is defined by the angle between the surface 2a of the opening 5 (the surface facing the substrate to be deposited) and the sidewall surface 5a. This taper angle θ3 is different from the taper angle θ of the side surface 4e of the support substrate 4. Note that when the side surface 4e is formed of multiple tapered surfaces, as shown in Figures 2 and 3, the taper angle of the support substrate 4 to be compared with the taper angle θ3 is compared with the taper angle θ2 of the tapered surface closest to the membrane 2 (in Figures 2 and 3, the second tapered surfaces 7 and 17).

[0055] Furthermore, it is preferable that the taper angle θ3 of the opening 5 of the membrane 2 is larger than the taper angles θ and θ2 of the side surface 4e of the support substrate 4.

[0056] In ultra-high resolution displays, the aperture pitch is narrow, which imposes constraints on reducing the taper angle θ3. While not limiting, the taper angle θ3 of the aperture 5 is in the range of 80° or more and less than 90°. On the other hand, the taper angles θ and θ2 of the side surface 4e of the support substrate 4 are preferably small to enhance the damage suppression effect, and it is desirable to control them so that taper angles θ and θ2 < taper angle θ3.

[0057] Furthermore, in this embodiment, the thickness dimensions of the membrane 2 and the support substrate 4 are different. Specifically, the membrane 2 is thinner than the support substrate 4. While there is no upper limit to the thickness of the membrane 2, it is 10 μm or less, and preferably 5 μm or less. A thinner thickness increases the deposition efficiency and makes it easier to achieve high resolution. While there is no lower limit to the thickness of the membrane 2, it is preferably 1 μm or more from the viewpoint of processability and durability.

[0058] On the other hand, the thickness of the support substrate 4 (corresponding to the height dimension t1 shown in Figure 3(a)) is, for example, about 100 μm to 1000 μm. The silicon substrate 30 accounts for the majority of the support substrate 4, with the silicon substrate 30 accounting for approximately 80% or more of the height dimension t1, preferably approximately 90% or more, more preferably approximately 95% or more, and even more preferably 99% or more.

[0059] Considering the pattern accuracy (rectangularity) and deposition efficiency of the deposited film 13 formed on the substrate 10 via the deposition mask 1, a thinner membrane 2 is preferable. On the other hand, a thicker support substrate 4 is preferable considering the mask strength and support stability to the membrane 2. Therefore, it is preferable to control the thickness of the support substrate 4 so that the thickness of the membrane 2 is greater than the thickness of the membrane 2.

[0060] As described above, a thinner membrane 2 is preferable, but the thinner it is, the more susceptible it is to damage. When the membrane 2 is 5 μm or less, the effects of damage become particularly significant, so it is preferable to minimize the taper angle θ of the side surface 4e of the support substrate 4, or to form the side surface 4e shown in Figure 3(a) with multiple tapered surfaces having different taper angles, or to form the tapered surface with a concave surface as shown in Figure 3(b), in order to enhance the damage suppression effect.

[0061] <Regarding the manufacturing method of the vapor deposition mask 1 in this embodiment> Figure 5 is a process diagram showing the first manufacturing method of the deposition mask 1 of this embodiment. Here, the deposition mask 1 in the manufacturing process shown in Figure 5 and Figure 6 (described later) shows only the vicinity of one aperture region 15, but in reality, multiple aperture regions 15 as shown in Figure 1 are formed simultaneously. In Figure 5(a), the SOI substrate 9 is prepared. The SOI substrate 9 consists of a laminated structure of a membrane 2, an insulating layer 3, and a silicon substrate 30 (the insulating layer 3 and the silicon substrate 30 together form a support substrate 4). The material and thickness of each layer are explained in Figure 1, so please refer to that.

[0062] In the case of the SOI substrate 9, there is no limit to the diameter, but in this embodiment, it can accommodate diameters up to approximately 500 mm.

[0063] In Figure 5(b), a mask layer 14 is patterned on the surface of the membrane 2. The mask layer 14 is preferably made of a resist and can be patterned by exposure and development. Multiple through holes 14a are formed in the mask layer 14. These through holes 14a form an opening pattern for creating openings 5 ​​in the membrane 2.

[0064] Next, in Figure 5(c), the membrane 2 exposed through the through-hole 14a of the mask layer 14 is dry-etched. For example, in this embodiment, the membrane 2 is deep-etched. It is preferable to use a so-called Bosch process, for example, in which etching of Si with SF6 and the formation of a polymer film with C4F8 are repeated to deeply etch the silicon, and sidewall protection and bottom etching are carried out alternately.

[0065] At this time, as shown in Figure 5(c), the composition and flow rate of the etching gas, the internal pressure of the etching chamber, the power of the high-frequency power supply, etc. are adjusted as appropriate to form an inverse tapered surface.

[0066] For example, the Bosch process was performed using a dry etching apparatus with alternating use of SF6 gas and C4F8 gas. Anisotropic dry etching using fluoride ions was performed by applying a bias to the substrate to be etched, using the same gas as in the mode of isotropic dry etching using fluorine radicals with SF6 gas. For example, the processing conditions were adjusted as follows: SF6 gas 0-500 sccm, C4F8 gas 0-300 sccm, Platen LF 0-1500 W, Coil RF 300-1500 W, and chamber pressure 1-10 Pa.

[0067] The Bosch process described above allows for the deep formation of multiple openings 5 ​​in the membrane 2, and at this time, the taper angle θ3 of the side wall surface 5a of the openings 5 ​​can be adjusted as appropriate. Next, in the step shown in Figure 5(d), the mask layer 14 is removed. This completes the SOI substrate 9 in which multiple openings 5 ​​are formed in the membrane 2.

[0068] Next, in the process shown in Figure 5(e), a protective layer 20 is formed on the surface of the membrane 2. This provides adequate protection for the entire surface of the membrane 2. The protective layer 20 is, but is not limited to, a resist film.

[0069] Next, in the process shown in Figure 5(f), a mask layer 21 is formed on the surface of the silicon substrate 30, which is the back surface of the SOI substrate 9. The mask layer 21 is a resist pattern, although this is not limited to it. As shown in Figure 5(f), the mask layer 21 is not formed in the opening region 15 that is opposite the opening 5 formed in the membrane 2 in the thickness direction, but is provided only in the surrounding region 16 (see also Figure 1). The mask layer 21 may also be formed together with the mask layer 14 during the process shown in Figure 5(b).

[0070] Then, in the step shown in Figure 5(g), the silicon substrate 30 not covered by the mask layer 21 is removed, for example, by dry etching, and in the step shown in Figure 5(h), the insulating layer 3 that appears after removing the silicon substrate 30 is removed by wet etching. At this time, the membrane 2 is not affected by wet etching and maintains its shape with multiple openings 5.

[0071] Then, in the process shown in Figure 5(i), the protective layer 20 and the mask layer 21 are removed. This completes the vapor deposition mask 1.

[0072] Figure 6 is a process diagram showing a second manufacturing method for the deposition mask 1 of this embodiment. In Figure 6(a), the SOI substrate 9 is prepared. The SOI substrate 9 consists of a laminated structure of a membrane 2, an insulating layer 3, and a silicon substrate 30. The material and thickness of each layer are explained in Figure 1, so please refer to that.

[0073] While the diameter of the SOI substrate 9 is not limited, in this embodiment it can accommodate diameters up to approximately 500 mm.

[0074] Next, in the process shown in Figure 6(b), a mask layer 21 is formed on the surface of the silicon substrate 30, which is the back surface of the SOI substrate 9. The mask layer 21 is a resist pattern, although this is not limited to it. Similar to Figure 6(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0075] Next, in the step shown in Figure 6(c), the silicon substrate 30 not covered by the mask layer 21 is removed, for example, by dry etching, and in the step shown in Figure 6(d), the insulating layer 3 that appears after removing the silicon substrate 30 is removed by wet etching.

[0076] Next, in the process shown in Figure 6(e), a mask layer 22 is formed on the back surface of the membrane 2. Although not limited to this, the mask layer 22 can be formed with a resist pattern. As shown in Figure 6(e), multiple openings 22a are patterned in the mask layer 22 by exposure and development.

[0077] Next, in the step shown in Figure 6(f), the membrane 2 exposed through the opening 22a is etched. This etching process is dry etching, and although not limited to this, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a noble gas.

[0078] For example, one or more fluorine compounds can be selected from CF4, SF6, NF3, BF3, PF5, and F2, and one or more noble gases can be selected from helium and argon.

[0079] For example, etching was performed using a dry etching apparatus with CF4 gas, O2 gas, and Ar gas. The processing conditions were adjusted as follows: CF4 gas at 10-100 sccm, O2 gas at 0-100 sccm, Ar gas at 0-200 sccm, IPC power at 200-1000 W, RIE power at 0-1000 W, and chamber pressure at 1-10 Pa.

[0080] In the step shown in Figure 6(f), an opening 5 can be formed in the membrane 2, which gradually decreases in width as it moves away from the mask layer 22 (towards the surface 2a of the membrane 2). This allows the side wall surface 5a of the opening 5 to be formed as a tapered surface. Then, in the step shown in Figure 6(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0081] The process shown in Figures 5(g) and 6(c) does not limit the method of forming the tapered surface of the side surface 4e of the silicon substrate 30 constituting the support substrate 4, but for example, etching was performed using a dry etching apparatus with CF4 gas, O2 gas, and Ar gas. One or more fluorine compounds can be selected from, for example, CF4, SF6, NF3, BF3, PF5, and F2, and one or more noble gases can be selected from helium and argon.

[0082] The processing conditions were set to 10-100 sccm of CF4 gas, 0-100 sccm of O2 gas, 0-200 sccm of Ar gas, IPC power of 200-1000 W, RIE power of 0-1000 W, and chamber pressure of 1-10 Pa, with various conditions adjusted accordingly. This allowed for the formation of a tapered surface on the side surface 4e of the silicon substrate 30.

[0083] Furthermore, as shown in Figures 3(a) and 3(b), if the side surface 4e of the support substrate 4 is formed by a combination of a first tapered surface (vertical surface) 6 and second tapered surfaces 7 and 17, this can be achieved, for example, by combining a vertical process with the dry etching process described above.

[0084] As a vertical process, for example, the Bosch process was performed using a dry etching apparatus with alternating use of SF6 gas and C4F8 gas. Anisotropic dry etching using fluoride ions was performed by applying a bias to the substrate to be etched using the same gas as in the mode of isotropic dry etching using fluorine radicals with SF6 gas. For example, the processing conditions were adjusted with SF6 gas at 0-500 sccm, C4F8 gas at 0-300 sccm, Platen LF at 0-1500 W, Coil RF at 300-1500 W, and chamber pressure at 1-10 Pa. Alternatively, the vertical process described above can be combined with the wet etching process.

[0085] For the wet etching process, we selected options such as a mixture of hydrofluoric acid, nitric acid, and acetic acid, electrolytic etching using hydrofluoric acid, and crystal anisotropy etching using potassium hydroxide and TMAH, and performed the treatment to obtain the desired angle. As an example, we used a mixture of hydrofluoric acid, nitric acid, and acetic acid, and the treatment temperature was set to 20°C to 40°C.

[0086] Alternatively, by combining the dry etching process described above with a wet etching process, or by changing the etching conditions during the dry etching process, the side surface 4e of the support substrate 4 can be formed with multiple tapered surfaces having different taper angles.

[0087] In Figures 5(h) and 6(d), during the process of removing the insulating layer 3 that constitutes the support substrate 4, the sides of the remaining insulating layer 3 tend to be formed following the taper angle of the silicon substrate 30. However, depending on the conditions, the sides of the insulating layer 3 may be formed as a nearly vertical surface or as an inverse tapered surface. Furthermore, because the insulating layer 3 is extremely thin compared to the silicon substrate 30, it can be difficult to determine the side surface of the insulating layer 3. Therefore, it is preferable to measure the taper angles θ and θ2 of the side surface 4e of the support substrate 4 using the angle of the side surface 4e of the silicon substrate 30, as shown in Figures 1 and 2.

[0088] According to the manufacturing method of this embodiment, the taper angles θ and θ2 of the side surface 4e of the support substrate 4 can be adjusted to less than 80°.

[0089] Furthermore, in this embodiment, when t1 is the height dimension drawn perpendicularly from the second surface 4b of the support substrate 4 toward the first surface 4a, t2 is the height dimension of the second tapered surface 7, and w is the protrusion width of the second tapered surface 7, it is preferable to control the etching conditions described above so that t2 / t1 is 0.3 or more and less than 0.85, and w / t2 is 0.4 or more and 1.4 or less.

[0090] Furthermore, in this embodiment, as shown in Figure 2, it is preferable to adjust the etching conditions described above so that the distance D between the edge 4c of the first surface 4a of the support substrate 4 and the opening 5 closest to the support substrate 4 is 30 μm or more and 100 μm or less.

[0091] <Method of manufacturing an electronic device according to this embodiment> In this embodiment, as shown in Figure 4, the deposition mask 1 is placed between the substrate 10 to be deposited and the deposition source 11. At this time, the surface 2a side of the membrane 2 of the deposition mask 1 is oriented toward the substrate 10, and the back surface 2b side of the membrane 2 is oriented toward the deposition source 11. Multiple openings 5 ​​are formed in the membrane 2, and the opening width is narrower on the substrate 10 side than on the deposition source 11 side.

[0092] The deposition mask 1 is placed in a holder (not shown) of the deposition apparatus, and at this time, the deposition mask 1 and the substrate 10 to be deposited can be fixed with an electrostatic chuck. The deposition mask 1 and the substrate 10 to be deposited are rotated with the center of the holder's axis as the axis of rotation.

[0093] The deposition material (deposited particles) 12 from the deposition source 11 reaches the surface 10a of the substrate 10 through the opening 5 of the deposition mask 1, and a deposition film 13 is formed.

[0094] In this embodiment, examples of electronic devices include OLED microdisplay panels, liquid crystal panels, and solar cells, and it is particularly suitable for manufacturing OLED microdisplay panels as organic electronic devices.

[0095] Although embodiments and modifications have been described above, other embodiments may include combinations of the above embodiments and modifications, either entirely or partially.

[0096] Furthermore, the present invention is not limited to the embodiments and modifications described above, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Moreover, if the technical idea can be realized in a different way by advances in the art or by other derived arts, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea.

[0097] An embodiment with a different layer configuration from the deposition mask 1 shown in Figure 1 will be described. The deposition mask 1 shown in Figure 1 is formed on an SOI substrate, but for example, as shown in Figure 7, a membrane 31 made of SiN or SiO2 may be deposited on the surface of a frame-shaped silicon substrate 30, and multiple openings 32 may be formed in the membrane 31 in the central region where the silicon substrate 30 has been removed. The membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easier stress control.

[0098] The silicon substrate 30 shown in Figure 7 constitutes the support substrate of this embodiment and preferably has at least one of the inventions (1) to (4) described above. This enhances the damage suppression effect.

[0099] In another embodiment shown in Figures 8 to 10, an SOI substrate 9 is used, similar to Figure 1. However, in Figure 8, a SiN layer 33 is formed on the back side of the SOI substrate 9 (the side facing the support substrate 4, the side facing the deposition source 11), in Figure 9, a SiN layer 33 is formed on the front side of the SOI substrate 9 (the side facing the semiconductor layer 2, the side facing the substrate to be deposited 10), and in Figure 10, a SiN layer 33 is formed on both the back and front sides of the SOI substrate 9. In the configuration where the SiN layer 33 is formed on the front side of the SOI substrate 9 (the side facing the semiconductor layer 2), an opening 5 is formed continuously with the semiconductor layer 2, as shown in Figures 9 and 10.

[0100] By providing the SiN layer 33, it is easier to control the stress on the deposition mask and suppress strain and other distortions. Furthermore, it is preferable that the SiN layer 33 formed on the surface side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited to these, the film thickness of the SiN layer 33 formed on the surface side of the SOI substrate 9 is approximately 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is approximately 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4, and also has numerous openings 5 ​​formed in the semiconductor layer 2, the SiN layer 33 formed on the surface side of the SOI substrate 9 is made thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control stress in a balanced manner between the surface and back sides.

[0101] Furthermore, at least one of the support substrate 4 and the membrane 2 may be a polycrystalline silicon structure. This makes the polycrystalline structure less susceptible to fracture in the cleavage direction than single-crystal silicon, which has cleavage planes, because the polycrystalline structure does not have distinct cleavage planes. Furthermore, while it is technically difficult to fabricate large substrates from single-crystal silicon material, by making the deposition mask 1 a polycrystalline silicon structure, silicon substrates larger than those made from single-crystal silicon substrates can be easily formed. In addition, by making the planar shape of the deposition mask 1 a polygonal shape (for example, a square shape), the chamfering efficiency can be increased compared to making the deposition mask 1 a round shape, and the number of surfaces can also be increased. It should be noted that a large silicon substrate is preferably 500 mm x 500 mm or larger. [Examples]

[0102] The effects of the present invention will be explained below with reference to examples and comparative examples of the present invention. However, the present invention is not limited in any way by the following examples. As shown in Figure 11, 30 cells were formed inside the deposition mask, and the extent of damage due to cleaning was checked.

[0103] The deposition mask used was an SOI substrate, consisting of a silicon substrate (675 μm), an insulating layer (0.5 μm), and a membrane (4 μm). The numbers in parentheses indicate the thickness. The membrane was a Si layer, and the insulating layer was an SiO2 layer. The silicon substrate and the insulating layer together constitute a support substrate that supports the membrane. The outer diameter of the SOI substrate was 200 mm.

[0104] The membrane had multiple openings in each cell, with opening widths of 5 to 10 μm. The side surface 4e of the support substrate 4 was formed with a single taper as shown in Figure 1, or a double taper as shown in Figures 3(a) and 3(b). The taper angle was measured using SEM observation. The instrument used for measurement was a Hitachi High-Technologies SU3500.

[0105] In the experiment, we repeatedly performed washing using Experimental Examples 1 to 10, which have different taper angles, and checked the damage status of 30 cells inside the mask.

[0106] Figure 12(a) is an SEM image of the support substrate in Experimental Example 5, and Figure 12(b) is a schematic diagram thereof. As shown in Figure 12(b), in Experimental Example 5, the substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was concave. The taper angle θ2 of the tapered surface was 10°. Figure 13(a) is an SEM image of the support substrate in Experimental Example 8, and Figure 13(b) is a schematic diagram thereof. As shown in Figure 13(b), in Experimental Example 8, the substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was approximately straight. The taper angle θ2 of the tapered surface was 60°. In this experiment, the taper angle θ2 of the side surface of the silicon substrate was measured as shown in Figure 2.

[0107] The cleaning was performed with the vapor deposition mask placed vertically (with the direction perpendicular to the mask thickness oriented vertically). One cycle consisted of immersion in sulfuric acid, immersion in pure water, and mask agitation (three up-and-down movements), and this was repeated five times.

[0108] "Damage" was defined as any condition that rendered the vapor deposition mask incapable of functioning as such, such as detachment or cracking. Damage was evaluated by visual inspection of the external appearance and by checking for the presence of cracks through visual inspection or microscopic observation. The experimental results for Experimental Examples 1-10 are shown in Table 1 below.

[0109] [Table 1]

[0110] As shown in Table 1, Experimental Examples 1 to 3 had a single-stage inclined shape as shown in Figure 1. In Experimental Example 4, the entire side surface of the support substrate was a vertical surface. Experimental Examples 5 to 10 had a two-stage inclined shape as shown in Figures 3(a) and 3(b). All of these were combinations of a vertical surface and a tapered surface.

[0111] The "Judgment" shown in Table 1 is as follows: ◎ if the damage rate is 2% or less, ○ if it is between 2% and 5%, △ if it is between 5% and 10%, and × if it is above 10%.

[0112] As shown in Table 1, in the experimental examples with a taper angle of 80° to 90°, the failure rate was very high, resulting in a "fail" rating. Therefore, based on these experimental results, the preferred taper angle was set to less than 80°, and the more preferred taper angle was set to 70° or less.

[0113] Furthermore, by forming it with a two-stage incline, the rate of failure was effectively reduced. In particular, by providing a vertical surface in part, it was possible to make the taper angle θ2 smaller, as shown in Figure 12, and by making the taper angle very gentle, between 10° and 30°, the rate of failure was reduced to approximately 0%.

[0114] Next, as shown in Table 2, the distance D, opening width W1, and opening dimension W2 were adjusted as appropriate, and the rate of damage was measured.

[0115] For the experimental example with a 30° taper angle in Table 2, a combination of dry etching and wet etching processes was used to create a two-stage shape with a second taper angle θ2 of 30° as shown in Figure 2. For the experimental example with a 60° taper angle in Table 2, only the dry etching process was used to create the inclined shape shown in Figure 1.

[0116] Distance D refers to the distance between the edge 4c of the first surface 4a on the membrane 2 side of the support substrate 4 and the nearest opening 5 of the membrane 2 from the edge 4c, as shown in Figure 14. The opening width W1 refers to the width dimension of the opening 5 along the surface 2a of the membrane 2, as shown in Figure 14(b). The opening-to-opening dimension W2 refers to the distance between openings on the surface 2a of the membrane 2.

[0117] The cleaning method was the same as in the experiment shown in Table 1. For the cleaning evaluation, cracks and damage occurring between openings near the support substrate were observed under a microscope at 40 locations after cleaning, and the damage occurrence rate was calculated. The experimental results are shown in Table 2 below.

[0118] [Table 2]

[0119] As shown in Table 2, in Experimental Examples 11 to 14, the distance D was 10 μm, and the failure rate was higher than 10%, resulting in a "fail" judgment. In other words, when the distance D is too close, the material is more susceptible to damage and cracking due to factors such as cleaning during the manufacturing process.

[0120] Therefore, in this embodiment, the distance D was set to 30 μm or more and 100 μm or less. It was also found that an aperture width of about 5 to 10 μm and an aperture spacing of about 3 to 10 μm were preferable.

[0121] This application is based on Japanese Patent Application No. 2023-195185, filed on November 16, 2023. All of its contents are included here.

Claims

1. A deposition mask, which is placed between a substrate to be deposited and a deposition source, and through an opening, deposits a deposition material from the deposition source onto the surface of the substrate to be deposited, A membrane having an opening region with a plurality of the aforementioned openings and a peripheral region located around the opening region, The system comprises a support substrate that supports the membrane in the surrounding region, The side surface of the support substrate includes a tapered surface such that the taper angle between it and the surface parallel to the surface supporting the membrane is less than 80°. A vapor deposition mask characterized by the following features.

2. The vapor deposition mask according to claim 1, characterized in that the taper angle is 70° or less.

3. The vapor deposition mask according to claim 1, characterized in that the taper angle is 60° or less.

4. The vapor deposition mask according to claim 1, characterized in that the tapered surface is formed as a concave surface.

5. A deposition mask, which is placed between a substrate to be deposited and a deposition source, and through an opening, deposits a deposition material from the deposition source onto the surface of the substrate to be deposited, A membrane having an opening region with a plurality of the aforementioned openings and a peripheral region located around the opening region, The system comprises a support substrate that supports the membrane in the surrounding region, The side surface of the support substrate has at least a first tapered surface and a second tapered surface, each having a different taper angle between them and the surface parallel to the surface supporting the membrane. The second tapered surface has a smaller taper angle than the first tapered surface and is formed on the side closer to the membrane. The taper angle of the second tapered surface is less than 80°. A vapor deposition mask characterized by the following features.

6. The vapor deposition mask according to claim 5, characterized in that the first tapered surface is substantially vertical.

7. The vapor deposition mask according to claim 5, characterized in that the taper angle of the second tapered surface is 70° or less.

8. A deposition mask, which is placed between a substrate to be deposited and a deposition source, and through an opening, deposits a deposition material from the deposition source onto the surface of the substrate to be deposited, A membrane having an opening region with a plurality of the aforementioned openings and a peripheral region located around the opening region, The system comprises a support substrate that supports the membrane in the surrounding region, The side surface of the support substrate has at least a first tapered surface and a second tapered surface, each having a different taper angle between them and the surface parallel to the surface supporting the membrane. The second tapered surface is formed closer to the membrane than the first tapered surface. A vapor deposition mask characterized in that, when the height dimension of the support substrate is t1, the height dimension of the second tapered surface is t2, and the protrusion width of the second tapered surface is w, t2 / t1 is 0.3 or more and less than 0.85, and w / t2 is 0.4 or more and 1.4 or less.

9. A deposition mask, which is placed between a substrate to be deposited and a deposition source, and through an opening, deposits a deposition material from the deposition source onto the surface of the substrate to be deposited, A membrane having an opening region with a plurality of the aforementioned openings and a peripheral region located around the opening region, The system comprises a support substrate that supports the membrane in the surrounding region, The side surface of the support substrate has an inclined portion, A vapor deposition mask characterized in that the distance between the edge of the support substrate facing the membrane and the opening closest to the support substrate is 30 μm or more and 100 μm or less.

10. The vapor deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the side wall surface of the opening of the membrane has a tapered surface that narrows in width from the vapor deposition source side to the substrate to be vapor-deposited, and the taper angle between the membrane surface on the substrate to be vapor-deposited and the side wall surface is greater than the taper angle of the support substrate.

11. The vapor deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the support substrate is thicker than the membrane.

12. The deposition mask is configured such that a membrane having the opening is supported on a silicon substrate which serves as the support substrate, or the support substrate is configured to have an insulating layer and a silicon substrate, and the insulating layer is provided between the silicon substrate and the membrane on an SOI substrate. A vapor deposition mask according to claim 1, or claim 5, or claim 8, or claim 9.

13. The deposition mask according to claim 12, characterized in that the membrane is made of SiN.

14. The deposition mask is composed of an SOI substrate, and a SiN layer is formed on the surface side where the opening is formed, or on the back side, or on both the surface and back sides. A vapor deposition mask according to claim 1, or claim 5, or claim 8, or claim 9.

15. The deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the thickness of the membrane is 5 μm or less.

16. The vapor deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that at least one of the membrane or the support substrate is a polycrystalline silicon structure.

17. The deposition mask according to claim 1, claim 5, claim 8, or claim 9 is placed between the substrate to be deposited and the deposition source, such that the membrane faces the substrate to be deposited. The deposition material is deposited onto the surface of the substrate to be deposited through the opening. A method for manufacturing an electronic device characterized by the following:

Images