Power converter

Abstract

To reduce the distortion rate of the input current. [Solution] The power conversion device includes a control unit. The control unit includes a feedforward unit 60 that derives the duty cycles of the upper arm switching element and the lower arm switching element by feedforward control of the input voltage and output voltage command value, a comparator 75 that outputs a PWM signal based on the duty cycle derived by the feedforward unit 60, a determination unit 58 that outputs a high-level or low-level output signal depending on whether the input voltage is positive or negative, and a logic circuit 80 that outputs control signals to control the upper arm switching element and the lower arm switching element based on the PWM signal and the output signal.

Description

Technical Field

[0001] This disclosure relates to a power conversion device.

Background Art

[0002] The power conversion device disclosed in Patent Document 1 includes a transformer, a first capacitor, a primary circuit, a rectifying and smoothing circuit, and a control unit. The transformer includes a primary winding and a secondary winding. The primary circuit includes an upper-arm switching element, a lower-arm switching element, and a buffer circuit. The primary circuit is connected to the primary winding via the first capacitor. The buffer circuit includes a buffer switching element. The rectifying and smoothing circuit is connected to the secondary winding.

[0003] In a power conversion device, feedback control is performed to cause the output value of the power conversion device to follow a command value. When hysteresis control is used as the control method of the feedback control, the control unit generates an input current command value from the difference between the output power command value and the output power measurement value, and performs control so that the input current measurement value changes between an upper limit and a lower limit determined according to the input current command value.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In hysteresis control, if the input current measurement reaches an upper or lower limit after switching a switching element, the switching element is switched again to bring the input current measurement within the upper and lower limits. For example, when increasing the input current by switching the lower arm switching element while keeping the upper arm switching element ON, if the input current measurement reaches the upper limit due to the lower arm switching element being ON, the lower arm switching element is turned OFF. When the lower arm switching element is turned OFF, the input current decreases, and the difference between the input current measurement and the upper limit increases.

[0006] Here, to suppress magnetic saturation of the transformer, the switching frequency and maximum duty cycle are kept constant. Because the switching frequency is constant, when the lower arm switching element turns ON and immediately after the input current measurement reaches the upper limit, the lower arm switching element turns OFF. As a result, most of the switching cycle is spent in the OFF period, and the input current continues to decrease for a relatively long time. Consequently, the difference between the input current measurement and the upper limit becomes large, and the amplitude of the input current in the opposite direction increases. The same is true when the input current measurement reaches the lower limit. In other words, the current tracking ability deteriorates, and the amplitude deviating from the target value becomes large, which may increase the distortion rate. Also, if a control delay occurs, it may exceed the upper and lower limits, which may increase the distortion rate. [Means for solving the problem]

[0007] A power converter that solves the above problems is a power converter that converts an input voltage input from an AC power source into a DC voltage, comprising: a transformer having a primary winding and a secondary winding; a pair of input terminals to which the AC power source is connected; a primary side circuit having a first inductor, an upper arm switching element, a lower arm switching element, an upper arm rectifier element, and a lower arm rectifier element; a rectifier and smoothing circuit having a second inductor, a secondary side rectifier element, an output capacitor, a first output terminal and a second output terminal; and a first capacitor having one end connected to the primary side circuit and the other end connected to the primary winding, wherein the series connection of the upper arm switching element and the lower arm switching element and the series connection of the upper arm rectifier element and the lower arm rectifier element constitute a bridge circuit, and the connection point of the upper arm switching element and the lower arm switching element and the connection point of the upper arm rectifier element and the lower arm rectifier element are the pair The input terminal of the first inductor is connected to the primary side circuit, and the primary side circuit includes a buffer circuit having a buffer switching element and a buffer capacitor. The rectifier and smoothing circuit is connected to the secondary winding and includes a control unit that controls the upper arm switching element, the lower arm switching element, and the buffer switching element. The control unit includes a feedforward unit that derives the duty cycles of the upper arm switching element and the lower arm switching element by feedforward control of the input voltage and output voltage command values, a comparator that outputs a PWM signal based on the duty cycles derived by the feedforward unit, a determination unit that outputs a high-level or low-level output signal depending on whether the input voltage is positive or negative, and a logic circuit that outputs a control signal to control the upper arm switching element and the lower arm switching element based on the PWM signal and the output signal.

[0008] The upper arm switching element and the lower arm switching element are controlled based on the duty cycle derived in the feedforward section. By controlling the upper arm switching element and the lower arm switching element based on the input voltage and output voltage command values, the distortion rate of the input current can be reduced.

[0009] The power converter described above may include an output voltage control unit that outputs a value obtained by multiplying the difference between the output voltage command value and the output voltage by a feedback gain, and an input current control unit that adds to the duty cycle a value obtained by multiplying the difference between the input current command value, derived from the output of the output voltage control unit and the phase of the input voltage, and the input current by a feedback gain. [Effects of the Invention]

[0010] According to the present invention, the distortion rate of the input current can be reduced. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a circuit diagram of a power converter. [Figure 2] Figure 2 is a block diagram of the control unit. [Figure 3] Figure 3 shows the switching period. [Figure 4] Figure 4 shows the input current and input voltage of the comparative example. [Figure 5] Figure 5 shows the input current and input voltage of the embodiment. [Figure 6] Figure 6 shows the voltage across the upper arm switching element in the comparative example. [Figure 7] Figure 7 shows the voltage across the upper arm switching element of the embodiment. [Figure 8] Figure 8 is a circuit diagram of a modified power converter. [Figure 9] Figure 9 is a circuit diagram of a modified power converter. [Figure 10] Figure 10 is a circuit diagram of a modified power converter. [Figure 11] Figure 11 is a circuit diagram of a modified power converter. [Figure 12] Figure 12 is a circuit diagram of a modified power converter. [Modes for carrying out the invention]

[0012] One embodiment of a power conversion device will be described. As shown in Figure 1, the power converter 1 comprises a primary circuit 10, a first capacitor 17, a transformer 18, a second capacitor 19, a rectifier and smoothing circuit 20, and a control unit 50. The power converter 1 is a device that converts the AC voltage supplied from the AC power source V1 into a DC voltage and supplies it to the load connected to the power converter 1.

[0013] The primary circuit 10 includes a first inductor 11, an upper arm diode 12, a lower arm diode 13, an upper arm switching element Q1, a lower arm switching element Q2, a first connecting line CL1, a second connecting line CL2, a first intermediate line ML1, a second intermediate line ML2, a first input terminal t21, a second input terminal t22, and a buffer circuit 40. The upper arm diode 12 is an example of an "upper arm rectifier element". The lower arm diode 13 is an example of a "lower arm rectifier element".

[0014] The AC power supply V1 and the primary circuit 10 are electrically connected. The AC power supply V1 has a first terminal t11 and a second terminal t12. The first terminal t11 of the AC power supply V1 and the first input terminal t21 of the primary circuit 10 are connected by a first input line L1. The second terminal t12 of the AC power supply V1 and the second input terminal t22 of the primary circuit 10 are connected by a second input line L2. As a result, the AC voltage is applied to the input terminals t21 and t22. in This is the input voltage V when the potential at the first terminal t11 is higher than that at the second terminal t12. in Let this be positive. Input voltage V when the potential at the first terminal t11 is lower than that at the second terminal t12. in Let it be negative.

[0015] The upper arm diode 12 and the lower arm diode 13 are connected in series by a second connecting wire CL2. The second connecting wire CL2 connects the anode of the upper arm diode 12 to the cathode of the lower arm diode 13.

[0016] The upper arm switching element Q1 comprises a first end t31 and a second end t32. The lower arm switching element Q2 comprises a first end t41 and a second end t42. The first connecting line CL1 connects the second end t32 of the upper arm switching element Q1 and the first end t41 of the lower arm switching element Q2. The upper arm switching element Q1 and the lower arm switching element Q2 are, for example, power switching elements, and in this embodiment they are n-type power MOSFETs. Both switching elements Q1 and Q2 have body diodes. The upper arm switching element Q1 and the lower arm switching element Q2 are not limited to MOSFETs, but can be any IGBT with antiparallel diodes, etc.

[0017] The first intermediate line ML1 connects the first connecting line CL1 to the first input terminal t21. The first inductor 11 is provided on the first intermediate line ML1. The second intermediate line ML2 connects the second connecting line CL2 to the second input terminal t22. Therefore, the connection point between the upper arm switching element Q1 and the lower arm switching element Q2, and the connection point between the upper arm diode 12 and the lower arm diode 13 are connected via the pair of input terminals t21 and t22 and the first inductor 11.

[0018] The cathode of the upper arm diode 12 is connected to the first terminal t31 of the upper arm switching element Q1. The anode of the lower arm diode 13 is connected to the second terminal t42 of the lower arm switching element Q2. Therefore, the series connection of the upper arm switching element Q1 and the lower arm switching element Q2, and the series connection of the upper arm diode 12 and the lower arm diode 13, constitute a bridge circuit 14.

[0019] The transformer 18 comprises a primary winding W1 and a secondary winding W2. The transformer 18 is an isolation transformer. The starting end of the primary winding W1 is connected to the cathode of the upper arm diode 12 and to the first end t31 of the upper arm switching element Q1 via the first capacitor 17. Specifically, the first capacitor 17 comprises a first end t51 and a second end t52. The starting end of the primary winding W1 is connected to the second end t52 of the first capacitor 17. The first end t51 of the first capacitor 17 is connected to the cathode of the upper arm diode 12 and to the first end t31 of the upper arm switching element Q1. Thus, the first end t51 of the first capacitor 17 is connected to the primary side circuit 10, and the second end t52 of the first capacitor 17 is connected to the primary winding W1. The first end t51 is an example of "one end of the first capacitor". The second end t52 is an example of "the other end of the first capacitor". The starting end of the primary winding W1 is the side marked with a black circle in Figure 1.

[0020] The termination of the primary winding W1 is connected to the anode of the lower arm diode 13 and to the second end t42 of the lower arm switching element Q2. The termination of the primary winding W1 is the side without a black circle in Figure 1.

[0021] The rectifier-smoothing circuit 20 includes a second inductor 21, a secondary diode 22, an output capacitor 23, a first output line OL1, a second output line OL2, a first output terminal t91, and a second output terminal t92. The second inductor 21 has a first terminal t71 and a second terminal t72. The output capacitor 23 has a first terminal t81 and a second terminal t82. The secondary diode 22 is an example of a "secondary rectifier element".

[0022] The starting end of the secondary winding W2 is connected to the first end t71 of the second inductor 21 and the anode of the secondary diode 22 via the second capacitor 19. Specifically, the second capacitor 19 has a first end t61 and a second end t62. The starting end of the secondary winding W2 is connected to the first end t61 of the second capacitor 19. The second end t62 of the second capacitor 19 is connected to the first end t71 of the second inductor 21 and the anode of the secondary diode 22. The starting end of the secondary winding W2 is the side marked with a black circle in Figure 1.

[0023] The termination of the secondary winding W2 is connected to the second end t72 of the second inductor 21. Therefore, the rectifier-smoothing circuit 20 is connected to the secondary winding W2 of the transformer 18 via the second capacitor 19. The termination of the secondary winding W2 is the side without a black circle in Figure 1.

[0024] The output capacitor 23 is connected to both the first output line OL1 and the second output line OL2. Specifically, the first terminal t81 of the output capacitor 23 is connected to the first output line OL1, and the second terminal t82 of the output capacitor 23 is connected to the second output line OL2.

[0025] The second inductor 21 is connected to both the secondary diode 22 and the second output line OL2. Specifically, the first end t71 of the second inductor 21 is connected to the anode of the secondary diode 22. The second end t72 of the second inductor 21 is connected to the second output line OL2.

[0026] The secondary diode 22 is located between the second inductor 21 and the output capacitor 23. As described above, the anode of the secondary diode 22 is connected to the first terminal t71 of the second inductor 21. The cathode of the secondary diode 22 is connected to the first terminal t81 of the output capacitor 23.

[0027] The buffer circuit 40 comprises a buffer switching element Q3, a buffer capacitor Cc, and a third connecting line CL3. The buffer switching element Q3 and the buffer capacitor Cc are connected in series by the third connecting line CL3. The buffer switching element Q3 comprises terminal tq1 and terminal tq2. The buffer capacitor Cc comprises terminal tc1 and terminal tc2. Terminal tq1 of the buffer switching element Q3 and terminal tc1 of the buffer capacitor Cc are connected by the third connecting line CL3. The buffer switching element Q3 has a body diode. The anode of the body diode of the buffer switching element Q3 is connected to terminal tq2. The cathode of the body diode of the buffer switching element Q3 is connected to terminal tq1.

[0028] The buffer circuit 40 is connected in parallel with the bridge circuit 14. Specifically, terminal tq2 of the buffer switching element Q3 is connected to the cathode of the upper arm diode 12 and the connection point of the first terminal t31 of the upper arm switching element Q1. Terminal tc2 of the buffer capacitor Cc is connected to the anode of the lower arm diode 13 and the connection point of the second terminal t42 of the lower arm switching element Q2.

[0029] The power converter 1 includes a current sensor C1 that detects the current flowing through the first inductor 11. The current flowing through the first inductor 11 is the input current i L1 That is the case. Power converter 1 receives an input voltage V in Voltage sensor C2 detects the voltage, and output voltage V out The system includes a voltage sensor C3 that detects current. The current sensor C1, voltage sensor C2, and voltage sensor C3 output their detection results to the control unit 50.

[0030] The control unit 50 switches the switching elements Q1 to Q3 ON and OFF based on signals from the current sensor C1, voltage sensor C2, and voltage sensor C3. The power converter 1 converts the AC voltage supplied from the AC power supply V1 into a DC voltage by controlling the switching elements Q1 to Q3, and outputs the DC voltage from both output terminals t91 and t92.

[0031] The control unit 50 controls the switching of each switching element Q1 to Q3 to improve the power factor of the input power. Alternatively, the control unit 50 may control the switching of each switching element Q1 to Q3 so that a predetermined voltage is output from the output terminals t91 and t92.

[0032] The control unit 50 comprises a processor and a memory unit. The processor is, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). The memory unit includes RAM (Random Access Memory) and ROM (Read Only Memory). The memory unit stores program code or instructions configured to cause the processor to execute processing. The memory unit, i.e., the computer-readable medium, includes any available medium that can be accessed by a general-purpose or dedicated computer. The control unit 50 may be composed of hardware circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control unit 50, which is a processing circuit, may include one or more processors that operate according to a computer program, one or more hardware circuits such as an ASIC or FPGA, or a combination thereof.

[0033] As shown in FIG. 2, the control unit 50 includes a buffer command generation unit 51, a phase derivation unit 56, a determination unit 58, a feed-forward unit 60, an output voltage control unit 64, a multiplier 69, an input current control unit 70, a comparator 75, and a logic circuit 80. These may be functional units that function by the control unit 50 executing predetermined processes.

[0034] <Buffer Command Generation Unit> The buffer command generation unit 51 includes a buffer duty derivation unit 52, a comparator 53, and a NOT circuit 54. The buffer duty derivation unit 52 derives a buffer duty d3, which is a command for driving the buffer switching element Q3, from the following equation (1).

[0035]

Equation

[0036] n is the turns ratio of the transformer 18. L p is the leakage inductance of the primary winding W1 of the transformer 18. I out is the output current of the power conversion device 1. T is the switching period. V C1 is the voltage across the first capacitor 17. V Cc is the voltage across the buffer capacitor Cc.

[0037] Equation (1) can be obtained from the ET product balance of the transformer 18 and the inductors 11 and 21 when considering the ON and OFF combinations of the upper-arm switching element Q1, the lower-arm switching element Q2, and the buffer switching element Q3.

[0038] The amount of current Q supplied to the load through the secondary-side diode 22 during the switching period T out can be expressed by the following equation (2).

[0039]

Equation

[0040] L m V is the excitation inductance on the primary side of transformer 18, including leakage inductance. C2 This is the voltage across the second capacitor 19. inc is the ON time of the buffer switching element Q3 during the switching period T. As shown in Figure 3, the buffer duty cycle d3 is the ratio of the ON time of the buffer switching element Q3 during the switching period T, so t inc This is the same as d3T. x is expressed by equation (3) below.

[0041]

number

[0042] The average value I of the current flowing to the load through the secondary diode 22 ave Q out It can be expressed as / T. Substituting equations (2) and (3), the mean value I ave This can be expressed by equation (4) below.

[0043]

number

[0044] I ave Since this is the current flowing on the output side, DC is ideal. ave and I out The buffer duty cycle d3, which is calculated to match the given values, can be expressed by equation (5) below. By further simplifying equation (5), we can obtain equation (1).

[0045]

number

[0046] The comparator 53 receives the buffer duty cycle d3 and the carrier wave as inputs. The comparator 53 generates a PWM signal by comparing the buffer duty cycle d3 and the carrier wave. The PWM signal is a signal that switches between high and low levels. The PWM signal is input to the NOT circuit 54. The NOT circuit 54 inverts the high and low levels and outputs them. The NOT circuit 54 controls the switching of the buffer switching element Q3 by outputting a control signal generated from the input PWM signal to the buffer switching element Q3.

[0047] <Phase derivation section> The phase derivation unit 56 receives the input voltage V in The input is V. The phase derivation unit 56 takes, for example, the input voltage V. in We derive a full-wave rectified waveform normalized to 1. That is, the input voltage V in We derive |sinθ| for the phase θ.

[0048] <Judgment part> The determination unit 58 determines the input voltage V in It outputs a High / Low level output signal depending on the positive or negative sign of the input voltage V. in The determination unit 58 determines whether sinθ is greater than or less than 0 with respect to the phase θ of the input voltage V in From this, we determine whether sinθ is greater than 0 or less than 0. If sinθ is greater than 0, the input voltage V in It is positive. When sinθ is less than 0, the input voltage V in The result is negative. The determination unit 58 determines the input voltage V in The determination unit 58 outputs a high-level or low-level output signal depending on whether the input voltage V is positive or negative. in If the value is positive, a high-level output signal is output. The determination unit 58 determines the input voltage V in If the value is negative, a low-level output signal is output.

[0049] <Feedforward Section> The feedforward unit 60 derives a duty cycle d1, which is a command for driving the upper arm switching element Q1 and the lower arm switching element Q2 by feedforward control. The feedforward unit 60 derives an output voltage command value V* out and input voltage V in Based on this, we derive duty cycle d1.

[0050] The feedforward section 60 includes a voltage derivation section 61 and a duty cycle derivation section 62. The voltage derivation section 61 receives the input voltage V from the phase derivation section 56. in A full-wave rectified waveform normalized to 1 is input. The voltage derivation unit 61 takes the input voltage V in The maximum value of V inmax Multiply by |V in The | is derived. Note that the voltage derivation unit 61 is the input voltage V in Directly from |V in You can also derive |.

[0051] The duty cycle derivation unit 62 derives the duty cycle d1 from the following equation (6).

[0052]

number

[0053] <Output Voltage Control Unit> The output voltage control unit 64 includes a band stop filter 65, a subtractor 66, and a feedback unit 67. The band stop filter 65 controls the output voltage V out The following is input. The bandstop filter 65 reduces the frequency components in a specific band, thereby reducing the output voltage V out Reduces the noise contained in the output voltage command value V*. The subtractor 66 receives the output voltage command value V* out And the output voltage V after noise reduction by the bandstop filter 65. out The following is input. Subtractor 66 outputs V out and output voltage command value V* outThe difference between this and the output is output as a voltage deviation. The feedback unit 67 multiplies the voltage deviation by a feedback gain and outputs it. The feedback gain is, for example, a proportional gain and an integral gain. The feedback gain only needs to include at least one of the proportional gain, integral gain, and differential gain.

[0054] The multiplier 69 receives the output of the feedback unit 67 and the output of the phase derivation unit 56 as input. The multiplier 69 multiplies the output of the feedback unit 67 and the output of the phase derivation unit 56 and calculates the input current command value i* L1 Output as follows.

[0055] <Input Current Control Unit> The input current control unit 70 includes a low-pass filter 71, a subtractor 72, a feedback unit 73, and an adder 74. The low-pass filter 71 receives the input current i L1 The absolute value of |i L1 | is input. The subtractor 72 receives the input current command value i* L1 And |i after noise reduction by the low-pass filter 71 L1 | is input. Subtractor 72 is |i L1 | and input current command value i* L1 The difference between this and the current is output as the current deviation. The feedback unit 73 multiplies the current deviation by the feedback gain and outputs the result. The feedback gain is, for example, a proportional gain and an integral gain. The feedback gain only needs to include at least one of the proportional gain, integral gain, and differential gain. The adder 74 receives the duty cycle d1 and the output of the feedback unit 73 as inputs. The adder 74 outputs a duty cycle d2, which is the sum of the duty cycle d1 and the output of the feedback unit 73. The duty cycle d2 is the duty cycle obtained by correcting the duty cycle d1 with the output of the feedback unit 73.

[0056] The comparator 75 receives the duty cycle d2 and the carrier wave as inputs. The comparator 75 generates a PWM signal by comparing the duty cycle d2 and the carrier wave. The PWM signal is input to the logic circuit 80.

[0057] <Logic Circuits> The logic circuit 80 outputs control signals that control the upper arm switching element Q1 and the lower arm switching element Q2 based on the PWM signal and the output signal. The logic circuit 80 includes a NAND gate 81, a NOT gate 82, four AND gates 83 to 86, and two OR gates 87 and 88.

[0058] The NAND gate 81 receives the output of the NOT gate 54 and the output of the comparator 75 as inputs. The NAND gate 81 outputs a low-level signal when both the output of the NOT gate 54 and the output of the comparator 75 are at a high level. The NAND gate 81 outputs a high-level signal when at least one of the outputs of the NOT gate 54 and the comparator 75 is at a low level.

[0059] The output of the comparator 75 and the output of the NOT gate 82 are input to the first AND gate 83. The first AND gate 83 outputs a high-level signal when both the output of the comparator 75 and the output of the NOT gate 82 are at a high level. The first AND gate 83 outputs a low-level signal when at least one of the outputs of the comparator 75 and the NOT gate 82 is at a low level.

[0060] The output of the NAND circuit 81 and the output of the determination unit 58 are input to the second AND circuit 84. The second AND circuit 84 outputs a high-level signal when both the output of the NAND circuit 81 and the output of the determination unit 58 are at a high level. The second AND circuit 84 outputs a low-level signal when at least one of the outputs of the NAND circuit 81 and the determination unit 58 is at a low level.

[0061] The output of the comparator 75 and the output of the determination unit 58 are input to the third AND circuit 85. The third AND circuit 85 outputs a high-level signal when both the output of the comparator 75 and the output of the determination unit 58 are at a high level. The third AND circuit 85 outputs a low-level signal when at least one of the outputs of the comparator 75 and the determination unit 58 is at a low level.

[0062] The output of the NAND gate 81 and the output of the NOT gate 82 are input to the fourth AND gate 86. The fourth AND gate 86 outputs a high-level signal when both the output of the NAND gate 81 and the output of the NOT gate 82 are at a high level. The fourth AND gate 86 outputs a low-level signal when at least one of the outputs of the NAND gate 81 and the NOT gate 82 is at a low level.

[0063] The first OR gate 87 receives the output of the first AND gate 83 and the output of the second AND gate 84 as inputs. If at least one of the outputs of the first AND gate 83 and the second AND gate 84 is at a high level, the first OR gate 87 outputs a high-level control signal to the upper arm switching element Q1. If both the outputs of the first AND gate 83 and the second AND gate 84 are at a low level, the first OR gate 87 outputs a low-level control signal to the upper arm switching element Q1. This controls the ON and OFF states of the upper arm switching element Q1.

[0064] The output of the third AND circuit 85 and the output of the fourth AND circuit 86 are input to the second OR gate 88. If at least one of the outputs of the third AND circuit 85 and the fourth AND circuit 86 is at a high level, the second OR gate 88 outputs a high-level control signal to the lower arm switching element Q2. If both the outputs of the third AND circuit 85 and the fourth AND circuit 86 are at a low level, the second OR gate 88 outputs a low-level control signal to the lower arm switching element Q2. This controls the ON and OFF state of the lower arm switching element Q2.

[0065] As described above, the switching pattern, which is a combination of ON and OFF states of switching elements Q1 to Q3, is switched by the control signal output from the control unit 50. As a result, the output voltage V is switched from the power converter 1. out The following will be output.

[0066] Input voltage V inIf the condition is positive, the switching patterns of switching elements Q1 to Q3 include the first to third patterns. The first pattern is a switching pattern in which the upper arm switching element Q1 and the lower arm switching element Q2 are turned ON, and the buffer switching element Q3 is turned OFF.

[0067] The second pattern is a switching pattern in which the upper arm switching element Q1 is OFF, the lower arm switching element Q2 is ON, and the buffer switching element Q3 is ON. The third pattern is a switching pattern in which the upper arm switching element Q1 is ON, the lower arm switching element Q2 is OFF, and the buffer switching element Q3 is ON.

[0068] Input voltage V in If the value is negative, the switching patterns of switching elements Q1 to Q3 include patterns 4 to 6. The fourth pattern is a switching pattern in which the upper arm switching element Q1 and the lower arm switching element Q2 are ON, and the buffer switching element Q3 is OFF. In other words, the fourth pattern is identical to the first pattern.

[0069] The fifth pattern is a switching pattern in which the upper arm switching element Q1 is ON, the lower arm switching element Q2 is OFF, and the buffer switching element Q3 is ON. The sixth pattern is a switching pattern in which the upper arm switching element Q1 is OFF, the lower arm switching element Q2 is ON, and the buffer switching element Q3 is ON.

[0070] [Operation of this embodiment] Figure 4 shows the input voltage V when hysteresis control is performed. in and input current i L1 This shows that in hysteresis control, the input current i L1 The control is performed so that the input current i changes between predetermined upper and lower limits. L1 The input voltage is Vin Because vibrations of very high harmonics are superimposed compared to the frequency, these vibration waveforms overlap and are shown as a black-filled waveform in the diagram. The upper and lower widths of the black-filled area represent the input current i L1 These are the harmonic amplitudes.

[0071] Figure 5 shows the input voltage V when the control of the embodiment is performed. in and input current i L1 This is shown. As can be seen from Figures 4 and 5, by controlling the embodiment, the input current i is compared to when hysteresis control is performed. L1 The tracking performance has been improved, the amplitude of harmonics has decreased, and the distortion rate has been reduced.

[0072] Figure 6 shows the voltage V across the upper arm switching element Q1 when hysteresis control is performed. q1 This shows that when the upper arm switching element Q1 is ON, the voltage across it is V q1 Since it becomes zero, when the upper arm switching element Q1 repeatedly turns ON and OFF in the control cycle, the voltage across its terminals V q1 The waveform oscillates at a frequency corresponding to the switching. Therefore, the voltage across both ends V q1 The waveforms are shown overlapping and filled in as black.

[0073] Figure 7 shows the voltage across the upper arm switching element Q1 when the control of the embodiment is performed. q1 This is shown. As can be seen from Figures 6 and 7, by controlling the embodiment, the number of switching cycles is reduced compared to when hysteresis control is performed, thereby reducing switching losses.

[0074] [Effects of this embodiment] (1) The feedforward unit 60 inputs the duty cycle d1 of the upper arm switching element Q1 and the lower arm switching element Q2 to the input voltage V in and output voltage command value V* out It is derived from the following. In hysteresis control, the input current i L1 When the input current i reaches its upper or lower limit, L1It becomes difficult to make it follow the upper or lower limits. In contrast, with feedforward control, the input voltage V in and output voltage command value V* out Based on the duty cycle d1 determined from this, the upper arm switching element Q1 and the lower arm switching element Q2 are controlled. Therefore, the output voltage V out The output voltage command value V* out Control can be performed to follow the input current i in the circuit configuration of the embodiment compared to when hysteresis control is used. L1 The distortion rate can be reduced.

[0075] (2) The control unit 50 generates a control signal that controls the upper arm switching element Q1 and the lower arm switching element Q2 by a duty cycle d2 obtained by correcting the duty cycle d1. By using a combination of feedforward control and feedback control, the input current i L1 The distortion rate can be further suppressed.

[0076] (3) When hysteresis control is performed, input current i L1 When the input current i reaches its upper or lower limit, it is necessary to switch the upper arm switching element Q1 and the lower arm switching element Q2 ON and OFF. In this case, a control delay occurs, which affects the input current i. L1 This can cause the input current i to exceed its lower or upper limit. L1 The distortion rate may increase further. By performing feedforward-based control as in the embodiment, control delay is less likely to occur, and the input current i L1 The distortion rate can be further suppressed.

[0077] <Example of changes> The embodiment may be modified as follows. Furthermore, the embodiment and the following modifications may be combined with each other to the extent that they do not contradict the technical standards.

[0078] ○The comparator 75 may output a PWM signal obtained by comparing the duty cycle d1 with the carrier wave. That is, the PWM signal input to the logic circuit 80 may be obtained from the duty cycle d1 derived by the feedforward unit 60.

[0079] ○The circuit configuration of power converter 1 may be changed as shown in Figure 8. As shown in Figure 8, the connection configuration of the primary circuit 10, the first capacitor 17, the transformer 18, and the buffer circuit 40 in power converter 2 is different from that of power converter 1. In power converter 2, the starting end of the primary winding W1 is electrically connected to the cathode of the upper arm diode 12 and to the first end t31 of the upper arm switching element Q1. The termination of the primary winding W1 is connected to the first end t51 of the first capacitor 17. The second end t52 of the first capacitor 17 is connected to the anode of the lower arm diode 13 and to the second end t42 of the lower arm switching element Q2. In power converter 2, the second end t52 is an example of "one end of the first capacitor". The first end t51 is an example of "the other end of the first capacitor".

[0080] The cathode and first terminal t31 of the upper arm diode 12 are connected to the starting end of the primary winding W1, and the terminal tq2 of the buffer switching element Q3 is connected to this point. The terminal tc2 of the buffer capacitor Cc is connected to the end of the primary winding W1 and the first terminal t51 of the first capacitor 17. Thus, the buffer capacitor Cc is connected in series with the first capacitor 17.

[0081] Even when the power converter 2 is configured as described above, the same effects as in the embodiment can be obtained by performing the same control as in the embodiment. ○The circuit configuration of the power converter 1 may be changed as shown in Figure 9. As shown in Figure 9, the power converter 3 comprises a primary circuit 10, a first capacitor 17, a transformer 18, a second capacitor 19, a rectifier and smoothing circuit 30, a buffer circuit 40, and a control unit 50. The rectifier and smoothing circuit 30 comprises a second inductor 21, a secondary diode 22, an output capacitor 23, a first output line OL1, a second output line OL2, a first output terminal t91, and a second output terminal t92.

[0082] The end of the secondary winding W2 is electrically connected to the first end t71 of the second inductor 21 and the cathode of the secondary diode 22 via the second capacitor 19. Specifically, the end of the secondary winding W2 is connected to the first end t61 of the second capacitor 19. The second end t62 of the second capacitor 19 is connected to the first end t71 of the second inductor 21 and the cathode of the secondary diode 22. The beginning of the secondary winding W2 is connected to the anode of the secondary diode 22 and the second output line OL2.

[0083] The output capacitor 23 is connected to both the first output line OL1 and the second output line OL2. Specifically, the first terminal t81 of the output capacitor 23 is connected to the first output line OL1, and the second terminal t82 of the output capacitor 23 is connected to the second output line OL2.

[0084] The second terminal t72 of the second inductor 21 is connected to the first output line OL1. As described above, the first terminal t71 of the second inductor 21 is connected to the cathode of the secondary diode 22. The second terminal t72 of the second inductor 21 is connected to the first terminal t81 of the output capacitor 23. Therefore, the rectifier and smoothing circuit 30 is connected to the secondary winding W2 of the transformer 18 via the second capacitor 19.

[0085] Even when the power converter 3 is configured as described above, the same effects as in the embodiment can be obtained by performing the same control as in the embodiment. In this case, the formula used by the buffer duty deriving unit 52 to derive the buffer duty d3 may be changed according to the circuit configuration of the power converter 3.

[0086] ○The power converter 3 may have a connection configuration between the primary circuit 10 and the buffer circuit 40 that differs from the example shown in Figure 9. As shown in Figure 10, the power converter 4 has a similar configuration to the power converter 3, but the connection configuration of the primary circuit 10, the first capacitor 17, the transformer 18, and the buffer circuit 40 differs from that of the power converter 3. Specifically, in the power converter 4, the starting end of the primary winding W1 is electrically connected to the cathode of the upper arm diode 12 and the first end t31 of the upper arm switching element Q1. The termination of the primary winding W1 is connected to the first end t51 of the first capacitor 17. The second end t52 of the first capacitor 17 is connected to the anode of the lower arm diode 13 and the second end t42 of the lower arm switching element Q2.

[0087] The cathode and first terminal t31 of the upper arm diode 12 are connected to the starting end of the primary winding W1, and the terminal tq2 of the buffer switching element Q3 is connected to the terminal tc2 of the buffer capacitor Cc is connected to the end of the primary winding W1 and the first terminal t51 of the first capacitor 17. As a result, the buffer capacitor Cc is connected in parallel with the primary winding W1 of the transformer 18 via the buffer switching element Q3. The buffer capacitor Cc is connected in series with the first capacitor 17.

[0088] Even when the power converter 4 is configured as described above, the same effects as in the embodiment can be obtained by performing the same control as in the embodiment. ○The circuit configuration of the power converter 1 may be changed as shown in Figure 11. As shown in Figure 11, the power converter 5 comprises a primary circuit 10, a first capacitor 17, a transformer 18a, a buffer circuit 40, a control unit 50, and a rectifier / smoothing circuit 90. The transformer 18a comprises a first secondary winding W21 and a second secondary winding W22 as secondary windings W2. The rectifier / smoothing circuit 90 comprises a second inductor 21, an output capacitor 23, a first secondary diode 24, a second secondary diode 25, a first output line OL1, a second output line OL2, a first output terminal t91, and a second output terminal t92.

[0089] The starting end of the first secondary winding W21 is electrically connected to the anode of the first secondary diode 24. The ending end of the second secondary winding W22 is electrically connected to the anode of the second secondary diode 25. The cathode of the first secondary diode 24 is connected to one end of the output capacitor 23 via the second inductor 21. Specifically, the cathode of the first secondary diode 24 is connected to the first end t71 of the second inductor 21. The cathode of the second secondary diode 25 is connected to the connection point between the cathode of the first secondary diode 24 and the first end t71. The ending end of the first secondary winding W21 and the starting end of the second secondary winding W22 are connected.

[0090] The first secondary diode 24 and the second secondary diode 25, when connected as described above, each allow one of the currents flowing through the first secondary winding W21 and the current flowing through the second secondary winding W22, while restricting the other. Specifically, when the potential at the starting end of the primary winding W1 is higher than the potential at the ending end, the first secondary diode 24 allows current to flow from the first secondary winding W21 of the secondary winding W2 to the second inductor 21 and beyond. Conversely, the second secondary diode 25 prevents current from flowing from the second secondary winding W22 of the secondary winding W2 to the second inductor 21 and beyond. Furthermore, when the termination potential of the primary winding W1 is higher than the starting potential, the first secondary diode 24 prevents current from flowing from the first secondary winding W21 of the secondary winding W2 to the second inductor 21 and beyond.

[0091] The output capacitor 23 is connected to both the first output line OL1 and the second output line OL2. Specifically, the first terminal t81 of the output capacitor 23 is connected to the first output line OL1, and the second terminal t82 of the output capacitor 23 is connected to the second output line OL2.

[0092] The second inductor 21 is located on the first output line OL1 between the first secondary diode 24 and the output capacitor 23. Specifically, the second inductor 21 is located on the first output line OL1 between the connection point of the first secondary diode 24 and the connection point of the output capacitor 23. As described above, the cathode of the first secondary diode 24 and the cathode of the second secondary diode 25 are connected to the first terminal t71 of the second inductor 21. The second terminal t72 of the second inductor 21 is connected to the first terminal t81 of the output capacitor 23.

[0093] The connection point between the first secondary winding W21 and the second secondary winding W22 is connected to the second terminal t82 of the output capacitor 23 and the second output line OL2. The connection point between the first secondary winding W21 and the second secondary winding W22 is, for example, the midpoint of the secondary winding W2. Therefore, the second terminal t82 of the output capacitor 23 is connected to the midpoint of the secondary winding W2.

[0094] Even when the power converter 5 is configured as described above, the same effects as in the embodiment can be obtained by performing the same control as in the embodiment. In this case, the formula used by the buffer duty deriving unit 52 to derive the buffer duty d3 may be changed according to the circuit configuration of the power converter 5.

[0095] ○The power converter 5 may have a connection configuration between the primary circuit 10 and the buffer circuit 40 that differs from the example shown in Figure 11. As shown in Figure 12, the power converter 6 has a similar configuration to the power converter 5, but the connections of the primary circuit 10, the first capacitor 17, the transformer 18 and the buffer circuit 40 differ from those of the power converter 5. Specifically, in the power converter 6, the starting end of the primary winding W1 is electrically connected to the cathode of the upper arm diode 12 and the first end t31 of the upper arm switching element Q1. The termination of the primary winding W1 is connected to the first end t51 of the first capacitor 17. The second end t52 of the first capacitor 17 is connected to the anode of the lower arm diode 13 and the second end t42 of the lower arm switching element Q2.

[0096] The cathode and first terminal t31 of the upper arm diode 12 are electrically connected to the connection point between the cathode and the first terminal t31 of the primary winding W1 and the starting end of the primary winding W1, and the terminal tq2 of the buffer switching element Q3. The terminal tc2 of the buffer capacitor Cc is connected to the end of the primary winding W1 and the first terminal t51 of the first capacitor 17. As a result, the buffer capacitor Cc is connected in parallel with the primary winding W1 of the transformer 18 via the buffer switching element Q3. The buffer capacitor Cc is connected in series with the first capacitor 17.

[0097] Even when the power converter 6 is configured as described above, the same effects as in the embodiment can be obtained by performing the same control as in the embodiment. ○Instead of diodes, switching elements may be used as the upper arm rectifier element and the lower arm rectifier element. In this case, so-called synchronous rectification control is performed, in which the switching elements are turned ON at the timing when the upper arm diode 12 and the lower arm diode 13 conduct. By using switching elements instead of diodes, conduction losses can be reduced.

[0098] ○The rectifier-smoothing circuits 20 and 30 may have switching elements instead of the secondary diode 22. The rectifier-smoothing circuit 90 may have switching elements instead of the first secondary diode 24 and the second secondary diode 25. In this case, the control unit 50 performs so-called synchronous rectification control, which turns on the switching elements when the secondary diode 22, the first secondary diode 24, and the second secondary diode 25 are in a switching pattern that conducts. As a result, the rectifier-smoothing circuits 20, 30, and 90 can reduce conduction losses by using switching elements instead of diodes.

[0099] ○The first inductor 11 may be connected between the second input terminal t22 and the second connecting line CL2. The first inductor 11 may be two inductors and connected both between the first input terminal t21 and the first connecting line CL1, and between the second input terminal t22 and the second connecting line CL2.

[0100] ○In power converters 1, 3, and 5, the first capacitor 17 may be connected between the end of the primary winding W1 and the second end t42 of the lower arm switching element Q2. The first capacitor 17 may be composed of two capacitors. In this case, it is connected both between the starting end of the primary winding W1 and the first end t31 of the upper arm switching element Q1, and between the end of the primary winding W1 and the second end t42 of the lower arm switching element Q2.

[0101] ○In power converters 1 and 2, the second capacitor 19 may be connected between the end of the secondary winding W2 and the second end t72 of the second inductor 21. The second capacitor 19 may be composed of two capacitors, in which case it is connected both between the starting end of the secondary winding W2 and the anode of the secondary diode 22, and between the end of the secondary winding W2 and the second end t72 of the second inductor 21.

[0102] ○In the power converter 3, the second capacitor 19 may be connected between the starting end of the secondary winding W2 and the anode of the secondary diode 22. Alternatively, the second capacitor 19 may be composed of two capacitors, in which case it will be connected both between the end of the secondary winding W2 and the cathode of the secondary diode 22, and between the starting end of the secondary winding W2 and the anode of the secondary diode 22.

[0103] ○The current sensor C1 may be installed on the second intermediate line ML2 instead of the first intermediate line ML1. ○The buffer circuit 40 may be provided separately from the primary circuit 10.

[0104] [Definition] As used herein, the expression "at least one" means "one or more" of the desired options. For example, as used herein, "at least one" means "only one option" or "both of the two options" if there are two options. As another example, as used herein, "at least one" means "only one option" or "a combination of two or more any options" if there are three or more options. [Explanation of Symbols]

[0105] Cc...buffer capacitor, Q1...upper arm switching element, Q2...lower arm switching element, Q3...buffer switching element, t21, t22...input terminals, V1...AC power supply, W1...primary winding, W2...secondary winding, 1...power converter, 10...primary side circuit, 11...first inductor, 12...upper arm diode, which is an example of an upper arm rectifier element, 13...lower arm diode, which is an example of a lower arm rectifier element, 14...bridge circuit, 17...first capacitor, 18...transformer, 20...rectifier and smoothing circuit, 21...second inductor, 22...secondary side diode, which is an example of a secondary side rectifier element, 23...output capacitor, 40...buffer circuit, 50...control unit, 58...determination unit, 60...feedforward unit, 64...output voltage control unit, 70...input current control unit, 80...logic circuit.

Claims

1. A power conversion device that converts an input voltage received from an AC power source into a DC voltage, A transformer having a primary winding and a secondary winding, A primary side circuit comprising a pair of input terminals to which the AC power supply is connected, a first inductor, an upper arm switching element, a lower arm switching element, an upper arm rectifier element, and a lower arm rectifier element, A rectifier and smoothing circuit having a second inductor, a secondary rectifier element, an output capacitor, and a first output terminal and a second output terminal, A first capacitor having one end connected to the primary circuit and the other end connected to the primary winding, The series connection of the upper arm switching element and the lower arm switching element, and the series connection of the upper arm rectifier element and the lower arm rectifier element constitute a bridge circuit, and the connection point of the upper arm switching element and the lower arm switching element and the connection point of the upper arm rectifier element and the lower arm rectifier element are connected to the pair of input terminals via the first inductor. The primary side circuit includes a buffer circuit having a buffer switching element and a buffer capacitor. The rectifier and smoothing circuit is connected to the secondary winding, The system comprises a control unit that controls the upper arm switching element, the lower arm switching element, and the buffer switching element, The control unit, A feedforward unit that derives the duty cycles of the upper arm switching element and the lower arm switching element by feedforward control of the input voltage and output voltage command value, A comparator that outputs a PWM signal based on the duty cycle derived by the feedforward unit, A determination unit that outputs a High level or Low level output signal depending on whether the input voltage is positive or negative, A power conversion device comprising a logic circuit that outputs control signals for controlling the upper arm switching element and the lower arm switching element based on the PWM signal and the output signal.

2. The control unit, An output voltage control unit outputs a value obtained by multiplying the deviation between the output voltage command value and the output voltage by a feedback gain, The power conversion device according to claim 1, further comprising: an input current control unit that adds to the duty cycle a value obtained by multiplying the difference between the input current command value derived from the output of the output voltage control unit and the phase of the input voltage and the input current by a feedback gain.

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