Semiconductor integrated circuit device and method for shutting off power to a circuit module in a semiconductor integrated circuit device

Abstract

This provides a new power cutoff technology for semiconductor integrated circuit devices. [Solution] The present invention is a semiconductor integrated circuit device comprising a bus, a processor circuit module, and a circuit module to be power-off. The bus comprises a bus core including data signal lines and a predetermined bus interface circuit for connecting the circuit module to the bus core. The predetermined bus interface circuit comprises a transaction control circuit for controlling transactions related to data transmission via the bus core, and a power control circuit including a power control register, which controls the power supply to the circuit module according to the register value held by the power control register. The power control circuit, under the control of the processor circuit module, controls the power supply to the circuit module to be cut off in accordance with a power-off instruction from the transaction control circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit device and a method for power-off of a circuit module in the semiconductor integrated circuit device.

Background Art

[0002] With the high integration (hierarchicalization and / or miniaturization of process rules) of semiconductor integrated circuit devices, power consumption increases, and furthermore, an increase in leakage current and an increase in switching power become significant problems. For this reason, in order to address such power problems, a power-off technology (sometimes called "power gating technology") that suppresses power consumption by dynamically shutting off the power supply (power) to unused circuit blocks in a semiconductor integrated circuit device is known. In the power-off technology, a certain type of control circuit called a power management unit (PMU) that controls the power supply to a circuit block is provided in the semiconductor integrated circuit device.

[0003] For example, Patent Document 1 below discloses a semiconductor integrated circuit device having a power-off switch. Specifically, the semiconductor integrated circuit device of Patent Document 1 includes a circuit block including a circuit block to be powered off and a circuit block such as a CPU that is constantly supplied with power and operates, and a power-off switch that selectively switches the power supply and non-power supply to the circuit block to be powered off. The power-off control circuit is controlled by the CPU, and outputs a necessary voltage to the power-off switch and controls the power-off switch in accordance with the operation timing of the circuit block to be powered off.

[0004] Furthermore, a problem arose where circuit blocks whose power was cut off by power-off technology would unintentionally operate and generate erroneous signals due to signals flowing in from adjacent operating circuit blocks, which would then flow into adjacent operating circuit blocks. In particular, the inrush current (transient current) associated with the power restoration operation after power cut-off could affect the operation of semiconductor integrated circuit devices. For this reason, isolators (sometimes called isolation cells) are generally provided around the circuit blocks to be cut off to prevent them from interfering with operating circuit blocks.

[0005] For example, Patent Document 2 discloses a semiconductor integrated circuit (LSI) that includes an isolation cell that fixes the output from a circuit domain when the power supply to that circuit domain is cut off. Specifically, in the LSI of Patent Document 2, the internal state of the LSI can be set to a desired state by a scan chain formed inside, and when the PMU stops supplying power to a domain, it asserts a signal input to the isolation cell to fix the output of the domain. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2010-245414 [Patent Document 2] Japanese Patent Publication No. 2012-008093 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] When applying power cut-off technology to semiconductor integrated circuit devices, it is necessary that the PMU is appropriately positioned within the semiconductor integrated circuit device and that signal wiring is appropriately arranged between the PMU and the circuit block or module to be cut off (hereinafter referred to as "power cut-off target circuit module"). Therefore, with the increasing integration of semiconductor integrated circuit devices, the number of power cut-off target circuit modules also increases, resulting in the problem of affecting the effective core area.

[0008] Furthermore, in layout design, such as the placement and wiring of PMUs, the high integration of semiconductor integrated circuit devices presented a challenge: it increased the time required for simulations using circuit models, leading to increased development man-hours and consequently higher costs. In particular, the problem of inrush current when power is restored to circuit modules subject to power cut-off had to be resolved through repeated iterative design. In addition, design changes to some circuit modules could affect the behavior of adjacent circuit modules subject to power cut-off, making it difficult to reduce development man-hours and costs. Moreover, after moving to the physical manufacturing process of the die following simulation, if unexpected problems arose due to insufficient simulation accuracy, significant losses in the development process occurred. This meant that an enormous amount of time was required in the hardware design phase in order to minimize the risk of hardware design errors.

[0009] Furthermore, the PMU itself within the semiconductor integrated circuit device does not participate in data transfer processing (transactions) via the bus by the circuit module targeted for power cut-off. Instead, the CPU checks the transaction status of the bus interface circuit (hereinafter referred to as the "bus IF circuit") to the circuit module targeted for power cut-off and controls the PMU. As a result, control flows such as signal exchanges between the CPU and the bus IF circuit, and between the CPU and the PMU, occur via the bus, which poses a problem as it affects the overall performance of the semiconductor integrated circuit device.

[0010] Furthermore, isolation cells are designed to fix the output voltage to either a high or low state in order to suppress the generation of inrush current associated with the recovery operation after a power outage. Isolation cells themselves are designed solely for the purpose of suppressing the generation of inrush current, and currently, there is no intention to use isolation cells for any other purpose.

[0011] Therefore, the present invention aims to propose a new architecture for semiconductor integrated circuit devices to which power cut-off technology is applied.

[0012] More specifically, one of the objectives of the present invention is to provide a semiconductor integrated circuit device and a method for enabling power shutdown in a semiconductor integrated circuit device, even without a power management unit (PMU) that was conventionally placed within the semiconductor integrated circuit device for power control of a circuit module to be shut off.

[0013] Furthermore, one of the objectives of the present invention is to provide a semiconductor integrated circuit device and a method for shutting off power in a semiconductor integrated circuit device that can suppress the influence of rush current in power control of a circuit module to be shut off power within the semiconductor integrated circuit device.

[0014] Another object of the present invention is to provide a semiconductor integrated circuit device and a method for shutting off power in a semiconductor integrated circuit device that enables signal control to other circuit blocks by a circuit module to be shut off power within the semiconductor integrated circuit device, even when the power supply to the circuit module to be shut off power is shut off.

[0015] Furthermore, one of the objectives of the present invention is to provide a semiconductor integrated circuit device and a method for shutting off power in a semiconductor integrated circuit device that can reduce the development man-hours for semiconductor integrated circuit devices to which power shutdown technology is applied, and thereby reduce the associated development costs. [Means for solving the problem]

[0016] The present invention, which solves the above problems, is comprised of the following inventive features or technical characteristics.

[0017] According to a certain view, the present invention is a semiconductor integrated circuit device comprising a bus, a processor circuit module, and a predetermined circuit module to be subject to power cutoff. The bus comprises a bus core including data signal lines and a predetermined bus interface circuit for connecting the predetermined circuit module to the bus core. The predetermined bus interface circuit comprises a transaction control circuit for controlling transactions related to data transmission via the bus core, and a power control circuit including a power control register, which controls the power supply to the predetermined circuit module according to the register value held by the power control register. The power control circuit, under the control of the processor circuit module, controls the supply of power to the predetermined circuit module to be cut off in accordance with a power cutoff instruction from the transaction control circuit.

[0018] Furthermore, the semiconductor integrated circuit device may further include a bus interface circuit different from the predetermined bus interface for connecting circuit modules that are not subject to power cut-off (always powered) to the bus core. In this disclosure, circuit modules that are not subject to power cut-off are shown as the first circuit module, and predetermined circuit modules that are subject to power cut-off are shown as the second circuit module.

[0019] Furthermore, the transaction control circuit may instruct the power control circuit to shut off the power in accordance with the power shutdown instruction set from the processor circuit module.

[0020] Furthermore, the semiconductor integrated circuit device may further include a power switch section that includes at least one switching element that selectively switches between supplying and cutting off the power to the predetermined circuit module.

[0021] Further, the power control circuit can perform control so that the switching element is selectively switched to either supply or cut off the power according to the register value held by the power control register.

[0022] The power switch unit may include a plurality of the switching elements and a selector that divides the plurality of switching elements into a first switching element consisting of a first group and a second switching element consisting of a second group.

[0023] Further, the power control circuit can control the selector so that the first switching element and the second switching element operate in parallel according to the register value.

[0024] Further, the power control circuit can control the selector so that the first switching element and the second switching element operate in order according to a predetermined offset time according to the register value.

[0025] The power control register may be configured such that the register value can be rewritten.

[0026] Further, the semiconductor integrated circuit device may further include an isolation region provided so as to surround at least a part of the predetermined module. The isolation region may include at least one or more isolation cells configured to be able to output a predetermined data signal to the outside under the control of the power control circuit.

[0027] Further, when the power control circuit performs control so that the power to the predetermined circuit module is cut off, the power control circuit can control the isolation cell to output the predetermined data signal in accordance with a predetermined clock signal.

[0028] Another aspect of the present invention is a method for shutting off power to a predetermined circuit module in a semiconductor integrated circuit device. The power shutdown method includes a bus interface circuit for connecting the predetermined circuit module to a bus receiving a power shutdown instruction set from a processor circuit module via the bus, and, when transaction processing for the predetermined circuit module is completed, performing control to shut off power to the predetermined circuit module according to the register value of a power control register.

[0029] Furthermore, the power cut-off method may include controlling the bus interface circuit to output a predetermined output signal to an isolation cell in an isolation region formed around the predetermined circuit module according to the register value, along with cutting off the power supply.

[0030] In this specification, "means" does not merely mean physical means, but also includes cases where the functions of those means are realized by software. Furthermore, the functions of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means. In addition, "system" refers to a logical collection of multiple devices (or functional modules that realize specific functions), and it is not particularly relevant whether each device or functional module is located in a single enclosure or not.

[0031] Furthermore, the functions of the elements disclosed herein may be implemented using general-purpose processors, dedicated processors, integrated circuits, ASICs ("Application-Specific Integrated Circuits"), conventional circuit configurations, and / or combinations thereof, or processing circuit configurations, which are configured or programmed to perform the disclosed functions. A processor is considered a processing circuit configuration or circuit configuration if it includes transistors and other circuit configurations within it. In this disclosure, a circuit configuration, unit, or means is hardware that performs the listed functions, or hardware programmed to perform such functions. The hardware may be any other known hardware disclosed herein or programmed or configured to perform the listed functions. If the hardware is a processor which may be considered a type of circuit configuration, then the circuit configuration, means, or unit is a combination of hardware and software, the software being used to constitute the hardware and / or processor. [Effects of the Invention]

[0032] The present invention provides a new architecture for semiconductor integrated circuit devices to which power cut-off technology is applied. In particular, the present invention makes it possible to cut off and restore power to a circuit module to be cut off, even without a separate power management unit (PMU) for power control of the circuit module to be cut off within the semiconductor integrated circuit device.

[0033] Furthermore, according to the present invention, it becomes possible to suppress the influence of rush current in the power control of circuit modules that are subject to power interruption within semiconductor integrated circuit devices.

[0034] Furthermore, according to the present invention, even when the power supply to a circuit module to be shut off within a semiconductor integrated circuit device is cut off, it becomes possible to control signals to other circuit blocks using the isolation cells of the circuit module to be shut off.

[0035] Furthermore, according to the present invention, the development man-hours for semiconductor integrated circuit devices to which power cut-off technology is applied can be reduced, and the associated development costs can be suppressed.

[0036] Other technical features, objectives, and effects or advantages of the present invention will be illustrated by the following embodiments described with reference to the accompanying drawings. The effects described herein are illustrative and not limiting, and other effects may also occur. [Brief explanation of the drawing]

[0037] [Figure 1] Figure 1 is a diagram illustrating an example of a schematic configuration of a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 2] Figure 2 shows a schematic configuration of a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 3] Figure 3 is a diagram illustrating power control of a second circuit module by a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 4] Figure 4 shows an example of the configuration of the power switch section of the second circuit module in a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 5] Figure 5 is a diagram illustrating the control of an isolation region by a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 6] Figure 6 shows an example of a data signal output by an isolation cell in a semiconductor integrated circuit device according to one embodiment of the present invention. [Figure 7] Figure 7 is a flowchart illustrating an example of the operation of a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0038] Embodiments of the present invention will be described below with reference to the drawings. However, the embodiments described below are merely illustrative, and there is no intention to exclude various modifications or applications of techniques not explicitly stated below. The present invention can be implemented by various modifications (for example, by combining each embodiment) without departing from its spirit. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily correspond to actual dimensions or proportions. There may be parts in the drawings where the dimensional relationships and proportions differ from those of other parts.

[0039] Figure 1 is a diagram illustrating an example of a schematic configuration of a semiconductor integrated circuit device according to one embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit device 1 of this embodiment is, for example, a system-on-a-chip (SoC) in which a plurality of electrode pads 11 for connecting bonding wires are arranged around it. The semiconductor integrated circuit device 1 comprises, for example, a processor circuit module 13, a first circuit module 14, and a second circuit module 15, which are interconnected via a bus 12. The semiconductor integrated circuit device 1 also includes an isolation region 16 formed around at least a portion of the second circuit module 15.

[0040] Bus 12 is a transmission circuit that enables data transmission between various circuit modules 13 to 15. Bus 12 is composed of, for example, a bus core 121 and a bus interface circuit (hereinafter referred to as "bus IF circuit") 122 (see Figure 2). The bus core 121 includes data signal lines for transmitting data. The bus IF circuit 122 is provided to correspond to each circuit module. The bus IF circuit 122 comprehensively controls when to send data blocks from connected circuit modules to the bus core 121 and when to retrieve data blocks from the bus core 121. The bus IF circuit 122 in this disclosure includes a first bus IF circuit 122a and a second bus IF circuit 122b. In this disclosure, as will be described later, the first bus IF circuit 122a and the second bus IF circuit 122b differ in their configuration. Although not shown, bus 12 may also include a DMA (Direct Memory Access) control circuit.

[0041] The first bus IF circuit 122a is provided for the processor circuit module 13 and the first circuit module 14. The first bus IF circuit 122a includes, for example, a transaction buffer 1221 and a transaction control circuit 1222 (see Figure 2). The first bus IF circuit 122a can, but is not limited to, the configuration of a conventional bus IF circuit.

[0042] The second bus IF circuit 122b is provided for the second circuit module 15. The second bus IF circuit 122b includes a transaction buffer 1221 and a transaction control circuit 1222, as well as a power control circuit 1223 (see Figure 2). As will be described later, the power control circuit 1223 is a circuit for controlling the power supply / shut-off of the second circuit module 15. In this way, by providing the power control circuit 1223 in the second bus IF circuit 122b for each second circuit module, the wiring from the PMU to the circuit module to be shut off is no longer necessary, and the time spent on the layout process due to wiring congestion can be reduced.

[0043] The processor circuit module 13 is a circuit that interprets and executes a predetermined program, thereby processing various data. A CPU or MPU is one embodiment of the processor circuit module 13. The processor circuit module 13 may be in a multiprocessor configuration. The processor circuit module 13 comprehensively controls the bus 12. For example, the processor circuit module 13 can control the operation of specific circuit modules (i.e., a first circuit module 14 and / or a second circuit module 15) via the bus 12 in accordance with the execution of a predetermined program. In this disclosure, the processor circuit module 13 instructs the power control circuit 1223 in the second bus IF circuit 122b to perform power control of a specific second circuit module 15.

[0044] The first circuit module 14 is a circuit module that is constantly powered by a power supply (not shown) during the operation of the semiconductor integrated circuit device 1. In this disclosure, such a constantly powered circuit module may be referred to as a constantly powered circuit module. For example, a constantly accessed SRAM or a small-scale, low-speed circuit module that does not offer significant power reduction benefits is one embodiment of the first circuit module 14. The first circuit module 14 is connected to the bus core 121 via the first bus IF circuit 122a.

[0045] The second circuit module 15 is a circuit module that, while the semiconductor integrated circuit device 1 is operating, is supplied with power from the power supply while it is performing processing under the control of the processor circuit module 13, and when there is no processing to be performed, the power supply from the power supply is cut off. In this disclosure, such a circuit module that can be cut off is sometimes referred to as a circuit module subject to power cut-off. For example, an image processing module that performs image resizing processing, defective pixel correction processing, shading correction processing, color space conversion processing, etc., is one embodiment of the second circuit module 15. An image processing module may be subject to power cut-off because it does not need to operate when there is no image data to be processed. The second circuit module 15 is configured to include a power switch unit 151 (see Figure 3). The power switch unit 151 is a switch circuit that includes one or more switching elements 1511 for selectively switching between a power supply or cut-off state under the control of the power control circuit 1223. The power switch unit 151 may be configured as part of the second circuit module 15, or it may be formed around the second circuit module 15. Furthermore, the second circuit module 15 is connected to the bus core 121 via the second bus IF circuit 122b. The second circuit module 15 is controlled by the power supply control circuit 1223 of the second bus IF circuit 122b, under the control of the processor circuit module 13, to supply / cut off power. In other words, when the power supply control circuit 1223 cuts off the power supply to a second circuit module 15, it ensures that there is no access to the bus 12 by the second circuit module before cutting off the power supply to that second circuit module.

[0046] The isolation region 16 is a region formed around the second circuit module 15 to block signals entering the second circuit module 15 and / or to control signals output from the second circuit module 15. The isolation region 16 is configured to include, for example, logic circuits. The isolation region 16 is configured to output bit signals consisting of a predetermined alternating voltage (e.g., a High or Low voltage) while the power supply to the second circuit module 15 is cut off. For example, the isolation region 16 can output predetermined enable signals, predetermined clock signals, predetermined data signals, etc., under the control of the power control circuit 1223.

[0047] Figure 2 is a diagram showing an example of a schematic configuration of a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. Specifically, the figure shows a functional configuration model of a second bus IF circuit 122b connected to a second circuit module 15, which is a circuit module to be shut off. As described above, the second bus IF circuit 122b differs from the first bus IF circuit 122a in that it further includes a power control circuit 1223. That is, as shown in the figure, the second bus IF circuit 122b is configured to include a transaction buffer 1221, a transaction control circuit 1222, and a power control circuit 1223.

[0048] The transaction buffer 1221 is a buffer circuit that enables pipeline processing of transactions related to data transmission. For example, the transaction buffer 1221 temporarily pipelines and buffers data blocks that the second circuit module 15 is outputting to the bus 12 or data blocks that have been taken in from the bus 12.

[0049] The transaction control circuit 1222 is a circuit for pipeline control of transactions of data blocks buffered in the transaction buffer 1221, stage by stage. For example, the transaction control circuit 1222 controls the data blocks of each stage buffered in the transaction buffer 1221 output from the second circuit module 15 to be output sequentially to the bus core 121. Alternatively, the transaction control circuit 1222 controls the data blocks of each stage taken from the bus core 121 to be written to the transaction buffer 1221 so that they are output sequentially to the second circuit module 15. In addition, the transaction control circuit 1222 controls the power control circuit 1223 according to the status of the transaction. For example, after the transaction control circuit 1222 obtains a power cut-off instruction set from the processor circuit module 13 and all transactions are completed, it instructs the power control circuit 1223 to cut off the power supply to the second circuit module 15. Furthermore, when the transaction control circuit 1222 obtains a power restoration instruction set from the processor circuit module 13, it instructs the power control circuit 1223 to resume supplying power to the second circuit module 15.

[0050] The power control circuit 1223 is a circuit for controlling the supply / cutoff of power to the connected second circuit module 15. The power control circuit 1223 includes a power control register 1224. The power control register 1224 is a register that rewrites values ​​for specifying the operation and state of each switching element 1511 of the power switch unit 151 for the second circuit module 15. In other words, the operation of each switching element 1511 is controlled according to the value of the power control register 1224. Therefore, by arbitrarily rewriting the value of the power control register 1224, the control of the supply / cutoff of power to the second circuit module 15 can be flexibly changed, overcoming the difficulty of making changes after the hardware has been determined. In addition, the register value of the power control register 1224 can be used to determine a predetermined output signal of the isolation cell 161, which will be described later.

[0051] For example, the power control circuit 1223 can control the switching elements 1511 (first switching elements) constituting the first group and the switching elements 1511 (second switching elements) constituting the second group to operate in parallel or simultaneously, depending on the register value of the power control register 1224. Alternatively, the power control circuit 1223 can control the first switching elements and the second switching elements to operate sequentially according to a predetermined offset time, depending on the register value. That is, by controlling the switching elements 1511 of the first group and the switching elements 1511 of the second group in parallel, the time required for power interruption and restoration can be shortened. However, in the case of such parallel control, the inrush current (transient current) becomes large, which may cause surrounding circuit modules to malfunction. In contrast, by controlling the switching elements 1511 of the first group and the switching elements 1511 of the second group in series, the time required for power interruption and restoration becomes longer, but the inrush current can be suppressed, reducing the risk of malfunction of surrounding circuit modules. Therefore, it is important to determine the optimal control points (such as operating timing and number) for the switching elements 1511 of the first group and the switching elements 1511 of the second group. In this disclosure, such optimal control points are determined during chip evaluation rather than during hardware design, and this is stored as the value of the power control register 1224, thereby shortening hardware design time and reducing the risk of hardware design errors.

[0052] Furthermore, in this disclosure, the power control circuit 1223 controls the isolation region 16 to output a bit signal consisting of a predetermined alternating voltage, based on the register value of the power control register 1224. Such a bit signal can be used to block signals from the surroundings from entering the second circuit module 15, which is in a power-off state, and to send predetermined information to other surrounding circuit modules. For example, the power control circuit 1223 outputs a data control signal to the isolation region 16 so that the isolation region 16 outputs a predetermined enable signal, a predetermined clock signal, a predetermined data signal, etc.

[0053] Figure 3 is a diagram illustrating power supply control for a second circuit module by a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. Specifically, the figure shows a power switch unit 151 in the second circuit module 15 and a power control circuit 1223 that controls it. The number of power switch units 151 depends on the size of the circuit module core, and may be more or less than the number shown in the figure.

[0054] As shown in the figure, for example, multiple power switch units 151 are arranged around the main part of the second circuit module 15 (referred to here as the "circuit module core"). Each power switch unit 151 is composed of multiple switching elements 1511 (see Figure 4). Each power switch unit 151 has terminals A to C, and is connected in series by connecting terminal B of the preceding power switch unit 151 to terminal A of the subsequent power switch unit 151, and is connected to the power control circuit 1223. In addition, terminal C of each power switch unit 151 is connected to the power control circuit 1223.

[0055] Figure 4 shows an example of the configuration of the power switch section of a second circuit module in a semiconductor integrated circuit device according to one embodiment of the present invention. As shown in the figure, the power switch section 151 is configured to include a plurality of switching elements 1511 connected in tandem between terminal A and terminal B. The switching elements 1511 are, for example, P-channel MOSFETs. The gate of the switching element 1511 is connected to terminal A, the source is connected to the power supply voltage line, and the drain is connected to the circuit module core (not shown). Therefore, the switching element 1511 supplies the power supply voltage to the circuit module core or cuts off the supply of the power supply voltage to the circuit module core in response to the power supply enable signal. In addition, the output of the drain of the switching element 1511 can be used as a power supply confirmation signal.

[0056] Furthermore, the power switch unit 151 includes a selector 1512 connected to terminal C. Multiple switching elements 1511 are divided into multiple groups by the selector 1512. In this example, the switching elements 1511 are divided into a first group and a second group. The number of switching elements 1511 in each group may be the same or different.

[0057] The selector 1512 selects either both the first group of switching elements 1511 and the second group of switching elements 1511, or selects only the second group of switching elements 1511, in response to the selector signal from terminal C. The selector signal depends on the value of the power control register 1224. In other words, when the semiconductor integrated circuit device 1 is actually fabricated as silicon, the power supply / cutoff operation by the grouped switching elements 1511 is evaluated, and the register value of the power control register 1224 is determined based on the evaluation result. For example, the register values ​​are determined so that the first and second switching elements operate in parallel. Alternatively, the register values ​​are determined so that the first and second switching elements operate sequentially according to a predetermined offset time. This allows for flexible selection of the optimal combination of switching elements 1511 for power supply / cutoff to the second circuit module 15.

[0058] Figure 5 is a diagram illustrating the control of an isolation region by a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. Specifically, the figure shows an isolation region 16 for a second circuit module 15 and a power control circuit 1223 that controls it.

[0059] As shown in the figure, the isolation region 16 is comprised of several isolation cells 161. Each isolation cell 161 is controlled by the power control circuit 1223 via a power enable signal line and an output signal control line for power supply / cutoff, respectively. For example, each isolation cell 161 may, under the control of the power control circuit 1223, output a bit signal consisting of a predetermined alternating voltage according to the register value of the power control register 1224 while the power to the second circuit module 15 is cut off.

[0060] For example, isolation cells 161a and 161b, under the control of the power control circuit 1223, can output predetermined clock signals and predetermined enable signals to the first circuit module 14, respectively, as shown in Figures 6(a) and (b). Furthermore, isolation cells 161c and 161d, under the control of the power control circuit 1223, can output predetermined data signals to circuit modules outside the semiconductor integrated circuit device 1, as shown in Figure 6(c).

[0061] Figure 7 is a flowchart illustrating an example of the operation of a bus interface circuit in a semiconductor integrated circuit device according to one embodiment of the present invention. Specifically, the figure is a flowchart illustrating an example of the operation of a bus interface circuit 122 corresponding to a second circuit module when the power supply is cut off.

[0062] As shown in the figure, the transaction control circuit 1222 of the bus interface circuit 122 monitors whether or not a power-off instruction set has been received (S701). A power-off instruction set is typically transmitted from the processor circuit module 13 via the bus 12. For example, the processor circuit module 13 transmits the power-off instruction set via the bus 12 as part of a predetermined instruction set to the second circuit module 15, or immediately following that instruction set.

[0063] If the transaction control circuit 1222 determines that it has received a power cut-off instruction set (Yes in S701), it refers to the transaction buffer 1221 (S702) and determines whether the transaction processing for the second circuit module 15 is complete (S703). That is, if there are still data blocks remaining in the transaction buffer 1221, the transaction control circuit 1222 determines that the transaction processing is not complete (No in S703) and monitors the transaction buffer 1221 until there are no more data blocks left in the transaction buffer 1221.

[0064] When the transaction control circuit 1222 determines that there are no more data blocks in the transaction buffer 1221 and that the transaction processing is complete (Yes in S703), the transaction control circuit 1222 instructs the power control circuit 1223 to cut off the power supply (S704).

[0065] When the power control circuit 1223 receives a power supply cutoff instruction from the transaction control circuit 1222, it refers to the power control register 1224 and obtains the register value (S705). The power control circuit 1223 then controls the power switch unit 151 based on the register value (S706). For example, the power control circuit 1223 controls several switching elements 1511 in each power switch unit 151 to be turned OFF according to the register value of the power control register 1224. As a result, the power supply to the second circuit module 15 is cut off.

[0066] Next, the power control circuit 1223 controls the isolation cell 161 to be driven based on the register value (S707). In this case, the power control circuit 1223 controls the isolation cell 161 to output a predetermined bit signal, for example, as shown in Figure 6. This effectively blocks signals entering the second circuit module 15, which has stopped operating, and also allows the predetermined bit signal to be output to other circuit modules even when the second circuit module 15 is stopped.

[0067] As described above, according to this embodiment, even without a separate power management unit (PMU) for power control of the second circuit module 15 (the circuit module to be powered off) within the semiconductor integrated circuit device 1, power to the second circuit module 15 can be cut off and restored using the second bus interface circuit connected to the second circuit module 15. Therefore, wiring from the PMU to the circuit module to be powered off, as in the past, becomes unnecessary, and the time spent on the layout process due to wiring congestion can be reduced.

[0068] Furthermore, according to this embodiment, in power supply control for the second circuit module 15 in the semiconductor integrated circuit device 1, the switching elements 1511 that constitute several groups are controlled for each specific group, so that the effects of inrush current can be suppressed and adverse effects on surrounding circuit modules can be reduced.

[0069] Furthermore, according to this embodiment, even when the power supply to the second circuit module 15 in the semiconductor integrated circuit device 1 is cut off, the isolation cell 161 can be used to control signals to other circuit blocks.

[0070] Furthermore, according to this embodiment, since power control is determined by software (register values) rather than hardware, the development man-hours for the semiconductor integrated circuit device 1 to which the power cut-off technology is applied can be reduced, and the associated development costs can be suppressed.

[0071] The embodiments described above are illustrative examples for illustrating the present invention and are not intended to limit the invention to these embodiments only. The present invention can be implemented in various forms without departing from its spirit.

[0072] For example, in the methods disclosed herein, steps, operations, or functions may be performed in parallel or in different orders, as long as this does not result in a contradiction in the outcome. The steps, operations, and functions described are provided merely as examples, and some of the steps, operations, and functions may be omitted, combined with each other to form a single unit, or other steps, operations, or functions may be added, without departing from the spirit of the invention.

[0073] Furthermore, although various embodiments are disclosed herein, specific features (technical matters) in one embodiment can be added to or replaced in other embodiments, with appropriate modifications, and such forms are also included in the gist of the present invention. [Explanation of Symbols]

[0074] 1… Semiconductor integrated circuit equipment 11… Electrode pads 12... Bus 121...Bascore 122, 122a, 122b… Bus interface circuits 1221... Transaction buffer 1222…Transaction control circuit 1223...Power control circuit 1224…Power control register 13…Processor circuit module 14…First circuit module (always-on circuit module) 15…Second circuit module (circuit module subject to power cut-off) 151...Power switch section 1511…Switching element 1512...Selector 16…Isolation area 161, 161a, 161b, 161c, 161d… Isolation Cells

Claims

1. bus and, Processor circuit module, A predetermined circuit module that is subject to power cut-off, The aforementioned bus, A bus core including data signal lines, The system comprises a predetermined bus interface circuit for connecting the predetermined circuit module to the bus core, The aforementioned predetermined bus interface circuit is A transaction control circuit that controls transactions related to data transmission via the aforementioned bus core, A power control circuit includes a power control register, which controls the power supply to a predetermined circuit module according to the register value held by the power control register, The aforementioned power supply control circuit is Under the control of the processor circuit module, the power supply to the predetermined circuit module is cut off in accordance with a power cut-off instruction from the transaction control circuit. Semiconductor integrated circuit equipment.

2. The system further includes a bus interface circuit different from the predetermined bus interface for connecting a circuit module that is not subject to power supply interruption to the bus core. The semiconductor integrated circuit apparatus according to claim 1.

3. The transaction control circuit instructs the power control circuit to shut off the power according to the power shut-off instruction set from the processor circuit module. The semiconductor integrated circuit apparatus according to claim 1.

4. The power switch unit further includes at least one switching element that selectively switches between supplying and cutting off the power to the predetermined circuit module. The semiconductor integrated circuit apparatus according to claim 1.

5. The power supply control circuit controls the switching element to selectively switch between supplying and cutting off the power supply, according to the register value. The semiconductor integrated circuit apparatus according to claim 4.

6. The aforementioned power switch unit is Multiple switching elements, The system includes a selector that divides the plurality of switching elements into a first group of switching elements and a second group of switching elements. The semiconductor integrated circuit apparatus according to claim 5.

7. The power control circuit controls the selector so that the first switching element and the second switching element operate in parallel, according to the register value. The semiconductor integrated circuit apparatus according to claim 6.

8. The power supply control circuit controls the selector such that the first switching element and the second switching element operate sequentially according to a predetermined offset time, in accordance with the register value. The semiconductor integrated circuit apparatus according to claim 6.

9. The power control register is configured such that the register value can be rewritten. The semiconductor integrated circuit apparatus according to claim 1.

10. The circuit module further comprises an isolation region provided so as to surround at least a portion of the predetermined circuit module. The isolation region includes at least one isolation cell configured to output a predetermined data signal to the outside under the control of the power control circuit. The semiconductor integrated circuit apparatus according to claim 1.

11. The power control circuit controls the isolation cell to output a predetermined data signal in accordance with a predetermined clock signal when it controls the power supply to the predetermined circuit module to be shut off. The semiconductor integrated circuit apparatus according to claim 10.

12. A method for shutting off power to a predetermined circuit module in a semiconductor integrated circuit device, wherein the power supply to the module is to be shut off, A bus interface circuit for connecting the aforementioned predetermined circuit module to the bus is provided. Receiving a power cut-off instruction set from the processor circuit module via the bus, When transaction processing for the predetermined circuit module is completed, control is performed to shut off the power supply to the predetermined circuit module according to the register value of the power control register. Execute Method for shutting off power.

13. The bus interface circuit, upon cutting off the power supply, controls the system to output a predetermined output signal to an isolation cell in an isolation region formed around the predetermined circuit module according to the register value. The power supply shutdown method according to claim 12.

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