Conformal titanium silicon nitride-based thin film and method for forming the same

Abstract

The disclosed technology generally relates to the formation of titanium nitride-based thin films, and more specifically to conformal and smooth titanium nitride-based thin films and methods for forming them. [Solution] One embodiment of the method involves forming a diffusion barrier containing TiSiN having an elastic modulus of 290 GPa and a Si content of more than 2.7 atomic percent by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, then to a silicon (Si) precursor, and then to an N precursor.

Description

[Technical Field]

[0001] Any or all applications that specify a foreign or domestic priority claim in the application data sheet submitted with this application are incorporated herein by reference pursuant to 37 CFR 1.57.

[0002] This application is a continuation of U.S. Application No. 16 / 595,916, “Conformal Titanium Nitride-Based Thin Films and Methods of Forming the Same,” filed on 8 October 2019, and claims priority to U.S. Provisional Application No. 63 / 171,970, “Conformal Titanium Nitride-Based Thin Films and Methods of Forming the Same,” filed on 7 April 2021 pursuant to 35 U.S.C. §119(e), and also claims priority to U.S. Provisional Application No. 63 / 172,002, “Conformal Titanium Nitride-Based Thin Films and Methods of Forming the Same,” filed on 7 April 2021 pursuant to 35 U.S.C. §119(e). Priority is claimed to be given to "NITRIDE-BASED THIN FILMS AND METHODS OF FORMING THE SAME," and the contents of each of them are explicitly included here by reference, in their entirety.

[0003] The disclosed technology relates in general to the formation of titanium nitride-based thin films, and more specifically to conformal and smooth titanium nitride-based thin films. [Background technology]

[0004] Titanium nitride (TiN) thin films are widely used in the fabrication of various structures within integrated circuits (ICs). For example, TiN has been used in diffusion barriers, various electrodes, and metallization structures. This widespread use of TiN in IC manufacturing can be attributed to its structural, thermal, and electrical properties. As IC structures shrink in size, TiN is formed on characteristic shapes with increasingly smaller sizes and complex topologies. For example, when technology nodes exceed the 10 nm node, thin films, such as diffusion barriers, are needed that can conformally line trenches and vias with high aspect ratios at small sizes, such as a few nanometers. While the IC industry has used techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) to form TiN diffusion barriers, their use may eventually be limited as the need for conformability of TiN films deposited on smaller trenches and vias increases. On the other hand, while atomic layer deposition (ALD) has been demonstrated for conformal TiN films, some electrical properties (e.g., conductivity) and physical properties (e.g., surface roughness) of the films may be inferior to those of TiN films formed using other methods such as physical vapor deposition (PVD). Therefore, in IC manufacturing, there is a need for a film deposition method that can form TiN-based films with superior properties, including barrier properties, surface smoothness, and step coverage, compared to TiN films formed by, for example, PVD and CVD. [Overview of the Initiative] [Means for solving the problem]

[0005] In one embodiment, a method for forming a diffusion barrier containing TiSiN includes exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases alternately and without overlap. Exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors alternately. Exposing a semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor without intervening exposure to an N precursor between them, and then exposing the semiconductor substrate to an N precursor.

[0006] In another embodiment, a method for forming a TiSiN-containing diffusion barrier includes exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases alternately and without overlap. Exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors alternately. Exposing a semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then a N precursor.

[0007] In another embodiment, a method for forming a TiSiN-containing diffusion barrier includes exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases alternately and without overlap. Exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors alternately. Exposing a semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor during the Ti precursor exposure time, followed by a silicon (Si) precursor during the Si precursor exposure time, and then a nitrogen precursor. The ratio of the Si precursor exposure time to the Ti precursor exposure time is between 2 and 130.

[0008] In another embodiment, a method for forming a TiSiN-containing diffusion barrier includes exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases alternately and without overlap. Exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors alternately. Exposing a semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to Ti precursors, silicon (Si) precursors, and N precursors. Exposing a semiconductor substrate to one or more of the Ti precursors, Si precursors, and N precursors during one or more second deposition phases includes making the main surface of the semiconductor substrate unsaturated.

[0009] In another embodiment, the method includes forming a diffusion barrier containing TiSiN having an elastic modulus greater than 290 GPa and a Si content greater than 2.7 atomic percent by alternately exposing a semiconductor substrate to one or more first deposition faces and one or more second deposition phases. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0010] In another embodiment, the method includes forming a diffusion barrier containing TiSiN having a hardness greater than 20 GPa and a Si content greater than 2.7 atomic percent by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing a semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then a N precursor.

[0011] In another embodiment, the method includes alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having a crystalline structure such that the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum of the diffusion barrier is greater than 0.4, and a Si content greater than 2.7 atomic percent. Exposing a semiconductor substrate to one or more first deposition phases includes alternating exposure of the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors. Exposing a semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then a N precursor.

[0012] In another embodiment, the method includes alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having a nanocrystalline structure with an average particle size of less than approximately 6.5 nm and a Si content of more than 2.7 atomic percent. Exposing a semiconductor substrate to one or more first deposition phases includes alternating exposure of the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors. Exposing a semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then a N precursor.

[0013] In another embodiment, the semiconductor structure has a semiconductor substrate having a plurality of trenches or vias thereon, the trenches or vias having an aspect ratio of more than 5 with respect to the dielectric sidewall surface. A diffusion barrier layer containing TiSiN conformally lines the surface of the trenches or vias, and the diffusion barrier layer has a Si content of 2.7 to 9 atomic percent and an elastic modulus of 290 to 350 GPa.

[0014] In another embodiment, the semiconductor structure has a semiconductor substrate having a plurality of trenches or vias thereon, wherein the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall surface. A diffusion barrier layer containing TiSiN conformally lines the surface of the trenches or vias, and the diffusion barrier layer has a Si content of 2.7 to 9 atomic percent and a hardness of 20 to 40 GPa.

[0015] In another aspect, a semiconductor structure has a semiconductor substrate with a plurality of trenches or vias thereon, and the trenches or vias have an aspect ratio greater than 5 with respect to the dielectric sidewall surface. A diffusion barrier layer containing TiSiN conformally lines the surface of the trenches or vias, and the diffusion barrier layer has a Si content of 2.7 to 9 atomic percent and a crystal structure such that the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the grazing-incidence X-ray diffraction spectrum is 0.4 to 4.5.

[0016] In another aspect, a semiconductor substrate has a semiconductor substrate with a plurality of trenches or vias thereon, and the trenches or vias have an aspect ratio greater than 5 with respect to the dielectric sidewall surface. A diffusion barrier layer containing TiSiN conformally lines the surface of the trenches or vias, and the diffusion barrier layer has a Si content of 2.7 to 9 atomic percent and a nanocrystalline structure having an average particle size of about 5.0 to 6.5 nm.

[0017] Embodiments of the present disclosure will be described using non-limiting examples with reference to the accompanying drawings.

Brief Description of the Drawings

[0018] [Figure 1] Figures 1A - 1D schematically show different nuclei and growth mechanisms of thin films under different growth modes. [Figure 2] Figure 2 is a cross-sectional transmission electron micrograph of a TiN layer grown by atomic layer deposition on a silicon substrate having topography. [Figure 3] Figure 3 schematically shows a cross-sectional view of a semiconductor structure having a thin film containing TiSiN or TiAlN formed on a semiconductor substrate according to an embodiment. [Figure 4] Figure 4 schematically shows a cross-sectional view of a via lined with a thin film containing TiSiN or TiAlN having different thicknesses at different portions of the via. [Figure 5A] Figure 5A is a flowchart showing a method of forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5B]FIG. 5B is a flowchart showing a film formation cycle for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5C] FIG. 5C is a diagram showing a film formation cycle for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5D] FIG. 5D is a diagram showing a sequence of a film formation cycle for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 6A] FIG. 6A shows a cross-sectional transmission electron micrograph obtained from a thin film containing TiSiN lining the upper part of a high aspect ratio via and a diffraction pattern of a corresponding selected area according to an embodiment. [Figure 6B] FIG. 6B shows a cross-sectional transmission electron micrograph obtained from a thin film containing TiSiN lining the middle part of the high aspect ratio via shown in FIG. 6A and a diffraction pattern of a corresponding selected area according to an embodiment. [Figure 6C] FIG. 6C shows a cross-sectional transmission electron micrograph obtained from a thin film containing TiSiN lining the lower part of the high aspect ratio via shown in FIGS. 6A and 6B and a diffraction pattern of a corresponding selected area according to an embodiment. [Figure 7A] FIG. 7A shows a diffraction pattern of a selected area obtained from a substantially amorphous thin film containing TiSiN lining a high aspect ratio according to an embodiment. [Figure 7B] FIG. 7B shows a diffraction pattern of a selected area obtained from a partially crystalline thin film containing TiSiN lining a high aspect ratio according to an embodiment. [Figure 7C] FIG. 7C shows a diffraction pattern of a selected area obtained from a substantially crystalline thin film containing TiSiN lining a high aspect ratio according to an embodiment. [Figure 8] FIG. 8 shows a small angle incident X-ray diffraction spectrum obtained from a substantially amorphous thin film containing TiSiN according to an embodiment. [Figure 9] FIG. 9 is a graph of resistivity measured experimentally as a function of silicon content in a thin film containing TiSiN according to an embodiment. [Figure 10A] Figure 10A is a cross-sectional transmission electron microscope image obtained from a substantially homogeneous thin film containing TiSiN according to an embodiment. [Figure 10B] Figure 10B is a cross-sectional transmission electron microscope image obtained from a nanolaminate thin film containing alternating regions or layers of SiN and regions or layers of TiN according to an embodiment. [Figure 11] Figure 11 schematically shows a partial cross-sectional view of a semiconductor device having contact lines or metal lines formed by filling holes lined with a thin film containing TiSiN or TiAlN with metal, according to an embodiment. [Figure 12] Figure 12 is a cross-sectional transmission electron microscope image of an ultrathin TiN layer grown by atomic layer deposition on a substrate with topography. [Figure 13] Figure 13 is a flow chart showing vapor deposition cycles for forming a thin film containing TiSiN according to several embodiments. [Figure 14] Figure 14 is a flow chart showing a vapor deposition cycle for forming a thin film containing TiSiN according to an embodiment. [Figure 15] Figure 15 is a flow chart showing a vapor deposition cycle for forming a thin film containing TiSiN according to an embodiment. [Figure 16] Figure 16 is a flow chart showing a vapor deposition cycle for forming a thin film containing TiSiN according to an embodiment. [Figure 17] Figure 17 is a flow chart showing vapor deposition cycles for forming a thin film containing TiSiN according to several embodiments. [Figure 18A] Figure 18A is a graph of the Si content measured experimentally in TiSiN thin films, where the Si content is shown as a function of the ratio of the number of first deposition phases to the number of second deposition phases. [Figure 18B] Figure 18B is a graph of the grazing incidence X-ray diffraction spectra of experimentally measured TiSiN thin films, where different curves corresponding to the TiSiN thin films have different ratios of the number of first deposition phases to the number of second deposition phases. [Figure 18C] Figure 18C is a graph of experimentally measured electrical resistivity from TiSiN thin films for the Si content shown in Figure 18A. [Figure 19] Figures 19A and 19B are graphs of experimentally measured electrical resistivity as a function of Ti exposure time during the second deposition phase of the deposition cycle shown in Figure 17, with the exposure time to dichlorosilane as a Si precursor fixed at 60 seconds and 90 seconds, respectively. [Figure 20] Figures 20A-20C are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiSiN thin film formed using different Ti exposure times during the second deposition phase of the deposition cycle shown in Figure 17. [Figure 21] Figures 21A to 21C are graphs of experimentally measured electrical resistivity as a function of Ti exposure time during the second deposition phase of the deposition cycle shown in Figure 17, with the exposure times to dichlorosilane as a Si precursor fixed at 3.5 seconds, 30 seconds, and 90 seconds, respectively. [Figure 22] Figures 22A-22C are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiSiN thin film formed using different Ti exposure times during the second deposition phase of the deposition cycle shown in Figure 17. [Figure 23] Figures 23A and 23B are graphs of experimentally measured electrical resistivity as a function of Ti exposure time during the second deposition phase of the deposition cycle shown in Figure 17, with the exposure time to dichlorosilane as a Si precursor fixed at 5 seconds and 30 seconds, respectively. [Figure 24] Figures 24A-24B are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiSiN thin film formed using different Ti exposure times during the second deposition phase of the deposition cycle shown in Figure 17. [Figure 25] Figures 25A and 25B are low-resolution and high-resolution cross-sectional transmission electron microscope images obtained from a high-aspect-ratio structure lined with a TiSiN thin film. [Figure 26A] Figure 26A is a flowchart illustrating a method for forming a nanolaminate thin film in several embodiments. [Figure 26B] Figure 26B is a flowchart illustrating a method for forming nanolaminate thin films using a vapor deposition cycle similar to that shown in Figure 13, according to several embodiments. [Figure 26C] Figure 26C is a flowchart illustrating a method for forming nanolaminate thin films using a vapor deposition cycle similar to that shown in Figure 17, according to several embodiments. [Figure 27A] Figure 27A is a graph of experimentally measured electrical resistivity in various nanolaminate thin films deposited according to the methods shown in Figures 26A and 26C, according to several embodiments. [Figure 27B] Figure 27B is a graph of experimentally measured grazing incidence X-ray diffraction spectra measured from various nanolaminate thin films deposited according to the methods shown in Figures 26A and 26C, according to several embodiments. [Figure 28] Figures 28A and 28B are cross-sectional transmission electron microscope images obtained from high aspect ratio structures lined with nanolaminate thin films according to several embodiments. [Figure 29] Figure 29 is a flow chart showing vapor deposition cycles for forming a thin film containing TiSiN according to several embodiments. [Figure 30] Figure 30 is a graph showing the possibility of adjusting the Si content of a TiSiN thin film by adjusting the precursor exposure time and / or the ratio of the number of first deposition phases to the number of second deposition phases, according to several embodiments. [Figure 31ABC] Figures 31A-31C show the grazing incidence X-ray diffraction (XRD) spectra of TiSiN thin films measured experimentally according to the embodiment. [Figure 31DEF] Figures 31D-31F show the grazing incidence X-ray diffraction (XRD) spectra of TiSiN thin films measured experimentally according to the embodiment. [Figure 31GHI]Figures 31G-I show the grazing incidence X-ray diffraction (XRD) spectra of TiSiN thin films measured experimentally according to the embodiment. [Figure 32] Figure 32 is a graph showing the ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks as a function of the Si content measured from a TiSiN thin film according to the embodiment. [Figure 33] Figure 33 is a graph of the average nanocrystal grain size estimated as a function of Si content, calculated from the grazing incidence X-ray diffraction (XRD) spectra (Figures 31A-31I). [Figure 34] Figure 34 is a graph showing the hardness value as a function of Si content measured in a TiSiN thin film according to the embodiment. [Figure 35] Figure 35 is a graph showing the elastic modulus value as a function of Si content of a TiSiN thin film according to an embodiment. [Figure 36] Figure 36 shows low-resolution and high-resolution cross-sectional transmission electron microscope images obtained from a high-aspect-ratio structure lined with a TiSiN thin film according to an embodiment. [Figure 37A] Figure 37A is an atomic force microscope image of a deposited TiSiN thin film according to an embodiment. [Figure 37B] Figure 37B shows an atomic force microscope image of a TiN thin film as a comparative example. [Modes for carrying out the invention]

[0019] As described above, there is a need in the integrated circuit (IC) industry for conformal thin films with excellent physical barrier properties, such as TiN-based thin films and methods for forming such thin films. To address these and other needs, thin films comprising TiSiN and / or TiAlN, which may be at least partially amorphous, and a cyclic vapor deposition method, which may be atomic layer deposition (ALD), for forming such thin films are disclosed herein. These thin films exhibit the conformability of films deposited by ALD, while also possessing barrier properties that are superior to or equivalent to those of TiN films formed by existing physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods. Thin films comprising TiSiN and / or TiAlN can be used as conformal diffusion barriers. These thin films are formed by methods adapted to substrates with relatively large areas due to the presence of topography, which may be dielectric pores such as vias or trenches, which may have a high aspect ratio (e.g., >1), in which case the exposed surface area has an area density at least twice that of a flat substrate surface area. This method involves exposing a semiconductor substrate to one or more vapor deposition cycles at relatively high pressures (e.g., >1 Torr). These vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to either or both a silicon (Si) precursor or an aluminum (Al) precursor. Thin films containing TiSiN and / or TiAlN deposited by the methods disclosed herein are advantageous in that they have excellent diffusion barrier properties, as well as excellent conformability, step height coverage, and low surface roughness. These and other properties of the thin films can be advantageously tuned by controlling the morphology of the thin film at the nanoscale, thereby changing the degree of crystallinity and / or homogeneity by adjusting the process conditions.

[0020] As described herein, compounds referred to by their constituent elements without specific stoichiometric ratios are understood to encompass all possible non-zero concentrations of each element unless explicitly limited. For example, titanium nitride (TiN) is given by the general formula Ti xThis is understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be expressed as N, x>0, including TiN, Ti3N4, Ti4N3, Ti6N5, Ti2N, and TiN2, as well as other non-stoichiometric compositions of Ti and N. Similarly, silicon nitride (SiN) is expressed by the general formula Si y It is understood that this includes all possible stoichiometric and non-stoichiometric compositions of silicon nitride that can be expressed as N, y > 0, including Si3N4. Aluminum nitride (AlN) has the general formula Al y It is understood that this includes all possible stoichiometric and non-stoichiometric compositions of aluminum nitride that can be expressed as N, y > 0, and includes AlN. Titanium silicon nitride (TiSiN) has the general formula Ti x Si y It is understood that this encompasses all possible stoichiometric and non-stoichiometric compositions of titanium silicon nitride that can be expressed as N, x>0, and y>0. Titanium aluminum nitride (TiAlN) has the general formula Ti x Al y This is understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium aluminum nitride that can be expressed as N, x>0, and y>0.

[0021] As mentioned above, titanium nitride thin films play a crucial role in integrated circuit (IC) manufacturing. While the IC industry has used technologies such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) to deposit TiN films, there is a growing need for a film deposition method that can form TiN-based films, and ternary or quaternary alloys containing, for example, Ti, N, and one or more other metals, with high conformability without significantly impairing their electrical and / or physical properties.

[0022] In addition, while plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) may be effective for forming conformal films on surfaces with relatively low aspect ratios, these processes may not be effective for depositing films inside vias or cavities with high aspect ratios. Although not bound by any theory, one possible reason for this is that, under given circumstances, the plasma may not reach the deeper parts of high-aspect-ratio vias. Under such circumstances, different parts of the via may be exposed to different amounts of plasma, potentially leading to undesirable structural effects resulting from heterogeneous deposition. For example, a thicker film may be deposited near the via opening compared to deeper parts (often referred to as cupping or keyhole formation). For these reasons, thermal cycle vapor deposition, such as thermal ALD, may be more advantageous because these thermal processes do not depend on the plasma's ability to reach different parts of the surface being deposited.

[0023] However, while thermal ALD technology can be suitable for forming relatively conformal TiN-based thin films on topography, particularly on topography with relatively high aspect ratios (e.g., greater than 1:1), the inventors recognized that TiN-based thin films formed by thermal ALD may be inferior to those formed by PVD or CVD in some respects, such as film roughness and electrical resistivity. In this regard, the inventors found that some electrical and / or physical properties of ALD-grown TiN-based films may be adversely affected by the growth mode. In particular, the inventors found that while it is sometimes desirable to grow TiN-based films in a two-dimensional layer-by-layer growth mode in ALD, such a layer-by-layer growth mode may not be easily achieved under certain circumstances. The inventors further found that growing TiN-based thin films by ALD in a layer-by-layer growth mode presents specific challenges in IC manufacturing when forming TiN-based thin films on non-metallic surfaces, particularly on insulating surfaces such as oxide and nitride surfaces or doped and undoped silicon surfaces. Not bound by any theory, the inventors recognized that the extent to which TiN-based thin films can grow in a layer-by-layer growth mode may depend on the initial growth mode, which is dependent on the surface type and crystallinity, as disclosed herein with reference to Figures 1A-1D.

[0024] Figure 1A schematically illustrates the nucleation of the TiN-based layer, and Figures 1B-1D show different growth modes of the TiN-based layer on different surfaces. Referring to Figure 1A, once precursor molecules 104 reach the substrate 100, they are physically adsorbed onto the substrate. Some of the adsorbed molecules 104 can diffuse along the surface of the substrate 100 until they reach energetically favorable positions for chemiadsorption. Surface diffusion is governed, in particular, by the substrate temperature, the substrate material, and the kinetic energy of the adsorbed molecules. When the size of the nuclei formed by chemiadsorbed molecules exceeds a predetermined size (sometimes called the "critical size") determined by the trade-off between volume free energy and surface energy, the nuclei become energetically stable and can begin to grow in size. The layer 108 of stable nuclei thus formed continues to grow by incorporating further precursor molecules 104. Subsequent film growth can be classified into different growth modes, as schematically shown in Figures 1B-1D.

[0025] Figure 1B schematically illustrates the three-dimensional island growth mode, sometimes referred to as the Volmer-Weber growth mode, where layer 112 consisting of three-dimensional islands is formed. While not constrained by any theory, the island growth mode can be dominant when the net surface free energy associated with the three-dimensional islands is positive. This indicates that the deposited atoms are more strongly bonded to one another than to the substrate. For example, when a metallic TiN-based layer is deposited on the surface of a given semiconductor and / or insulating material, the energy theory of ALD growth of the TiN-based layer will be understood to support the island growth mode.

[0026] Figure 1C shows a layer-by-layer growth mode, sometimes referred to as the Frank-van der Merwe growth mode, which forms a relatively smooth two-dimensional layer 116. While not constrained by any theory, the layer-by-layer growth mode may be dominant when the deposited atoms bond more strongly to the substrate than to each other, thereby making the stable two-dimensional layer 116 energetically preferable. The layer-by-layer growth mode can persist when the interlayer bonding energy decreases continuously from the first monolayer of the TiN-based layer down to the bulk crystal value.

[0027] Figures 1B and 1C show two different possible growth modes for TiN-based thin films, but under given conditions, an intermediate growth mode between the layer-by-layer growth mode and the three-dimensional growth mode is possible. Figure 1D shows an example of an intermediate growth mode known as the Stranski-Krastanov (SK) growth mode. Although not bound by any theory, the SK growth mode can occur in thin film growth that begins with the layer-by-layer growth mode. If the layer-by-layer growth mode becomes undesirable after the formation of one or more monolayers, the island growth mode begins and becomes dominant over the layer-by-layer growth mode, resulting in a thin film structure 120 in which three-dimensional islands are formed on top of the two-dimensional initial layers. The SK growth mode can occur as a strain relaxation mechanism (strain-induced roughening).

[0028] In addition to the interaction between the deposited material and the substrate, other factors such as substrate temperature, pressure, and deposition rate can significantly influence the nucleation and initial growth processes. This affects the final nanostructure or microstructure of the resulting thin film. For example, deposition at relatively high substrate temperatures and / or slow deposition rates may promote the growth of relatively large grains, while relatively low substrate temperatures and fast deposition rates may favor the growth of smaller grains.

[0029] In IC manufacturing, when TiN-based thin films are grown by ALD on various intended surfaces, dielectric surfaces, and semiconductor surfaces, it has been discovered that the ALD growth can begin in a three-dimensional island growth mode or a SK growth mode. For example, under given conditions, the ALD growth of TiN-based thin films on substrate surfaces containing doped and undoped Si, SiO2, Si3N4, and other high-K or low-K materials can proceed in either an island growth mode or a SK growth mode. The inventors have found that, in part, due to either the island growth mode or the SK growth mode as the initial growth mode, the subsequent growth of the TiN-based layer by ALD often results in undesirable film morphology in various applications of extremely thin conformal diffusion barriers for high aspect ratio structures, as shown in Figure 2.

[0030] Figure 2 is a cross-sectional transmission electron microscope image of a TiN layer grown by thermal ALD on a topography including an insulating (Si3N4) surface. After initial film growth in either the 3D island growth or SK growth mode, ALD growth of TiN is often characterized by the competitive growth of adjacent crystals with different orientations. As a result, under given conditions, V-shaped grains are formed near the nucleation layer, leading to columnar morphology at larger film thicknesses. As shown in Figure 2, the resulting film morphology includes cross-shaped prism heads that result in high surface roughness and columnar boundaries with lower density than the grains. It can be understood that columnar boundaries may have extremely poor diffusion barrier properties compared to the grains themselves and may function as the least-resistance pathway for transporting undesirable contaminants through the TiN layer. Furthermore, due to the columnar morphology, relatively thick TiN layers may need to be deposited to observe sufficient diffusion barrier properties. Therefore, the effective TiN barrier for acceptable overall contact or line conductivity may become too thick, leaving little room for low-resistivity filler materials such as W or Cu.

[0031] The inventors have found that when thin films containing TiSiN and / or TiAlN that are at least partially amorphous are formed on a nonmetallic surface by a thermal cycling vapor deposition process such as thermal ALD, the three-dimensional mode or SK growth mode is substantially suppressed, and the layer-by-layer growth mode can be promoted. Among other reasons, this is thought to be because, when a TiN-based thin film has Si or Al added as an alloying element and / or an amorphous phase present therein, the nuclei can wet the nonmetallic surface at a relatively low contact angle. The resulting thin film covers a relatively large area of ​​the nonmetallic surface, and island formation is reduced. This is because, for example, the growth of the thin film tends to proceed more favorably in a layer-by-layer growth mode on the substrate surface. As mentioned above, TiN-based thin films usually prefer the three-dimensional island mode or SK growth mode on the substrate in ALD. Therefore, unlike TiN layers grown directly by ALD on some nonmetallic surfaces, where columnar growth tends to be dominant as described above, thin films containing at least partially amorphous TiSiN and / or TiAlN formed on nonmetallic surfaces according to the embodiment tend to exhibit a predominant layer-by-layer growth mode, resulting in higher conformability and surface smoothness. Furthermore, the presence of the amorphous phase reduces grain boundaries, suppressing fast diffusion pathways for some elements such as Cu and W. The presence of the amorphous phase, higher conformability, and / or surface smoothness allow for a reduction in the thickness of the diffusion barrier. When formed for lining high aspect ratio vias or trenches, thinner thicknesses allow for relatively larger pores for subsequent processes such as metal filling of vias or trenches for contact via formation and / or reduction of contact resistance.

[0032] Figure 3 shows a schematic cross-sectional view of a semiconductor structure 300 having a thin film 320 containing TiSiN and / or TiAlN, which can be formed using the methods of the various embodiments disclosed herein. The semiconductor thin film structure 300 has a substrate 310, which is, for example, a semiconductor substrate. The substrate 310 includes a non-metallic surface, which is, for example, a dielectric and / or semiconductor surface, and a thin film 320 containing at least partially amorphous TiSiN and / or TiAlN is formed thereon by the methods disclosed herein. The thin film 320 has excellent conformability, step coverage, and low surface roughness, while having excellent diffusion barrier properties. These and other properties of the thin film can be advantageously tuned by controlling the degree of crystallinity and / or homogeneity of the thin film at the nanoscale, and by adjusting the various process conditions disclosed herein.

[0033] Thin films containing TiSiN and / or TiAlN are shown in Figure 3 as being formed on a flat substrate for clarity, but are not limited thereto in the embodiments. Thin films containing TiSiN and / or TiAlN have particular advantages when formed on substrates with topography, such as substrates having high aspect ratio (e.g., >1) vias and trenches and / or relatively high density characteristic shapes, thereby providing a relatively large surface area exposed to the precursor during cyclic vapor deposition, such as ALD (e.g., more than twice the surface area of ​​a flat substrate).

[0034] One measure of conformality in the concept of high aspect ratio structures is referred herein and industrially to as step coverage. High aspect ratio structures can be, for example, vias, holes, trenches, cavities, or similar structures. As an illustrated example, Figure 4 schematically shows a semiconductor structure 400 formed inside an example high aspect ratio structure 416, thereby illustrating several exemplary metrics for defining and / or measuring the conformality of a thin film formed on a high aspect ratio structure. The illustrated high aspect ratio structure 416 has an inner surface lined with a thin film 412, which is a thin film containing TiSiN and / or TiAlN having different thicknesses in different parts, for example. As described above, a high aspect ratio structure has an aspect ratio, for example, the ratio of the depth or height (H) in the pore region of the high aspect ratio structure 416 divided by the width (W), which is greater than 1. In the illustrated example, the high aspect ratio structure 416 is a via formed through a dielectric layer 408, which is, for example, an interlayer insulating film (ILD) layer formed on a semiconductor material 404. In the illustrated example, the bottom surface of the high aspect ratio structure 416 exposes the semiconductor substrate 404 located below. The thin film 412 can coat different surfaces of the high aspect ratio structure 416 with different thicknesses. As described above, step coverage can be defined as the ratio between the thickness of the thin film in the lower or bottom region of the high aspect ratio structure and the thickness of the thin film in the upper or top region of the high aspect ratio structure. The upper or top region can be a region of the high aspect ratio structure with a relatively shallow depth, for example, 0-10% or 0-25% from the top surface of the hole. The lower or bottom region can be a region of the high aspect ratio structure with a relatively deep depth, for example, 90-100% or 75-100% from the top surface of the hole. In some high aspect ratio structures, step coverage can be defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thin film 412C formed on the top or top sidewall surface of the high aspect ratio structure. However, it will be understood that some high aspect ratio structures may not have a clearly defined bottom surface or a bottom surface with a small radius of curvature.In such a structure, step coverage can be more consistently defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thickness of the thin film 412C formed on the top or top sidewall surface in a high aspect ratio structure.

[0035] [Cycle vapor deposition of thin films containing TiSiN and / or TiAlN] Figure 5A shows a flow diagram of a method 500 for forming a thin film containing TiSiN and / or TiAlN according to an embodiment. Method 500 includes providing a substrate 510. The substrate can be a flat semiconductor substrate, or, as described above, a semiconductor substrate having surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor phase deposition cycles to the surface area of ​​the unpatterned semiconductor substrate is greater than 2. The surface topography that produces a relatively large surface area can be a plurality of holes such as trenches and vias formed on the substrate, as described above. The holes have dielectric sidewall surfaces and can have an aspect ratio greater than 5.

[0036] Method 500 further comprises forming a thin film that can function as a diffusion barrier, comprising titanium silicon nitride (TiSiN) or titanium aluminum nitride (TiAlN). The thin film is formed by exposing a semiconductor substrate to multiple vapor deposition cycles under a pressure in a reaction chamber greater than 1 Torre. In this case, the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

[0037] As described above and throughout the specification, it will be understood that semiconductor substrates on which a thin film, for example a diffusion barrier layer containing TiSiN and / or TiAlN is formed can be implemented as a variety of substrates. These include, but are not limited to, doped semiconductor substrates, which include alloys formed from group IV elemental materials (e.g., Si, Ge, C, or Sn) or group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from group III-V materials; and group II-VI semiconductor materials (e.g., CdSe, CdS, ZnSe, etc.) or alloys formed from group II-VI materials.

[0038] According to a given embodiment, the substrate can be implemented as having a semiconductor on an insulator, such as a silicon-on-insulator (SOI) substrate. An SOI substrate typically includes a silicon-insulator-silicon structure, in which the various structures described above are insulated from the support substrate using an insulating layer such as an embedded SiO2 layer (BOX). Furthermore, it will be understood that the various structures described above can be formed at least partially on an epitaxial layer formed in or near the surface region.

[0039] Referring further to Figure 5A, it will be understood that Method 500 may be performed on a substrate processed by a front-end line and may include a variety of devices, such as transistors. Furthermore, the semiconductor substrate may include one or more diverse structures, such as diffusion regions, insulating regions, electrodes, and metallization structures such as contacts and metal lines, which are pre-formed thereon, and Method 500 can be performed thereon. Thus, a diffusion barrier containing TiSiN and / or TiAlN can be formed on a variety of topographic structures, including vias, cavities, holes, or trenches. Surfaces on which a diffusion barrier containing TiSiN and / or TiAlN can be formed according to the embodiment include, for example, a metallic surface which is the surface of a metallization structure; a semiconductor surface which is, for example, a doped or undoped Si surface; and / or a dielectric surface which is an interlayer dielectric (ILD) surface, a mask or hard mask surface, or a gate dielectric surface.

[0040] According to a given embodiment, when formed as a diffusion barrier, a thin film containing TiSiN and / or TiAlN can be interposed between a dielectric layer, such as an interlayer insulating film (e.g., 408 in Figure 4), and a metallization structure formed by filling vias or trenches (e.g., 416 in Figure 4), and / or between a semiconductor substrate 404 and a metallization structure formed by filling vias or trenches. This allows it to function as a diffusion barrier between them, among other functions such as electrical contacts. In these embodiments, the dielectric material can be any dielectric material used in integrated circuit manufacturing, such as silicon oxide, silicon nitride, high dielectric constant dielectrics, or low dielectric constant dielectrics. The metallization structure may include, for example, metal lines, contact structures, or other conductive structures made of metal or metallic material for electrically connecting the underlying semiconductor material 404, which is a diffusion region, to other parts of the integrated circuit device being manufactured. The metallization structure can be formed from any suitable metal or metallic material, including, for example, metals containing Al, Cu, Ni, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides containing TiN, TaN, WN, and TaCN; conductive metal silide containing tantalum silide, tungsten silide, nickel silide, cobalt silide, and titanium silide; and conductive metal oxides containing RuO2, etc.

[0041] Referring further to Figure 5A, for example, a method 500 for forming a thin film that is a diffusion barrier layer further includes forming a thin film containing TiSiN and / or TiAlN by exposing a semiconductor substrate in a reaction chamber to multiple vapor deposition cycles, which can be atomic layer deposition (ALD) cycles. These vapor deposition cycles include one or more exposures to a titanium (Ti) precursor, one or more exposures to a nitrogen (N) precursor, and one or more exposures to a silicon (Si) precursor or an aluminum (Al) precursor. At least one of the vapor deposition cycles can be carried out under a pressure in the reaction chamber that is about 1 Torrell.

[0042] As described above and throughout the specification, the reaction chamber means any reaction chamber including a single-wafer processing reaction chamber or a batch-wafer processing reaction chamber appropriately configured for cyclic vapor deposition, which may be, for example, a thermal cyclic vapor deposition or atomic layer deposition (ALD). In a thermal cyclic vapor deposition or ALD reaction chamber, the substrate can be placed on a suitable base such as a susceptor or carrier boat. The substrate can be heated directly by heat conduction from a heated susceptor, or indirectly by radiation from an illumination source such as a lamp or by convection from a heated chamber wall.

[0043] Generally, in cyclic vapor deposition (ALD) processes, reactants, or precursors, such as oxidation and reduction reactants, are alternately introduced into a reaction chamber containing a substrate. The introduction of one or more reactants or precursors can be performed sequentially, alternating with purging and / or pumping steps to remove excess reactants or precursors from the reaction chamber. The reactants can be introduced into the reaction chamber under predetermined conditions for a suitable period of time, such that the surface on which the diffusion barrier is deposited is exposed to the reactants. This allows the substrate surface to be saturated, at least partially, with the precursors or reactants and / or the reaction products of the reactants. Excess or residual precursors or reactants can then be purged and / or pumped out of the reaction chamber. The pumping step can be performed by a suitable vacuum pumping step, and the purging step can be performed by introducing an unreactive or inert gas, such as nitrogen or a noble gas, into the reaction chamber. Other techniques also exist to prevent the mixing of reactants that react with each other in the gas phase.

[0044] Figure 5B is a flow diagram illustrating a method for forming a diffusion barrier containing TiSiN and / or TiAlN according to an embodiment, and Figures 5C and 5D are block diagrams. Figure 5C shows a deposition phase including exposure to a precursor and a cycle including exposure to the deposition phase. Figure 5D shows a sequence of cycle deposition phases as part of multiple cycles. Referring to Figures 5B-5D, in various embodiments, exposing a semiconductor substrate to one or more vapor deposition cycles which may constitute an ALD cycle 520 (Figure 5A) includes exposing the substrate to one or more first vapor deposition phases ("first deposition phases") 525. In this case, at least one first deposition phase includes exposure to a Ti precursor and exposure to an N precursor. Exposing a semiconductor substrate to one or more vapor deposition cycles that may constitute an ALD cycle 520 (Figure 5A) further includes exposing the substrate to one or more second vapor deposition phases ("second deposition phases") 530, in which case at least one second deposition phase includes exposure to a Si and / or Al precursor, or a combination of exposure to a Si and / or Al precursor and further exposure to an N precursor. One or more first deposition phases and one or more second deposition phases can be combined to form a single cycle, which can be repeated sequentially multiple times or for multiple cycles. Different cycles may have the same or different numbers of first and second deposition phases. By combining exposure of the substrate to one or more first deposition phases 525 and exposure of the substrate to one or more second deposition phases 530, a diffusion barrier layer containing a layer or region of TiSiN and / or TiAlN is obtained. Each of exposure of the substrate to one or more first deposition phases 525 and exposure of the substrate to one or more second deposition phases 530 may sequentially include exposing individual precursors one or more times, such as in a pulsed manner as described later.

[0045] Referring further to Figures 5B-5D, in various embodiments, exposing the substrate to each of one or more first deposition phases 525 may include one or more exposures of the substrate to a Ti precursor and one or more exposures to an N precursor. Each exposure to the Ti precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Ti precursor. This allows the surface to be almost entirely or partially saturated with the Ti precursor. After the substrate has been exposed to the Ti precursor, any excess or residual Ti precursor, or any reaction products that did not remain on the substrate surface due to physicoadsorption or chemiadsorption, may be removed from the substrate surface by pumping or purging the process chamber. Similarly, each exposure to the N precursor is carried out so that the surface of the substrate on which the diffusion barrier is deposited is exposed to the N precursor. This allows the surface to be almost entirely or partially saturated with the N precursor. After the substrate is exposed to the N precursor, any excess or residual N precursor, or any reaction products that did not remain on the substrate surface due to physicoadsorption or chemiadsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more first deposition phases, each including one or more exposures to a Ti precursor and one or more exposures to an N precursor, one or more monolayers or regions substantially formed from deposited TiN can be locally formed.

[0046] In some embodiments, exposure to the Ti precursor in a given first deposition phase can be performed multiple times consecutively. Similarly, exposure to the N precursor in a given first deposition phase can be performed multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to the Ti and / or N precursors can result in a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption or reaction of individual precursors.

[0047] Referring further to Figures 5B-5D, in various embodiments, exposing the substrate to one or more second deposition phases 530 includes one or more exposures of the substrate to a Si and / or Al precursor. Each exposure to the Si and / or Al precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Si and / or Al precursor. This allows the surface to be almost entirely or partially saturated with the Si and / or Al precursor. After the substrate is exposed to the Si and / or Al precursor, any excess or residual Si and / or Al precursor, or any reaction products that did not remain on the substrate surface by physicoadsorption or chemiadsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more second deposition phases, each including one or more exposures to the Si and / or Al precursor, one or more monolayers or regions substantially formed from the deposited Si or Al can be locally formed.

[0048] In some embodiments, exposure to the Si and / or Al precursor in a given second deposition phase can be carried out multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to the Si and / or Al precursor can result in a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption or reaction of individual precursors.

[0049] Referring further to Figures 5B-5D, in some embodiments, exposing the substrate to each of one or more second deposition phases 530 includes one or more exposures of the substrate to a Si and / or Al precursor, and one or more further exposures of the substrate to an N precursor. The N precursor may be the same as or different from the N precursor of the first deposition phase. Each exposure to the Si and / or Al precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Si and / or Al precursor. This allows the surface to be saturated with the Si and / or Al precursor almost entirely or partially. After the substrate has been exposed to the Si and / or Al precursor, any excess or residual Si and / or Al precursor, or any reaction products that did not remain on the substrate surface by physicoadsorption or chemiadsorption, may be removed from the substrate surface by pumping or purging the process chamber. Each exposure to the N precursor is carried out so that the surface of the substrate on which the diffusion barrier is deposited is exposed to the N precursor. This allows the surface to be almost entirely or partially saturated with the N precursor. After the substrate is exposed to the N precursor, any excess or residual N precursor, or any reaction products that did not remain on the substrate surface due to physicoadsorption or chemiadsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more second deposition phases, each including one or more exposures to a Si precursor and one or more exposures to an N precursor, one or more monolayers or regions substantially formed from deposited SiN or AlN can be locally formed.

[0050] In some embodiments, exposure to the Si precursor in a given second deposition phase can be carried out multiple times consecutively. Similarly, further exposure to the N precursor can be carried out multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to the Si and / or Al and / or N precursor, as described above, can lead to a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption of individual precursors.

[0051] In various embodiments, it will be understood that the number of cycles, each including one or both of the first and second deposition phases, the frequency and number of repetitions of the first deposition phase and the second deposition phase, the frequency and number of repetitions of substrate exposure to the Ti and N precursors during the first deposition phase, and the frequency and number of repetitions of substrate exposure to the Si and / or Al precursor or Si and / or Al precursor and N precursor during the second deposition phase can be modified based on various considerations, including the sensitivity of the precursors to steric hindrance effects, in order to obtain the desired thickness, stoichiometry, and other properties of the resulting TiSiN and / or TiAlN diffusion barrier layer.

[0052] Referring further to Figures 5B-5D, depending on the required conditions or film properties, it may be advantageous to initiate the deposition of a diffusion barrier containing TiSiN and / or TiAlN by either or both exposure of the substrate to the first deposition phase or the second deposition phase. For example, the inventors have found that first exposing the substrate to one or more second deposition phases (Si and / or Al precursor or N precursor) 530, followed by exposure to the first deposition phase (Ti precursor or N precursor) 525, may be particularly advantageous in promoting the layer-by-layer growth mode of the diffusion barrier. This improves conformability and reduces surface roughness, for example, when the substrate surface is a non-metallic surface such as an insulating surface like the sidewalls of trenches or vias formed in the interlayer insulating film (ILD) layer, or a semiconductor surface such as a Si diffusion region.

[0053] However, the embodiments are not limited in this way, and in other embodiments, first exposing the substrate to one or more first deposition phases (Ti precursor or N precursor) 525, and then exposing the substrate to one or more second deposition phases (Si and / or Al precursor or N precursor) 530, may be more advantageous, for example, when the substrate surface includes a metallic surface (e.g., metallization of W, Al, or Cu metal), in order to maintain good conformability and surface roughness while reducing contact resistance.

[0054] Referring to Figure 5D, under certain conditions, depending on the sequence described above, the sequence of the first and second deposition phases can result in a thin film having regions rich in TiN and Si and / or Al or SiN and / or AlN to a detectable degree. However, under other conditions, despite different sequences of exposure to the first and second deposition phases, the resulting thin film may be substantially homogeneous TiSiN and / or TiAlN, as will be discussed later.

[0055] In various embodiments, non-limiting examples of Ti precursors for forming thin films that are diffusion barrier layers or regions include titanium tetrachloride (TiCl4), tetrakis(dimethylamino)titanium (TDFMAT), or tetrakis(diethylamino)titanium (TDEAT).

[0056] In various embodiments, non-limiting examples of N precursors for forming thin films, such as diffusion barrier layers or regions, include ammonia (NH3), hydrazine (N2H4), or monomethylhydrazine (CH3(NH)NH2, "MMH"). As described above, different N precursors can be used in the first and second deposition phases, and completely different precursors can be used in different cycles of the same phase.

[0057] In various embodiments, non-limiting examples of the inert gas for purging include nitrogen (N2) or noble gases such as Ar.

[0058] In some embodiments, the Si precursor for forming the diffusion barrier layer can be a hydride precursor. Examples of hydride precursors include silane (SiH4) and disilane (Si2H6). In some other embodiments, the Si precursor for forming the diffusion barrier can be a chlorine-containing precursor such as silicon chloride or chlorosilane. Examples include silicon tetrachloride (SiCl4), monochlorosilane (SiH3Cl, "MCS"), dichlorosilane (SiH2Cl2, "DCS"), trichlorosilane (SiHCl3), hexachlorodisilane (Si2Cl6, "HCDS"), and octachlorotrisilane (Si3Cl8, "OCTS"). The inventors have found that when a higher level of surface saturation by the precursor is desired, a TiSiN-containing diffusion barrier layer can be desirablely formed using silicon and chlorine-containing Si precursors because they exhibit less steric hindrance compared to organosilicon precursors under a wide range of conditions.

[0059] In some embodiments, the Al precursor for forming the diffusion barrier layer can be an organometallic precursor. Examples of organometallic precursors include trimethylaluminum ("TMA"), triisobutylaluminum, and tris(dimethylamide)aluminum. In some other embodiments, the Al precursor for forming the diffusion barrier layer can be a chlorine-containing Al precursor, such as AlCl3.

[0060] While not bound by any theory, the inventors found that when these Si and Al precursors are introduced as the first non-nitrogen precursors, they may be particularly advantageous compared to other Si or Al precursors for promoting a layer-by-layer growth mode of the TiSiN or TiAlN layer. This layer-by-layer growth mode is achieved by improving the wettability of the substrate surface by the nuclei of the TiSiN or TiAlN layer in the early stages of growth, which can be characterized by a small contact angle between the nuclei and the substrate surface. As a result of the layer-by-layer growth mode, improved conformability and reduced surface roughness can be achieved, which may be particularly advantageous for forming diffusion barriers through deposition at small sizes and high aspect ratios. Furthermore, while not bound by any theory, chlorine-containing Si and / or Al precursors may allow for more precise control of the composition in the growth direction by suppressing or self-limiting adsorption.

[0061] For example, to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, thin films containing TiSiN and / or TiAlN may, according to embodiments, have a thickness not exceeding about 25 nm, 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, 2 nm, or 1 nm, or a thickness within a range defined by any of these values ​​or other values. These thicknesses may be substantially smaller than those of TiN barriers having similar effectiveness as a diffusion barrier.

[0062] For example, to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, thin films comprising TiSiN and / or TiAlN can be formed, according to embodiments, at substrate temperatures of 250°C to 300°C, 300°C to 400°C, 350°C to 400°C, 400°C to 450°C, 450°C to 500°C, 500°C to 550°C, 550°C to 600°C, 600°C to 650°C, or within a range defined by any of these values, for example, at a temperature of about 400°C.

[0063] For example, in order to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, the exposure time or pulse duration of various precursors is, according to embodiments, a duration within a range defined by approximately 0.1 to 5 seconds, 5 to 10 seconds, 10 to 20 seconds, 20 to 30 seconds, 30 to 40 seconds, 40 to 50 seconds, 50 to 60 seconds, or any of these values ​​or greater.

[0064] In summary, the formation of a thin film, such as a diffusion barrier layer, containing TiSiN and / or TiAlN, involves exposing the substrate to one or more cycles, each cycle comprising one or more first deposition phases and / or one or more second deposition phases. Each of the first deposition phases sequentially comprises alternating exposures to one or more Ti precursors and one or more N precursors. In some embodiments, each of the second deposition phases sequentially comprises alternating exposures to one or more Si precursors and / or Al precursors and one or more N precursors. The resulting diffusion barrier layer comprises layers or regions of TiSiN or layers or regions of TiAlN. In various embodiments, the frequency and number of exposures of the substrate to each of the Ti precursors, N precursors, and Si and / or Al precursors, as well as the frequency and number of exposures of the substrate to each of the cycles, first deposition phases, and second deposition phases, and the order of exposures, can be adjusted to obtain the desired stoichiometry, thickness, and crystallinity, as described herein.

[0065] [Deposition on substrates having a large surface area and / or a high aspect ratio structure] The inventors have found that when a substrate has a relatively large surface area resulting from a relatively large area density, for example, a high aspect ratio structure, coating the exposed surface with a thin film using an ALD process recipe developed based on the characterization of thin films formed on flat or unpatterned substrates or substrates with a relatively small surface area or low area density of a high aspect ratio structure can result in thin films with different properties in different parts of the exposed surface. For example, the conformality and step coverage mentioned above can be significantly degraded in high aspect ratio structures of substrates with relatively large area densities. Other properties that can also differ in different parts of the exposed surface include film stoichiometry, surface roughness, electrical resistivity, and film density. While not bound by any theory, one possible reason for the low homogeneity of properties is that the exposed surface area of ​​the substrate is significantly increased compared to a flat substrate. Because the exposed surface area is increased, different parts of the exposed surface may receive fluxes of different sizes of precursors, and thus different amounts of precursors may be adsorbed on different parts of the exposed surface. In a simplified example, a 330mm semiconductor substrate has hundreds of dies formed on it, each 1 x 10¹⁶ 10 If the transistors described above are present, and each transistor has one or more vias with a diameter of 10-100 nm and an aspect ratio of 1-100, the surface area exposed to the precursor during thin film deposition may exceed 10, 100, 1000 times, or more the surface area of ​​the corresponding unpatterned substrate. Furthermore, local deposition conditions may differ in different parts of the exposed surface. For example, the local pressure inside a deep trench or via may differ, for example, being lower than in the area outside that deep trench or via. In addition, under vacuum conditions, gas molecules collide more frequently with the sidewalls of the trench or via, so the upper part of a deep trench or via may adsorb more precursor molecules due to exposure to a larger flux.

[0066] In the various embodiments described herein, the inventors have found that the deposition methods disclosed herein are particularly advantageous in forming thin films containing TiSiN and / or TiAlN that exhibit higher homogeneity with respect to various physical properties, including conformality, step coverage, film stoichiometry, surface roughness, electrical resistivity, and film density, across different portions of the exposed surface. Accordingly, thin films containing TiSiN and / or TiAlN formed by the deposition methods disclosed herein exhibit higher homogeneity with respect to one or more of these physical properties, both at a local (e.g., inside a trench or via) level and at an overall (e.g., within a wafer) level. Therefore, the deposition method according to the embodiment is particularly advantageous for forming a thin film containing TiSiN and / or TiAlN on a substrate having surface topography, thereby having a ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor phase deposition cycles to the corresponding surface area of ​​the unpatterned semiconductor substrate that exceeds 2, 5, 10, 20, 50, 100, 200, 500, 1000, or within a range defined by any one of these values ​​or a value greater than or equal to these values.

[0067] Alternatively or in addition thereto, the deposition method according to the embodiment is particularly advantageous in forming a thin film on a substrate having a high aspect ratio structure having an aperture width in the range defined by 1 micron, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, or any of these values ​​or less, an aspect ratio exceeding 5, 10, 20, 50, 100, 200, or any of these values, and an area density such that the surface area is larger than that of the flat substrate described above. A substrate having such topography can be conformally coated with a thin film containing TiSiN and / or TiAlN according to the embodiment. In this case, the step coverage defined above is greater than 50%, 60%, 70%, 80%, 90%, 95%, or within the range defined by any of these values ​​or greater. As described above, the inventors have found that process conditions for conformally coating substrates with a relatively large area density and a high aspect ratio structure can be optimized in embodiments to achieve these results. The inventors have found that these results can be achieved, in particular, by controlling the reaction chamber pressure or precursor partial pressure during substrate exposure, the deposition rate, the temperature or partial pressure of the precursor introduced into the reaction chamber, the precursor flow rate, and the exposure time.

[0068] The inventors have found that, according to the embodiments, when coating substrates with a relatively high area density and a high aspect ratio structure, relatively high total or partial pressures can lead to improvements in conformality and step coverage. While not bound by any theory, such improvements may, among other things, relate to reducing the effect of locally small precursor partial pressures within high aspect ratio vias or trenches. Accordingly, according to the embodiment, referring again to Figures 5B and 5C, during the exposure of the substrate to one or more first deposition phases (Ti precursor and / or N precursor) 525 and / or during the exposure of the substrate to one or more second deposition phases (Si and / or Al precursor and / or N precursor) 530, the total pressure or partial pressure of any individual precursor can be within the range defined by 1.0 to 3.0 Torr, 3.0 to 5.0 Torr, 5.0 to 7.0 Torr, 7.0 to 9.0 Torr, 9.0 to 11.0 Torr, 11.0 to 13.0 Torr, 13.0 to 15.0 Torr, or any of these values. In each exposure to the Ti precursor, N precursor, and / or Si and / Al precursor, the individual precursor can account for a proportion within the range defined by 1 to 2%, 2 to 5%, 5 to 10%, 10 to 20%, 20 to 50%, 50 to 100%, or any of these values. The inventors found that, under given conditions, step coverage may begin to deteriorate, particularly when the total pressure or partial pressure is other than these values.

[0069] According to the embodiment, the total pressure or partial pressure can be controlled to a relatively high value during the exposure of the substrate to one or more first deposition phases (Ti precursor and / or N precursor) 525 and / or during the exposure of the substrate to one or more second deposition phases (Si and / or Al precursor and / or N precursor) 530, in relation to the flow rates of the individual precursors and inert gases and the pump exhaust capacity of the reaction chamber, thereby making the deposition rate per first and / or second deposition phase relatively high within the range defined by 0.20~0.30 Å / deposition phase, 0.30~0.40 Å / deposition phase, 0.40~0.50 Å / deposition phase, 0.50~0.60 Å / deposition phase, 0.60~0.70 Å / deposition phase, 0.70~0.80 Å / deposition phase, or any of these values.

[0070] In part, the inventors have found that, in order to enable a relatively high throughput while supplying a relatively large amount of precursor to the reaction chamber for deposition at a relatively high total pressure or partial pressure, the flow rate of the precursor into the reaction chamber should be much higher than the flow rate used in the process conditions for forming a thin film on a flat substrate or a substrate having a low (e.g., <1) aspect ratio structure. The high flow rate can be achieved by increasing one or both of the temperature or pressure of the precursor before introduction into the reaction chamber. For example, for a precursor in liquid form under manufacturing conditions, the precursor bottle can be heated to a temperature higher than room temperature, such as 30 - 60°C, 60 - 80°C, 80 - 100°C, 100 - 120°C, 120 - 150°C, or within a range defined by any of these values, in order to increase the vapor generation rate. In part, these bottle temperatures can be determined to be lower or higher than these ranges respectively based on the vapor pressure of the precursor and the decomposition temperature of the precursor. As an example, TiCl4 is heated to about 60 - 80°C. On the other hand, for a precursor in gas form under manufacturing conditions, a high flow rate can be achieved by increasing the gas line pressure to a much higher value compared to the gas line pressure used when forming a thin film on a relatively small area or flat substrate and / or a substrate having a low (e.g., <1) aspect ratio structure. It will be understood that the relatively high flow rates at which the various advantages described herein are obtained can depend, inter alia, on the pump exhaust speed, the exposure time, and the volume of the reactor. In order to achieve a flow rate suitable for depositing a thin film on a substrate having a large surface area and / or a high aspect ratio structure, the flow rate of each of the Ti, N, Si, and Al precursors can be, for example, 100 - 1000 standard cm 3 / min (sccm), 1000 - 2000 sccm, 2000 - 5000 sccm, 5000 - 10000 sccm, 10000 - 15000 sccm, 15000 - 20000 sccm, or within a range defined by any of these values or a value greater than these, and in particular, the temperature and / or pressure of the precursor can be adjusted. It will be understood that the appropriate flow rate can depend, inter alia, on the volume of the reactor, and that some of these flow rates are suitable for a single wafer reactor having a volume of about 1 - 2 liters.

[0071] Figures 6A–6C show experimental transmission electron microscope (TEM) images of conformal TiSiN films lining high-aspect-ratio vias formed by the deposition technique described herein. The high-aspect-ratio vias have a deposited silicon oxide surface. Figures 6A, 6B, and 6C are TEM images taken of the top, middle, and bottom of TiSiN films formed on vias with an aspect ratio of approximately 40, respectively. In each of Figures 6A–6C, the left image is a bright-field image of each portion of the high-aspect-ratio via, and the right image shows the limited-field diffraction (SAD) pattern obtained from the thin film formed on each portion of the high-aspect-ratio via using an electron beam with a spot diameter approximately equal to the thickness of the TiSiN thin film. Unlike the polycrystalline TiN with a rough surface due to columnar growth shown in Figure 2, the bright-field TEM images in Figures 6A–6C show that the deposited TiSiN is far smoother and more conformal. The inventors found that these and other improvements can be attributed in part to the presence of at least several amorphous phases of TiSiN. These may be present together with several nanocrystalline layers of TiSiN, as indicated by the SAD pattern. The TiSiN thin film is substantially amorphous and substantially conformal throughout the entire via depth and has good step height coverage (~60%).

[0072] [Control of thin-film morphology at the nanoscale] Advantageously, the diverse embodiments of the cyclic vapor deposition process disclosed herein, which can be an ALD process, enable the nanoscale control and improvement of the film morphology and structure of thin films containing TiSiN and / or TiAlN, due to their ability to control precursor adsorption at the sub-monolayer level using the diverse process parameters described herein. The controlled morphology and structure include the degree of crystallinity, homogeneity, and surface roughness. In particular, the inventors have found that the degree of crystallinity and / or homogeneity at the nanoscale can be advantageously controlled in thin films containing TiSiN and / or TiAlN by controlling the diverse parameters of the exposure cycle as described herein.

[0073] In various embodiments, when forming a thin film, such as a diffusion barrier layer containing TiSiN and / or TiAlN, the thin film morphology can be controlled using a specific ratio of the number of exposures of the substrate to a first deposition phase (including a combination of exposure to Ti and N precursors) and the number of exposures of the substrate to a second deposition phase (including exposure to Si and / or Al precursors or a combination of exposure to Si and / or Al precursors and N precursors), in addition to the various parameters described above. The ratio can be approximately 1:30-1:15, 1:15-1:6, 1:6-1:3, 1:3-1:2, 1:2-2:3, 2:3-5:6, 5:6-1:1, 1:1-6:5, 6:5-3:2, 3:2-2:1, 2:1-3:1, 3:1-6:1, 6:1-15:1, 15:1-30:1, or a ratio within the range defined by any of these values. For example, the ratio can be any of the following: 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, and 15:1. Alternatively, exposure to the Ti precursor and the Si and / or Al precursor may have these ratios. Under the combination of process conditions described herein for forming a diffusion barrier containing TiSiN and / or TiAlN, the ratio of exposure to the first deposition phase to exposure to the second deposition phase results in an average concentration of Si or Al in the diffusion barrier that exceeds a value defined by approximately 3%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or any of these values, based on the total number of atoms in the diffusion barrier.

[0074] The inventors found that the crystallinity of the resulting TiSiN and / or TiAlN thin films can be continuously adjusted, as shown in Figures 7A-7C, by controlling the ratio of the number of exposures of the substrate to the first deposition phase (i.e., the Ti precursor) to the number of exposures of the substrate to the second deposition phase (i.e., the Si or Al precursor). Figures 7A-7C show the limited-field diffraction (SAD) patterns obtained from conformal thin films containing TiSiN deposited on the sidewalls of high-aspect-ratio vias, similar to those shown in Figures 6A-6C, at different crystallinity levels. Figures 7A-7C show the SAD patterns of a substantially amorphous TiSiN thin film, a partially amorphous TiSiN thin film, and a substantially polycrystalline or nanocrystalline TiSiN thin film, respectively. It will be understood that the presence of nanocrystalline or polycrystalline domains and the quantitative degree of crystallinity can be determined from the location and relative sharpness of diffraction spots and / or rings that can be indexed to the (111), (200), and (220) crystal planes of crystalline TiSiN, as shown in Figure 7C. For example, a SAD pattern dominated by diffusion rings can be associated with substantially amorphous TiSiN, while a SAD pattern dominated by spots can be associated with substantially polycrystalline TiSiN having domain sizes comparable to the restricted field of view used to obtain the SAD pattern. SAD patterns of nanocrystalline and amorphous phases of TiSiN can contain a mixture of both diffusion rings and spots. The inventors have found, among other things, that increasing the proportion of the amorphous phase contributes to improvements in the smoothness, conformability, and step coverage of TiSiN thin films.

[0075] Figure 8 shows the minute-angle incident X-ray diffraction pattern of a blanket TiSiN layer formed on a substantially amorphous Si substrate according to an embodiment. The measured TiSiN layer is similar to the TiSiN layer imaged in the SAD patterns of Figures 7A and 6A-6C. The absence of distinct crystallographic peaks due to the crystalline phase of the TiSiN layer indicates that the TiSiN layer is substantially amorphous.

[0076] As described herein, the relative crystallinity of thin films containing TiSiN and / or TiAlN can be adjusted to optimize various material properties, such as diffusion barrier properties. In some circumstances, a lower degree of crystallinity may be preferable, for example, to reduce grain boundaries. Reducing grain boundaries can suppress the diffusion of a given element through the thin film and improve its smoothness. However, in other circumstances, a higher degree of crystallinity may be preferable, for example, to reduce the electrical resistivity of the thin film. Figure 9 shows a graph of experimentally measured resistivity as a function of silicon content in TiSiN-containing thin films according to the examples. This graph shows that the resistivity of TiSiN thin films can be adjusted over a wide range of values ​​by adjusting the relative Si content (atomic %) within the thin film. By extension, this adjustment can also be made by adjusting the number of exposures to the Si precursor in cycle vapor deposition or ALD cycles. The inventors found that at relatively low Si content, the resistivity of the TiSiN layer increases relatively slowly as a function of Si content, while at relatively high Si content, the resistivity increases relatively rapidly as a function of Si content. The inventors found that the relatively rapid increase in resistivity as a function of Si content generally coincides with the starting point 910 of the appearance of the amorphous layer of TiSiN, which has been experimentally verified by transmission electron microscopy as described above. It will be understood that this starting point 910 and the electrical resistivity may depend, in particular, on the deposition temperature and the precursor used. As described above, it may be desirable for the Si content to be higher than about 10% in order to form at least partially amorphous TiSiN layers. As a result, the resistivity may increase, while the overall thickness can be reduced compared to a perfectly crystalline layer such as a TiN layer.

[0077] Therefore, in situations where thin films with relatively high diffusion barrier performance and / or relatively low surface roughness are advantageous, it is advantageous to be able to adjust the composition of the electrode layer such that the thin film containing TiSiN and / or TiAlN is at least partially amorphous. In such embodiments, the thin film may be substantially amorphous overall or may contain nanocrystalline regions surrounded by an amorphous matrix. For example, the electrode may contain one or more TiSi / TiAl, TiN, and TiAlN / TiSiN nanocrystals in an amorphous matrix containing Ti, Al / Si, and N. In the illustrated embodiment, the starting point 910 at about 1600 μΩ·cm corresponds to an average atomic concentration of Si of about 10%. However, in other embodiments, depending on the deposition conditions and the precursor used, the starting point can correspond to an average atomic concentration of Si of about 10%, 15%, 20%, or 25%, or within the range defined by any of these values. Alternatively, starting point 910 corresponds to the ratio of the number of exposures of the substrate to one or more first deposition phases (each including a combination of exposure to a Ti precursor and exposure to an N precursor, but no exposure to a Si and / or Al precursor), where the ratio is within the range defined by 1:1~2:1, 2:1~3:1, 3:1~6:1, 6:1~15:1, 15:1~30:1, or any of these values, to the number of exposures of the substrate to one or more second deposition phases (each including exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and an N precursor). Alternatively, these ratios can represent the ratio of the number of exposures to a Ti precursor to the number of exposures to an N precursor.

[0078] The composition of a thin film containing TiSiN and / or TiAlN can be adjusted to have an electrical resistivity within the range defined by any of the following values: <1000 μΩ·cm, 1000-2000 μΩ·cm, 2000-300 μΩ·cm, 3000-4000 μΩ·cm, 4000-5000 μΩ·cm, 5000-6000 μΩ·cm, 6000-7000 μΩ·cm, 7000-8000 μΩ·cm, 8000-9000 μΩ·cm, 9000-10000 μΩ·cm, or 10000 μΩ·cm or more.

[0079] In addition to crystallinity, the inventors found that the degree of homogeneity at the nanoscale can also be controlled by controlling the number of exposures to the first deposition phase and / or the second deposition phase. Under certain circumstances, the sequence of the first and second deposition phases can be controlled to form thin films having TiN and Si and / or Al or SiN and / or AlN-rich regions or layers, such as nanolaminates that alternately contain TiN-rich regions or layers and Si and / or Al-rich regions or layers or SiN / AlN-rich regions or layers. Under several other circumstances, the resulting thin film may be a substantially homogeneous TiSiN and / or TiAlN thin film, despite different sequences of exposure to the first and second deposition phases, as will be discussed later. Examples are shown with reference to Figures 10A and 10B. Figure 10A shows a TEM image of a substantially homogeneous TiSiN layer, while Figure 10B shows a TEM image of a TiSiN layer in the form of a nanolaminate containing alternating TiN-rich regions or layers and SiN-rich regions or layers.

[0080] In various embodiments, when forming a thin film containing, for example, TiSiN and / or TiAlN as a diffusion barrier layer to form a substantially homogeneous layer, the number of consecutive runs of the first and / or second deposition phases can be smaller than a value defined by approximately 50, 30, 25, 20, 15, 10, 5, or any of these values, when the film is deposited at the temperatures described above. If the number of consecutive runs of the first and / or second deposition phases exceeds these values, the thin film may have a nanolaminate structure. It will be understood that the number of consecutive runs of the first and / or second deposition phases to form a substantially homogeneous or laminated structure may depend on various factors, including temperature, pressure, and the precursor used. For example, at relatively high temperatures, increased diffusive mixing of atoms may lead to a predominance of a homogeneous composition. Conversely, at relatively low temperatures, reduced diffusive mixing of atoms may lead to predominance of nanolaminate formation.

[0081] The inventors have found that, as an advantage, when thin films containing TiSiN and / or TiAlN are formed by the embodiments disclosed herein, the surface roughness can also be reduced compared to other diffusion barrier materials such as TiN or TiSiN formed using other techniques such as CVD or PVD. The reduction in surface roughness is particularly advantageous compared to other materials or techniques when the surface on which the diffusion barrier is deposited includes non-metallic surfaces such as dielectric surfaces and / or semiconductor surfaces exposed by holes such as vias or trenches. A deposited diffusion barrier having the aforementioned thickness can have a root mean square (RMS) surface roughness within the range defined by 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, and 5%, or any of these values ​​or smaller. Alternatively, the deposited diffusion barrier with the aforementioned thickness may have a root-mean-square (RMS) surface roughness less than the range defined by 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or any of these values ​​or less. The reduced RMS roughness can, in turn, improve the conformability of the diffusion barrier layer.

[0082] [Application] Thin films of TiSiN or TiSiN formed using the various process parameters of the various embodiments disclosed herein can be used in a variety of applications. This is particularly true when the substrate has a topography having a relatively large area, a relatively high aspect ratio structure, and / or a non-metallic surface that can benefit from the various advantageous properties disclosed herein. Exemplary applications include, for example, the deposition of films for lining vias, holes, trenches, cavities, or similar structures having an aspect ratio defined as the depth divided by the width of the top surface, where the aspect ratio exceeds a value within the range defined by 1, 2, 5, 10, 20, 50, 100, 200, or any of these values.

[0083] Figure 11 shows one exemplary application of the concept of forming a diffusion barrier for contact structures, such as source or drain contacts, formed on an active semiconductor substrate region that can be heavily doped. A portion of a semiconductor device 1100 is shown, including a material 1104 on which a dielectric layer 1108, such as an interlayer insulating film (ILD) layer containing a dielectric material such as silicon oxide or silicon nitride, is formed. Vias or trenches can be formed through the dielectric layer 1108 to form contacts in various regions of the substrate 1104, including various doping regions such as source and drain regions. Vias or trenches may expose various non-metallic surfaces, such as the exposed bottom surface including the substrate surface such as the silicon substrate surface, or the dielectric sidewalls of the vias. Subsequently, the bottom and sides of the vias can be conformally coated with a thin film containing TiSiN and / or TiAlN in a manner similar to that shown in Figures 6A-6C, according to various embodiments described herein. Then, to form a contact plug 1116, the lined vias can be filled with a more conductive material, in particular a metal or metal alloy such as W, Al, or Cu. For example, vias can be filled with tungsten by CVD using WF6 or similar materials.

[0084] The barrier layer 1112 formed by the embodiment can be advantageous for the various reasons described above. Furthermore, the conformability of the barrier layer 1112 can significantly suppress the occurrence of pinching in the subsequent metal filling process. In addition, as described above, the barrier layer 1112 can effectively prevent cross-transport of substances such as external diffusion of dopants (B, P) from the substrate 1104 and internal diffusion of reactants, etchants, and metals (F, Cl, W, or Cu, etc.) during the contact plug formation process. The barrier effect can be enhanced by reduced surface roughness, improved step coverage, partially amorphous morphology (which can be partially nanocrystalline), and / or homogeneous / nanolaminate morphology. These advantageous effects can be achieved with a smaller thickness compared to a TiN thin film. Furthermore, as described above, the layer-by-layer growth mode can reduce the overall contact resistance of the barrier layer 1112.

[0085] Other applications of thin films containing TiSiN and / or TiAlN formed by the various embodiments disclosed herein include, to name a few, a variety of conductive structures such as recessed substrates (e.g., embedded electrodes or lines), electrodes (e.g., DRAM capacitor electrodes or gate electrodes), higher metal-level metallization barriers (e.g., vias / trench barriers for Cu contacts / lines), high aspect ratio vertical rod electrodes or vias for 3D memory, and through-silicon vias (TSVs).

[0086] [TiSiN film deposition including Ti surface treatment before Si precursor exposure] The various embodiments described herein address the demand for improved diffusion barriers for industrial use, such as the TiN-based diffusion barrier described above with respect to Figure 2. As mentioned above, among other properties of thin films containing TiSiN, low resistivity and high step coverage are desirable in many applications, such as forming diffusion barriers lining electrodes and / or high aspect ratio vias and trenches. As described above, the process conditions described with respect to Figures 5A-5D, for example, can be optimized for conformally coating substrates with relatively high area density and high aspect ratio structures by controlling, in particular, the reaction chamber pressure or precursor partial pressure during deposition, the deposition rate, the temperature or pressure of the precursor introduced into the reaction chamber, the precursor flow rate, and the exposure time.

[0087] In addition to the improvements provided by TiSiN that surpass other diffusion barrier materials such as TiN, the inventors found that TiSiN may offer another advantage for advanced technology nodes. Figure 12 shows a cross-sectional transmission electron microscope image of an ultrathin TiN layer grown by atomic layer deposition on a substrate with topography. The inventors found that even when grown by atomic layer deposition, ultrathin (e.g., <5 nm) TiN layers may have discontinuities and not continuously cover the underlying surface. Such discontinuities may limit the effectiveness of the TiN layer as a diffusion barrier. In contrast, the inventors have found that when deposited under the specified deposition conditions described herein, TiSiN provides continuous and uniform coating even when reduced to ultrathin sizes, such as less than 5 nm, which can be particularly important in applications in ultrathin diffusion barriers for advanced technology nodes. As described herein, in order to enhance the step coverage of the TiSiN film and / or reduce its electrical resistivity, the inventors have found alternative and / or improved methods to the various methods described above, for example with respect to Figures 5A to 5D. In particular, in the alternative or improved methods described herein, the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases alternately and without overlap. In this case, exposure of the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors. Exposure of the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then to an N precursor. That is, in the second deposition phase, exposure to the Ti precursor precedes exposure to the Si precursor, followed by exposure to the N precursor. This alternative method further reduces roughness and enhances layer-by-layer growth, allowing the TiSiN film to maintain continuity even at ultra-thin sizes (e.g., <5 nm). In addition, the inventors found that this method allows for more precise control of Ti uptake even when one or more precursors are unsaturated on the substrate surface during growth. As a result, the inventors found that this method significantly reduces resistivity and improves the stability of resistivity.

[0088] Figure 13 is a flowchart illustrating a method for forming a thin film containing TiSiN, similar to what is described above with respect to Figures 5B-5D. The method for depositing a thin film containing TiSiN includes exposing the semiconductor substrate to one or more (m) first deposition phases 525 and exposing the semiconductor substrate to one or more (n) second deposition phases 530. Each of the first deposition phases includes multiple alternating exposures to Ti precursors and N precursors, and each of the second deposition phases includes multiple alternating exposures to Si precursors and N precursors. Further details of the method shown in Figure 13 are described above with respect to Figures 5B-5D, and for simplicity, those details will not be repeated here.

[0089] Figures 14-16 show alternative or improved methods for forming a TiSiN-containing diffusion barrier, where further improvements in roughness and continuity at ultrathin thicknesses and high-precision control of the Ti content can reduce resistivity with less variation.

[0090] Figure 14 is a flowchart illustrating a method for forming a diffusion barrier containing TiSiN according to an embodiment. The method includes step 1402 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposure to one or more first deposition phases 1404 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposure to one or more second deposition phases 1406 includes sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor without intervening exposure to an N precursor between them, and then exposing the semiconductor substrate to an N precursor.

[0091] Figure 15 is a flowchart illustrating a method for forming a diffusion barrier containing TiSiN according to another embodiment. The method includes step 1502 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposure of the semiconductor substrate to one or more first deposition phases 1504 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposure of the semiconductor substrate to one or more second deposition phases 1506 includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0092] Figure 16 is a flowchart illustrating a method for forming a TiSiN-containing diffusion barrier according to another embodiment. The method includes step 1602 of alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. In the method, exposure of the semiconductor substrate to one or more first deposition phases 1604 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. In the method, exposure of the semiconductor substrate to one or more second deposition phases 1606 includes exposing the semiconductor substrate to a Ti precursor during the Ti precursor exposure time, followed by a silicon (Si) precursor during the Si precursor exposure time, followed by an N precursor, where the ratio of the Si precursor exposure time to the Ti precursor exposure time is between 2 and 130.

[0093] Figure 17 is a flowchart showing a method for forming a thin film containing TiSiN according to an embodiment that shows a precursor exposure sequence compatible with any of the embodiments described above with respect to Figures 14-16. In this case, unlike the method described above with respect to Figure 13, in the second deposition phase, the Ti precursor exposure precedes the Si precursor exposure, followed by the N precursor exposure. The illustrated method includes exposing the semiconductor substrate to one or more (x) vapor phase deposition cycles 1720, each cycle including exposing the semiconductor substrate to one or more (m) first deposition phases 1725 and exposing the semiconductor substrate to one or more (n) second deposition phases 1730. In the illustrated embodiment, the first and second deposition phases are performed alternately without overlapping in time. In the illustrated method, exposing the semiconductor substrate to one or more first deposition phases 1725 may be substantially the same as exposing the semiconductor substrate to one or more (m) first deposition phases 525 described above with respect to Figures 5B-5D and 13. In particular, exposing the semiconductor substrate to one or more first deposition phases 1725 involves alternately exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors in a manner similar to that described above with respect to Figures 5B-5D and 13, and for simplicity, the details are not repeated here.

[0094] However, unlike the methods described above with respect to Figure 13 (and Figures 5B-5D), in the method shown in Figure 17, exposing the semiconductor substrate to each second deposition phase further includes exposing the substrate to a titanium (Ti) precursor. In particular, exposing the semiconductor substrate to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0095] Additionally or alternatively, exposure of the semiconductor substrate 1730 includes sequentially exposing the semiconductor substrate to a Ti precursor and a Si precursor without intervening exposure to an N precursor, and then exposing the semiconductor substrate to an N precursor. In the embodiment shown in Figure 17, when the second deposition phase follows immediately after the first deposition phase, exposure of the semiconductor substrate to the first deposition phase 1725 includes exposing the semiconductor substrate to an N precursor as the last precursor, and then exposing the semiconductor substrate to a Ti precursor as the first precursor of the second deposition phase.

[0096] For the sake of simplicity, details are omitted here, but the various process parameters used in the embodiment shown in Figure 17, including the precursor, chamber pressure during deposition, and deposition temperature, may be similar to those used in the methods described above with respect to Figures 13 and / or 5B-5D. For the sake of simplicity, each of the similar parameters is not repeated here.

[0097] The inventors have found that performing Ti precursor exposure prior to Si precursor exposure, as described herein, can be advantageous for the various reasons mentioned above. To enhance the advantageous effect, Ti precursor exposure during the second deposition phase can be optimized with respect to various parameters, including precursor flow rate and exposure time, relative to other exposures.

[0098] To achieve suitable flow rates for depositing TiSiN thin films on substrates with large surface area and / or high aspect ratio structures using a deposition process involving Ti surface treatment prior to Si precursor exposure, the flow rates of the Ti precursor and Si precursor, respectively, can be adjusted to less than or greater than values ​​within the range defined by 1000 standard cubic centimeters / min (sccm), 800 sccm, 600 sccm, 400 sccm, 200 sccm, or any of these values. The flow rate of the N precursor can be adjusted more significantly, for example, to less than or greater than values ​​within the range defined by 10000 standard cubic centimeters / min (sccm), 8000 sccm, 6000 sccm, 4000 sccm, 2000 sccm, or any of these values. It will be understood that the appropriate flow rates may depend in particular on the reactor volume, and that these flow rates may be appropriate for a single wafer reactor with a volume of approximately 1-2 liters. For reactors with multiple processing stations, these flow rates may be appropriate for each processing station.

[0099] Referring back to Figure 17, the inventors found that exposing the semiconductor substrate to the Ti precursor during exposure to the second deposition phase 1730 can be particularly effective when the exposure time is shorter than the exposure time to the Si precursor. Advantageously, in certain embodiments, the relatively short exposure time to the Ti precursor during the second deposition phase yields a surprisingly large improvement in electrical resistivity and / or step coverage. In various embodiments, the ratio of the exposure time of the semiconductor substrate to the Si precursor to the exposure time of the semiconductor substrate to the Ti precursor during the second deposition phase exceeds a value within the range defined by 0.05, 0.1, 0.5, 1, 2, 5, 10, 20, 50, 100, 130, 200, 240, or any of these values. For example, in the embodiment shown in Figure 17, the Si precursor exposure time in the second deposition phase can be less than a value within the range defined by 120 seconds, 90 seconds, 60 seconds, 30 seconds, 10 seconds, 5 seconds, 3 seconds, 2 seconds, 1 second, 0.5 seconds, 0.1 seconds, or any of these values, whereas the Ti exposure time in the second deposition phase can be less than a value within the range defined by 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, 0.5 seconds, or any of these values.

[0100] Referring further to Figure 17, the inventors found that exposing the semiconductor substrate to the Ti precursor during exposure to the second deposition phase 1730 can be particularly effective when the exposure time is longer than the exposure time to the Ti precursor during exposure to the first deposition phase 1725. Advantageously, in various embodiments, the ratio of the exposure time of the semiconductor substrate to the Ti precursor during the second deposition phase to the exposure time of the semiconductor substrate to the Ti precursor during the first deposition phase exceeds a value defined by 0.5, 1, 3, 5, 10, 20, 30, 40, or any of these values. For example, in the embodiment shown in Figure 17, the Ti precursor exposure time in the first deposition phase can be less than a value defined by 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, 0.05 seconds, or any of these values, while the Ti exposure time in the second deposition phase can be less than a value defined by 2 seconds, 1.5 seconds, 1.2 seconds, 1.0 seconds, 0.7 seconds, 0.5 seconds, or any of these values.

[0101] Referring further to Figure 17, the inventors have found that exposing the semiconductor substrate to the N precursor during exposure to the second deposition phase 1730 can be particularly effective when the exposure time is longer than the exposure time to the N precursor during exposure to the first deposition phase 1725. Advantageously, in various embodiments, the ratio of the exposure time of the semiconductor substrate to the N precursor during the second deposition phase to the exposure time of the semiconductor substrate to the N precursor during the first deposition phase exceeds a value defined by 1, 2, 5, 10, 20, 50, 100, 200, 500, 600, or any of these values. For example, in the embodiment shown in Figure 17, the N precursor exposure time in the first deposition phase may be less than a value defined by 1 second, 0.5 seconds, 0.2 seconds, 0.1 seconds, or any of these values, while the N precursor exposure time in the second deposition phase may be less than a value defined by 60 seconds, 30 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, 0.5 seconds, 0.2 seconds, or any of these values.

[0102] Furthermore, referring to Figure 17, although this is merely an example, the typical durations of the Ti precursor pulse / Ti precursor purge / N precursor pulse / N precursor purge in the first deposition phase can be 0.05-1 second / 0.2-1 second / 0.1-1 second / 0.2-1 second, respectively, while the typical durations of the Ti precursor pulse / Ti precursor purge / Si precursor pulse / Si precursor purge / N precursor pulse / N precursor purge in the second deposition phase can be 0.5-2 seconds / 0.2-1 second / 0.2-120 seconds / 0.5-5 seconds / 0.2-120 seconds / 0.5-5 seconds, respectively.

[0103] By controlling the diverse Ti precursor exposure conditions in the second deposition phase as described herein, TiSiN thin films formed using the methods of the embodiments may have a resistivity at least within the range defined by 200 μΩ·cm, 500 μΩ·cm, 1000 μΩ·cm, 1500 μΩ·cm, or any of these values, compared to diffusion barriers formed using the same method except that the semiconductor substrate is exposed to the Ti precursor as part of one or more second deposition phases. TiSiN thin films thus formed may have a resistivity less than the range defined by 2500 μΩ·cm, 2000 μΩ·cm, 1500 μΩ·cm, 1000 μΩ·cm, 500 μΩ·cm, or any of these values.

[0104] In addition to exposure time, the ratio (m / n) of the number of first deposition phases (m) to the number of second deposition phases (n) can be adjusted to control the diverse properties of the resulting TiSiN thin film.

[0105] Figure 18A is a graph of the Si content measured experimentally in TiSiN thin films deposited by the method shown in Figure 17. The Si content is shown as a function of the ratio of the number of first deposition phases to the number of second deposition phases. As shown in the figure, the Si content of the deposited TiSiN thin film was observed to decrease as a function of the increasing m / n ratio. As shown in the figure, the rate of decrease in Si content as a function of the m / n ratio decreases unexpectedly when the m / n ratio is greater than approximately 7 (showing an inflection point). This decrease is consistent with the trend of resistivity (Figure 18C). The experimental results shown in the figure indicate that it is important to have an m / n ratio greater than 7 to form TiSiN thin films with low resistivity (e.g., less than approximately 2000 μΩ·cm) corresponding to a Si content of 15% or less. For Si content of 15% or more, corresponding to an m / n ratio greater than approximately 7, the nanostructure of TiSiN becomes substantially amorphous, as shown in Figure 18B.

[0106] Figure 18B is a graph of the grazing incidence X-ray diffraction (XRD) spectra experimentally measured for TiSiN thin films deposited by the method shown in Figure 17. Different curves correspond to TiSiN thin films with different ratios of the number of first deposition phases to the number of second deposition phases. As shown in the figure, the XRD peak intensities of the (111), (002), and (220) domains were observed to decrease as the m / n ratio decreased. As indicated by the signal / noise ratio, the amount of amorphous phase in the TiSiN thin film increases as the m / n ratio decreases.

[0107] Figure 18C is a graph of experimentally measured electrical resistivity for TiSiN thin films with the Si content shown in Figure 18A. As shown in the figure, it was observed that the resistivity of the TiSiN thin film decreases as the m / n ratio increases. As shown in the figure and as mentioned above, when the m / n ratio becomes small enough to be less than 7, the resistivity increases unexpectedly. Based on the experimental results shown in the figure, it may be important to adjust the m / n ratio to be greater than 7 in order to form a TiSiN thin film with a resistivity of 2000 μΩ·cm. Below this ratio, in addition to the large resistivity value, the resistivity fluctuates with even small changes in Si content, making it unsuitable for mass production.

[0108] The inventors have found that by prioritizing Si precursor exposure in the second deposition phase, even when the substrate surface is left unsaturated during one or more exposures to Ti, Si, and N precursors in the second deposition phase, the variation in resistivity as a function of exposure time is relatively small, and the resistivity of the resulting TiSiN thin film can be lowered. As a result, the variation between runs of the TiSiN thin film is reduced, and its manufacturability is improved. This is shown below for various precursors. Furthermore, throughput can be improved because there is no need for unnecessarily long exposure times during the second deposition phase. Therefore, according to the embodiment, as shown in any of Figures 14 to 17, exposing the semiconductor to one or more Ti precursors, Si precursors, and N precursors one or more times during one or more second deposition phases includes leaving the main surface of the semiconductor substrate unsaturated.

[0109] As described herein, a precursor surface saturation state refers to a state in which the degree of surface saturation due to a particular precursor does not substantially change even when the exposure time to that precursor is increased. Conversely, unsaturated state refers to a state in which the degree of surface saturation due to a particular precursor substantially changes when the exposure time to that precursor is increased. While it is difficult to measure surface saturation absolutely, it can be estimated by measuring the relevant electrical or physical parameters. For example, if a given value of a parameter is obtained using exposure for a certain duration, and the value of that parameter does not change by more than, for example, 10% with further exposure for the same or longer duration, then the surface can be presumed to be substantially saturated.

[0110] Figures 19A-19B are graphs of the electrical resistivity of TiSiN thin films measured experimentally as a function of exposure time to the Ti precursor (TiCl4) during the second deposition phase of the deposition cycle shown in Figures 14-17. Exposure to dichlorosilane (SiH2Cl2, "DCS") as the Si precursor was fixed at 60 seconds and 90 seconds, respectively. As shown in the figures, a decrease in the electrical resistivity of the TiSiN thin film can be observed as the Ti precursor exposure time in the second deposition phase increases. Compared to a TiSiN thin film deposited using the same process except for the omission of Ti precursor exposure in the second deposition phase, the TiSiN thin film deposited with a short Ti precursor exposure time of 0.7 seconds in the second deposition phase can be shown to have substantially lower resistivity. Longer exposure times further decrease resistivity, but it can be seen that the substantial decrease is achieved with a short Ti precursor pulse duration of 0.7 seconds. As shown in the figure, compared to 60 seconds of exposure to DCS, 90 seconds of exposure to DCS increases the resistivity by more than 10%, from approximately 2800 μΩ·cm to approximately 3200 μΩ·cm, compared to the initial absence of Ti exposure in the second deposition phase (zero value on the x-axis). That is, it can be inferred that 60 seconds of DCS is not sufficient to substantially saturate the surface. However, regardless of the degree of DCS saturation, it was observed that a short exposure of 0.7 seconds to the Ti precursor was effective in substantially reducing the resistivity. In the end, further increases in the Ti precursor exposure time resulted in only very small changes in resistivity. As shown in the figure, the TiSiN thin film obtained with a Ti exposure time of 1.2 seconds has an electrical resistivity that changes by only a relatively small amount, for example, less than 10%, compared to the TiSiN thin film obtained with a Ti precursor exposure time of 0.7 seconds in the second deposition phase. These results indicate that inserting a relatively short Ti precursor prior to the Si precursor in the second deposition phase yields two advantageous technical effects: a substantial reduction in resistivity and a substantial reduction in resistivity variability.

[0111] Figures 20A–20C are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiSiN thin film formed using different Ti precursor (TiCl4) exposure times during the second deposition phase of a deposition cycle similar to that shown in Figure 17. Figures 20A–20C show the results after lining a flat semiconductor substrate with a TiSiN thin film of equivalent thickness of approximately 4 nm to create a high aspect ratio structure with an aspect ratio of 57:1 (measured using the width of the top aperture). The TiSiN thin films imaged in the microscope images of Figures 20A–20C were formed using the method shown in Figures 14–17, with the Si precursor (dichlorosilane) exposure time fixed at 90 seconds during the second deposition phase, while the Ti precursor exposure times were 0 seconds, 0.7 seconds, and 1.2 seconds, respectively. As shown, the step coverage was measured to be 83%, 85%, and 87% from the microscope images of Figures 20A–20C, respectively.

[0112] Figures 21A-21C are graphs of experimentally measured electrical resistivity as a function of Ti precursor (TiCl4) exposure time during the second deposition phase of the deposition cycle shown in Figures 14-17. The exposure time to monochlorosilane (SiH3Cl, "MCS") as the Si precursor was fixed at 3.5 seconds, 30 seconds, and 90 seconds, respectively. As shown in the figures, it can be observed that the electrical resistivity of the TiSiN thin film decreases as the Ti precursor exposure time in the second deposition phase increases. Compared to a TiSiN thin film deposited using the same process except that the Ti precursor exposure in the second deposition phase is omitted, the resistivity of the TiSiN thin film deposited with a short Ti precursor exposure time of 0.7 seconds in the second deposition phase is significantly lower. Further reductions in resistivity can be achieved with longer exposure times, but it can be seen that the substantial reduction is achieved with a short pulse duration of 0.7 seconds. Similar observations can be made with respect to Figures 19A and 19B. As shown in the figure, without the initial Ti exposure in the second deposition phase (zero value on the x-axis), it is observed that a short duration of 0.7 seconds of Ti precursor exposure is effective in significantly reducing resistivity, regardless of MCS saturation. Ultimately, the change in resistivity due to further increasing the Ti precursor exposure time is only a small change in resistivity. As shown in the figure, the TiSiN thin film obtained with a Ti exposure time of 1.2 seconds shows only a relatively small change in electrical resistivity, e.g., less than about 10%, compared to the TiSiN thin film obtained with a Ti precursor exposure time of 0.7 seconds in the second deposition phase. This result indicates that the insertion of a relatively short Ti precursor before the Si precursor in the second deposition phase yields two advantageous technical effects: a significant reduction in resistivity and a significant reduction in resistivity variability.

[0113] Figures 22A-22C are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiSiN thin film formed using different Ti precursor (TiCl4) exposure times in the second deposition phase of a deposition cycle similar to that shown in Figure 17. The microscope images in Figures 22A-22C were obtained after lining a flat semiconductor substrate with a TiSiN thin film of equivalent thickness 4 nm to create a high aspect ratio structure with an aspect ratio of 57:1 (measured using the width of the top aperture). The TiSiN thin films imaged in the microscope images of Figures 22A and 22B were formed using a method similar to that shown in Figures 14-17, where the Si precursor (monochlorosilane) exposure time was fixed at 3.5 seconds in the second deposition phase, while the Ti exposure times were 0 seconds and 1.2 seconds, respectively. The TiSiN thin film imaged in the micrograph in Figure 22C was formed using a method similar to that shown in Figures 14-17, where the Si precursor (monochlorosilane) exposure time was fixed at 90 seconds during the second deposition phase, while the Ti exposure time was 1.2 seconds. As can be seen, the step coverage was measured at 86%, 93%, and 96% from the micrographs in Figures 22A-22C, respectively.

[0114] Figures 23A-23B are graphs of experimentally measured electrical resistivity as a function of Ti precursor (TiCl4) exposure time during the second deposition phase of the deposition cycle shown in Figures 14-17. The exposure time to monochlorosilane (SiH3Cl, "MCS") as the Si precursor was fixed at 5 seconds and 30 seconds, respectively. As shown in the figures, it can be observed that increasing the Ti precursor exposure time during the second deposition phase decreases the electrical resistivity of the TiSiN thin film. Compared to a TiSiN thin film deposited using the same process except that the Ti precursor exposure was omitted in the second deposition phase, the TiSiN thin film deposited with a short Ti precursor exposure time of 1.2 seconds has significantly lower resistivity. Here, similar observations can be made with respect to Figures 19A and 19B. As shown in the figures, it was observed that, regardless of the OTCS saturation, a short duration of 1.2 seconds of Ti precursor exposure time is effective in significantly reducing resistivity, provided there is no initial Ti exposure in the second deposition phase (zero value on the x-axis). Similarly, the insertion of a relatively short Ti precursor before the Si precursor in the second deposition phase yields two advantageous technical effects: a significant reduction in resistivity and a significant reduction in resistivity variability.

[0115] Figures 24A-24B are cross-sectional transmission electron microscope images obtained from a high aspect ratio structure lined with a TiCl4 thin film formed using different Ti precursor (TiCl4) exposure times in the second deposition phase of a deposition cycle similar to that shown in Figure 17. Figures 24A-24B were obtained after lining a flat semiconductor substrate with a TiSiN thin film of equivalent thickness 4 nm to create a high-specific ratio structure with an aspect ratio of 57:1 (measured using the width of the top aperture). The TiSiN thin films imaged in the microscope images of Figures 24A-24B were formed using a method similar to that shown in Figures 14-17, with the Si precursor (OTCS) exposure time fixed at 5 seconds in the second deposition phase, while the Ti precursor exposure times were 0 seconds and 1.2 seconds, respectively. As can be seen, the step coverage was measured at 96% and 100% from the microscope images of Figures 24A-24B.

[0116] Advantageously, the transmission electron microscope images shown in Figures 20A-20C, 22A-22C, and 24A-24B demonstrate that TiSiN significantly improves the smoothness of the ultrathin diffusion barrier compared to the TiN thin film of ALD (see Figure 12). In the transmission electron microscope images shown in Figures 20A-20C, 22A-22C, and 24A-24B, the TiSiN thin film continuously coats the substrate surface with a thickness of less than 5 nm.

[0117] In the transmission electron microscope images shown in Figures 20A–20C, 22A–22C, and 24A–24B, an aspect ratio of 57:1 was measured as the ratio of height to the width of the top aperture. The overall view of the trench structure is shown in Figure 25A. It will be understood that the aspect ratio can be defined in various ways. For example, the ratio of height to the width of the bottom aperture is approximately 171:1.

[0118] [TiN / TiSiN nanolaminate diffusion barrier deposition] Referring back to the method described above with respect to Figures 13-17, the inventors found that the ratio (m / n) of the number of first deposition phases (m) to the number of second deposition phases (n) can be adjusted to form either a substantially homogeneous film containing TiSiN or a nanolaminate containing TiN and TiSiN as separate layers.

[0119] Figure 26A is a flowchart illustrating a method for forming a nanolaminate thin film according to several embodiments. As shown in Figure 26A, this method includes depositing a thin film containing TiN by exposing a semiconductor substrate to one or more (y1) first deposition phases, depositing a thin film containing TiSiN by exposing the semiconductor substrate to one or more (x) second deposition phases, and forming another thin film containing TiN by exposing the semiconductor substrate to one or more (y2) first deposition phases. In some embodiments, y1 and y2 differ. Figure 26B is a flowchart illustrating a method for forming a nanolaminate thin film using a vapor deposition cycle similar to those shown in Figures 5B-5D and 13, according to several embodiments. Figure 26C is a flowchart illustrating a method for forming a nanolaminate thin film using a vapor deposition cycle similar to those shown in Figures 14-17, according to several embodiments.

[0120] In various embodiments, when forming a diffusion barrier layer in a thin film, for example, containing TiSiN, the number of consecutive runs of the first and / or second deposition phases can be less than approximately 50, 30, 25, 20, 15, 10, 5 times, or any of these values, when the thin film is deposited at the temperatures described above, in order to form a substantially uniform layer. On the other hand, when the number of consecutive runs of the first and / or second deposition phases exceeds these values, the thin film may contain a nanolaminate structure.

[0121] Figure 27A is a graph of experimentally measured electrical resistivity for various nanolaminate thin films deposited by the methods shown in Figures 26A and 26C according to several embodiments. The measured nanolaminate thin films include a TiSiN thin film interposed between two TiN thin films. It can be seen that the electrical resistivity can be adjusted by independently adjusting the thickness of the upper and lower TiN thin films. Surprisingly, while the overall thickness of the TiN thin film combination was the same for the three nanolaminates measured, the electrical resistivity unexpectedly decreased when the lower TiN thin film was thinner than the upper TiN thin film. At least the various advantages described above for a uniform TiSiN thin film were equally observed in the nanolaminates according to the embodiments.

[0122] Figure 27B is a graph of grazing incidence X-ray diffraction spectra experimentally measured from various nanolaminate thin films deposited by the methods shown in Figures 26A and 26C, according to several embodiments.

[0123] Figures 28A and 28B are cross-sectional transmission electron microscope images obtained from high aspect ratio structures lined with nanolaminate thin films according to several embodiments. It can be seen that the step coverage is comparable to that of a uniform TiSiN thin film.

[0124] [TiSiN thin film with excellent mechanical properties including high elastic modulus and hardness] As described above, thin films containing TiSiN are desirable in many applications, for example, for forming electrodes and / or diffusion barriers that line high aspect ratio vias and trenches. As described above, in order to conformally coat substrates with relatively high area density and high aspect ratio structures, the process conditions described with respect to Figures 5A to 5D can be optimized in particular by controlling the reaction chamber pressure during deposition, the partial pressure of the precursor, the deposition rate, the temperature and pressure of the precursor introduced into the reaction chamber, the precursor flow rate and exposure time, etc.

[0125] The diverse applications of TiSiN require improved structural and mechanical properties of thin films containing TiSiN, in addition to their electrical and barrier properties. For example, as the features of integrated circuit devices continue to shrink in size and / or increase in aspect ratio, the physical requirements for thin films used as diffusion barriers and / or electrodes also continue to increase. The thickness of the thin films also decreases along with the shrinking feature size, and the thin films may be subjected to correspondingly higher levels of thermodynamic stress. Although TiN is one of the pioneering materials in many applications, structural failure of TiN in high aspect ratio structures is a major problem in the reliability and yield of integrated circuit devices. Failure modes such as defects, bending, and buckling are related to insufficient physical properties of TiN films, such as hardness and modulus. Therefore, as the demand for complex three-dimensional structures increases, there is a need for alternative barrier materials with superior physical properties. To address these and other needs, a method for forming and preparing thin films containing TiSiN with superior physical properties, and thin films formed using this method, are described here.

[0126] As described herein, the inventors have found alternative forms and / or further improvements to the various methods described above to improve the mechanical and structural properties of TiSiN films, in addition to their electrical and structural properties. As described above, the inventors have found that even with atomic layer deposition, ultrathin (e.g., <5 nm) TiN layers may not continuously cover the underlying surface but may be discontinuous. Such discontinuities can significantly impair the mechanical and structural properties of the TiN film, in addition to limiting the effectiveness of the TiN layer as a diffusion barrier.

[0127] Unlike TiN thin films, the inventors have found that when deposited under the specified deposition conditions described herein, TiSiN can provide continuous and uniform coverage even when reduced to these ultrathin dimensions, such as <5 nm. This is particularly important for providing excellent mechanical and structural properties for ultrathin diffusion barrier applications in advanced technology nodes. For example, in a manner similar to that described with respect to Figures 14-17, the semiconductor substrate is alternately and non-overlappingly exposed to one or more first deposition phases and one or more second deposition phases. In this case, exposure to one or more first deposition phases includes alternately exposing the semiconductor substrate to titanium (Ti) precursors and nitrogen (N) precursors, and exposure to one or more second deposition phases includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, and then an N precursor. That is, in the second deposition phase, exposure to the Ti precursor precedes exposure to the S precursor, followed by exposure to the N precursor. This method improves mechanical integrity and enhances the continuity and structural properties of TiSiN films, even when scaled down to ultra-thin dimensions (e.g., <5nm).

[0128] Figure 29 is a flow chart illustrating a method for forming a TiSiN-containing thin film with improved mechanical and structural properties according to several embodiments. In these embodiments, the method comprises forming a TiSiN-containing diffusion barrier by alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases. The diffusion barrier has: an elastic modulus greater than 290 GPa and a Si content greater than 2.7 atomic%; or a hardness greater than 20 GPa and a Si content greater than 2.7 atomic%; or a crystalline structure with a Si content greater than 2.7 atomic% and a ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum of the diffusion barrier greater than 0.4; or a nanocrystalline structure with an average grain size of less than approximately 6.5 nm and a Si content greater than 2.7 atomic%. Exposing a semiconductor substrate to one or more first deposition phases 2904 includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor. Exposing a semiconductor substrate to one or more second deposition phases 2906 includes sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor.

[0129] Various embodiments of the method shown in Figure 29 may include the features described above with respect to Figures 5B-5D and 13 or Figures 14-17, so for simplicity, their details will not be repeated here. For example, in the embodiments, the exposure times for the Ti precursor in the first deposition phase, the N precursor in the first deposition phase, and the N precursor in the second deposition phase can be less than 1.0 seconds, 0.8 seconds, 0.6 seconds, 0.4 seconds, 0.2 seconds, 0.1 seconds, or any of these values. The thin-film deposition system can be configured to introduce each precursor at a specific flow rate, thereby ensuring that the substrate surface reaches a predetermined degree of saturation within these exposure times, for example, a saturation level greater than 40%, 60%, 80%, or any of these values. In an embodiment where rapid purging is performed following the precursor exposure shown in Figure 17, the duration of the rapid purging step can be less than 1.0 second, 0.8 seconds, 0.6 seconds, 0.4 seconds, 0.2 seconds, 0.1 seconds, or any of these values.

[0130] Referring to Figure 17, in another example, the inventors found that exposing the semiconductor substrate to the Ti precursor during exposure to the second deposition phase 1730 is particularly effective when the exposure time is the same as or shorter than the exposure time to the N precursor. In various embodiments, the ratio of the exposure time of the semiconductor substrate to the Ti precursor to the exposure time of the semiconductor substrate to the Si precursor in the second deposition phase is greater than 1, 0.2, 0.4, 0.6, 0.8, and 1.0 or a value within the range defined by these values. For example, in the embodiment shown in Figure 17, the Si precursor exposure time in the second deposition phase may be less than 30 seconds, 15 seconds, 10 seconds, 5 seconds, 1 second, 0.5 seconds or a value within the range defined by any of these values, while the Ti precursor exposure time in the second deposition phase may be less than 0 seconds or less than 2 seconds, 1.5 seconds, 1.0 seconds, 0.5 seconds, 0.2 seconds or a value within the range defined by any of these values.

[0131] Referring again to Figure 17, for illustrative purposes only, in one particular embodiment, the typical durations of the Ti precursor pulse / Ti precursor purge / N precursor pulse / N precursor purge in the first deposition phase can be 0.15 seconds / 0.53 seconds / 0.2 seconds / 0.32 seconds, respectively, while the typical durations of the Ti precursor pulse / Ti precursor purge / Si precursor pulse / Si precursor purge / N precursor pulse / N precursor purge in the second deposition phase can be 0-1.0 seconds / 0.3 seconds / 1-10 seconds / 0.5 seconds / 0.5 seconds / 0.5 seconds, respectively.

[0132] In addition to exposure time, the ratio of the number of first deposition phases (m) to the number of second deposition phases (n) (m / n) can be adjusted to control various properties of the resulting TiSiN thin film. m / n can be greater than 5, 10, 20, 40, 60, 80, and 100.

[0133] Figure 30 is a graph showing the controllability of the Si content of a TiSiN thin film by adjusting the precursor exposure time and / or the ratio of the number of first deposition phases to the number of second deposition phases, according to the embodiment. The x-axis plots the m:n ratio, and the y-axis plots the Si content in the TiSiN thin film measured by X-ray photoelectron spectroscopy (XPS). The three curves showing the decrease in Si content as the m / n ratio increases correspond to Si precursor exposure times of 1 second, 0.5 seconds, and 10 seconds, with the Ti precursor exposure time fixed at 1 second. It can be seen that TiSiN thin films with Si content in the range of approximately 2.7 to 9 atomic percent can be fabricated by different combinations of the m / n ratio and Si precursor exposure time. This range has been shown to be particularly effective in yielding excellent mechanical properties.

[0134] The area under a predetermined peak in the grazing incidence X-ray diffraction spectrum can be monitored as an indicator of a predetermined structural performance parameter of the TiSiN thin film deposited according to the embodiment. In particular, the inventors have found that the TiSiN thin film deposited according to the embodiment has a crystalline structure such that the grazing incidence X-ray diffraction spectrum of the TiSiN thin film exhibits a ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks, which can be monitored as an indicator of a predetermined structural performance parameter of the TiSiN thin film. Although not bound by any theory, this ratio R may be related to the preferred (002) structure of the nanocrystalline domains of the TiSiN thin film. Figures 31A to 31I show the grazing incidence X-ray diffraction spectra (XRD) of TiSiN thin films with different Si content, measured experimentally.

[0135] Figure 32 is a graph summarizing the XRD spectra shown in Figures 31A to 31I. Table 1 summarizes the results for the ratio (R) of TiSiN thin films with different Si contents. According to various embodiments, the ratio (R) of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks for TiSiN thin films with a Si content exceeding 2.7 atomic percent may exceed 0.4, 1.0, 2.0, 3.0, 4.0, or 4.5, or may have a value within the range defined by any of these values. As shown in the figure, in a TiSiN thin film with a Si content of approximately 7 atomic percent, the R ratio peaked at approximately 4.5 and then unexpectedly decreased. As described below, the inventors discovered that a higher R ratio may correlate with an improvement in hardness and elastic modulus.

[0136] [Table 1]

[0137] Figure 33 is a graph of the estimated average nanocrystalline grain size as a function of Si content, calculated from the oblique incidence X-ray diffraction (XRD) spectra (XRD) measurements shown in Figures 31A-31I. The average grain size was calculated using the broadened peaks of the XRD spectra with the technically known Scherrer method. The TiSiN thin film has a nanocrystalline structure with an average grain size less than approximately 6.5 nm, 6.0 nm, 5.5 nm, 5.0 nm, or any of these values. As described below, the inventors found that for grain sizes larger than approximately 5.5 nm, corresponding to approximately 7 atomic percent Si, the hardness and elastic modulus improve as the grain size decreases.

[0138] Figure 34 is a graph of hardness values ​​as a function of Si content measured in TiSiN thin films corresponding to the process conditions shown in Figure 30. Figure 35 is a graph of elastic modulus values ​​as a function of Si content measured in TiSiN thin films corresponding to the process conditions shown in Figure 30. The hardness and elastic modulus values ​​were measured using nanoindentation technology. As shown, the hardness and elastic modulus values ​​are generally proportional to the R ratio and follow the same general trend (Figure 32). As shown, the peaks in the hardness and elastic modulus values ​​coincide with the peak of the R ratio, showing a peak in TiSiN thin films with a Si content of approximately 7 atomic percent, and then unexpectedly decreasing. In addition, the hardness and elastic modulus values ​​are generally inversely proportional to the particle size up to a particle size of approximately 5.5 nm, which corresponds to approximately 7 atomic percent Si.

[0139] While not bound by any theory, the increase in hardness and modulus may be related to the grain boundary hardening effect, where increasing the Si content reduces grain size and therefore increases grain boundary density. Grain boundaries can interact with each other to form a dense three-dimensional network of grain boundaries. Under such circumstances, the movement of grains under external force becomes extremely restricted due to the three-dimensional network of grain boundaries, resulting in increased hardness and modulus. However, as shown in the figure, this effect peaks around a Si content of 7 atomic percent, and above that, hardness and modulus actually decrease. While not bound by any theory, this may be attributable to an increase in the proportion of amorphous phase, which can reduce the grain boundary hardening effect. Therefore, increasing the Si content to improve the values ​​of hardness and modulus may be effective up to a critical value of about 7 atomic percent. In various embodiments, the TiSiN thin film according to the embodiment has a Si content exceeding any of the values ​​listed in Table 1 to achieve the modulus and hardness described here. In certain embodiments, the Si content does not exceed 7%.

[0140] Figure 36 shows low-resolution and high-resolution cross-sectional transmission electron microscope images obtained from a high-aspect-ratio structure lined with a TiSiN thin film according to the embodiment. The high-aspect-ratio structure is similar to that described above with respect to Figures 25A-25B. According to the embodiment, the TiSiN thin film with high elastic modulus and hardness described herein also exhibits excellent uniformity and step coverage, which can exceed 85% when measured using the cross-sectional transmission electron microscope image of the high-aspect-ratio structure shown in Figure 36. As an example of a method for measuring step coverage, the distances indicated by (upper top surface) TT, (upper left side) TS-L, (upper right side) TS-R, (bottom left side) BS-L, and (bottom right side) BS-R were measured by averaging multiple measurements using an image processing software program. For the specific high aspect ratio structure shown in Figure 36, the measured values ​​were TT=12.87nm, TS-L=11.96nm, TS-R=11.81nm, BS-L=10.67nm, and BS-R=11.11nm. The step coverage was calculated as SC=(BS-L+BS-R) / (TS-L+TS-R)=21.78nm / 23.77nm=92%. Alternatively, the step coverage can be calculated as (BS-L+BS-R)² / (TT)=10.89 / 12.87 nm / 23.77 nm=85%.

[0141] According to the embodiment, the TiSiN diffusion barrier deposited for high modulus and high hardness may have a root mean square (RMS) surface roughness of 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or a value within the range defined by any of these values, or less. Reducing the RMS roughness can, conversely, improve the conformability of the diffusion barrier layer. Figure 37A is an atomic force microscope image of a TiSiN thin film deposited according to the embodiment. The measured RMS roughness was 0.27 nm. Figure 37B is an atomic force microscope image of a comparative example TiN thin film. For a TiN thin film of similar thickness, the RMS roughness was significantly larger at 0.67 nm.

[0142] [Another Embodiment I] 1. A method for forming a diffusion barrier, wherein the method is The process involves forming a thin film containing either TiSiN or TiAlN, or both, on a semiconductor substrate by exposing it to multiple vapor-phase deposition cycles under a pressure in a reaction chamber greater than 1 Torre. The vapor deposition cycle includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to either or both of a silicon (Si) precursor or an aluminum (Al) precursor. The semiconductor substrate has a surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor phase deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 2. The method according to Embodiment 1, wherein the surface topography has a plurality of trenches or vias having an aspect ratio greater than 5. 3. The method according to Embodiment 2, wherein the number and size of the trenches or vias are such that the ratio of the surface area exceeds 20. 4. The method according to Embodiment 1, wherein forming the thin film involves exposing the semiconductor substrate to one or more vapor-phase deposition cycles under a pressure of 3 to 10 tors in a reaction chamber. 5. The method according to Embodiment 1, wherein one or more of the Ti precursors, the N precursors, and the Si or Al precursors are liquids at room temperature and atmospheric pressure. 6. Exposing the semiconductor substrate to one or more vapor phase deposition cycles, The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, Each of the first deposition phases includes exposure to the Ti precursor and exposure to the N precursor, The method according to Embodiment 1, wherein each of the second deposition faces includes exposure to one or both of the Si precursor or the Al precursor. 7. The method according to Embodiment 6, wherein at least one of the second deposition phases further comprises further exposure to the N precursor. 8. The method according to Embodiment 6, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the thin film is at least partially amorphous. 9. The method according to Embodiment 8, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is equal to or less than 15:1. 10. The method according to Embodiment 8, wherein the thin film contains TiSiN having a silicon concentration of more than about 10 atomic percent. 11. The method according to Embodiment 6, wherein the number of times the first deposition phase and the second deposition phase are such that the thin film is substantially homogeneous in the depth direction of the layer. 12. The method according to Embodiment 11, wherein the number of times the first deposition phase or the second deposition phase does not exceed approximately 50 cycles. 13. The method according to Embodiment 1, wherein the thin film contains TiSiN, and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 14. The method according to Embodiment 1, wherein the thin film contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum. 15. The method according to Embodiment 1, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C. 16. A method for forming a diffusion barrier, A semiconductor substrate is provided with multiple holes formed thereon, This includes lining the surface of the pores with a diffusion barrier layer containing at least partially amorphous TiSiN or TiAlN, or both, by exposing the semiconductor substrate to multiple vapor-phase deposition cycles, The hole has a dielectric sidewall and an aspect ratio greater than 5. A method wherein the vapor phase deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 17. The method according to embodiment 16, wherein the aspect ratio of the hole is greater than 5. 18. The method according to Embodiment 17, wherein the surface of the hole is lined such that the ratio of the thickness of the diffusion barrier formed in the lower 25% of the height of the hole to the upper 25% of the height of the hole is greater than 0.6. 19. The method according to Embodiment 16, wherein the number and size of the holes are set such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 20. The method according to Embodiment 16, wherein lining the surface of the holes involves exposing the semiconductor substrate to the vapor deposition cycle under a pressure of 3 to 10 Torr in a reaction chamber. 21. The method according to embodiment 16, wherein the hole further has an exposed semiconductor bottom surface. 22. Exposing the semiconductor substrate to the vapor deposition cycle, The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, The first deposition phase includes exposure to the Ti precursor and exposure to the N precursor, The method according to Embodiment 16, wherein the second deposition face includes exposure to either or both of the Si precursor or the Al precursor. 23. The method according to Embodiment 22, wherein the second deposition phase further includes further exposure to the N precursor. 24. The method according to Embodiment 22, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the diffusion barrier layer is at least partially amorphous. 25. The method according to Embodiment 24, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, or 15:1. 26. The method according to Embodiment 22, wherein the number of times the first deposition phase and the number of times the second deposition phase are such that the diffusion barrier layer is substantially homogeneous in the depth direction of the layer. 27. The method according to Embodiment 26, wherein the number of times the first deposition phase or the second deposition phase does not exceed approximately 50 cycles. 28. The method according to Embodiment 22, wherein the number of times the first deposition phase and the number of times the second deposition phase are performed are such that the diffusion barrier layer has a nanolaminate structure. 29. The method according to Embodiment 16, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 30. The method according to Embodiment 16, wherein the diffusion barrier layer contains TiSiN, and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 31. The method according to Embodiment 16, wherein the diffusion barrier layer contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum. 32. The method according to Embodiment 16, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C. 33. A method for forming a thin film, wherein the method is The process involves forming a thin film containing TiSiN and / or TiAlN on a semiconductor substrate by exposing it to multiple vapor-phase deposition cycles under a pressure in a reaction chamber higher than 5 Torre. A method wherein the vapor deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. 34. The method according to Embodiment 33, wherein the pressure inside the reaction chamber is less than 10 Torr. 35. The method according to Embodiment 33, wherein the semiconductor substrate has a topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor-phase deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 36. The method according to Embodiment 35, wherein the semiconductor substrate has a plurality of trenches or vias formed thereon, and the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall. 37. Exposing the semiconductor substrate to one or more vapor phase deposition cycles The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, The first deposition phase includes exposure to the Ti precursor and exposure to the N precursor, The method according to Embodiment 33, wherein the second deposition phase includes exposure to either the Si precursor or the Al precursor. 38. The method according to embodiment 37, wherein the second deposition phase further comprises further exposure to the N precursor. 39. The method according to Embodiment 37, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the thin film is at least partially amorphous. 40. The method according to Embodiment 39, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is equal to or less than 15:1. 41. The method according to Embodiment 37, wherein the number of times the first deposition phase and the second deposition phase are such that the diffusion barrier layer is substantially homogeneous in the depth direction of the layer. 42. The method according to Embodiment 41, wherein the number of times the first deposition phase and the number of times the second deposition phase do not exceed approximately 50 cycles. 43. The method according to Embodiment 33, wherein the thin film contains TiSiN, and the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 44. The method according to Embodiment 33, wherein the thin film contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum. 45. The method according to Embodiment 33, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C. 46. ​​A semiconductor substrate having a plurality of trenches or vias thereon, wherein the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall surface, A semiconductor structure comprising a diffusion barrier layer conformally lining the surface of the trench or via, the diffusion barrier layer comprising one or both of TiSiN and TiAlN, wherein the diffusion barrier layer is at least partially amorphous. 47. The semiconductor structure according to embodiment 46, wherein the aspect ratio of the trench or via is greater than 5. 48. The semiconductor structure according to Embodiment 47, wherein the diffusion barrier layer conformally lining the surface is such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the pore to the upper 25% of the height of the pore exceeds 0.6. 49. The semiconductor structure according to Embodiment 46, wherein the area density of the trenches or vias is such that the ratio of the surface area on which the diffusion barrier layer is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 50. The semiconductor structure according to Embodiment 49, wherein the ratio of the surface areas exceeds 100. 51. The semiconductor structure according to Embodiment 46, wherein the diffusion barrier layer is substantially completely amorphous. 52. The semiconductor structure according to Embodiment 46, wherein the diffusion barrier layer is substantially homogeneous in the depth direction of the pores. 53. The semiconductor structure according to Embodiment 46, wherein the diffusion barrier layer has a nanolaminate structure. 54. The semiconductor structure according to Embodiment 46, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer. 55. The semiconductor structure according to Embodiment 46, wherein the diffusion barrier layer contains TiSiN having a silicon concentration of more than about 10 atomic percent. 56. The semiconductor structure according to embodiment 46, wherein the trench or via further has a semiconductor bottom surface. 57. The semiconductor structure according to Embodiment 46, wherein the trenches or vias are filled with tungsten or copper. 58. The semiconductor structure according to Embodiment 46, wherein the diffusion barrier layer has a thickness of about 1 to 10 nm. 59. The semiconductor structure according to Embodiment 46, wherein the trench or via has a width of about 10 to 1000 nm. 60. The semiconductor structure according to Embodiment 23, wherein the diffusion barrier layer has an electrical resistivity of less than approximately 1600 μΩ·cm.

[0143] [Another Embodiment II] 1. A method for forming a diffusion barrier containing TiSiN, wherein the method is This includes alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases, Exposing the semiconductor substrate to the first deposition phase once or more times includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, A method for exposing a semiconductor substrate to one or more of the second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor without intervening exposure to an N precursor between them, and subsequently exposing the semiconductor substrate to an N precursor. 2. A method for forming a diffusion barrier containing TiSiN, wherein the method is This includes alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases, Exposing the semiconductor substrate to the first deposition phase once or more times includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, A method for exposing a semiconductor substrate to one or more of the second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. 3. A method for forming a diffusion barrier containing TiSiN, wherein the method is This includes alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases, Exposing the semiconductor substrate to the first deposition phase once or more times includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, Exposing the semiconductor substrate to the second deposition phase once or more times includes exposing the semiconductor substrate to a Ti precursor during the Ti precursor exposure time, then to a silicon (Si) precursor during the Si precursor exposure time, and then to an N precursor, and A method wherein the ratio of the Si precursor exposure time to the Ti precursor exposure time is between 2 and 130. 4. The method according to any of the above embodiments, wherein the diffusion barrier formed using the above method has a resistivity of 2000 μΩ·cm or less. 5. The method according to any of the above embodiments, wherein the diffusion barrier formed using the method has a resistivity at least 500 μΩ·cm lower than that of a diffusion barrier formed using the same method, except that the semiconductor substrate is exposed to the Ti precursor as part of one or more second deposition phases. 6. The semiconductor substrate has an aspect ratio greater than 50, and the diffusion barrier is formed as follows: The method according to any of the above embodiments, wherein the step of forming a diffusion barrier includes lining the surface of the pore such that the ratio of the thickness of the diffusion barrier formed in the lower 25% of the pore height to the upper 25% of the pore height is greater than 0.9. 7. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to an N precursor as the final precursor of one or more first deposition phases. 8. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor as the first precursor of one or more second deposition phases. 9. The method according to any of the above embodiments, wherein the exposure of the semiconductor substrate to the Ti precursor as the first precursor in the second deposition phase follows immediately after the exposure of the semiconductor substrate to the N precursor as the last precursor in the first deposition phase, without intervention of exposure to the precursor. 10. The method according to any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor to the exposure time of the semiconductor substrate to the Ti precursor in the second deposition phase is greater than 2. 11. The method according to any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor to the exposure time of the semiconductor substrate to the Ti precursor in the second deposition phase is less than 130. 12. The method according to any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Si precursor to the exposure time of the semiconductor substrate to the Ti precursor in the second deposition phase is between 2 and 130. 13. The method according to any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the Ti precursor in the second deposition phase to the exposure time of the semiconductor substrate to the Ti precursor in the first deposition phase is between 3 and 34. 14. The method according to any of the above embodiments, wherein the ratio of the exposure time of the semiconductor substrate to the N precursor in the second deposition phase to the exposure time of the semiconductor substrate to the N precursor in the first deposition phase is between 5 and 50. 15. The method according to any of the above embodiments, wherein in the second deposition phase, the exposure time for the semiconductor substrate to the Si precursor is longer than 3 seconds, and the exposure time for the semiconductor substrate to the Ti precursor is less than 2 seconds. 16. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases, the exposure being performed under a pressure in a reaction chamber greater than 1 Torrell. 17. The method according to any of the above embodiments, wherein the semiconductor substrate has a surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more first deposition phases and one or more second deposition phases to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 18. The method according to Embodiment 17, wherein the surface topography includes a plurality of trenches or vias having an aspect ratio greater than 5. 19. The method according to Embodiment 17 or 18, wherein the number and size of the trenches or vias are such that the ratio of the surface area exceeds 20. 20. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases, the exposure being performed under a pressure in a reaction chamber of 3 to 10 Torr. 21. The method according to any of the above embodiments, wherein the ratio of the number of first deposition phases to the number of second deposition phases is such that the diffusion barrier is at least partially amorphous. 22. The method according to any of the above embodiments, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed is greater than 3. 23. The method according to any of the above embodiments, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed is 3 to 60. 24. The method according to any of the above embodiments, wherein the diffusion barrier comprises TiSiN having a silicon content of more than 5 atomic percent. 25. The method according to any of the above embodiments, wherein the diffusion barrier comprises TiSiN having a silicon content of 5 to 30 atomic percent. 26. The method according to any of the above embodiments, wherein the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 27. The method according to any of the above embodiments, wherein the Ti precursor comprises TiCl4. 28. The method according to any of the above embodiments, wherein the N precursor is NH3. 29. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to a vapor deposition cycle at a substrate temperature of 400°C to 600°C. 30. The method according to any of the above embodiments, wherein the number of times the first deposition phase and the number of times the second deposition phase are provided such that the diffusion barrier layer is substantially uniform in the depth direction of the layer. 31. The method according to Embodiment 30, wherein the number of times the first deposition phase and the number of times the second deposition phase do not exceed approximately 50. 32. The method according to any of the above embodiments, wherein the number of times the first deposition phase and the number of times the second deposition phase are provided such that the diffusion barrier layer has a nanolaminate structure comprising alternating TiN and TiSiN layers. 33. The method according to Embodiment 32, wherein the number of times one or both of the first deposition phase and the second deposition phase exceeds approximately 50. 34. The method according to Embodiment 32 or 33, wherein the thickness of one or both of the TiN layer and the TiSiN layer exceeds 1.5 nm. 35. The method according to any one of embodiments 32 to 34, wherein the nanolaminate has TiSiN layers between TiN layers. 36. The method according to any of the above embodiments, wherein the semiconductor substrate has a plurality of holes formed thereon, the holes have an aspect ratio of more than 5 with respect to the dielectric sidewall surface, and the diffusion barrier is formed by lining the surface of the holes. 37. The method according to Embodiment 36, wherein lining the hole is such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the hole to the thickness of the diffusion barrier layer formed in the upper 25% of the height of the hole is greater than 0.8. 38. The method according to Embodiment 37, wherein the Si precursor is SiH2Cl2 and the ratio exceeds 83%. 39. The method according to Embodiment 37, wherein the Si precursor is SiH3Cl and the ratio exceeds 86%. 40. The method according to Embodiment 37, wherein the Si precursor is Si3Cl8 and the ratio exceeds 86%. 41. The method according to any one of embodiments 38 to 40, wherein the aspect ratio exceeds 50. 42. The method according to any of the above embodiments, wherein the number and size of the holes are provided such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the corresponding surface area of ​​the unpatterned semiconductor substrate is greater than 2. 43. The method according to any of the above embodiments, wherein lining the surface of the pores is performed by exposing the semiconductor substrate to a vapor deposition cycle under a pressure of 3 to 10 tors in a reaction chamber. 44. The method according to any of the above embodiments, wherein the pore further includes an exposed semiconductor bottom surface. 45. The method according to any of the above embodiments, wherein one or more first deposition phases do not overlap with one or more second deposition phases. 46. ​​The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to a Ti precursor, a Si precursor, and an N precursor during one or more second deposition phases, thereby unsaturating the surface of the semiconductor substrate. 47. The method according to Embodiment 42, wherein the diffusion barrier has a resistivity greater than 10% than a reference diffusion barrier containing TiSiN obtained using the same method, except that the diffusion barrier contains TiSiN and is unsaturated. 48. Nanolaminates comprising alternating TiN-rich regions or layers and Si-rich and / or Al-rich regions or layers or SiN / AlN-rich regions or layers.

[0144] [Another Embodiment III] 1. A method for forming a diffusion barrier, wherein the method is The method involves alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having an elastic modulus exceeding 290 GPa and a Si content exceeding 2.7 atomic percent. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and A method for exposing the semiconductor substrate to one or more second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. 2. A method for forming a diffusion barrier, wherein the method is The method involves alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having a hardness exceeding 20 GPa and a Si content exceeding 2.7 atomic percent. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and A method for exposing the semiconductor substrate to one or more second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. 3. A method for forming a diffusion barrier, wherein the method is The method involves alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having a crystalline structure in which the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum of the diffusion barrier exceeds 0.4, and a Si content exceeding 2.7 atomic percent. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and A method for exposing the semiconductor substrate to one or more second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. 4. A method for forming a diffusion barrier, wherein the method is The method involves alternately exposing a semiconductor substrate to one or more first deposition phases and one or more second deposition phases to form a diffusion barrier containing TiSiN having an average particle size of less than approximately 6.5 nm and a Si content of more than 2.7 atomic percent. Exposing the semiconductor substrate to one or more first deposition phases includes alternately exposing the semiconductor substrate to a titanium (Ti) precursor and a nitrogen (N) precursor, and A method for exposing the semiconductor substrate to one or more second deposition phases, comprising sequentially exposing the semiconductor substrate to a Ti precursor, followed by a silicon (Si) precursor, followed by an N precursor. 5. The method according to any of the above embodiments, wherein the diffusion barrier has a Si content of 2.7 to 9 atomic percent. 6. The method according to any of the above embodiments, wherein the diffusion barrier has a Si content of 2.7 to 7 atomic percent. 7. The method according to any of the above embodiments, wherein the diffusion barrier has an elastic modulus of 290 to 350 GPa. 8. The method according to any of the above embodiments, wherein the diffusion barrier has a hardness of 20 to 40 GPa. 9. The method according to any of the above embodiments, wherein the diffusion barrier has a crystalline structure in which the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum is 0.4 to 4.5. 10. The method according to any of the above embodiments, wherein the diffusion barrier has a nanocrystalline structure with an average particle size of about 5.0 to 6.5 nm. 11. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor and a silicon (Si) precursor without interposing an N precursor between them, and subsequently exposing the semiconductor substrate to an N precursor. 12. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases comprises sequentially exposing the semiconductor substrate to a Ti precursor as the first precursor, followed by a silicon (Si) precursor, followed by an N precursor as the last precursor. 13. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor during the Ti precursor exposure time, then to a silicon (Si) precursor during the Si precursor exposure time, and then to an N precursor, and the ratio of the Ti precursor exposure time to the Si precursor exposure time is 0 to 1. 14. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor during a Ti precursor exposure time of 0 to 1 second, and then to a silicon (Si) precursor during a Si precursor exposure time of 1 to 10 seconds. 15. The method according to any of the above embodiments, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed is greater than 10. 16. The method according to any of the above embodiments, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed is 10 to 50. 17. The method according to any of the above embodiments, wherein the semiconductor substrate has holes with an aspect ratio of 5 or more, and the diffusion barrier is formed such that the ratio of the thickness of the diffusion barrier formed in the lower 25% of the height of the hole to the thickness of the diffusion barrier formed in the upper 25% of the height of the hole is greater than 0.80. 18. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more first deposition phases includes exposing the semiconductor substrate to an N precursor as the final precursor. 19. The method according to any of the above embodiments, wherein exposing the semiconductor substrate to one or more second deposition phases includes exposing the semiconductor substrate to a Ti precursor as the first precursor. 20. The method according to any of the above embodiments, wherein the exposure of the semiconductor substrate to the Ti precursor as the first precursor of the second deposition phase follows immediately after the exposure of the semiconductor substrate to the N precursor as the last precursor of the first deposition phase, without intervening exposure to the N precursor. 21. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases, the exposure being performed under a pressure in a reaction chamber greater than 1 Torrell. 22. The method according to any of the above embodiments, wherein the semiconductor substrate has a surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more first deposition phases and one or more second deposition phases to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 23. The method according to Embodiment 22, wherein the surface topography has a plurality of trenches or vias having an aspect ratio greater than 5. 24. The method according to Embodiment 22 or 23, wherein the number and size of the trenches or vias are arranged such that the ratio of the surface area exceeds 20. 25. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to one or more first deposition phases and one or more second deposition phases, the exposure being performed under a pressure in a reaction chamber of 3 to 10 Torr. 26. The method according to any of the above embodiments, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the diffusion barrier is at least partially amorphous. 27. The method according to any of the above embodiments, wherein the Si precursor is a compound selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH2Cl, Si2Cl6, and Si3Cl8. 28. The method according to any of the above embodiments, wherein the Ti precursor comprises TiCl4. 29. The method according to any of the above embodiments, wherein the N precursor is NH3. 30. The method according to any of the above embodiments, wherein the semiconductor substrate is exposed to a vapor deposition cycle at a substrate temperature of 400°C to 600°C. 31. The method according to any of the above embodiments, wherein the number of times the first deposition phase and the number of times the second deposition phase are provided such that the diffusion barrier layer is substantially uniform in the depth direction of the layer. 32. The method according to any of the above embodiments, wherein the semiconductor substrate has a plurality of holes formed thereon, the holes have an aspect ratio of more than 5 with respect to the dielectric sidewall surface, and the diffusion barrier is formed by lining the surface of the holes. 33. The method according to Embodiment 32, wherein lining the surface of the hole is conformally lined such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the hole to the thickness of the diffusion barrier layer formed in the upper 25% of the height of the hole is greater than 0.8. 34. The method according to Embodiment 32 or 33, wherein the number and size of the holes are provided such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the corresponding surface area of ​​the unpatterned semiconductor substrate is greater than 2. 35. The method according to any one of embodiments 32 to 34, wherein lining the surface of the holes involves exposing the semiconductor substrate to a vapor deposition cycle under a pressure of 3 to 10 tors in a reaction chamber. 36. The method according to any of the above embodiments, wherein the hole further includes an exposed semiconductor bottom surface. 37. Semiconductor structure, A plurality of trenches or vias are formed thereon, and the trenches or vias are a dielectric sidewall surface and a semiconductor substrate having an aspect ratio greater than 5. A semiconductor structure comprising a diffusion barrier layer containing TiSiN, conformally lining the surface of the trench or via, having a Si content of 2.7 to 9 atomic percent and an elastic modulus of 290 to 350 GPa. 38. Semiconductor structure, A plurality of trenches or vias are formed thereon, and the trenches or vias are a dielectric sidewall surface and a semiconductor substrate having an aspect ratio greater than 5. A semiconductor structure comprising a diffusion barrier layer containing TiSiN, conformally lining the surface of the trench or via, having a Si content of 2.7 to 9 atomic percent and a hardness of 20 to 40 GPa. 39. Semiconductor structure, A plurality of trenches or vias are formed thereon, and the trenches or vias are a dielectric sidewall surface and a semiconductor substrate having an aspect ratio greater than 5. A semiconductor structure comprising a diffusion barrier layer containing TiSiN, conformally lining the surface of the trench or via, having a Si content of 2.7 to 9 atomic percent, and a crystalline structure in which the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum is 0.4 to 4.5. 40. Semiconductor structure, A plurality of trenches or vias are formed thereon, and the trenches or vias are a dielectric sidewall surface and a semiconductor substrate having an aspect ratio greater than 5. A semiconductor structure comprising a diffusion barrier layer containing TiSiN, conformally lining the surface of the trench or via, and having a nanocrystalline structure with a Si content of 2.7 to 9 atomic percent and an average particle size of approximately 5.0 to 6.5 nm. 41. The semiconductor structure according to any one of embodiments 37 to 41, wherein the Si content is 2.7 to 7 atomic percent. 42. The semiconductor structure according to any one of embodiments 37 to 41, wherein the aspect ratio of the trench or via is greater than 10. 43. The semiconductor structure according to any one of embodiments 37 to 42, wherein the diffusion barrier layer conformally lining the surface is provided such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the trench or via to the thickness of the diffusion barrier layer formed in the upper 25% of the height of the trench or via exceeds 0.8. 44. The semiconductor structure according to any one of embodiments 37 to 43, wherein the area density of the trenches or vias is set such that the ratio of the surface area on which the diffusion barrier is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2. 45. A semiconductor structure according to any one of embodiments 37 to 44, wherein the ratio of the surface areas exceeds 100. 46. ​​The semiconductor structure according to any one of embodiments 37 to 45, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 0.3 nm. 47. The semiconductor structure according to any one of embodiments 37 to 46, wherein the trench or via further has a semiconductor bottom surface. 48. The semiconductor structure according to any one of embodiments 37 to 47, wherein the trenches or vias are filled with tungsten or copper. 49. The semiconductor structure according to any one of embodiments 37 to 44, wherein the diffusion barrier has a thickness of about 1 to 10 nm. The semiconductor structure according to any one of embodiments 37 to 48. 50. The semiconductor structure according to any one of embodiments 37 to 49, wherein the trench or via has a width of about 10 to 1000 nm. 51. The semiconductor structure according to any one of embodiments 37 to 50, wherein the diffusion barrier layer has an electrical resistivity of less than approximately 1600 μΩ·cm.

[0145] Although the present invention has been described herein with reference to specific embodiments, these embodiments are not intended to limit the invention but are provided for illustrative purposes only. It will be obvious to those skilled in the art that modifications and improvements can be made without departing from the spirit and scope of the invention.

[0146] Such simple modifications and improvements to the various embodiments disclosed herein fall within the scope of the disclosed technology, and the specific scope of the disclosed technology will be further defined by the appended claims.

[0147] It will be understood from the above that any one feature of an embodiment can be combined with or substituted for any other feature of an embodiment.

[0148] Unless the context clearly requires otherwise, throughout this specification and the claims, words such as “comprise,” “consisting,” “include,” and “including” shall be interpreted in a comprehensive sense, that is, “including but not limited to,” as opposed to an exclusive or exhaustive sense. The term “coupled,” as commonly used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Similarly, the term “connected,” as commonly used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Furthermore, in this specification, “herein,” “above,” “below,” and similar terms shall refer to this specification as a whole, not to any particular part thereof. In addition, in the above description of modes for carrying out the invention, words used singular or plural may include plural or singular, respectively, where the context permits. The word "or" referring to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0149] Furthermore, conditional words used herein, particularly “can,” “could,” “might,” “may,” “eg,” “for example,” and “such as,” are generally intended to convey that a particular embodiment includes certain features, elements, and / or states, while other embodiments do not, unless otherwise specified or understood within the context in which they are used. Therefore, such conditional words are generally not intended to suggest that features, elements, and / or states are required in any way in one or more embodiments, or that these features, elements, and / or states are included in or performed in any particular embodiment.

[0150] While specific embodiments have been described, these embodiments are presented for illustrative purposes only and are not intended to limit the scope of the disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications to the forms of methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while a function is shown in a given mechanism, in an alternative embodiment, a similar function may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions can be performed in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. The various functions and processes described above may be performed independently of each other or combined in a variety of ways. All possible combinations and subcombinations of the features of the disclosure are intended to fall within the scope of the disclosure.

Claims

1. It is a semiconductor structure, A semiconductor substrate having multiple trenches or vias formed thereon, wherein the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall surface, The trench or via surface is conformally lined with a diffusion barrier layer containing TiSiN and having a Si content of 2.7 to 9 atomic percent, The aforementioned diffusion barrier layer is Modulus of elasticity of 290-350 GPa, Hardness of 20-40 GPa, A crystal structure in which the ratio of the area under the (002) peak to the sum of the areas under the (111) and (222) peaks in the oblique incidence X-ray diffraction spectrum is 0.4 to 4.5, or A semiconductor structure having one or more nanocrystalline structures with an average particle size of 5.0 to 6.5 nm.

2. The semiconductor structure according to claim 1, wherein the Si content is 2.7 to 7 atomic percent.

3. The semiconductor structure according to claim 1, wherein the aspect ratio of the trench or via exceeds 10.

4. The semiconductor structure according to claim 1, wherein the diffusion barrier layer conformally lines the surface of the trench or via such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the trench or via to the thickness of the diffusion barrier layer formed in the upper 25% of the height of the trench or via exceeds 0.

8.

5. The semiconductor structure according to claim 1, wherein the area density of the trenches or vias is set such that the ratio of the surface area on which the diffusion barrier layer is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2.

6. The semiconductor structure according to claim 5, wherein the ratio of the surface areas exceeds 100.

7. The semiconductor structure according to claim 1, wherein the root mean square surface roughness of the diffusion barrier layer is less than 0.3 nm.

8. The semiconductor structure according to claim 1, wherein the trench or via further has a semiconductor bottom surface.

9. The semiconductor structure according to claim 1, wherein the trench or via is filled with tungsten or copper.

10. The semiconductor structure according to claim 1, wherein the diffusion barrier layer has a thickness of 1 to 10 nm.

11. The semiconductor structure according to claim 1, wherein the trench or via has a width of 10 to 1000 nm.

12. The semiconductor structure according to claim 1, wherein the diffusion barrier layer has an electrical resistivity of less than 1600 μΩ·cm.

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