Hybrid delay synchronization circuit

Abstract

To provide a delay synchronization circuit that enables high-speed and stable operation. [Solution] The hybrid delay synchronization circuit includes a digital control loop that includes a digital phase comparator with a dead zone, and an analog control loop that includes an analog phase comparator that operates in the dead zone.

Description

[Technical Field]

[0001] The present invention relates to a hybrid delay synchronization circuit comprising a digital control loop and an analog control loop. [Background technology]

[0002] In recent years, software-defined radio (Software Defined Radio) has attracted attention, and receivers such as N-pass filters and mixer-first systems have been proposed. These circuits require a multiphase clock. Methods for generating a multiphase clock include using registers, as described in Non-Patent Document 1, and using a delay-locked loop (DLL), as described in Non-Patent Document 2. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation,” X.Gao,B.Nauta, E.Klumperink, Circuits and Systems II: Express Briefs, IEEE Trans., vol.55, no.3, pp.244-248, Mar. 2008. [Non-Patent Document 2] “Clock buffer chip with multiple target automatic skew compensation,” RB Watson, Jr., RBIknaian, IEEE J. Solid-State Circuits, vol.30, pp.1267-1276, Nov. 1995. [Overview of the project] [Problems that the invention aims to solve]

[0004] Multiphase clock generation circuits using registers are said to have better jitter characteristics than those using DLLs, but the frequency f CK To create an N-phase clock, N × f CK (N: odd number) or N × f CK A reference clock frequency of / 2 (N: an even number) is required.

[0005] When a wide frequency range is required, steady-state frequency fluctuations due to increased loop gain are a problem in analog-controlled DLLs. Digital-controlled DLLs (fully digital DLLs) can expand the range without changing the loop gain, thus reducing steady-state frequency fluctuations, but require high resolution (increased control bits) and a longer time for the output to converge.

[0006] This invention has been made in view of the circumstances described above, and its purpose is to provide a delay synchronization circuit that can operate at high speed and stably. [Means for solving the problem]

[0007] In other words, the present invention relates to a hybrid delay synchronization circuit having a digital control loop including a digital phase comparator with a dead zone, and an analog control loop including an analog phase comparator operating in the dead zone. [Effects of the Invention]

[0008] The hybrid delay synchronization circuit of the present invention enables high-speed and stable operation with a relatively simple structure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of a delay synchronization circuit. [Figure 2] This is a block diagram of a phase comparator. [Figure 3] This is a timing chart diagram used to explain the operation of the control loop. [Figure 4] It is a block diagram of a fully digital delay synchronization circuit. [Figure 5] It is a graph showing the relationship between the number of control bits and the normalized frequency deviation. [Figure 6] It is a block diagram of a hybrid DLL. [Figure 7A] It is a block diagram of Simulink. [Figure 7B] It is a diagram showing the output result of MATLAB (registered trademark) simulation. [Figure 8A] It is a block diagram of a digital phase comparator. [Figure 8B] It is a block diagram of an analog phase comparator. [Figure 9] It is a model diagram of a counter with a trigger. [Figure 10] It is a model diagram of a charge pump and a loop filter. [Figure 11] It is a model diagram of a delay line having a frequency counter and a frequency limit. [Figure 12] It is a model diagram of a four-stage delay line. [Figure 13] It is a MATLAB simulation model diagram. [Figure 14] It is a graph showing the output waveforms of a counter and a phase comparator. [Figure 15] It is a graph showing the transition of the output frequency of a hybrid DLL. [Figure 16] It is a graph showing the output waveforms of a reference clock and a hybrid DLL. [Figure 17] It is a graph showing the output waveforms of each phase of a hybrid DLL.

Embodiments for Carrying Out the Invention

[0010] The present invention relates to a hybrid delay synchronization circuit having a digital control loop including a digital phase comparator with a dead zone, and an analog control loop including an analog phase comparator operating in the dead zone. Specifically, the hybrid delay synchronization circuit of the present invention is a hybrid control type DLL configured by combining an analog control loop and a digital control loop, and can be configured to have a dead zone of phase difference for comparison with the phase comparator for the digital control loop, to operate the phase comparator for the analog control loop within this dead zone, and to stop the phase comparator for the analog control loop outside the dead zone. The dead zone refers to the range of phase differences in which the phase comparator cannot detect the input phase difference and therefore cannot perform phase comparison. Preferably, the phase difference of the dead zone is twice or more the control range of the phase difference of the analog phase comparator.

[0011] This hybrid delay-synchronization circuit enables switching between analog and digital control loops with a relatively simple structure. Specifically, by reducing the number of control bits in the digital control phase comparator and creating a wider dead zone, the circuit switches to the analog control loop when the digital control phase comparator enters the dead zone. This allows for rapid frequency transition to the target frequency and subsequent frequency stabilization at the target frequency.

[0012] In this delay-synchronization circuit, the analog control loop further includes a charge pump and a loop filter, and the digital control loop may further include at least one of a shift register or a counter. This allows for the construction of a hybrid delay-synchronization circuit with a simple configuration.

[0013] Furthermore, in this delay synchronization circuit, it is preferable that the control frequency is coarsely adjusted in the digital control loop by coarsely adjusting the delay time, and that the control frequency is finely adjusted in the analog control loop by finely adjusting the delay time to fill the gaps between the coarsely adjusted control frequencies in the digital control loop. In other words, by coarsely controlling the frequency with digital control and then finely controlling the frequency gaps with analog control, the number of control bits can be reduced compared to the case of digital control alone, the digital control circuit can be simplified, and the range of controllable frequencies can be widened compared to the case of analog control alone. As a result, the number of control bits in the digital control loop can be reduced, the circuit size can be reduced, and the circuit can be miniaturized and power-efficient.

[0014] In digital control loops, digital phase comparators have a dead zone where they cannot respond even if there is a phase difference, causing frequency fluctuations. To reduce frequency fluctuations, it is necessary to increase the number of control bits, which increases the circuit size and power consumption. By reducing the number of control bits in the digital control phase comparator, creating a wider dead zone, and switching to an analog control loop when the digital control phase comparator enters the dead zone, it is possible to rapidly transition the frequency to the target frequency and stabilize the frequency at the target frequency. [Examples]

[0015] The following describes various control schemes for DLLs. Specifically, we will describe a control scheme using an analog discrete-time control loop, as well as a control scheme using a digital control loop for an all-digital DLL. These hybrid control schemes, which combine analog and digital control loops, can reduce steady-state errors and accelerate transient responses.

[0016] [1. Introduction] In recent years, software-defined radio (Software Defined Radio) has attracted attention, and receivers such as N-pass filters and mixer-first systems have been proposed. These circuits require a multiphase clock. Multiphase clocks can be generated using registers or DLLs. Multiphase clock generation circuits using registers are said to have better jitter characteristics than those using DLLs, but the frequency is f CK To create an N-phase clock, N × f CK (N: odd number) or N × f CK A reference clock frequency of / 2 (N: an even number) is required. On the other hand, in a DLL, the output frequency and input frequency are the same, so the requirement for the reference clock is relaxed.

[0017] When a wide frequency range is required, steady-state frequency fluctuations due to increased loop gain are a problem in analog-controlled DLLs. While all-digital DLLs can expand the range without changing the loop gain, thus reducing steady-state frequency fluctuations, they require high resolution (increased control bits). Furthermore, the time it takes for the output to converge also increases. To solve these problems, a hybrid DLL combining analog and digital control loops is preferable. This hybrid DLL achieves switching between analog and digital control loops with a relatively simple structure.

[0018] The following explains the principles and problems of DLLs. Then, an overview of hybrid DLLs is presented, along with simulation results.

[0019] [2.DLL] This section will discuss the principles and problems of DLLs.

[0020] First, a DLL using an analog control loop will be described. FIG. 1 is a block diagram of a DLL using an analog control loop. This DLL is composed of a phase detector, a charge pump, a loop filter, and a delay line. The transfer function of the DLL is defined as T(s)=C ko / C ki When defined as such, the transfer function T(s) is

Equation

[0021] Here, assuming that the charge pump and the loop filter form a lossless integrator,

Equation

Equation

Equation

Equation

[0022] Looking at equations 3 and 5, we see that the order of the DLL's transfer function is determined solely by the order of the loop filter. In other words, if the loop filter is a first-order filter, the DLL will not be unstable.

[0023] The phase comparator used in many DLLs consists of a D flip-flop as shown in Figure 2. As a prerequisite, the two inputs f1 and f2 of the phase comparator are square waves. When the rising edges of f1 and f2 are detected by this D flip-flop, the UP signal and DN signal each become high (logic 1). In the circuit in Figure 2, when f1 rises first, the UP signal becomes high, and the charging current of the charge pump increases the output of the loop filter. Next, when f2 rises, the DN signal becomes high, and the discharge current of the charge pump cancels out the charging current. As a result, the output of the loop filter becomes constant. When both UP and DN are high, the D flip-flop is reset via the NAND gate, and the output becomes low (logic 0). If the time difference (phase difference) between the rising edges of f1 and f2 becomes small, in actual circuits, the D flip-flop will reset before it has fully risen, preventing normal operation. As a result, there is an input range (dead zone) where the phase comparator cannot respond when the phase difference between f1 and f2 is around 0 degrees. To solve the dead zone problem, add a delay to the reset signal.

[0024] A schematic of the time waveforms of these operations is shown in Figure 3. Figure 3 is a timing chart diagram to explain the operation of the control loop. V in the figure CThis is the output signal of the loop filter and the control signal of the delay line. Observing the operation of the phase comparator, the control signal of the delay cell only changes near the rising edge of the input. In other words, it is a discrete control signal, not a continuous-time one. The control loop temporarily ceases to function between the reset of the phase comparator output and the next rising edge of the input. In this case, if the loop gain is large, although the transfer function is theoretically stable, a phenomenon may occur where the transient response of the control signal does not converge. In situations where the amplitude of the control signal is limited, achieving a wider frequency variable range requires high loop gain, so steady-state frequency fluctuations become a problem in conventional DLLs.

[0025] Next, we will explain all digital DLLs.

[0026] All-digital DLLs use a shift register instead of an analog control loop consisting of a charge pump and a loop filter. Figure 4 is a block diagram of an all-digital DLL. The shift register used in all-digital DLLs is called a bidirectional shift register, which shifts the control bits to the right or left according to the signal from the phase comparator. Since the delay time of the delay line is controlled discretely, high resolution (high bit count) of the digital control signal is necessary to suppress frequency fluctuations in the steady state. If the control signal is a thermometer code, increasing the control step lengthens the shift register, and clock propagation delay becomes a problem in the high-frequency bandwidth. If it is necessary to significantly increase the control step, it is better to use a counter instead of a shift register and control it with a binary-weighted code.

[0027] Figure 5 shows the minimum number of control bits and steady-state frequency deviation for all digital DLLs. Figure 5 is a graph showing the relationship between the number of control bits and the normalized frequency deviation. The center frequency of the reference clock is set to f0, the variable range to ±20%, and the frequency deviation is normalized by the reference clock frequency (0.8f0, 1.0f0, 1.2f0). For example, if f0 = 100MHz and the frequency deviation is within 10kHz, the most stringent condition is when the clock frequency is 120MHz (1.2f0), and the normalized frequency deviation is 10kHz / 120MHz = 8.34%. From Figure 5, the required number of control bits is 15 bits, which is not easily achievable. Furthermore, as the range of frequency change increases, a higher number of bits is required to maintain the same frequency deviation.

[0028] [3. Hybrid DLL] Next, we will explain hybrid DLLs.

[0029] To realize a DLL with a wide frequency range and low steady-state frequency error, a combination of an analog control loop using a charge pump and a digital control loop using a shift register or counter can be considered. Here, a DLL using both analog and digital control loops is called a hybrid DLL. A schematic of the proposed hybrid DLL is shown in Figure 6. Figure 6 is a block diagram of the hybrid DLL.

[0030] This hybrid DLL uses two phase detectors with different operation. The analog phase detector is the one shown in Figure 2. The digital phase detector, on the other hand, can only be high at any given time, either UP or DN. It also has no reset function; it determines whether it is high or low at the rising edge of the input and holds until the next rising edge. For example, if the rising edge of IN comes first, UP will be high. If the next rising edge also comes first, the UP signal will remain high. However, if the next rising edge comes first, such as OUT, the UP signal will be low and the DN signal will be high.

[0031] The digital phase comparator has a dead zone; when the input phase difference enters the dead zone, the digital phase comparator's outputs UP and DN go low. The simultaneous low state of UP and DN is detected, and the analog phase comparator is activated (lock detection). When either UP or DN of the digital phase comparator goes high again, the charge pump output is reset, and the analog phase comparator stops. As a result, at any given time, only either the digital control loop or the analog control loop is operating. The digital control loop is used for coarse adjustment and low resolution is sufficient. Furthermore, its large step size allows for high loop gain and fast transient response. On the other hand, the analog control loop is for fine adjustment and covers only a narrow frequency range, allowing for lower charge pump gain and reduced steady-state frequency fluctuations.

[0032] [4. MATLAB Model] To perform functional verification using MATLAB Simulink, a functional block model for the DLL is necessary. This section describes the details of each functional block.

[0033] [4.1 Frequency Switching Reference Clock] A reference clock with a switchable frequency is needed to verify the operation of the DLL. Figure 7A is a Simulink block diagram, and Figure 7B shows the output of a MATLAB simulation. As shown in Figure 7A, Simulink uses two pulse generation blocks and a switch to switch the frequency. Here, as shown in Figure 7B, a single pulse is used for the switching timing. All numerical values ​​are normalized. In the example in Figure 7B, the frequency of the square wave becomes high at time t=10s and maintains that for 20 seconds. The set value is a value normalized to an arbitrary period.

[0034] [4.2 Phase comparator] The phase comparison model is shown in Figures 8A and 8B. Figure 8A is a block diagram of a digital phase comparator. Figure 8B is a block diagram of an analog phase comparator. As shown in Figure 8A, the digital phase comparator consists of a D flip-flop and an AND gate, and a transmission delay is added to the input to create a dead zone. In this embodiment, the dead zone of the digital phase comparator was set to a phase difference 2.4 times the control range of the phase difference of the analog phase comparator to ensure stable operation of the digital phase comparator, but it will also work with a phase difference of 2. As shown in Figure 8B, the trigger of the analog phase comparator is created by the output of the digital phase comparison and an XOR (exclusive OR) gate. The inverted signal of this is used as the reset signal for the charge pump (RST). Since logic blocks such as D flip-flops handle Boolean data, data type conversion is necessary between them and other blocks that handle numerical data. Data type conversion is performed using a convert block.

[0035] [4.3 Triggered Counters] Figure 9 is a model diagram of a triggered counter. The counter integrates +1 or -1 based on the output of a digital phase comparator. The integration is implemented using a lossless integrator with a finite output. Output limitation is achieved using a saturation block. The minimum value is set to 0, and the maximum value is equal to the number of control steps, in accordance with the specifications of the propagation delay block used in the delay line.

number

[0036] [4.4 Charge Pump and Loop Filter] Figure 10 is a model diagram of a charge pump and a loop filter. The charge pump takes the difference of the output signals of the analog phase comparator and integrates it with the loop filter, which is represented by a lossless integration block of 1 / s. stepThis is the value output from the delay line block and is represented by equation 7 below.

[0037]

number

[0038] However, f min This is the minimum frequency of the DLL output, and f max d is the maximum frequency of the DLL output, and N is the number of phases. step This is the delay amount of the delay cell corresponding to 1 LSB of the digital control signal. The delay cell constitutes the delay line. The delay control amount of the analog control loop is 2.4 × d step Set to 1.2 × d, and the center value of the loop filter output is 1.2 × d step Theoretically, these coefficients should be greater than or equal to 1, but the dead zone value must be considered to ensure that the digital phase comparator operates reliably.

[0039] [4.5 Delay Line] Figure 11 is a model diagram of a delay line with a frequency counter and a frequency limiter. The delay cell control signal CTRL controls the delay time t of the delay cell. d This is equivalent to and is expressed in equation 8.

[0040]

number

[0041] The frequency fout of the DLL output is given by the delay time t in Equation 8. d Therefore, it is expressed in Equation 9.

[0042]

number

[0043] Figure 12 is a model diagram of a four-stage delay line. As shown in Figure 12, the delay line consists of four delay cells and assumes a four-phase clock (N=4). The delay cells use variable propagation delay blocks and relay blocks. Although it will operate without the relay blocks, abnormal values ​​may be output until the output of the delay cells is determined.

[0044] [5. Simulation Results] The simulation is performed using MATLAB Simulink. Figure 13 is a MATLAB simulation model diagram. Table 1 shows the simulation parameters. In the MATLAB simulation, the operation of the hybrid DLL is verified using the simulation parameters shown in Table 1. min ,f max The Hz and dead zone values ​​are normalized values. If you change the control bit n, you must also change the dead zone value accordingly. The reference clock is set to switch from 1.1Hz to 0.95Hz.

[0045] [Table 1]

[0046] Figure 14 is a graph showing the output waveforms of the counter and phase comparator. As can be seen from Figure 14, when the digital phase comparator is operating, either D_UP or D_DN goes high, and the counter output changes. At this time, the analog phase comparator stops, and the UP and DN signals remain low. On the other hand, when the digital phase comparator stops, the analog phase comparator operates, and the UP and DN signals are output. From these results, it can be seen that the control loop switches between analog mode and digital mode normally.

[0047] Figure 15 is a graph showing the transition of the hybrid DLL output frequency. In the initial settings, the output beyond the second stage of the delay line is not defined, so around time t=0s, there is an invalid output. At time t=4s, a 1.1Hz reference clock is introduced, and the DLL enters a transient state. First, the digital phase comparator operates, so a large increase in frequency can be observed. The digital phase comparator enters the dead zone, and the system switches to the analog control loop, and the output frequency gradually converges to 1.1Hz. At time t=25s, when the reference clock frequency is changed to 0.95Hz, the digital phase comparator moves out of the dead zone, and the digital control loop operates again. The output frequency rapidly decreases, and when it reaches around 0.95Hz, it gradually converges to 0.95Hz again in the analog control loop. From these results, it can be seen that a fast transient response and a stable steady-state response are obtained.

[0048] Figure 16 is a graph showing the waveforms of the reference clock and the hybrid DLL output. As shown in Figure 16, it can be seen that the DLL output is synchronized with the reference clock when locked.

[0049] Figure 17 is a graph showing the output waveforms of each phase of a hybrid DLL. The figure shows the four-phase output (P1-P4) waveforms of the DLL. From this figure, it can be observed that when synchronized, each phase of the DLL output is shifted by 90 degrees. From these results, it can be seen that the hybrid DLL operates normally under the conditions set up as an example design.

[0050] [6. Conclusion] This study clarifies the problems with DLLs in multiphase clocks requiring a wide frequency range and proposes a hybrid DLL combining analog and digital control. A model of this DLL was created using MATLAB's Simulink, and its operation was verified. The verification results confirmed that the control loop switching and output convergence occurred, demonstrating the DLL's normal operation. Furthermore, the DLL's fast transient response and stable steady-state operation were also confirmed.

[0051] (Other embodiments) The hybrid delay synchronization circuit according to the present invention has been described above based on examples, but the hybrid delay synchronization circuit according to the present invention is not limited to the above examples. Other examples realized by combining any of the components in the above examples, modified examples obtained by applying various modifications to the above examples that a person skilled in the art can conceive of without departing from the spirit of the present invention, and various devices incorporating the above hybrid delay synchronization circuit are also included in the present invention. [Industrial applicability]

[0052] The hybrid delay synchronization circuit of the present invention can be used in various wireless systems, including software-defined radio.

Claims

1. A digital control loop including a digital phase comparator with a dead zone, The analog control loop includes an analog phase comparator that operates in the dead zone, Hybrid delay synchronization circuit.

2. The analog control loop further includes a charge pump and a loop filter. The digital control loop further includes at least one of a shift register or a counter. The hybrid delay synchronization circuit according to claim 1.

3. In the aforementioned digital control loop, the control frequency is coarsely adjusted by coarsely adjusting the delay time. In the analog control loop, the control frequency is finely tuned by fine-tuning the delay time to fill the gaps between the control frequencies that have been coarsely tuned in the digital control loop. The hybrid delay synchronization circuit according to claim 1.

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