Multilayer wiring board

Abstract

The present invention aims to provide a technology that can suppress the occurrence of cracks when using a stiffener. [Solution] The multilayer wiring board of the present invention is a rectangular multilayer wiring board having a first surface on which a semiconductor device is mounted and a second surface opposite to the first surface, wherein the amount of warping of the multilayer wiring board due to the heating and mounting of the semiconductor device occurs in a straight section from the first side of the multilayer wiring board to the second side opposite to the first side, and the reversal of the amount of warping occurs at only one location.

Description

[Technical Field]

[0001] This invention relates to a multilayer wiring board. [Background technology]

[0002] FC-BGA (Flip Chip-Ball Grid Array) substrates and other package substrates are boards that provide wiring structures to connect CPUs, GPUs, and other chips when mounting them on a printed circuit board such as a motherboard. In recent years, in order to support high-speed and high-capacity data communication, mounting methods are sometimes used in which multiple chips are integrated using interposer substrates and bridge substrates before being mounted on a package substrate. As a result, there is a trend in package substrate development towards larger sizes to accommodate multiple chips.

[0003] As package substrates become larger, the effects of warping that occurs during the mounting of chips and other components also increase, making it necessary to take measures against warping. For example, Patent Document 1 aims to provide a method for manufacturing a wiring board with a reinforcement that can reliably relieve the stress applied to the reinforcing material and prevent warping of the wiring board, and discloses the following as an invention for a method for manufacturing a wiring board with a reinforcement: "The wiring board with a stiffener 11 comprises a wiring board 40 having a main substrate surface 41 and a back substrate surface 42, and a structure in which a plurality of resin insulating layers 43 to 46 and a plurality of conductor layers 51 are laminated, and a stiffener 31 that is joined to the main substrate surface 41 side. In the joining process, a collection of divided pieces 36 arranged through a slit is joined to the main substrate surface 41 side, and then in the separation process, the collection of divided pieces is separated into individual divided pieces 36, thereby manufacturing the wiring board with a stiffener 11." [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 5356883 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] While package substrates are becoming larger, development is also underway to reduce data transmission loss and improve communication quality by developing low-Dk (dielectric constant) / Df (dielectric loss tangent) resin materials for use as substrates. However, low-Dk / Df materials tend to be weaker against temperature cycles and more prone to cracking compared to conventional resin materials. Furthermore, as described in Patent Document 1, when a metal reinforcing plate (stiffener) is placed on the substrate to suppress warping, the difference in thermal expansion coefficients makes it easy for cracks to occur in the resin located between the chip and the stiffener. Patent Document 1 does not consider the occurrence of cracks caused by the stiffener. Therefore, the present invention aims to provide a technology that can suppress the occurrence of cracks caused by stiffeners. [Means for solving the problem]

[0006] To solve the above problems, one representative multilayer wiring board of the present invention is a rectangular multilayer wiring board having a first surface on which a semiconductor device is mounted and a second surface opposite to the first surface, wherein the amount of warping of the multilayer wiring board due to the heating and mounting of the semiconductor device occurs in a straight section from the first side of the multilayer wiring board to the second side opposite to the first side, and the reversal of the amount of warping occurs at only one place. [Effects of the Invention]

[0007] According to the present invention, it is possible to suppress the occurrence of cracks caused by stiffeners. Other issues, configurations, and effects not mentioned above will be clarified by the description of the embodiments for carrying out the invention below. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a multilayer wiring board. [Figure 2]FIG. 2 is a diagram showing a case where a semiconductor device is mounted on a multilayer wiring board on which a stiffener is arranged. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of a multilayer wiring board. [Figure 4] FIG. 4 is a plan view of a multilayer wiring board. [Figure 5] FIG. 5 is a diagram showing a case where a semiconductor device is mounted on a multilayer wiring board. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of a multilayer wiring board. [Figure 7] FIG. 7 is a perspective view of a stiffener. [Figure 8] FIG. 8 is a diagram showing a case where a semiconductor device is mounted on a multilayer wiring board. [Figure 9] FIG. 9 is a diagram showing physical property values of members applied to simulation. [Figure 10] FIG. 10 is a diagram showing the result of calculating the amount of warpage generated when a semiconductor device is mounted on a multilayer wiring board by simulation. [Figure 11] FIG. 11 is a diagram showing the result of calculating the amount of warpage generated when a semiconductor device is mounted on a multilayer wiring board by simulation in the case where the substrate size is a square with a side length of 50 mm. [Figure 12] FIG. 12 is a diagram showing the result of calculating the amount of warpage generated when a semiconductor device is mounted on a multilayer wiring board by simulation in the case where the substrate size is a square with a side length of 90 mm. [Figure 13] FIG. 13 is a diagram showing the result of calculating the amount of warpage generated when a semiconductor device is mounted on a multilayer wiring board by simulation in the case where the substrate size is a square with a side length of 120 mm. [Figure 14] FIG. 14 is a diagram showing a modification (first modification) of the first embodiment. [Figure 15] FIG. 15 is a diagram showing a modification (second modification) of the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited by these embodiments. Also, in the description of the drawings, the same parts are denoted by the same reference numerals. When there are a plurality of components having the same or similar functions, they may be described with the same reference numeral and different subscripts. Also, when it is not necessary to distinguish these plurality of components, the subscripts may be omitted in the description. In the drawings, the positions, sizes, shapes, ranges, etc. of the respective components shown may not represent the actual positions, sizes, shapes, ranges, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0010] In the present disclosure, the "substrate size" indicates the size of the outer shape of the substrate when the substrate is placed on a plane. Note that the substrate may refer to a multilayer wiring substrate in the present disclosure.

[0011] (Configuration of Multilayer Wiring Substrate 1) FIG. 1 is a diagram showing an example of the configuration of a multilayer wiring substrate 1. FIG. 1 shows a part of the cross section of the multilayer wiring substrate 1. The multilayer wiring substrate 1 is used as a package substrate, and is a rectangular substrate having a first surface 1F on the side where a semiconductor device described later is mounted and a second surface 1B facing the first surface 1F. As will be described later, the multilayer wiring substrate 1 includes a core layer 10, a resin layer 11, a resin layer 12, a solder resist (SR) portion 18, an SR portion 19, and an electrode portion 20. The resin layer 11 is disposed on the first surface 1F side of the multilayer wiring substrate 1, and the resin layer 12 is disposed on the second surface 1B side of the multilayer wiring substrate. Note that the side surface 1S of the multilayer wiring substrate 1 is a portion between the first surface 1F and the second surface 1B, and is a portion exposed in the xy-plane direction of the multilayer wiring substrate 1. Also, since the core layer 10, the resin layer 11, the resin layer 12, the solder resist (SR) portion 18, the SR portion 19, and the electrode portion 20 included in the multilayer wiring substrate 1 are portions having functions as a package substrate, they may be referred to as a substrate main body portion.

[0012] The core layer 10 is a layered member parallel to the xy plane, and is made of, for example, a glass substrate. Through holes are formed in the core layer 10 that penetrate in the z-axis direction, and through electrodes 13 are formed by placing a conductive member in the through holes. The through electrodes 13 electrically connect the wiring 15 formed on the z-positive side surface 10a of the core layer 10 and the wiring formed on the z-negative side surface 10b.

[0013] The resin layer 11 is a component placed on the surface 10a of the core layer 10 and includes a resin portion 14 and wiring 15. The resin portion 14 is made of, for example, a low Dk / Df insulating resin material. The wiring 15 has a predetermined circuit pattern that extends in the xy plane direction and also forms a circuit connecting the surface 10a of the core layer 10 to the surface of the resin layer 11 (plus the z-axis direction) in the z-axis direction. Since the resin layer 11 is formed by stacking layers including wiring, it is also called a build-up layer. The same applies to the resin layer 12 described later.

[0014] The resin layer 12 is positioned on the surface 10b of the core layer 10 and includes a resin portion 17. The resin portion 17 is made of, for example, a low Dk / Df insulating resin material, and may be made of the same material as the resin portion 14. Although not shown in the figure, wiring similar to that of the wiring 15 is also formed on the resin layer 12.

[0015] The solder resist (SR) portion 18 is a film of insulating material placed on the resin layer 11, and protects the wiring 15 exposed on the resin layer 11.

[0016] The SR portion 19 is a film of insulating material placed on the resin layer 12, protecting the wiring exposed on the resin layer 12. The electrode portion 20 is an electrode formed in the opening portion of the SR portion 19. When mounting the multilayer wiring board 1 to a motherboard, for example, solder balls are placed on the electrode portion 20 to connect the multilayer wiring board 1 and the motherboard.

[0017] In this disclosure, the multilayer wiring board 1 is shown to be a square with side length k1 in the xy plane and a thickness k2, but this disclosure is not limited to this case. This disclosure can also be applied to multilayer wiring boards with shapes other than those described above. In addition, although the wiring 15 is composed of three layers, the number of layers is not limited to three. Furthermore, the through-electrode 13 may be formed by filling the entire through-hole of the core layer 10 with a conductive material, or by placing a conductive material on the inner surface of the through-hole and filling the remaining cavity portion of the through-hole with a resin material.

[0018] (Conventional example) (Conventional configuration example) A conventional configuration example will be explained with reference to Figure 2. Figure 2 shows a case where a semiconductor device 23 is mounted on a multilayer wiring board 1 on which a stiffener 21 is placed. Figure 2 shows a part of the cross-section, similar to Figure 1. The configuration including the multilayer wiring board 1, stiffener 21 and semiconductor device 23 shown in Figure 2 will be conveniently referred to as the package structure 100. The package structure 100 in Figure 2 is an example of a conventional package structure.

[0019] The stiffener 21 is fixed to the multilayer wiring board 1, for example, by an adhesive. In a plan view of the package structure 100 (viewed from the plus z-axis direction), the stiffener 21 has, for example, a rectangular frame shape and is positioned to surround the semiconductor device 23 when it is mounted. For example, the stiffener 21 covers the first surface 1F of the multilayer wiring board 1 with a width lo0 in the xy-plane direction and a thickness lt0 in the z-axis direction, extending inward from the side surface 1S of the multilayer wiring board 1 to the main body of the board. The stiffener 21 is positioned on the first surface 1F of the multilayer wiring board 1 and is not positioned on the second surface 1B or the side surface 1S.

[0020] The adhesive layer 22 fixes the semiconductor device 23 to the multilayer wiring board 1 when the semiconductor device 23 is mounted, and also electrically connects the semiconductor device 23 to the wiring 15 of the resin layer 11. The adhesive layer 22 includes, for example, solder bumps formed on the portion of the wiring 15 exposed on the resin layer 11, and an underfill member such as resin that is filled between the semiconductor device 23 and the multilayer wiring board 1.

[0021] The semiconductor device 23 may be, for example, an IC or other chip, or an interposer substrate in which multiple chips are integrated. It may also have a configuration in which multiple chips are integrated by a bridge substrate.

[0022] When mounting the semiconductor device 23 onto a multilayer wiring board 1, for example, the semiconductor device 23 is mounted onto the multilayer wiring board 1 in a heated environment (hereinafter also simply referred to as "heat mounting"). The stiffener 21 suppresses warping that occurs between the semiconductor device 23 and the multilayer wiring board 1 due to the difference in thermal expansion coefficients. On the other hand, since the warping generated by the stiffener 21 and the semiconductor device 23 is in opposite directions, there is a possibility of cracking.

[0023] (First Embodiment) The first embodiment will be described with reference to Figures 3 to 5. In the following description, components that are the same as or equivalent to those in the conventional example described above will be denoted by the same reference numerals, and their descriptions will be simplified or omitted.

[0024] (Example configuration of multilayer wiring board 1a) Figure 3 shows an example of the configuration of a multilayer wiring board 1a. Figure 3(a) shows a part of the cross-section of the multilayer wiring board 1a, and Figure 3(b) shows a perspective view of the multilayer wiring board 1a. Figure 3(a) is the AA cross-section of Figure 3(b). In Figure 3(b), the wiring 15 is omitted from the description. Figure 4 is a plan view of the multilayer wiring board 1a. In the following description, the stiffeners of the multilayer wiring board 1a are denoted by reference numerals 21a1 to 21a4, but different reference numerals are assigned for convenience depending on their location, and all stiffeners have the same configuration. Unless there is a particular need to distinguish them, they will simply be described as "stiffener 21a".

[0025] The multilayer wiring board 1a comprises a first surface 1F, a second surface 1B, a main board portion defined by a side surface 1S between the first surface 1F and the second surface 1B, and a stiffener 21a located on the side surface 1S. It can also be said that the multilayer wiring board 1a is the same as the multilayer wiring board 1 in Figure 1, but with the stiffener 21a. Therefore, the portion corresponding to the multilayer wiring board 1 is referred to as the main board portion and will be described using the same reference numerals as the multilayer wiring board 1 in Figure 1.

[0026] As shown in Figure 3(a), the stiffener 21a covers the first surface 1F and the second surface 1B from the side surface 1S of the substrate body toward the inside of the substrate body (in the xy plane) with a width lo and a thickness lt in the z axis direction (hereinafter also referred to as "overlapping"). Regarding the second surface 1B side of the multilayer wiring board 1a, when the multilayer wiring board 1a is mounted on a motherboard or the like, solder balls are placed on the electrode portion 20 and the multilayer wiring board 1a is mounted on the motherboard. The width lo and thickness lt are set so as not to interfere with the solder balls or the motherboard. Furthermore, the stiffener 21a has a thickness lt (hereinafter also referred to as "side thickness") extending from the side surface 1S of the substrate body outward (in the xy plane direction).

[0027] In this disclosure, the size of the substrate body is shown to be a square with side length k1 in the xy plane direction, and the thickness of the substrate body is k2.

[0028] As shown in Figure 3(b), the stiffener 21a has a U-shaped (concave, groove-shaped) cross-section. As a method for manufacturing the multilayer wiring board 1a, for example, the stiffener 21a can be manufactured in a different process from the main board body, and then fixed to the side surface 1S by sandwiching the first surface 1F to the second surface 1B of the main board body with the U-shaped portion. By adopting this sandwiching method, it becomes easy to create a tight bond between the main board body and the stiffener 21a, thereby efficiently suppressing the occurrence of warping, which will be described later. An adhesive may be used for fixing.

[0029] Furthermore, the stiffener 21a is fixed to each side of the main body of the substrate, specifically to the peripheral portion of the first surface F1, the side surface 1S, and the peripheral portion of the second surface 1B. Figure 4 shows the relationship between the first surface 1F of the main body of the substrate and the stiffener 21a, with the stiffener 21a shown by a dashed line. As shown in Figure 4, the main body of the substrate is rectangular, enclosed by sides s1 to s4. At side s1 of the main body of the substrate, the stiffener 21a1 is fixed to the peripheral portion p1 of the first surface 1F and the side surface 1S. Peripheral portion p1 is a strip-shaped portion with width lo on the first surface 1F. The second surface 1B also has a peripheral portion similar to the peripheral portion p1 of the first surface 1F, and the stiffener 21a1 is also fixed to the peripheral portion of the second surface 1B.

[0030] Similarly, at edge s2 of the main body of the substrate, the stiffener 21a2 is fixed to the peripheral portion p2 of the first surface 1F, the side surface 1S, and the peripheral portion of the second surface 1B. Also, at edge s3 of the main body of the substrate, the stiffener 21a3 is fixed to the peripheral portion p3 of the first surface 1F, the side surface 1S, and the peripheral portion of the second surface 1B. Furthermore, at edge s4 of the main body of the substrate, the stiffener 21a4 is fixed to the peripheral portion p4 of the first surface 1F, the side surface 1S, and the peripheral portion of the second surface 1B. The peripheral portions p1 to p4 on the first surface 1F and the peripheral portion on the second surface 1B all have a strip-like (rectangular) shape with a width lo.

[0031] In the multilayer wiring board 1a, corners R1 to R4 are areas to which the stiffeners 21a are not fixed. This allows deformation that occurs in the stiffeners 21a when the semiconductor device is heated and mounted to be relieved in corners R1 to R4, thus avoiding interference between adjacent stiffeners 21a. Furthermore, regarding the four-sided stiffeners 21a1, 21a2, 21a3, and 21a4, it is preferable that, for example, the ends of 21a1 and 21a2 are in contact with each other. This is because the stiffeners on adjacent sides can perform their function to the fullest without interfering with each other.

[0032] Figure 5 shows a case where a semiconductor device 23 is mounted on a multilayer wiring board 1a. Figure 5(a) shows a part of the cross-section of the package structure 100a, and Figure 5(b) shows a perspective view of the package structure 100a. Figure 5(a) is the AA cross-section of Figure 5(b). As shown in Figures 5(a) and 5(b), when the semiconductor device 23 is mounted on the multilayer wiring board 1a, the semiconductor device 23 is arranged to be surrounded by the stiffener 21a. In this disclosure, the semiconductor device 23 is shown to have a square shape with side length c1 in the xy plane direction.

[0033] (Second Embodiment) The second embodiment will be described with reference to Figures 6 and 7. The second embodiment differs from the first embodiment in that the stiffener is not divided but formed as a single component. In the following description, components that are the same as or equivalent to those in the first embodiment will be denoted by the same reference numerals, and their descriptions will be simplified or omitted.

[0034] Figure 6 shows an example of the configuration of the multilayer wiring board 1b. Figure 6(a) shows a part of the cross-section of the multilayer wiring board 1b, and Figure 6(b) shows a perspective view of the multilayer wiring board 1b. Figure 6(a) is the AA cross-section of Figure 6(b). In Figure 6(b), the wiring 15 is omitted. Figure 7 is a perspective view of the stiffener 21b.

[0035] The stiffener 21b is fixed to the side surface 1S and the peripheral area of ​​the second surface 1B of the substrate body. Specifically, as shown in Figure 6(a), the cross-section of the stiffener 21b is L-shaped. The first surface 1F of the substrate body is not covered by the stiffener 21b, but since the stiffener 21b has a shape that extends inward toward the inside of the substrate body toward the second surface 1B side, the second surface 1B of the substrate body is covered by a width of lo. In other words, the peripheral area of ​​the second surface 1B has a strip-like (rectangular) shape with a width of lo.

[0036] As shown in Figure 7, the stiffener 21b has a frame-like shape. On the first surface 1F side (positive z-axis direction side), an opening the same size as the main substrate is formed, and on the second surface 1B side (negative z-axis direction side), an opening smaller than the size of the main substrate is formed so that it can be fixed to the peripheral part of the second surface 1B of the main substrate. As a method of manufacturing the multilayer wiring board 1b, for example, the stiffener 21b can be manufactured in a process different from the manufacturing of the main substrate, and the main substrate can be fitted into the stiffener 21b from the positive z-axis direction and fixed to the peripheral part of the side surface 1S and the second surface 1B of the main substrate. Adhesive may be used for fixing.

[0037] Figure 8 shows the case where the semiconductor device 23 is mounted on the multilayer wiring board 1b. Figure 8(a) shows a part of the cross-section of the package structure 100b, and Figure 8(b) shows a perspective view of the package structure 100b. Figure 8(a) is the AA cross-section of Figure 8(b). As shown in Figures 8(a) and 8(b), when the semiconductor device 23 is mounted on the multilayer wiring board 1b, the semiconductor device 23 is arranged to be surrounded by the stiffener 21b.

[0038] (Evaluation of the amount of warping) Next, the amount of warping that occurs when semiconductor devices are mounted on a multilayer wiring board was calculated through simulation.

[0039] Regarding the simulation conditions, the substrate size was set to a square with sides of 50 mm (for example, k1 is 50 mm in Figures 1 to 3, 5, 6, and 8), and the substrate thickness was set to 1.86 mm (for example, k2 is 1.85 mm in Figures 1 to 3, 5, 6, and 8). The semiconductor device 23 was defined as a square with sides of 28 mm (for example, c1 is 28 mm in Figures 2, 5, and 8). In the simulation, the semiconductor device 23 was assumed to be a silicon-based chip. Regarding the stiffener, the overlap with the substrate was set to 2 mm (for example, width lo0 in Figure 2 is 2 mm, and width lo is 2 mm in Figures 3 to 6 and Figure 8), the thickness to 2 mm (for example, thickness lt0 is 2 mm in Figure 2, and thickness lt is 2 mm in Figures 3, 5, 6, and 8), and the side thickness to 3 mm (for example, side thickness ls is 3 mm in Figures 3, 5, 6, and 8). The stiffener material was assumed to be ceramic. In the case of ceramic, the thickness can be reduced, so it is possible to avoid interference between the stiffener and the motherboard or other electronic components when a multilayer wiring board is used. Furthermore, the structural analysis simulator ANSYS Mechanical was used for the simulation. Furthermore, in the simulation, the heating temperature for the heat-packing was set to 240°C and the room temperature to 22°C, and structural analysis was performed as the temperature changed from 240°C to 22°C.

[0040] Figure 9 shows the physical properties of the components applied to the simulation. The item "Stiffener (Ceramic)" shows the physical properties (density, thermal expansion coefficient, Young's modulus, and Poisson's ratio) when a ceramic material is used for the stiffener. The item "SR" shows the physical properties of SR parts 18 and 19. The item "Resin Layer" shows the physical properties of resin layers 11 and 12. The item "Core Layer" shows the physical properties of core layer 10. The item "IC" shows the physical properties of semiconductor device 23 (silicon-based chip in this disclosure). For reference, the item "Stiffener (Metal)" shows the physical properties when the stiffener is metal.

[0041] Figure 10 shows the results of a simulation calculating the amount of warping that occurs when a semiconductor device is mounted on a multilayer wiring board. The simulation was performed assuming that the semiconductor device 23 is mounted in the center of the multilayer wiring board (or the main body of the board if a stiffener is placed therein). The legend "Conventional structure" refers to the package structure 100 in Figure 2. The legend "Substrate only" is a control experiment and shows the case where only the multilayer wiring board 1 in Figure 1 is placed in an environment where a chip is mounted. The legend "Substrate + semiconductor device" refers to the case where the semiconductor device 23 is mounted on the multilayer wiring board 1 in Figure 2. The legend "First embodiment" refers to the package structure 100a in Figure 5. The legend "Second embodiment" refers to the package structure 100b in Figure 8. The units on both the horizontal and vertical axes are mm.

[0042] The graph in Figure 10 shows the amount of warping of a multilayer wiring board due to the heating and mounting of a semiconductor device, and indicates the displacement in the cross-section of the package structure. To explain using the first embodiment as an example, the range from 0 to 50 on the horizontal axis in the legend "First Embodiment" represents the range from the negative end in the x-axis direction to the positive end in the x-axis direction in the package structure 100a of Figure 5(a) (in Figure 4, it is the range of the straight section from side s1 (first side) to side s3 (second side) opposite to side s1), and the change on the vertical axis of the graph corresponds to the change in the z-axis direction of the package structure 100a. Furthermore, the amount of warping is the difference in the z-axis direction between the reference position and a position on the main body of the substrate, and as shown in Figure 10, in the case of the legend "First Embodiment", the reference position is the end of the main body of the substrate (horizontal axis is 0 or 50). The reference position for the amount of warping is the edge of the multilayer wiring board 1 (horizontal axis is 0 or 50) in the case of the legend "Substrate only" and the legend "Substrate + semiconductor device", and the edge of the main body of the substrate (horizontal axis is 0 or 50) in the case of the legend "Second embodiment". In the case of the legend "Conventional structure", the reference position for the amount of warping is the location where a reversal of the amount of warping occurs in the range r1 or range r2 described later. In all cases, the amount of warping is greatest in the central part of the multilayer wiring board 1 or the main body of the substrate, so the amount of warping in the central part is also called the maximum amount of warping.

[0043] In the case of a substrate alone, there are no semiconductor devices on the multilayer wiring substrate 1, and there are no objects with a different coefficient of thermal expansion than the multilayer wiring substrate 1, so warping hardly occurs.

[0044] In the case of a substrate + semiconductor device, the amount of warping in the central part is approximately 0.24 mm. It is thought that the warping occurred due to thermal changes during mounting, as there is a difference in thermal expansion coefficients between the multilayer wiring substrate 1 and the semiconductor device 23. Furthermore, the amount of warping increases as the horizontal axis moves from 0 to 25, and decreases as the horizontal axis moves from 25 to 50. A reversal of the amount of warping occurs once in the central part.

[0045] In the conventional structure (package structure 100), the amount of warping in the central part was approximately 0.13 mm, which is about 50% less than in the case of a substrate + semiconductor device. This reduction in warping is thought to be due to the effect of the stiffener 21 placed on the first surface 1F. On the other hand, compared to other areas, the reversal of the amount of warping occurs not only in the central part but also in the peripheral part of the substrate. Specifically, the direction of warping changes at locations approximately 5 and 45 on the horizontal axis. This change in the direction of warping occurs because the stiffener 21 and the semiconductor device 23 generate warping in opposite directions. The areas near where the direction of warping changes, namely the range r1 from approximately 3 to approximately 7 on the horizontal axis and the range r2 from approximately 43 to approximately 47 on the horizontal axis, are areas where cracks tend to occur.

[0046] In the first embodiment, the amount of warping in the central part was approximately 0.14 mm, which is about 40% less than in the case of a substrate + semiconductor device. Because the stiffener 21a of the first embodiment has a shape that fixes both the front and back surfaces of the edge portion of the substrate body, it is thought that the amount of warping in the central part is slightly larger than in the conventional structure and the second embodiment described later, as a reaction to suppressing the warping that occurs in the edge portion of the substrate body. Furthermore, the amount of warping of the multilayer wiring board 1a due to the heating and mounting of the semiconductor device 23 is such that the reversal of the warping amount occurs only at one point in the straight section between opposing edges of the main body of the board. Specifically, since the occurrence of warping in the opposite direction is also suppressed in ranges r1 and r2, it is possible to suppress the occurrence of cracks.

[0047] In the second embodiment, the amount of warping in the central part was approximately 0.13 mm, which was reduced to about 50% compared to the case of a substrate + semiconductor device. Furthermore, similar to the first embodiment, the occurrence of reverse warping in ranges r1 and r2 is also suppressed, making it possible to suppress the occurrence of cracks.

[0048] In both the first and second embodiments, the amount of warping could be kept to 0.15 mm or less when the main body of the substrate is a square with sides of 50 mm, and the occurrence of warping in the reverse direction was also suppressed.

[0049] (Evaluation of warpage based on the size of the main body of the circuit board) To confirm the effect of substrate size, the amount of warping that occurs when semiconductor devices are mounted was evaluated for cases where the substrate size was changed. Figure 11 shows the results of simulation calculations of the amount of warping that occurs when semiconductor devices are mounted on a multilayer wiring board when the substrate size is a square with sides of 50 mm. Figure 12 shows the results of simulation calculations of the amount of warping that occurs when semiconductor devices are mounted on a multilayer wiring board when the substrate size is a square with sides of 90 mm. Figure 13 shows the results of simulation calculations of the amount of warping that occurs when semiconductor devices are mounted on a multilayer wiring board when the substrate size is a square with sides of 120 mm.

[0050] Regarding the simulation conditions, there is a difference compared to the evaluation of the amount of warpage in Figure 10, in that the substrate size now includes cases of a square with sides of 90 mm and a square with sides of 120 mm. The conditions for the semiconductor device 23 and the stiffener are the same as in Figure 10. The configuration of the multilayer wiring board and the main body of the substrate is also the same as in Figure 10.

[0051] As shown in Figure 11, when the substrate size is a square with sides of 50 mm, the amount of warping of the substrate + semiconductor device is approximately 0.24 mm in the center. In the first embodiment, the amount of warping is approximately 0.14 mm in the center. The stiffener 21a of the first embodiment reduced the amount of warping by approximately 40% compared to the case of substrate + semiconductor device.

[0052] Furthermore, as shown in Figure 12, when the substrate size is a square with sides of 90 mm, the amount of warping of the substrate + semiconductor device is approximately 0.35 mm in the center. In addition, the amount of warping in the first embodiment is approximately 0.20 mm in the center. The stiffener 21a of the first embodiment reduced the amount of warping by approximately 42% compared to the case of substrate + semiconductor device.

[0053] Furthermore, as shown in Figure 13, when the substrate size is a square with sides of 120 mm, the amount of warping of the substrate + semiconductor device is approximately 0.70 mm in the center. In addition, the amount of warping in the first embodiment is approximately 0.50 mm in the center. The stiffener 21a of the first embodiment reduced the amount of warping by approximately 29% compared to the case of substrate + semiconductor device.

[0054] From the simulation results above, it can be concluded that in the first embodiment, the stiffener 21a reduces the amount of warping by 30% to 40%. Furthermore, in the case of the first embodiment, if the substrate size is a square with sides of 50 mm, then 0.14 mm / 50 mm ≈ 0.28 × 10 -2 A warp of several millimeters occurred. Therefore, for example, if the substrate size fluctuates by 10% and the sides are in the range of 45mm to 55mm, the warp will be 0.13mm (0.28 × 10 -2 (mm x 45mm) to 0.15mm (0.28 x 10 -2 It is thought to vary within the range of (mm x 55mm). Also, if the circuit board is a square with sides of 90mm, then the distance per side of the board is 0.20mm / 90mm ≈ 0.22 × 10 -2A warp amount of -2 mm occurred. Therefore, for example, in the case of a square with a substrate size variation of 10% and one side ranging from 81 mm to 99 mm, the warp amount is considered to vary within the range of 0.18 mm (0.22 × 10 -2 mm × 81 mm) to 0.22 mm (0.22 × 10 mm × 99 mm). -2 Also, in the case of a square with a substrate size of 120 mm on one side, a warp of 0.50 mm / 120 mm ≈ 0.42 × 10 -2 mm occurred per side of the substrate. Therefore, for example, in the case of a square with a substrate size variation of 10% and one side ranging from 108 mm to 131 mm, the warp amount is considered to vary within the range of 0.45 mm (0.42 × 10 -2 mm × 108 mm) to 0.55 mm (0.42 × 10

[0055] mm × 131 mm). -2 Referring to FIG. 10 and making the same consideration for the second embodiment, in the case of the second embodiment, when the substrate size is a square with one side of 50 mm, a warp amount of 0.13 mm / 50 mm ≈ 0.26 × 10 -2 mm occurred per side of the substrate. Therefore, for example, in the case of a square with a substrate size variation of 10% and one side ranging from 45 mm to 55 mm, the warp amount is considered to vary within the range of 0.12 mm (0.26 × 10 -2 mm × 45 mm) to 0.14 mm (0.26 × 10

[0056] mm × 55 mm).

[0057] (Modification) Although the structures of the stiffeners in the first and second embodiments are shown, the present disclosure is not limited to this case. It is considered that by arranging the stiffeners at least on the side surface 1S of the substrate main body portion, the occurrence of warping in the reverse direction can be suppressed.

[0058] Figure 14 shows a modified example of the first embodiment (first modified example). Figure 14 corresponds to Figure 4. In the first embodiment, the stiffener 21a was composed of four parts, but in the first modified example, it is divided into two parts, stiffener 21c1 and 21c2.

[0059] Furthermore, Figure 15 shows a modified example of the second embodiment (second modified example). Figure 15 corresponds to Figure 6(a). In the second embodiment, the stiffener 21b had a shape that covered up to the second surface 1B of the substrate body, but in the second modified example, the stiffener 21d is positioned on the side surface 1S but does not cover up to the second surface 1B.

[0060] By adopting the configuration shown in Figures 14 and 15, a stiffener can be placed on the side surface 1S of the substrate body, thereby suppressing the occurrence of warping in the reverse direction.

[0061] (Effects / Actions) As described above, this disclosure makes it possible to suppress the occurrence of cracks caused by stiffeners. Even in multilayer wiring boards using large-scale and low Dk / Df materials, it is possible to suppress the occurrence of cracks while also suppressing the occurrence of warping that occurs during the heating and mounting of semiconductor devices.

[0062] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention.

[0063] The following describes, but is not limited to, embodiments that may constitute the present invention. (Aspect 1) In a rectangular multilayer wiring board having a first surface on which semiconductor devices are mounted and a second surface opposite to the first surface, The amount of warping of the multilayer wiring board due to the heating and mounting of the semiconductor device is such that the reversal of the amount of warping occurs at only one location in the straight section from the first side of the multilayer wiring board to the second side opposite the first side. Multilayer wiring board. (Aspect 2) In the multilayer wiring board described in Embodiment 1, The aforementioned multilayer wiring board is The substrate body portion formed by the first surface, the second surface, and the side surface between the first surface and the second surface, A stiffener disposed on the side surface is provided, Multilayer wiring board. (Aspect 3) In the multilayer wiring board described in Embodiment 1 or Embodiment 2, The stiffener is characterized in that it is fixed to the side surface and the peripheral portion of the second surface of the substrate body. Multilayer wiring board. (Aspect 4) In the multilayer wiring board described in any one of Embodiments 1 to 3, The stiffener is characterized in that it is fixed to each side of the main body of the substrate, to the peripheral portion of the first surface, the side surface, and the peripheral portion of the second surface. Multilayer wiring board. (Appendix 5) A multilayer wiring board according to claim 3, If the size of the main body of the circuit board is a square with sides ranging from 45 mm to 55 mm, The maximum amount of curvature is characterized by being in the range of 0.12 mm to 0.14 mm. Multilayer wiring board. (Aspect 6) A multilayer wiring board according to any one of embodiments 1 to 5, If the size of the main body of the circuit board is a square with sides ranging from 45 mm to 55 mm, The maximum amount of curvature among the aforementioned curvature amounts is characterized by being in the range of 0.13 mm to 0.15 mm. Multilayer wiring board. (Aspect 7) A multilayer wiring board according to any one of embodiments 1 to 6, If the size of the main body of the circuit board is a square with sides ranging from 81 mm to 99 mm, The maximum amount of curvature among the aforementioned curvature amounts is characterized by being in the range of 0.18 mm to 0.22 mm. Multilayer wiring board. (Pattern 8) A multilayer wiring board according to any one of embodiments 1 to 7, If the size of the main body of the circuit board is a square with sides ranging from 108 mm to 131 mm, The maximum amount of curvature is characterized by being in the range of 0.45 mm to 0.55 mm. Multilayer wiring board. [Explanation of symbols]

[0064] 1, 1a, 1b: Multilayer wiring board 10: Core Layer 11, 12: Resin layer 13:Through electrode 14, 17: Resin part 15: Wiring 18, 19: Solder Resist (SR) section 20: Electrode part 21, 21a, 21b, 21c, 21d: Stifna 22: Adhesive layer 23: Semiconductor equipment 100, 100a, 100b: Package structure

Claims

1. In a rectangular multilayer wiring board having a first surface on which semiconductor devices are mounted and a second surface opposite to the first surface, The amount of warping of the multilayer wiring board due to the heating and mounting of the semiconductor device is such that the reversal of the amount of warping occurs at only one location in the straight section from the first side of the multilayer wiring board to the second side opposite the first side. Multilayer wiring board.

2. In the multilayer wiring board according to claim 1, The aforementioned multilayer wiring board is The substrate body portion formed by the first surface, the second surface, and the side surface between the first surface and the second surface, A stiffener disposed on the side surface is provided, Multilayer wiring board.

3. In the multilayer wiring board according to claim 2, The stiffener is characterized in that it is fixed to the side surface and the peripheral portion of the second surface of the substrate body. Multilayer wiring board.

4. In the multilayer wiring board according to claim 2, The stiffener is characterized in that it is fixed to each side of the main body of the substrate, to the peripheral portion of the first surface, the side surface, and the peripheral portion of the second surface. Multilayer wiring board.

5. A multilayer wiring board according to claim 3, If the size of the main body of the circuit board is a square with sides ranging from 45 mm to 55 mm, The maximum amount of curvature is characterized by being in the range of 0.12 mm to 0.14 mm. Multilayer wiring board.

6. A multilayer wiring board according to claim 4, If the size of the main body of the circuit board is a square with sides ranging from 45 mm to 55 mm, The maximum amount of curvature is characterized by being in the range of 0.13 mm to 0.15 mm. Multilayer wiring board.

7. A multilayer wiring board according to claim 4, If the size of the main body of the circuit board is a square with sides ranging from 81 mm to 99 mm, The maximum amount of curvature is characterized by being in the range of 0.18 mm to 0.22 mm. Multilayer wiring board.

8. A multilayer wiring board according to claim 4, If the size of the main body of the circuit board is a square with sides ranging from 108 mm to 131 mm, The maximum amount of curvature is characterized by being in the range of 0.45 mm to 0.55 mm. Multilayer wiring board.

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