Memory device

Abstract

A storage device that has an error detection function and can store a large amount of data per unit area. provide. [Solution] A drive circuit for a memory device is constructed using transistors formed on a semiconductor substrate. Thin-film transistors are used to construct the memory cells of the memory device. The layers in which the memory cells are composed can be stacked in multiple layers on top of the semiconductor substrate, and This increases the amount of data that can be stored per unit area. Furthermore, by using thin-film transistors... Since it can constitute part of the peripheral circuitry of the memory device, thin-film transistors are used. This constitutes an error detection circuit, which is then stacked and mounted on top of the semiconductor substrate.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a memory device, particularly one that can function by utilizing semiconductor properties. Regarding memory devices.

[0002] Furthermore, one embodiment of the present invention relates to a semiconductor device. In this specification, a semiconductor device is defined as: This refers to a device that utilizes the properties of semiconductors, such as semiconductor elements (transistors, diodes). This refers to circuits including photodiodes, etc., and devices having such circuits. In this context, semiconductor devices refer to all devices that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronics in which chips are housed in a package. Electronic devices, which include components and integrated circuits, are an example of semiconductor devices.

[0003] Furthermore, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Or, one embodiment of the present invention. This refers to a process, machine, manufacture, or composition. This concerns (the tar). [Background technology]

[0004] DRAM (Dynamic Random Access Memory) is a type of electronic memory. It is widely known as a storage device (also called memory) used in devices. A Morissel consists of one transistor and one capacitive element, and DRAM uses an electric current in the capacitive element. It is a type of memory that stores data by accumulating loads.

[0005] Even if there are no malfunctions in the operation of memory devices such as DRAM, memory cells may be affected by cosmic rays and other factors. The data obtained may have an error. Therefore, there is a storage device called an ECC (Error Check and Correct) memory that has an error detection and correction function. ECC memory is used in electronic devices where data errors are not allowed, such as computers used in scientific and technical calculations and financial institutions.

[0006] On the other hand, a transistor having a metal oxide in a region where a channel of a transistor is formed (also referred to as a channel formation region) has attracted attention. For example, as a metal oxide applicable to a transistor, In-Ga-Zn oxide (referred to as IGZO, Igzo, etc.) is known.

[0007] Since the drain current (also referred to as the off-current) of an OS transistor when the transistor is in the off state is very small (see, for example, Non-Patent Documents 1 and 2), by using an OS transistor for a memory cell of a DRAM, the charge stored in a capacitance element can be held for a long time.

[0008] In addition, since an OS transistor is a thin film transistor, it can be provided in a stacked manner. For example, Patent Document 1 discloses a configuration in which a peripheral circuit of a DRAM is configured using transistors formed on a semiconductor substrate, and a plurality of layers each having a DRAM memory cell configured using an OS transistor are stacked above the peripheral circuit. By stacking a plurality of layers each having a DRAM memory cell, the chip area of the DRAM can be reduced.

[0009] In this specification and the like, a DRAM in which an OS transistor is used for a memory cell A semiconductor DRAM, or DOSRAM (registered trademark, Dynamic Oxide Se miconductor Random Access Memory, referred to as DOSRAM and read as such).

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Non-Patent Documents

[0011]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0012] Generally, an ECC memory includes a storage area for storing data, a storage area for storing an error detection code or an error correction code (also referred to as redundant bits or check bits), and the above two It has a memory controller that controls the storage area of ​​the memory. And the ECC memory is data When storing (or writing) data, the check bit corresponding to the data to be stored is calculated. The check bit is stored along with the data to be stored.

[0013] The check bit is read out along with the data when reading stored data. Mori verifies the read data using a check bit, thereby adding an error to the stored data. You can find out if a bug has occurred, or if there has been an error in the stored data. If this occurs, the ECC memory can be corrected using the check bit.

[0014] In other words, at least the ECC memory has a memory area for storing the check bits, and the same A memory controller that controls the memory region is required in addition to non-ECC memory. be.

[0015] One embodiment of the present invention is an error detection function (having a memory area for storing check bits, and checking A storage device that has a function to determine whether there are any errors in the data stored using bits. One of the objectives is to provide a solution. Alternatively, one embodiment of the present invention has an error detection function. One of the challenges is to provide a storage device that can store a large amount of data per unit area. ru.

[0016] Furthermore, one embodiment of the present invention does not necessarily have to solve all of the above problems, but at least It is sufficient if it can solve one problem. Also, the description of the problem above is based on the existence of other problems. This does not preclude the following. Other issues are described in the specification, claims, drawings, etc. This becomes clear from the description in the specification, claims, drawings, etc. It is possible to identify other issues besides those mentioned above. [Means for solving the problem]

[0017] One embodiment of the present invention comprises a first element layer having a memory cell and a second element having an error detection circuit. The memory device has a layer and a semiconductor substrate having a drive circuit. The second element layer is a semiconductor substrate It is provided between the plate and the first element layer.

[0018] Furthermore, one embodiment of the present invention comprises a plurality of first element layers and a second element layer having an error detection circuit. This is a memory device having a semiconductor substrate with a drive circuit. The second element layer is a semiconductor substrate and A plurality of first element layers are provided between the first element layer and each of the first element layers has a memory cell, The first element layer is provided in a stacked configuration.

[0019] Furthermore, in the above configuration, the transistor constituting the memory cell and the error detection circuit Each of the transistors that make up the device has a metal oxide in its channel formation region.

[0020] Furthermore, in the above configuration, the transistor constituting the memory cell and the error detection circuit Each of the transistors that make up the system has a front gate and a back gate.

[0021] Furthermore, in the above configuration, the transistor constituting the memory cell and the error detection circuit Each transistor that makes up the memory has a metal oxide in the channel formation region. The transistors that make up the circuit and the transistors that make up the error detection circuit are each It has a front gate and a rear gate.

[0022] Furthermore, one embodiment of the present invention comprises a first element layer (N is a natural number of 2 or more) from the first to the Nth element layer, and a second element layer This is a memory device having a sublayer and a semiconductor substrate. The first K (where K is an integer between 1 and N) In the element layer, a memory cell is constructed using a transistor formed in the first element layer of the Kth element. Furthermore, in the second element layer, an error detection circuit is formed using a transistor formed in the second element layer. The semiconductor substrate is configured, and the drive circuit uses transistors formed on the semiconductor substrate. The second element layer is stacked on top of the semiconductor substrate, and the first element layer is , stacked above the second element layer, the first element layer of the L (where L is an integer between 2 and N) It is stacked on top of the first element layer of the L-1.

[0023] Furthermore, in the above embodiment, a transistor formed in the first element layer of the Kth element, and a second element Each transistor formed in the sublayer has a metal oxide in its channel formation region.

[0024] Furthermore, in the above embodiment, a transistor formed in the first element layer of the Kth element, and a second element Each transistor formed in the sublayer has a front gate and a back gate. .

[0025] Furthermore, in the above embodiment, a transistor formed in the first element layer of the Kth element, and a second element Each transistor formed in the sublayer has a metal oxide in the channel formation region, A transistor formed in the first element layer of K, and a transistor formed in the second element layer Each of the two has a front gate and a back gate. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a storage device having an error detection function can be provided. According to one embodiment of the present invention, the system has an error detection function and can store data per unit area. It can provide a large-capacity storage device.

[0027] Furthermore, the description of these effects does not preclude the existence of other effects. The form does not necessarily have to possess all of these effects. Other effects are specified in the details. This will become clear from the description in the document, claims, drawings, etc., and the specification, patent It is possible to extract effects other than those listed above from the scope of the claims, drawings, and other descriptions. [Brief explanation of the drawing]

[0028] [Figure 1] Figure 1A is a block diagram showing an example of a storage device configuration. Figure 1B is a schematic diagram showing an example of a storage device configuration. [Figure 2] Figure 2 is a schematic diagram showing an example of a storage device configuration. [Figure 3] Figure 3 is a circuit diagram showing an example of a memory device configuration. [Figure 4] Figure 4 is a schematic diagram showing an example of a storage device configuration. [Figure 5] Figures 5A and 5B are schematic diagrams showing examples of storage device configurations. [Figure 6] Figure 6A is a circuit diagram showing an example configuration of the test bit generation circuit. Figure 6B is a timing chart. Figure 6C is a truth table. [Figure 7] Figure 7A is a circuit diagram showing an example of the error detection circuit configuration. Figure 7B is a timing chart. [Figure 8] Figure 8 is the truth table. [Figure 9] Figure 9A is a symbol representing an XOR circuit. Figure 9B is a circuit diagram showing an example configuration of an XOR circuit. Figure 9C is a timing chart. Figure 9D is a truth table. [Figure 10] Figure 10A is a symbol representing a NAND gate. Figure 10B is a circuit diagram showing an example of a NAND gate configuration. Figure 10C is a timing chart. Figure 10D is a truth table. [Figure 11] Figure 11A is a symbol representing a delay circuit. Figure 11B is a circuit diagram showing an example of a delay circuit configuration. Figure 11C is a timing chart. Figure 11D is a truth table. [Figure 12] Figure 12 is a schematic diagram showing an example of a storage device configuration. [Figure 13] Figure 13 is a schematic cross-sectional view showing an example of a storage device configuration. [Figure 14] Figures 14A and 14B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 15] Figures 15A to 15C are schematic cross-sectional diagrams showing examples of the configuration of a storage device. [Figure 16] Figure 16 is a schematic cross-sectional view showing an example of a storage device configuration. [Figure 17] Figure 17 is a schematic cross-sectional diagram showing an example of a storage device configuration. [Figure 18] Figure 18A is a top view showing an example of a storage device configuration. Figures 18B and 18C are schematic cross-sectional views showing an example of a storage device configuration. [Figure 19] Figure 19A illustrates the classification of IGZO crystal structures. Figure 19B illustrates the XRD spectrum of quartz glass. Figure 19C illustrates the XRD spectrum of crystalline IGZO. [Figure 20] Figures 20A and 20B are schematic diagrams illustrating an example of an electronic component. [Figure 21] Figure 21 shows an example of an electronic device. [Figure 22] Figure 22 is a diagram showing various types of storage devices in a hierarchical structure. [Modes for carrying out the invention]

[0029] The embodiments will be described below with reference to the drawings. However, the embodiments may differ in many ways. It is possible to implement it in any form, without deviating from its purpose and scope. It will be easily understood by those skilled in the art that the details can be changed in various ways. The Specification shall not be interpreted as being limited to the contents of the following embodiments.

[0030] Furthermore, the multiple embodiments shown below can be combined as appropriate. If multiple configuration examples are shown within a single embodiment, the configuration examples may be combined as appropriate. It is possible to do so.

[0031] In the drawings attached to this specification, the components are classified by function and are shown as independent blocks. Although a block diagram is shown as an example, the actual components are not completely separated by function. This can be difficult, and a single component may be involved in multiple functions.

[0032] Furthermore, in drawings and other documents, the size, layer thickness, area, etc., may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawing schematically represents an ideal example. This is an illustration, and is not limited to the shapes or values ​​shown in the drawings.

[0033] Furthermore, in drawings, etc., identical elements or elements with similar functions, elements made of the same material, Alternatively, elements formed simultaneously may be assigned the same reference numeral, and the explanation of this repetition is provided. This may be omitted.

[0034] Furthermore, in this specification, the terms "membrane" and "layer" are interchangeable. It is possible to change the term "conductive layer" to "conductive film". In some cases, this may be possible. Or, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the terminology to this.

[0035] Furthermore, in this specification, terms indicating placement such as "above" and "below" refer to the relative positions of the constituent elements. The term "directly above" or "directly below" is not necessarily limited to this. For example, "gate absolute" The expression "gate electrode on the margin layer" implies that there are other components between the gate insulating layer and the gate electrode. Items containing this will not be excluded.

[0036] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" refer to the constituent elements. This is added to avoid confusion and does not limit the number.

[0037] Furthermore, in this specification, when the same reference numeral is used for multiple elements, we will not specifically distinguish them. When necessary, use identifiers such as "_1", "_2", "[n]", "[m,n]" in the code. Sometimes, a symbol is added to indicate the wiring. For example, the second wiring GL may be written as wiring GL[2]. To include.

[0038] Furthermore, in this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. Switching elements, resistive elements, inductors, capacitive elements, and other elements with various functions This includes elements and components. Also, even when it is described as "electrically connected," it refers to the actual circuitry. In some cases, there are no physical connections, and only wiring extends from the site.

[0039] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true.

[0040] Furthermore, in this specification, etc., "terminal" in an electrical circuit means an input of current or potential ( This refers to the part where output or signal reception (or transmission) takes place. Therefore, wiring... Alternatively, a portion of the electrode may function as a terminal.

[0041] Furthermore, generally speaking, "capacitance" refers to a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the aforementioned "capacitance." In other words, in this specification, a "capacitive element" refers to a device in which two electrodes face each other across an insulator. Those with a matching configuration, those with a configuration in which two wires face each other with an insulator in between, This includes cases where two wires are arranged with an insulator in between.

[0042] Furthermore, in this specification, "voltage" refers to a potential and a reference potential (for example, ground). It often refers to the potential difference (potential). Therefore, voltage and potential difference can be used interchangeably. can.

[0043] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, the drain (drain terminal, drain (Drain region, or drain electrode) and source (source terminal, source region, or source electrode) It has a channel-forming region between it, and the source and drain are separated by the channel-forming region. Current can be passed between them. In this specification, etc., channel forming region A region refers to an area where electric current primarily flows.

[0044] Furthermore, the source and drain functions may vary depending on whether transistors with different polarities are used, or the circuit dynamics may change. In the process, the direction of the current may change, causing the order to be reversed. Therefore, this specification In written documents and other materials, the terms "source" and "drain" may be used interchangeably.

[0045] Furthermore, unless otherwise specified in this specification, off-current refers to the state in which a transistor is in the off state. This refers to the drain current when the device is in a non-conductive state (also called a closed state). The off state is: Unless otherwise specified, in an n-channel transistor, the gate voltage relative to the source is V When gs is lower than the threshold voltage Vth, in a p-channel transistor, the source is This refers to the state where the gate voltage Vgs is higher than the threshold voltage Vth. The off-current of a Nell-type transistor is the voltage Vgs of the gate relative to the source relative to the threshold voltage. In some cases, the drain current is defined as the current when it is lower than the voltage Vth.

[0046] In the above explanation of off-current, you may substitute "drain" for "source." That is, off-current This can refer to the source current when the transistor is in the off state. In the same sense, it is sometimes called leakage current. Also, in this specification, etc., off current is The field refers to the current that flows between the source and drain when the transistor is in the off state. There is a match.

[0047] Furthermore, in this specification, on-current refers to the state in which a transistor is on (conductive state, also known as... In the case of (u), it can refer to the current flowing between the source and the drain.

[0048] Furthermore, in this specification, metal oxide refers to a broad term. It is a metal oxide. Metal oxides are oxide insulators and oxide conductors (transparent oxide conductors). It is classified as an oxide semiconductor, etc. (including).

[0049] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide It is sometimes called an oxide semiconductor. In other words, the metal oxide has amplification, rectification, and If it has at least one switching action, the metal oxide is a metal oxide semiconductor. It can be called a (metal oxide semiconductor). A transistor having a metal oxide in the channel formation region is called an "oxide semiconductor transistor". It can be called a "transistor" or "OS transistor."

[0050] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxi They are sometimes referred to as (de). Also, metal oxides containing nitrogen are called metal oxynitrides (met It may also be called al oxynitride. Details about metal oxides will be described later. .

[0051] (Embodiment 1) An example of the configuration of a storage device according to one embodiment of the present invention will be described with reference to Figures 1 to 11. One form of memory is a memory device that can function by utilizing semiconductor properties, and is called memory. It is also known as

[0052] Furthermore, one embodiment of the present invention is a memory device having a layer having transistors formed on a semiconductor substrate. The structure has multiple layers stacked on top of each other, each containing an OS transistor. The inverter has the property of having a very low off-current.

[0053] <Block diagram of storage device> Figure 1A is a block diagram showing an example configuration of a storage device 10A, which is one embodiment of the present invention. In the diagrams described herein, the main signal flow is indicated by arrows or lines. Power lines and other connections may be omitted.

[0054] The storage device 10A has peripheral circuits 20 and memory cell array 30. Peripheral circuits 20 In addition to the low driver 21 and column driver 22, there is a pre-charge circuit 24 and a senser A circuit 25, a test bit generation circuit 54, an error detection circuit 55, and a switch circuit 23 are provided. It has an element layer 26 (see Figure 3).

[0055] The row driver 21 outputs a signal to the word line WL to drive the memory cell array 30. It has the function of providing power. Specifically, the low driver 21 is the word line WL (WL_1 in Figure 1A). It has the function of outputting a word signal to WL_N (where N is a natural number greater than or equal to 2). The w driver 21 is sometimes called the word line drive circuit. The row driver 21 is a finger Decoder circuit for selecting word line WL according to a defined address, and buffer Includes circuits, etc. Word lines (WL) are sometimes simply called wiring.

[0056] The column driver 22 sends a signal to the bit line BL to drive the memory cell array 30. It has the function of outputting. Specifically, the column driver 22 has the bit line BL (BL in Figure 1A). Column driver 22 has the function of outputting data signals to _1 and BL_2 (illustrated). This is sometimes called a bit line driving circuit. Note that the column driver 22 is specified as an address Includes a decoder circuit for selecting the bit line corresponding to the response. The bit line BL is simply It is sometimes called a line. Also, in drawings, bit lines BL are thicker to improve visibility. Alternatively, it may be illustrated with a thick dotted line.

[0057] The data signal applied to bit line BL is a signal to be written to a memory cell, or a memory cell This corresponds to the signal read from the terminal. The data signal is either data 1 or data 0 (data H High level (also called igh or dataLow, dataH or dataL) It is described as a binary signal with a high or low potential. A high potential is a potential VDD, the low-level potential, is the potential VSS, or the ground potential (GND). The data signal may be a multi-level signal with three or more levels.

[0058] Other signals applied to the bit line BL include a precharge signal for reading data. There are potentials, etc. The precharge potential can be, for example, VDD / 2.

[0059] The memory cell array 30 has, for example, N layers (where N is a natural number greater than or equal to 2) of element layers 34_1 to 3 It has 4_N. The element layer 34_1 has one or more memory cells 31_1. Layer 31_1 has a transistor 32_1 and a capacitor 33_1. Element layer 34_ N has one or more memory cells 31_N. Memory cell 31_N is connected to transistor 3 It has 2_N and capacitor 33_N.

[0060] Note that capacitors are sometimes called capacitance or capacitive elements. The element layer refers to the capacitor and This refers to a layer on which elements such as transistors are installed, and which is made of materials such as conductors, semiconductors, and insulators. This is a layer that possesses [this characteristic].

[0061] Transistors 32_1 to 32_N are the words supplied to word lines WL_1 to WL_N. Depending on the signal, it will be in a conductive state (also called on or on state) or a non-conductive state (off or It functions as a switch that controls the (also called the off state). Also, transistor 32_ 1 through 32_N are, respectively, either the source or the drain of either bit line BL. They are connected as one.

[0062] Transistors 32_1 to 32_N have a metal oxide in the channel formation region. It is preferable that it be a transistor (hereinafter referred to as an OS transistor). This is achieved by using an OS transistor in the memory cell, so when the transistor is in the off state, The property of having a very small leakage current (hereinafter referred to as off-current) flowing between the casing and the drain. Using this, a charge corresponding to the desired potential is applied to the source of transistors 32_1 to 32_N. This is held by capacitors 33_1 to 33_N which are electrically connected to the other side of the drain. It is possible.

[0063] In other words, memory cells 31_1 to 31_N retain data once it has been written for a long period of time. Therefore, the storage device 10A can reduce the frequency of data refreshes and This allows for reduced power consumption.

[0064] In addition, memory cells 31_1 to 31_N using OS transistors charge and By discharging, data can be rewritten and read, so effectively Unlimited data writing and reading operations are possible.

[0065] Memory cells 31_1 to 31_N using OS transistors are magnetic memory or resistors. Unlike variable-change memory, it does not involve structural changes at the atomic level, thus offering superior rewrite endurance. Furthermore, memory cells 31_1 to 31_N using OS transistors are flat As seen in Schmemori, the increase in electron trapping centers due to repeated rewriting operations No instability was observed.

[0066] Furthermore, memory cells 31_1 to 31_N using OS transistors have a channel formation region. A silicon transistor (hereinafter referred to as a Si transistor) is formed on a silicon It can be mounted on a circuit board or the like. Therefore, integration can be easily performed. Furthermore, OS transistors can be manufactured using the same manufacturing equipment as Si transistors. Therefore, it can be manufactured at a low cost.

[0067] OS transistors have an gate electrode, source electrode, and drain electrode, in addition to a backgear. It can be a 4-terminal semiconductor element including a gate electrode or back gate. Depending on the potential applied to the electrodes, the input and output of the signal flowing between the source and drain are independently controlled. It can be constructed using a possible electrical circuit network. Therefore, LSI (Large Scale Circuit design can be performed using the same thinking process as Integration.

[0068] In addition, OS transistors offer superior electrical performance compared to Si transistors in high-temperature environments. It possesses the following characteristics: Specifically, it can operate on high temperatures, such as between 125°C and 150°C. The ratio of current to off-current is large, enabling good switching operation.

[0069] Note that the memory device 10A shown in Figure 1A uses an OS transistor as a memory cell in a DOSR AM(Dynamic Oxide Semiconductor Random Ac It can be called a memory cell. A memory cell is made up of a single transistor and Because it can be constructed with a single capacitor, it can store a large amount of data, high density Memory can be implemented. Furthermore, by using OS transistors, the data retention time can be extended. It is possible.

[0070] Capacitors 33_1 to 33_N have a configuration in which an insulator is sandwiched between conductive electrodes. Furthermore, in addition to metals, conductive semiconductors can be used as the conductors that make up the electrodes. It is possible to do so. Furthermore, details regarding the arrangement of capacitors 33_1 to 33_N will be described later. However, the configuration is arranged in an overlapping position above or below transistors 32_1 to 32_N. In addition to the formation, a part of the semiconductor layer or electrodes that constitute transistors 32_1 to 32_N It can be used as one of the electrodes of capacitors 33_1 to 33_N.

[0071] Precharge circuit 24, sense amplifier 25, test bit generation circuit 54, error detection circuit 5 5. The element layer 26 on which the switch circuit 23 is provided detects when writing data to the memory cell. The function of generating check bits, and when reading data from a memory cell, the bit line BL Functions for precharging, amplification of the bit line BL potential, and memory using test bits. It has a function to detect whether there are any errors in the data read from the cell.

[0072] Each circuit in element layer 26 (pre-charge circuit 24, sense amplifier 25, test bit generation) Circuit 54, error detection circuit 55, and switch circuit 23 are constructed using OS transistors. It is preferable that each circuit of the element layer 26 is configured using an OS transistor. By doing so, the element layer 26 is provided on a silicon substrate on which the Si transistor is formed. This is possible. Therefore, integration can be easily carried out. Also, OS transistors Since it can be manufactured using the same manufacturing equipment as Si transistors, it can be produced at low cost. It is possible.

[0073] <Schematic diagram of a memory device> In each configuration described in Figure 1A, regarding the element layers 34_1 to 34_N and the element layer 26 To explain this, a schematic diagram showing an example of the configuration of the storage device 10A is shown in Figure 1B. The schematic diagram below illustrates the arrangement of each component described in Figure 1A, specifying the x, y, and z axes. This is a defined perspective.

[0074] As shown in Figure 1B, the memory device 10A has an element layer 26 and an element layer 34_1 to an element layer A layer having a total of (1+N) OS transistors of 34N is stacked on the semiconductor substrate 11. They are arranged in layers. In addition, element layer 26 and element layers 34_1 to 34_N are provided Each of the memory cells 31_1 to 31_N is located in a column provided on the semiconductor substrate 11. It has an overlapping region with the driver 22. The element layer 26 is made up of the semiconductor substrate 11 and the element layer It is located between 34_1 and 34_1.

[0075] The semiconductor substrate 11 is not limited as long as it is possible to form the channel region of the transistor. Not specified. For example, single-crystal silicon substrate, single-crystal germanium substrate, compound semiconductor substrate (SiC substrates, GaN substrates, etc.), SOI (Silicon on Insulator) ) A substrate or the like can be used.

[0076] Then, the transistor of the memory cell 31_1 located in the element layer 34_1, and the element layer 34_N The transistor of the memory cell 31_N has a bit line BL that is arranged vertically. They are electrically connected via. Also, the bit line BL is electrically connected to the element layer 26, and the element Layer 26 is electrically connected to a column driver 22 provided on the semiconductor substrate 11.

[0077] For example, bit line BL_1 is in contact with the semiconductor layer of the transistor of memory cell 31_1. It is provided in this way. Alternatively, bit line BL_1 is a transient of memory cell 31_1 It is provided in contact with a region that functions as a source or drain in the semiconductor layer of the sta. The bit line BL_1 is the source of the semiconductor layer of the transistor in memory cell 31_1. Alternatively, it may be provided in contact with a conductor that is provided in contact with a region that functions as a drain.

[0078] In other words, the bit line BL is the source or bit of the transistor that memory cell 31_1 has. One of the rains and one of the source or drains of the transistor in memory cell 31_N It can be said that this is wiring that electrically connects the element layer 26 to the other side.

[0079] Furthermore, the bit line BL is perpendicular to the surface of the semiconductor substrate 11 on which the column driver 22 is provided. It can be said that it is provided extending in a direction or approximately vertically. That is, as shown in Figure 1B As such, the bit line BL is connected to the transistor of memory cell 31_1, and the memory It is connected to the transistor of cell 31_N and on the surface (xy plane) of the semiconductor substrate. It is provided perpendicular (z-direction) or approximately perpendicular to it. Note that "approximately perpendicular" means This refers to a state where objects are arranged at an angle between 85 and 95 degrees.

[0080] In a memory device 10A, which is one embodiment of the present invention, the transistors provided in each element layer are: OS transistors with very low off-currents are used. Therefore, the memory cells are held... This storage device reduces the frequency of data refreshes and achieves lower power consumption. It is possible.

[0081] OS transistors can be stacked and manufactured using the same process repeatedly in the vertical direction. Because it can be manufactured in this way, manufacturing costs can be reduced. 10A arranges the transistors that make up the memory cell vertically, rather than in a planar direction. Memory density can be improved. Therefore, the size of the storage device 10A can be reduced. can.

[0082] Furthermore, OS transistors exhibit superior electrical characteristics compared to Si transistors, even in high-temperature environments. Because the fluctuations are small, the fluctuations in the electrical characteristics of transistors when stacked and integrated are small, and reliability It can function as a highly reliable memory device.

[0083] The storage device 10A can arrange memory cells above the column driver, etc. Therefore, the storage device 10A is a small, high-density storage device that can store a large amount of data. This is possible. Furthermore, it is possible to operate even if the capacitance of the memory cell's capacitor is reduced. It is possible.

[0084] Furthermore, the memory device 10A provides bit lines extending from the memory cell array to the semiconductor substrate By providing it in a direction roughly perpendicular to the surface of the plate 11, the memory cell array and the element layer 26 are separated. The length of the bit line can be shortened. Therefore, the parasitic capacitance of the bit line can be reduced, thus reducing the memory cell. Even if the data signal held in the device is multi-leveled, the potential can still be read out.

[0085] <Cross-section of a storage device> Figure 2 shows the vertical direction (z-axis direction) of the storage device 10A, as explained using Figures 1A and 1B. A schematic diagram of a cross-section parallel to ) is shown.

[0086] As shown in Figure 2, the memory device 10A has memory cells 31_1 provided in each element layer. The 31_N, the element layer 26, and the column driver 22 provided on the semiconductor substrate 11 are connected vertically. It can be connected via a bit line BL provided perpendicularly. By positioning it in the direction of the bit line BL, the length of the bit line BL can be shortened, thus reducing the negative aspect of the bit line BL. The load can be reduced.

[0087] In Figure 3, the memory cell array 30 consists of element layers 34_1 to 34_N and a precharge circuit. 24. Sense amplifier 25. Test bit generation circuit 54. Error detection circuit 55. Switch circuit Element layer 26 having 23, and write / read circuit 2 of column driver 22 Figure 9 is shown.

[0088] Furthermore, Figure 3 shows the bit line BL_A or BL_B and the pre-charge circuit 24 and sensor. Transistors 28_a and 28_b control the conduction with amplifier 25, and switch Switches 23_A to 23_C of circuit 23 are shown in the diagram. BL_A is connected to either the source or drain of transistor 28_a, and the bit line BL_B is connected to either the source or the drain of transistor 28_b.

[0089] Above the element layer 26 shown in Figure 3, element layers 34_1 to 34_N are provided, and bit Line BL_A and bit line BL_B are provided in a vertical direction. That is, as part of the peripheral circuitry. The element layer 26 that constitutes the element layer can be stacked in the same manner as the element layers 34_1 to 34_N. Also, bit lines BL_A and BL_B are connected to transistor 28_a and The pre-charge circuit 24 and sense amplifier 25 are configured via transistor 28_b. It is connected to the transistor.

[0090] The pre-charge circuit 24 is composed of n-channel transistors 24_1 to 24_3. The precharge circuit 24 responds to the precharge signal supplied to the precharge line PCL. Then, bit lines BL_A and BL_B are connected, for example, to potentials VDD and VSS. This circuit is for precharging the intermediate potential VPC, which corresponds to the potential VDD / 2 between the two points.

[0091] The sense amplifier 25 has n-channel type transistors 25_1 to 25_4, Transistor 25_1 and transistor 25_2 are connected to wiring VHH, and transistor 25 _3 and transistor 25_4 are connected to wiring VLL. Wiring VHH is at potential VDD. The supply function, wiring VLL has the function of supplying potential VSS. Also, transistor 2 5_1 through 25_4 are transistors that constitute the inverter loop.

[0092] When reading data from a memory cell, the precharge circuit 24 precharges the bit line. The low driver 21 then sets the word line of the selected memory cell to a high level, The potential of the recharged bit line changes. The sense amplifier 25 responds to this change. The potential of the pair of wires connected to the sense amplifier 25 is defined as potential VDD or potential VSS, and The potential is output to the write / read circuit 29 via the switch circuit 23.

[0093] The test bit generation circuit 54, when writing data to the memory cell, interacts with the write / read circuit 2 It has a function to generate test bits based on the data signal output from 9, and error detection cycle When reading data from a memory cell, path 55 uses a check bit to read data from the memory cell. The system detects whether there are any errors in the output data and outputs the result to the write / read circuit 29. It has the function of [doing something]. Details of the test bit generation circuit 54 and the error detection circuit 55 will be described later. .

[0094] Furthermore, as shown in Figure 2, the element layers 34_1 to 34_N and elements in the memory device 10A If layer 26 is referred to as unit 39, the units 39 may be stacked vertically. Figure 4 shows the unit 39 described in Figure 2 in M ​​stages (unit 39_1 to unit 39_ Figure 4 shows a storage device 10B with a stacked configuration of M (where M is a natural number greater than or equal to 2). This is a schematic diagram of a cross-section parallel to the vertical direction (z-axis direction) of B.

[0095] As shown in Figure 4, the storage device 10B is located in units 39_1 to 39_M. Each has element layers 34_1 to 34_N and element layer 26, respectively. One of units 39_1 through 39_M is selected, and the selected unit 39 The wiring BL_U and element layer 26 provide signal input or signal output. U is selected by a switch circuit 41 that can be switched by a selection signal SEL, and via wiring GBL It is then connected to the column driver 22. The switch circuit 41 constitutes the element layer 26. It may also be constructed using OS transistors.

[0096] By configuring the storage device 10B, each of units 39_1 to 39_M The number of stacked element layers 34_1 to 34_N can be reduced. By reducing the number of layers from 1 to 34_N, the length of the bit line BL can be shortened. The load on the bit line BL can be reduced. Note that in the drawing, the wiring GBL is visible. To improve clarity, diagrams may be drawn with thick lines or thick dotted lines. Wiring GBL is global It is sometimes called a rubit line.

[0097] Note that the wiring GBL shown in Figure 4 is provided after the element layer containing the OS transistor has been fabricated. It is possible to do so. For example, as shown in the schematic cross-sectional diagram in Figure 5A, an OS transistor is used. An element layer is fabricated, and an opening is provided on the outer circumference of the sealing layer 40A surrounding each element layer, and the opening A wiring GBL can be provided. Alternatively, as shown in the schematic cross-sectional view in Figure 5B, OS A device layer containing transistors is fabricated, and the outer periphery of the sealing layer 40B surrounds each device layer collectively. An opening can be provided, and wiring GBL can be installed in the opening. See Figures 5A and 5 In B, the switch circuit 41 and the like are omitted, and the details of each element layer equipped with wiring GBL are not described. This will be described in detail in Embodiment 3.

[0098] <Test bit generation circuit, error detection circuit> Figure 6A is a circuit diagram showing an example configuration of the test bit generation circuit 54. Test bit generation circuit 5 4 has XOR circuits 53_1 to 53_3. Note that the structure of XOR circuit 53 Examples will be given later.

[0099] For the sake of clarity, in the memory device 10A, the memory cell array 30 is The element layers 34_1 to 34_N are described assuming that N is 5. Of layers 1 through 34, one layer is used to hold the check bits, and the remaining four layers are used for data The data is held. That is, the test bit generation circuit 54 described in this embodiment is It is a circuit that handles 4 bits of data and 1 bit of check bit.

[0100] The test bit generation circuit 54 has input terminals T_A0 to T_A3, and each of them A 4-bit data represented by bits A0 through A3 is input, and a check bit is raw. The circuit 54 has input terminals T_CK1 to T_CK4, each of which controls The clock signals CK1 to CK4 are input. Then, the test bit is raw Circuit 54 outputs a test bit from the output terminal OUT.

[0101] Figure 6B shows the clock signals CK1 to C input to the test bit generation circuit 54. The relationship between K4 and the input period PDI of the 4-bit data and the output period PDO of the check bit. This is a timing chart showing the relationship between clock signals CK1 to CK4 and In 4-bit data, high levels are represented using the potential VDD, and low levels are represented using the potential VSS. Since they are represented using these terms, in Figure 6B they are denoted as Vdd(H) and Vss(L), respectively.

[0102] Furthermore, Figure 6C shows the output for the 4-bit data input to the test bit generation circuit 54. This is a truth table expressed at high level (H) or low level (L). Truth values ​​shown in Figure 6C The table shows that if the number of high-level (H) bits among bits A0 to A3 is odd, the check bit... The signal generation circuit 54 outputs a high level (H), and if the number of high levels (H) is even or zero In this case, the test bit generation circuit 54 outputs a low level (L).

[0103] Next, Figure 7A is a circuit diagram showing an example configuration of the error detection circuit 55. Error detection circuit 55 This consists of XOR circuits 53_4 to 53_7 and delay circuits 52_1 to delay It has circuit 52_4. An example of the configuration of the delay circuit 52 will be described later.

[0104] Furthermore, similar to the test bit generation circuit 54, the error detection circuit described in this embodiment Circuit 55 is a circuit that handles 4 bits of data and 1 bit of check bit.

[0105] The error detection circuit 55 has input terminals T_A0 to T_A3, and each of them When 4-bit data represented by bit A0 to bit A3 is input, the error detection circuit 55, It has input terminals T_CK1 to T_CK4, each containing a control signal, which is a clock. Signal CK1 to clock signal CK4 is input, and the error detection circuit 55 is input terminal It has T_B0 and the test bit B0 is input. Then the error detection circuit 55 has the test bit If no errors are found in the relationship between bit B0 and bits A0 through A3, then output terminal O The UT outputs a low level (L), and if an error is found, it outputs a high level (H).

[0106] Figure 7B shows the clock signals CK1 to CK4 input to the error detection circuit 55. The output of the error detection circuit 55 includes 4-bit data, the input period PDI of the test bit, and the output of the error detection circuit 55. This is a timing chart showing the relationship with the PDO period. Clock signal CK1 to clock The signal CK4, 4-bit data, and the check bit, are expressed using the potential VDD when the high level is reached. Therefore, since the low level is represented using the potential VSS, in Figure 7B, Vdd( It is denoted as H) and Vss(L).

[0107] Furthermore, Figure 8 shows the 4-bit data and the check bit input to the error detection circuit 55. This is a truth table that represents the output as either high level (H) or low level (L). (See Figure 8) The truth table is such that the check bit B0 is low level (L), and bits A0 through A3 are If the number of high-level (H) signals is odd, the error detection circuit 55 outputs a high-level (H) signal. This indicates that it is powerful. This means that among bits A0 to A3, the high level ( If the number of H) is odd, the test bit generation circuit 54 generates a high level (H) as the test bit. Since this output indicates that an error is found in the relationship between check bit B0 and bits A0 through A3. This indicates that it was used.

[0108] Furthermore, the truth table shown in Figure 8 indicates that the check bit B0 is high (H), and bit A0 is When the number of high levels (H) among bits A0 to A3 is even or zero, error detection circuit 5 5 indicates that it outputs a high level (H). This means that among bits A0 to A3, when the number of high levels (H) is even or zero, test bit generation circuit 54 outputs a low level (L) as a test bit, indicating that an error has been found in the relationship between test bit B0 and bits A 0 to A3.

[0109] That is, by including test bit generation circuit 54, test bit B0, and error detection circuit 55 memory device 10A can perform parity checks both during data writing and reading inside the memory device. Also, the output signal of error detection circuit 55 is output to column driver 22 via switch 23_C.

[0110] <XOR circuit, NAND circuit, delay circuit> Fig. 9A is a symbol representing XOR circuit 53, and Fig. 9B is a circuit diagram showing a configuration example of XOR circuit 53. As shown in Fig. 9B, XOR circuit 53 includes NAND circuits 51_1 to NAND circuits 51_4, delay circuit 52_1, and delay circuit 52_2. Also, XOR circuit 53 has input terminal D, input terminal E, and input terminals C5 to C8 to which control signals S_C5 to control signals S_C8 are input, and outputs a signal from output terminal Z .

[0111] Fig. 9C is a timing chart showing the relationship between control signals S_C5 to S_C8 input to XOR circuit 53, the input period PDI of the signals input to input terminal D and input terminal E, and the output period PDO of XOR circuit 53. Control signals S_C5 to control signals S_C8 The high level of the signal S_C8 and the input signal is represented using the potential VDD, and the low level is represented using the potential VDD. Since the potential VSS is used, in Figure 9C, Vdd(H) and Vss( It is written as L).

[0112] Furthermore, Figure 9D shows the output of the signal input to the XOR circuit 53, which is set to a high level (H). This is a truth table expressed at low levels (L). The truth table shown in Figure 9D is for input terminal D, This shows the relationship between the signal input to input terminal E and the signal output from output terminal Z.

[0113] Figure 10A is a symbol representing the NAND circuit 51, and Figure 10B is a symbol representing the NAND circuit 51. This is a circuit diagram showing an example configuration. As shown in Figure 10B, the NAND circuit 51 is a transistor It has transistors 61 to 64 and capacitor C61. Transistor 64 is an n-channel transistor. Also, the NAND circuit 51 is... Input terminal A, input terminal B, and control signals S_C1 and S_C2 are input. It has input terminals C1 and C2, and outputs a signal from output terminal X.

[0114] Figure 10C shows the control signals S_C1 and S_C2 input to the NAND circuit 51. The input period PDI of the signals input to input terminals A and B, and the NAND gate This is a timing chart showing the relationship between the output period of path 51 and the PDO. Control signal S_C1, The high levels of the control signal S_C2 and the input signal are represented using the potential VDD. - Since the level is expressed using the potential VSS, in Figure 10C, Vdd(H) and It is written as Vss(L).

[0115] Furthermore, Figure 10D shows that the output for the signal input to the NAND circuit 51 is set to a high level (H This is a truth table expressed at ) or low level (L). The truth table shown in Figure 10D is an input terminal Show the relationship between the signal input to input terminal B and the signal output from output terminal X. Yes, they are.

[0116] Figure 11A is a symbol representing the delay circuit 52, and Figure 11B is a symbol representing the delay circuit 52. This is a circuit diagram showing an example configuration. As shown in Figure 11B, the delay circuit 52 is a transistor It has transistor 71, transistor 72, and capacitor C71. Transistor 71 and Transistor 72 is an n-channel transistor. Also, delay circuit 52 is... Input terminal C, input terminal C3 to which control signals S_C3 and S_C4 are input It has an input terminal C4 and outputs a signal from the output terminal Y.

[0117] Figure 11C shows the control signals S_C3 and S_C4 input to the delay circuit 52. The input period PDI of the signal input to input terminal C, and the output period of the delay circuit 52. This is a timing chart showing the relationship with PDO. Control signal S_C3, control signal S_C4 The high levels of the input signal are represented using potential VDD, and the low levels are represented using potential V Since they are expressed using SS, in Figure 11C they are shown as Vdd(H) and Vss(L), respectively. It is written.

[0118] Furthermore, Figure 11D shows that the output for the signal input to the delay circuit 52 is set to high level (H This is a truth table expressed at ) or low level (L). The truth table shown in Figure 11D is an input terminal This shows the relationship between the signal input to child C and the signal output from output terminal Y.

[0119] <Storage device> One embodiment of the present invention is a memory device in which, as transistors provided in each element layer, the off-current is non Always use small OS transistors. OS transistors are, for example, Si transistors. Since it can be laminated on a silicon substrate on which it is provided, it can be repeatedly arranged in the vertical direction. It can be manufactured using the same manufacturing process, thereby reducing manufacturing costs. Furthermore, One embodiment of the present invention is a memory device in which the transistors constituting the memory cell are not oriented in a planar direction, By arranging them vertically, memory density can be improved, and storage devices can be made smaller. can.

[0120] In addition, one embodiment of the present invention includes a test bit generation circuit, a test bit, and an error - It is equipped with a detection circuit. Therefore, one embodiment of the present invention is a storage device, inside the storage device, Parity checks can be performed along with data writing and reading. Furthermore, the test bit generation circuit and error detection circuit can also be constructed using OS transistors. By arranging the circuit vertically, the size of the memory device can be reduced.

[0121] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0122] (Embodiment 2) In this embodiment, a modification of the circuit applicable to the storage device 10A described in Embodiment 1 above is provided. An example will be explained using Figure 12.

[0123] Figure 2 shows the memory cells 31_1 to 31_N and the element layer 26. As the transistor, a top gate structure or a bottom gate structure without a back gate electrode is shown, but the structure of the transistor is not limited to this. For example, as shown in FIG. 12 a transistor having a back gate electrode connected to the back gate electrode line BGL like the memory device 10C may be used. By adopting the configuration of FIG. 12, the threshold voltage of the transistor can be controlled from the outside.

[0124] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0125] (Embodiment 3) Hereinafter, an example of a memory device according to an aspect of the present invention will be described.

[0126] FIG. 13 is a diagram showing an example of a memory device in which memory units 470 (memory units 470_1 to memory units 470_m: m is a natural number of 1 or more) are stacked on an element layer 411 having a circuit provided on a semiconductor substrate 311. In FIG. 13, the element layer 411 and a plurality of memory units 470 are stacked on the element layer 411, and in the plurality of memory units 4 70, an example is shown in which one transistor layer 413 (any one of transistor layers 413_1 to transistor layers 413_m) and a plurality of memory device layers 41 5 (memory device layers 415_1 to memory device layers 415_n: n is a natural number of 2 or more ) are provided. Note that in each memory unit 470, an example is shown in which the memory device layer 41 5 is provided on the transistor layer 413, but this is not limited in this embodiment. The transistor layer 413 may be provided on the plurality of memory device layers 415. 13, but this is not limited in this embodiment. Alternatively, memory device layers 415 may be provided above and below the transistor layer 413.

[0127] The element layer 411 has transistors 300 provided on the semiconductor substrate 311, and the memory device It can function as a peripheral circuit. Examples of peripheral circuits include column drivers and load drivers. Drivers, column decoders, row decoders, amplifier circuits, input / output circuits, control logic Circuits and the like are examples.

[0128] The transistor layer 413 has transistor 200T and controls each memory unit 470. It can function as a circuit. The memory device layer 415 is memory device 42 It has 0. The memory device 420 shown in this embodiment has a transistor 200M and a capacity It has 292.

[0129] There are no particular restrictions on the value of m mentioned above, but it is preferably between 1 and 100, and more preferably between 1 and 5. It is 0 or less, more preferably 1 or more and 10 or less. Furthermore, the value of n is particularly There are no restrictions, but the number should be between 2 and 100, preferably between 2 and 50, and more preferably 2 or more. It is 100 or less. Also, the product of m and n is 2 or more and 256 or less, preferably 2 or more and 12 It is 8 or less, more preferably 2 to 64.

[0130] Figure 13 also shows transistor 200T and transistor included in memory unit 470. This shows a cross-sectional view of the ZISTA 200M in the channel length direction.

[0131] As shown in Figure 13, a transistor 300 is provided on the semiconductor substrate 311, On 300 are the transistor layer 413 and memory device layer of the memory unit 470. 415 is provided, and the transistor 200T included in the transistor layer 413 within one memory unit 470 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424. The transistor 200T included in the transistor layer 413 in each memory unit 470 is electrically connected by a conductor 426. Also, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 that electrically connects to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. Also, the conductor 426 is preferably provided in each layer of the transistor layer 413 and the memory device layer 415. Furthermore, although details will be described later, it is preferable to provide an insulator that suppresses the permeation of impurities such as water or hydrogen and oxygen on the side surfaces of the conductor 424 and the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon oxynitride may be used. The memory device 420 includes a transistor 200M and a capacitor 292, and the transistor 200M can have the same structure as the transistor 200T included in the transistor layer 413. Also, the transistor 200T and the transistor 200M may be collectively referred to as the transistor 200. Here, for the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the semiconductor including the region where the channel is formed. The transistor 200T included in the transistor layer 413 within one memory unit 470 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424. The transistor 200T included in the transistor layer 413 in each memory unit 470 is electrically connected by a conductor 426. Also, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 that electrically connects to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. Also, the conductor 426 is preferably provided in each layer of the transistor layer 413 and the memory device layer 415.

[0132] Furthermore, although details will be described later, it is preferable to provide an insulator that suppresses the permeation of impurities such as water or hydrogen and oxygen on the side surfaces of the conductor 424 and the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon oxynitride may be used. The memory device 420 includes a transistor 200M and a capacitor 292, and the transistor 200M can have the same structure as the transistor 200T included in the transistor layer 413. Also, the transistor 200T and the transistor 200M may be collectively referred to as the transistor 200.

[0133] Here, for the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the semiconductor including the region where the channel is formed. The transistor 200M can have the same structure as the transistor 200T included in the transistor layer 413. Also, the transistor 200T and the transistor 200M may be collectively referred to as the transistor 200. Here, for the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the semiconductor including the region where the channel is formed.

[0134] The transistor 200T included in the transistor layer 413 within one memory unit and the memory device included in the memory device layer are electrically connected by a plurality of conductors . The transistor 200T included in the transistor layer 413 in each memory unit is electrically connected by a conductor <000095>:

[0135] As an oxide semiconductor, for example, In-M-Zn oxide (where element M is aluminum, galvanic acid) M, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium (One or more types selected from tantalum, tungsten, or magnesium, etc.) It is preferable to use metal oxides such as those listed above. In addition, indium oxide and In-G are suitable as oxide semiconductors. α oxide and In-Zn oxide may also be used. Note that an oxide with a high proportion of indium may also be used. By using a semiconductor material, the on-current or field-effect mobility of the transistor can be increased. It is possible.

[0136] Transistor 200, which uses an oxide semiconductor in the channel formation region, exhibits poles in the non-conductive state. Furthermore, because the leakage current is small, it is possible to provide a low-power memory device. Because it can be deposited using methods such as sputtering, it can be used to construct highly integrated memory devices. It can be used with the 200.

[0137] On the other hand, transistors using oxide semiconductors are affected by impurities and oxygen vacancies in the oxide semiconductor. However, its electrical characteristics fluctuate, and it exhibits normally-on characteristics (even without applying voltage to the gate electrode). This is a characteristic where a channel exists and current flows through the transistor.

[0138] Therefore, it is preferable to use oxide semiconductors with reduced impurity concentration and defect level density. In this specification, a low impurity concentration and defect level density is considered to indicate high purity or intrinsic purity. It is essentially high-purity genuine.

[0139] Therefore, it is preferable that the impurity concentration in the oxide semiconductor be reduced as much as possible. Examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, and alkaline earth elements. Examples include metals such as iron, nickel, and silicon.

[0140] In particular, hydrogen as an impurity contained in oxide semiconductors causes oxygen vacancies (V) in oxide semiconductors. O It can form an oxygen vacancy. Also, water can form in oxygen vacancies. A defect that contains raw material (hereinafter, V O (Sometimes called H) is the site where carrier electrons are generated. There is a combination. Furthermore, some of the hydrogen reacts with oxygen that bonds with the metal atom, forming electron carriers. This may generate

[0141] Therefore, transistors using oxide semiconductors with a high hydrogen content are normally-on It is prone to becoming a characteristic. Also, hydrogen in oxide semiconductors moves due to stress such as heat and electric fields. Because it is prone to this, if oxide semiconductors contain a lot of hydrogen, the reliability of transistors deteriorates. There is a risk that this may happen.

[0142] Therefore, the oxide semiconductor used in transistor 200 is free of impurities such as hydrogen and oxygen. It is preferable to use a high-purity, intrinsic oxide semiconductor with reduced loss.

[0143] <Sealing structure> Therefore, in order to suppress the intrusion of impurities from the outside, a material that suppresses the diffusion of impurities (hereinafter, It is preferable to encapsulate transistor 200 using a barrier material (also known as an impurity barrier material). .

[0144] In this specification, etc., barrier properties refer to the function of suppressing the diffusion of the corresponding substance (permeability). It is said that the amount is low. Alternatively, it captures and fixes the corresponding substance (gettarin). (Also known as "g") This function is intended to be used.

[0145] For example, aluminum oxide is a material that has the function of suppressing diffusion to hydrogen and oxygen. Indium, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride , or silicon nitride oxide, etc. In particular, silicon nitride or silicon nitride oxide, Because it has high barrier properties against hydrogen, it is preferable to use it as a sealing material.

[0146] Furthermore, for example, aluminum oxide is a material that has the function of capturing and fixing hydrogen. Metal oxides such as hafnium oxide, gallium oxide, and indium gallium zinc oxide be.

[0147] Between transistor 300 and transistor 200, there is an insulating layer acting as a barrier. It is preferable that insulators 211, 212, and 214 are provided. Insulator 211 , diffusion or permeation of impurities such as hydrogen into at least one of the insulator 212 and insulator 214 By using materials that suppress the effects contained in semiconductor substrate 311, transistor 300, etc. This can suppress the diffusion of impurities such as hydrogen and water into transistor 200. Also, insulator 2 11. A material that suppresses oxygen permeability is provided in at least one of the insulators 212 and 214. By using this, the channel of transistor 200, or the transistor layer 413, This can suppress the diffusion of oxygen into the element layer 411. For example, the insulator 211 and the insulating As body 212, a material that suppresses the permeation of impurities such as hydrogen and water is used, and as insulator 214 It is preferable to use a material that suppresses oxygen permeation. Also, hydrogen absorbent material is used as the insulator 214. It is even more preferable to use a material that has the properties of absorbing and storing. Insulator 211, and For example, nitrides such as silicon nitride and silicon nitride oxide can be used as the insulator 212. This is possible. As the insulator 214, for example, aluminum oxide, hafnium oxide, oxide Metal oxides such as gallium and indium gallium zinc oxide can be used. In this case, it is preferable to use aluminum oxide as the insulator 214.

[0148] Furthermore, the sides of the transistor layer 413 and the memory device layer 415, i.e., the memory unit Preferably, an insulator 287 is provided on the side of the 470, and the memory unit 470 It is preferable that an insulator 282 is provided on the upper surface. In this case, the insulator 282 is an insulator It is preferable that it be in contact with 287, and the insulator 287 is insulator 211, insulator 212, and It is preferable that it be in contact with at least one of the insulators 214. Insulator 287 and insulator 2 For 82, it is preferable to use a material that can be used for the insulator 214.

[0149] Furthermore, insulators 283 and 287 are placed so as to cover insulators 282 and 287. It is preferable that 4 is provided, and the insulator 283 is an insulator 211, an insulator 212, and It is preferable that it be in contact with at least one of the insulators 214. In Figure 13, the insulator 287 is an insulator. It is in contact with the side surface of the edge 214, the side surface of the insulator 212, and the top and side surfaces of the insulator 211. This shows an example where insulator 283 is in contact with the side surface of insulator 287 and the top surface of insulator 211. However, this embodiment is not limited to this. The insulator 287 is on the side surface of the insulator 214, and the insulator The insulator 283 is in contact with the top and side surfaces of 212, and the insulator 283 is in contact with the side surfaces of insulator 287 and insulator 21 It may be in contact with the upper surface of 2. Insulator 282 and insulator 287 are insulator 211 It is preferable to use a material that can be used for the insulator 212.

[0150] In the above structure, the insulator 287 and the insulator 282 are materials that suppress oxygen permeation. It is preferable to use the following. Also, hydrogen is captured as insulator 287 and insulator 282. Furthermore, it is even more preferable to use a material that has the property of fixing. By using a material on the adjacent side that has the function of capturing and fixing hydrogen, the transient Hydrogen in the sta200 or memory unit 470 is contained in insulator 214, insulator 287, And because it is captured and fixed to the insulator 282, the hydrogen concentration in transistor 200 This can reduce the amount of hydrogen and water used as insulators 283 and 284. It is preferable to use a material that suppresses the permeation of impurities.

[0151] With the above structure, the memory unit 470 has an insulator 211 and an insulator 212 , by insulator 214, insulator 287, insulator 282, insulator 283, and insulator 284 It is surrounded. More specifically, the memory unit 470 has an insulator 214, an insulator 287, and surrounded by an insulator 282 (sometimes referred to as the first structure), the memory unit The first structure comprises insulator 211, insulator 212, insulator 283, and It is surrounded by an insulator 284 (sometimes referred to as the second structure). When a structure in which the memory unit 470 is surrounded by two or more layers of structures is called a nested structure Here, the memory unit 470 is surrounded by multiple structures, which is called the memory unit. It may be stated that Knit 470 is sealed with multiple insulators.

[0152] Furthermore, the second structure encapsulates the transistor 200 through the first structure. The hydrogen outside the second structure is, by the second structure, inside the second structure ( Diffusion to the Rangista 200 side is suppressed. In other words, the first structure is suppressed by the second structure. It can efficiently capture and fix hydrogen present in its internal structure.

[0153] Specifically, the first structure uses a metal oxide such as aluminum oxide. For the second structure, nitrides such as silicon nitride can be used. More specifically, When an aluminum oxide film is placed between transistor 200 and silicon nitride film, good.

[0154] Furthermore, the hydrogen concentration in the film can be controlled by appropriately setting the film deposition conditions for the materials used in the structure. It can be reduced.

[0155] Generally, films deposited using CVD are more durable than films deposited using sputtering. , high coating properties. On the other hand, compound gases used in CVD often contain hydrogen, CV Films deposited using method D have a higher hydrogen content than films deposited using the sputtering method. There are many.

[0156] Therefore, for example, a film with a reduced hydrogen concentration in the film is placed in close proximity to the transistor 200. Specifically, it is preferable to use a film deposited using the sputtering method. On the other hand, the spread of impurities As a membrane that suppresses dispersion, a membrane that has high film-forming properties while also having a relatively high hydrogen concentration within the membrane (specifically) When using a film deposited using the CVD method, the hydrogen concentration is relatively high for transistor 200. It has the function of capturing and fixing hydrogen between itself and a film that is highly protective and has high film-forming properties, and hydrogen It is advisable to place a membrane with reduced concentration.

[0157] In other words, the film placed in close proximity to transistor 200 is a film with a relatively low hydrogen concentration within it. It is good to use it. On the other hand, a film with a relatively high hydrogen concentration in the film is far from transistor 200. It's best to arrange them like this.

[0158] Specifically, the above structure involves a transistor 200 with a nitride film deposited using the CVD method. When sealing with Ricon, the transistor 200 and the nitride film deposited using the CVD method are used. When an aluminum oxide film deposited using the sputtering method is placed between the recon film and the aluminum oxide film, Good. More preferably, a silicon nitride film deposited using the CVD method and sputtering A nitrogen film deposited using the sputtering method is placed between the aluminum oxide film deposited using the method and the aluminum oxide film deposited using the sputtering method. It is advisable to place a silicon dioxide film.

[0159] Furthermore, when forming a film using the CVD method, the hydrogen atom-free or hydrogen atom-containing material may be used. By using a small amount of compound gas to form the film, the hydrogen concentration in the formed film can be reduced. That's good too.

[0160] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device It is preferable that insulators 282 and 214 are also provided between layers 415. Furthermore, it is preferable that an insulator 296 is provided between the insulator 282 and the insulator 214. The insulator 296 can be made of the same material as insulators 283 and 284. Alternatively, silicon oxide or silicon oxide nitride can be used. Alternatively, a known aqueous solution can be used. Edge material may be used. Here, insulator 282, insulator 296, and insulator 214 are These may also be elements that make up transistor 200. Insulator 282, insulator 296, The insulator 214 also serves as a component of the transistor 200, thus making it easier to manufacture a memory device. This is preferable because it reduces the number of steps involved in the manufacturing process.

[0161] Also, between each transistor layer 413 and the memory device layer 415, or between each memory device Each of the insulators 282, 296, and 214 provided between layers 415 The side surface is preferably in contact with the insulator 287. This structure allows the transient The star layer 413 and the memory device layer 415 are insulators 282 and 296, respectively. Surrounded and sealed by insulators 214, 287, 283, and 284 It can be done.

[0162] Furthermore, an insulator 274 may be provided around the insulator 284. The conductor 430 is provided so as to be embedded in the edge 284, the insulator 283, and the insulator 211. Alternatively, the conductor 430 is connected to the transistor 300, i.e., the circuit included in the element layer 411. To connect electrically.

[0163] Furthermore, in the memory device layer 415, the capacitance 292 is formed on the same layer as the transistor 200M. Therefore, the height of the memory device 420 is made to be about the same as that of the transistor 200M. This allows us to prevent the height of each memory device layer 415 from becoming excessively large. This makes it relatively easy to increase the number of memory device layers 415. For example, a stack consisting of transistor layers 413 and memory device layers 415, approximately 100 layers You can do it any number of times.

[0164] <Transistor 200> Using Figure 14A, the transistor 200T in the transistor layer 413 and the memory Transistor 200 can be used in transistor 200M of device 420 I will explain this.

[0165] As shown in Figure 14A, the transistor 200 consists of an insulator 216 and a conductor 205 (conductor 205a, and conductor 205b), insulator 222, insulator 224, and oxide 230 (Oxide 230a, oxide 230b, and oxide 230c) and conductor 242 (conductor 242a and conductor 242b), and oxide 243 (oxide 243a and oxide 2 43b) and insulator 272, insulator 273, insulator 250, and conductor 260 (conductor It has 260a and a conductor 260b.

[0166] Furthermore, the insulator 216 and the conductor 205 are provided on the insulator 214, and the insulator 273 Insulators 280 and 282 are provided on top. Insulator 214, insulator 280, And the insulator 282 can be considered to constitute part of the transistor 200. .

[0167] Furthermore, a memory device according to one aspect of the present invention is electrically connected to a transistor 200 and a plug It has a conductor 240 (conductor 240a and conductor 240b) that functions as a conductor. Insulator 241 (insulator 241a, and An insulator 241b) may be provided. Also, on the insulator 282 and on the conductor 240 , Conductor 246 (Conductor 246a, conductor And a conductor 246b) is provided.

[0168] Furthermore, conductors 240a and 240b may be made of tungsten, copper, or aluminum. It is preferable to use a conductive material whose main component is . Also, conductor 240a and conductor 240b may also be a laminated structure.

[0169] Furthermore, when the conductor 240 is made into a laminated structure, impurities such as water or hydrogen, and oxygen permeability... It is preferable to use a conductive material that has a function to suppress overheating. For example, tantalum, nitride Tantalum, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. It is preferable. It also has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. The conductive material may be used in a single layer or in a multilayer structure. By using this conductive material, an insulator Impurities such as water or hydrogen diffusing from 280, etc., affect conductor 240a and conductor 24 The incorporation of 0b into the oxide 230 can be further reduced. Also, the insulator 2 To prevent the oxygen added to 80 from being absorbed by conductors 240a and 240b. It is possible.

[0170] Furthermore, the insulator 241 provided in contact with the side surface of the conductor 240 may be, for example, silica nitride. Cone, aluminum oxide, or silicon nitride can be used. Insulator 241 is , provided in contact with insulator 272, insulator 273, insulator 280, and insulator 282 Therefore, impurities such as water or hydrogen are released from the insulator 280, and the conductor 240a and the conductor This can suppress contamination of oxide 230 through 240b. In particular, silica nitride N is suitable because it has high blocking properties for hydrogen. Also, the insulator 280 contains This prevents oxygen from being absorbed by conductors 240a and 240b.

[0171] Conductor 246 uses a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable that it be present. Furthermore, the conductor may also have a laminated structure, for example, titanium or This may be a laminate of titanium nitride and the above conductive material. It may be formed to be embedded in the cut-out opening.

[0172] In transistor 200, the conductor 260 functions as the first gate of the transistor. Furthermore, conductor 205 functions as the second gate of the transistor. Also, conductor 242 a, and conductor 242b function as source or drain electrodes.

[0173] Oxide 230 functions as a semiconductor having a channel-forming region.

[0174] Insulator 250 functions as the first gate insulator, and insulators 222 and 224 It functions as a second gate insulator.

[0175] Here, the transistor 200 shown in Figure 14A consists of insulator 280, insulator 273, and insulator 2 72. In the openings provided in the conductor 242 and the like, the conductor 260 is made of oxide 230c and an insulating material. It is formed self-aligningly via the edge body 250.

[0176] In other words, the conductor 260 is connected to the insulator 280 via the oxide 230c and the insulator 250. Because it is formed to fill the opening provided in the place, between conductor 242a and conductor 242b In this region, alignment of the conductor 260 becomes unnecessary.

[0177] In this case, it is preferable to provide oxide 230c in the opening provided in the insulator 280 or the like. Therefore, the insulator 250 and the conductor 260 are separated by oxide 230c, and oxide 230 It has a region that overlaps with the layered structure of b and oxide 230a. By adopting this structure, Since it becomes possible to form oxide 230c and insulator 250 by continuous film deposition, oxidation The interface between material 230 and insulator 250 can be kept clean. Therefore, the interface scattering can be kept clean. The impact on carrier conduction is reduced, and transistor 200 has high on-current and high frequency Numerical properties can be obtained.

[0178] Furthermore, the transistor 200 shown in Figure 14A has an insulator on the bottom and sides of the conductor 260. It is in contact with 250. In addition, the bottom surface and sides of the insulator 250 are in contact with the oxide 230c.

[0179] Furthermore, as shown in Figure 14A, transistor 200 consists of an insulator 282 and an oxide 230c The two are in direct contact. This structure allows the acid contained in the insulator 280 to be in direct contact with each other. This can suppress diffusion into the basic conductor 260.

[0180] Therefore, the oxygen contained in the insulator 280 is transferred to oxide 230a via oxide 230c. Since it can be efficiently supplied to oxide 230b, in oxide 230a and oxide Reduces oxygen deficiency in 230b, improving the electrical characteristics and reliability of transistor 200. It is possible.

[0181] The following describes the detailed configuration of a memory device having a transistor 200 according to one aspect of the present invention. I will explain.

[0182] Transistor 200 includes an oxide 230 (oxide 230a, oxide) containing a channel formation region. It is preferable to use an oxide semiconductor for 230b and oxide 230c).

[0183] For example, metal oxides that function as oxide semiconductors have an energy gap of 2 eV or more. Preferably, one with an energy gap of 2.5 eV or higher is used. By using a metal oxide, the leakage current in the non-conductive state of transistor 200 (off) The current can be made very small. By using such transistors, low power consumption can be achieved. It can provide a power consumption memory device.

[0184] Specifically, as oxide 230, In-M-Zn oxide (where element M is aluminum, gas) Rium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from um, tantalum, tungsten, or magnesium. It is preferable to use metal oxides such as (types). In particular, element M can be aluminum, gallium, or yt. It is preferable to use lium or tin. Also, as oxide 230, In-M oxide, In- Zn oxide or M-Zn oxide may also be used.

[0185] As shown in Figure 14A, oxide 230 is oxide 230a on the insulator 224 and oxide 2 Oxide 230b on 30a, and disposed on oxide 230b, at least a portion of which is oxide 2 It is preferable to have oxide 230c in contact with the upper surface of 30b. Here, oxide 23 The sides of 0c are oxide 243a, oxide 243b, conductor 242a, conductor 242b, and insulating It is preferable that the edge 272, the insulator 273, and the insulator 280 are provided in contact with each other. .

[0186] In other words, oxide 230 consists of oxide 230a, oxide 230b on oxide 230a, and acid It has oxide 230c on oxide 230b, and oxide 230a below oxide 230b. This prevents the structure formed below oxide 230a from transferring to oxide 230b. The diffusion of pure substances can be suppressed. In addition, the oxide 230c is located on the oxide 230b. As a result, impurities from the structure formed above oxide 230c are transferred to oxide 230b. This can suppress the spread of [the substance].

[0187] Furthermore, in transistor 200, the channel formation region and its vicinity contain oxide 230 The diagram shows a configuration in which three layers of oxide 230b and oxide 230c are stacked. However, the present invention is not limited thereto. For example, a single layer of oxide 230b, oxide 230 A two-layer structure of b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or 4 A multilayer structure with more than one layer may also be used. For example, a two-layer structure of oxide 230c may be used. Alternatively, a configuration with a four-layer laminated structure may be used.

[0188] Furthermore, oxide 230 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. It is preferable that the metal oxide used in oxide 230a contains constituent elements The atomic ratio of element M in the oxide is the element of the constituent elements in the metal oxide used in oxide 230b. It is preferable that the ratio is greater than the atomic ratio of element M. Also, the metal oxide used in oxide 230a In this case, the atomic ratio of element M to In is in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In is greater than that of In. Also, in oxide 230b In the metal oxide used, the atomic ratio of In to element M is used in oxide 230a. It is preferable that the atomic ratio of In to element M in the metal oxide is greater than that of In. Oxide 230c is a metal oxide that can be used in place of oxide 230a or oxide 230b. The object can be used.

[0189] Specifically, as oxide 230a, In:Ga:Zn = 1:3:4 [atomic ratio], Metals with compositions in the vicinity of that, or a 1:1:0.5 [atomic ratio], or compositions in the vicinity of that. You can use an oxide. Also, as oxide 230b, In:Ga:Zn=4:2:3[ Atomic ratio, or a composition near that ratio, or 1:1:1 [atomic ratio], or a composition near that ratio. A metal oxide with the following composition can be used. Also, as oxide 230c, In:Ga:Zn = 1:3:4 [atomic ratio], or a composition near that, In:Ga:Zn=4:2:3 [atomic ratio] [Atomic ratio], or a composition in its vicinity, In:Ga:Zn=5:1:3 [atomic ratio], or Compositions in the vicinity of, In:Ga:Zn=10:1:3 [atomic ratio], or compositions in the vicinity of, Ga:Zn=2:1 [atomic ratio], or a composition near that, or Ga:Zn=2:5 A metal oxide with a composition of [atomic ratio] or a similar composition may be used. Also, oxide 230 A specific example of a layered structure for c is In:Ga:Zn=4:2:3 [atomic ratio] or a composition in its vicinity, and In:Ga:Zn=1:3:4 [atomic ratio] or its vicinity Layered structure with neighboring compositions, In:Ga:Zn=4:2:3 [atomic ratio], or in its vicinity The composition, and the layered structure of In:Ga:Zn=5:1:3 [atomic ratio], or a composition close to that. Compositions include Ga:Zn=2:1 [atomic ratio] or near that, and In:Ga:Zn=4 :2:3 [atomic ratio], or a layered structure with a composition near that, Ga:Zn=2:5 [atomic ratio] [Atomic ratio], or a composition in its vicinity, and In:Ga:Zn=4:2:3 [atomic ratio], A layered structure with nearby compositions, or gallium oxide and In:Ga:Zn=4:2:3 [Atomic ratio], or layered structures with compositions in the vicinity of that ratio, etc. This includes a range of ±30% of the desired atomic ratio.

[0190] Furthermore, oxide 230b may be crystalline. For example, CAAC-OS, which will be described later. (c-axis aligned crystalline oxide semico It is preferable to use nductor. It has a dense structure with few impurities or defects (such as oxygen deficiencies) and high crystallinity. Therefore, the extraction of oxygen from oxide 230b by the source electrode or drain electrode It can be suppressed. Also, even if heat treatment is performed, oxygen is extracted from oxide 230b. Because it can reduce the risk of failure, transistor 200 is designed to withstand high temperatures during the manufacturing process (so It is stable against thermal budgets.

[0191] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. It is preferable that the conductor 205 is embedded in the insulator 216.

[0192] When the conductor 205 functions as a gate electrode, the potential applied to the conductor 205 is determined by the conductor By changing the potential applied to 260 independently, without being linked to it, transistor 200 The threshold voltage (Vth) can be controlled. In particular, a negative potential is applied to the conductor 205. By adding this, the Vth of transistor 200 is increased and the off-current is reduced. This becomes possible. Therefore, applying a negative potential to the conductor 205 is preferable to not applying one. Rather than combining, the drain current when the potential applied to the conductor 260 is 0V is reduced. can.

[0193] Furthermore, as shown in Figure 14A, the conductor 205 is made of the conductor 242a of oxide 230 and conductor It is preferable to provide a region larger than the area that does not overlap with the electric body 242b. (Not shown in the diagram.) However, the conductor 205 has oxide 230a and acid in the channel width direction of oxide 230. It is preferable that the extension extends to the region outside of oxide 230b. That is, oxide 230 On the outer side of the channel width direction, the conductor 205 and the conductor 260 are insulated. It is preferable that they are superimposed via the edge body. By providing a large conductor 205, In the plasma processing of the fabrication process after the formation of the conductor 205, localized charging In some cases, the charge-up can be mitigated. However, one embodiment of this invention does not It is not limited to the above. Conductor 205 is at least between conductor 242a and conductor 242b. It should be superimposed with oxide 230 located at [location].

[0194] Furthermore, with respect to the bottom surface of the insulator 224, oxide 230a and oxide 230b and conductive In the region where body 260 and the conductor 260 do not overlap, the height of the bottom surface of the oxide 230b is It is preferable that it be positioned lower than the height of the base.

[0195] Although not shown in the diagram, in the channel width direction, the conductor 260, which functions as a gate, The sides and top surfaces of the oxide 230b in the formation region are separated by the oxide 230c and the insulator 250. By creating a structure that covers the conductor 260, the electric field generated from the conductor 260 is generated in the oxide 230b. This makes it easier to apply the effect to the entire channel formation region. Therefore, the on-current of transistor 200 This can increase the frequency characteristics. In this specification, the conductor 260, And the electric field of the conductor 205 electrically surrounds the channel formation region of the transistor. This structure is called a surrounded channel (S-channel) structure.

[0196] Furthermore, conductor 205a is a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. This is preferable. For example, using titanium, titanium nitride, tantalum, or tantalum nitride. This is possible. In addition, the conductor 205b is mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material. Although the conductor 205 is shown as two layers, it is preferable to use three layers. The above multi-layered structure may also be used.

[0197] Here, an oxide semiconductor, an insulator or conductor located beneath the oxide semiconductor, and an oxide A different film type is used to separate an insulator or conductor located on top of a semiconductor without opening it to the atmosphere. By continuously depositing the film, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity film. This is preferable because it allows for the formation of intrinsic oxide semiconductor films.

[0198] Insulator 222, and at least one of insulators 272 and 273 are exposed to water or water This prevents impurities such as ions from entering transistor 200 from the substrate side or from above. It is preferable that it functions as a barrier insulating film that controls. Therefore, insulator 222, insulator 272, and at least one of the insulators 273, contain hydrogen atoms, hydrogen molecules, water molecules, and nitrogen atoms. Diffusion of impurities such as ions, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. It is preferable to use an insulating material that has a function to suppress (i.e., the above-mentioned impurities do not easily permeate) i. Or, inhibit the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use an insulating material that has the function of (being impermeable to the above-mentioned oxygen).

[0199] For example, as the insulator 273, silicon nitride or silicon nitride oxide is used, Aluminum oxide or hafnium oxide can be used as 222 and the insulator 272. It is preferable.

[0200] As a result, impurities such as water or hydrogen can enter through the insulator 222 and reach the transistor 200 side. This can suppress diffusion. Alternatively, oxygen contained in the insulator 224, etc. This prevents diffusion towards the substrate side via the edge body 222.

[0201] Furthermore, impurities such as water or hydrogen are disposed through insulators 272 and 273. This can suppress diffusion from the insulator 280 to the transistor 200 side. In this way, transistor 200 allows for the diffusion of impurities such as water or hydrogen, and oxygen. It is preferable to adopt a structure surrounded by insulators 272 and 273 having a function of suppression. Preferably.

[0202] Here, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. In this specification and the like, oxygen desorbed by heating may be referred to as excess oxygen. For example, the insulator 224 may be appropriately silicon oxide or silicon oxynitride. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved. Preferably, as the insulator 224, an oxide material from which a part of oxygen desorbs by heating is used. An oxide that desorbs oxygen by heating means that, by temperature-programmed desorption spectroscopy (TDS (Thermal Desorption Spectroscopy) analysis), the desorption amount of oxygen atoms is 1.0×10 molecules / cm or more, preferably 1.0×1

[0203] 0 molecules / cm or more, more preferably 2.0×10 molec 18 ules / cm 3 or more, or 3.0×10 0 19 molecules / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 7 19 00°C or lower, or 100°C or higher and 400°C or lower. ules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more. The insulator 222 prevents impurities such as water or hydrogen from mixing into the transistor 200 from the substrate side. Preferably.

[0204] Preferably, the insulator 222 prevents impurities such as water or hydrogen from mixing into the transistor 200 from the substrate side. It is preferable that it functions as a barrier insulating film that suppresses leakage. For example, the insulator 222 is It is preferable that the hydrogen permeability is lower than that of insulator 224. Insulator 222 and insulator 273 By surrounding the insulator 224 and oxide 230, water or water from the outside is prevented from entering. This can prevent impurities such as elemental particles from entering transistor 200.

[0205] Furthermore, the insulator 222 contains oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable that the material has a function to suppress diffusion (i.e., the oxygen does not easily permeate it). For example, insulation It is preferable that body 222 has lower oxygen permeability than insulator 224. By having the function of suppressing the diffusion of impurities, the oxygen contained in oxide 230 becomes insulator 2 This is preferable because it reduces diffusion below 22. Also, the conductor 205 is an insulator. This can suppress the reaction of body 224 with oxygen present in oxide 230.

[0206] Insulator 222 is an acid made of aluminum and hafnium, which are insulating materials, or one or both. An insulator containing an oxide is preferable. An acid containing either aluminum or hafnium. As insulators containing phosphates, aluminum oxide, hafnium oxide, aluminum and haf It is preferable to use an oxide containing nium (such as hafnium aluminate). When an insulator 222 is formed using such a material, the insulator 222 absorbs oxygen from the oxide 230. This suppresses the release of impurities and the ingress of hydrogen and other impurities from the periphery of transistor 200 into oxide 230. They function as the dominant force.

[0207] Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, germanium oxide. M, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, acid Zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide-nitride, or silicon nitride may be used as an insulator in a laminated form.

[0208] Furthermore, the insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, acid Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi Includes so-called high-k materials such as O3 or (Ba,Sr)TiO3 (BST). The insulator may be used in a single layer or multilayer configuration. This is due to the miniaturization and high integration of transistors. Furthermore, thinning the gate insulator can sometimes lead to problems such as leakage current. By using a high-k material as the insulator that functions as the edge, the physical film thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0209] The insulators 222 and 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, but can also be a laminated structure made of different materials. stomach.

[0210] In addition, oxide 230b and conductor 242( which functions as a source electrode or drain electrode) Conductors 242a and 242b) and between them oxide 243 (oxide 243a and An oxide 243b may be placed. Therefore, the conductor 242 can suppress the absorption of oxygen from the oxide 230b. By preventing oxidation of the conductor 242, the decrease in the conductivity of the conductor 242 is suppressed. Therefore, oxide 243 has the function of suppressing the oxidation of conductor 242. preferable.

[0211] Between the conductor 242, which functions as a source electrode and drain electrode, and the oxide 230b, oxygen is present. By arranging oxide 243 which has the function of suppressing transmission, the conductor 242 and oxide 2 This is preferable because it reduces the electrical resistance between 30b and the other element. The electrical characteristics and reliability of transistor 200 can be improved. .

[0212] As oxide 243, aluminum, gallium, yttrium, tin, copper, vanadium, Lilium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium Even when using a metal oxide containing one or more elements M selected from um, Good. In particular, element M can be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may be used as oxide 243. Alternatively, In- Metal oxides such as M-Zn oxide may also be used. Specifically, the metal used in oxide 243 In oxides, the atomic ratio of element M to In is the metal oxide used in oxide 230b. In this case, it is preferable that the atomic ratio of element M to In is greater than that. Also, oxide 24 The film thickness of 3 is preferably 0.5 nm to 5 nm, and more preferably 1 nm to 3 nm. The following applies. Furthermore, it is preferable that oxide 243 is crystalline. When this is present, the release of oxygen from the oxide 230 can be suitably suppressed. For example, acid If oxide 243 has a hexagonal or other crystalline structure, it suppresses the release of oxygen from oxide 230. It can be controlled in some cases.

[0213] Note that oxide 243 is not necessarily required. In that case, conductor 242 (conductor 24 When 2a and the conductor 242b) come into contact with the oxide 230, oxygen in the oxide 230 The ions may diffuse into the conductor 242, causing the conductor 242 to oxidize. Therefore, there is a high probability that the conductivity of conductor 242 will decrease. Furthermore, the oxygen in oxide 230 Diffusion into the conductor 242 is described as the conductor 242 absorbing oxygen from the oxide 230. It can be replaced.

[0214] Furthermore, oxygen in oxide 230 is conductor 242 (conductor 242a and conductor 242b) By diffusion, the conductor 242a and oxide 230b, and the conductor 242b and A different layer may be formed between the oxide 230b and the conductor 242. Because it contains a large amount of oxygen, this different layer is presumed to have insulating properties. At this time, conductor 242 The three-layer structure of the aforementioned heterogeneous layer and oxide 230b is a three-layer structure consisting of metal-insulator-semiconductor. It can be considered a structure, and MIS (Metal-Insulator-Semiconductor) It is sometimes called a ctor structure, or a diode junction structure that mainly consists of MIS structures. ru.

[0215] Furthermore, the above-mentioned heterogeneous layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, when a different layer is formed between the conductor 242 and the oxide 230c, or when the conductor 24 The fields formed between 2 and oxide 230b, and between conductor 242 and oxide 230c There is a match.

[0216] On the oxide 243, there is a conductor 242 that functions as a source electrode and a drain electrode. A conductive body 242a and a conductive body 242b are provided. The thickness of the conductive body 242 is, for example, The wavelength should be between 1 nm and 50 nm, preferably between 2 nm and 25 nm.

[0217] The conductive material 242 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, and nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, ma Gnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metallic element selected from lanthanum, or an alloy containing the aforementioned metallic elements. It is preferable to use an alloy or the like that which combines the above-mentioned metal elements. For example, tantalum nitride Titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing ruthenium, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel. Tantalum, titanium nitride, titanium and aluminum nitrides, tantalum and aluminum Includes nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium oxides Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation, or that absorb oxygen. It is preferable because it is a material that maintains its conductivity even after being subjected to certain conditions.

[0218] The insulator 272 is provided in contact with the upper surface of the conductor 242 and functions as a barrier layer. This is preferable. With this configuration, the excess of the insulator 280 due to the conductor 242 is eliminated. Oxygen absorption can be suppressed. Also, by suppressing the oxidation of conductor 242, This can suppress the increase in contact resistance between the converter 200 and the wiring. This can provide the 200 motor with excellent electrical characteristics and reliability.

[0219] Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. For example, It is preferable that the insulator 272 has a function that suppresses oxygen diffusion more effectively than the insulator 280. As the insulator 272, for example, an acid made of either or both aluminum and hafnium. It is preferable to form an insulating film containing an oxide. For example, aluminum nitride can be used as the insulating film 272. An insulator containing nium should be used.

[0220] As shown in Figure 14A, the insulator 272 is a part of the upper surface of the conductor 242b, and the conductor 2 It is in contact with the side surface of 42b. Also, the insulator 272 is in contact with a part of the upper surface of the conductor 242a, and the conductor It is in contact with the side surface of the electric body 242a. In addition, the insulator 273 is placed on top of the insulator 272. In this way, for example, the oxygen added to the insulator 280 is absorbed by the conductor 242. This can suppress the action.

[0221] The insulator 250 functions as a gate insulator. The insulator 250 is on the upper surface of the oxide 230c. It is preferable to place it in contact with the. The insulator 250 is silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon Silicon, silicon oxide with added carbon and nitrogen, and porous silicon oxide are used. This is possible. In particular, silicon oxide and silicon oxide-nitride are stable to heat. preferable.

[0222] Similar to insulator 224, insulator 250 is formed using an insulator that releases oxygen when heated. It is preferable to make this happen. An insulator that releases oxygen upon heating is used as insulator 250, and acid By being placed in contact with the upper surface of the oxide 230c, it effectively affects the channel formation region of the oxide 230b. In effect, oxygen can be supplied. Also, similar to insulator 224, water in insulator 250 Alternatively, it is preferable that the concentration of impurities such as hydrogen is reduced. The film thickness of the insulator 250 is It is preferable that the wavelength be between 1 nm and 20 nm.

[0223] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable to suppress oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses this, the diffusion of oxygen from the insulator 250 to the conductor 260 is It is suppressed. In other words, the decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0224] Furthermore, the metal oxide may function as part of the gate insulator. When silicon oxide or silicon oxide nitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high dielectric constant. The insulator is made of a laminated structure of insulator 250 and the metal oxide, making it stable against heat. Furthermore, a laminated structure with a high dielectric constant can be formed. Therefore, the physical film of the gate insulator This makes it possible to reduce the gate potential applied during transistor operation while maintaining the thickness. This makes it possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0225] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tan From gusten, titanium, tantalum, nickel, germanium, or magnesium, etc. A metal oxide containing one or more selected types can be used. In particular, aluminum Aluminum oxide is an insulator containing an oxide of either or both of aluminum or hafnium. Aluminum, hafnium oxide, aluminum, and hafnium-containing oxides (hafnium aluminum It is preferable to use materials such as laminate.

[0226] Alternatively, the metal oxide may function as part of the gate. In this case, It is preferable to provide an oxygen-containing conductive material on the channel formation region side. By providing it on the channel-forming region side, oxygen released from the conductive material can be channeled into the channel-forming region It will become easier to supply to the region.

[0227] In particular, the conductor that functions as a gate is contained in the metal oxide in which the channel is formed. It is preferable to use a conductive material containing a metallic element and oxygen. And conductive materials containing nitrogen may be used. Also, indium tin oxide, tungsten oxide Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide containing titanium dioxide, indium zinc oxide Indium tin oxide with added silicon may also be used. Mougalium zinc oxide may be used. Using such a material allows for channel formation. In some cases, hydrogen contained in the metal oxide can be captured. Alternatively, the outer atmosphere In some cases, it may be possible to capture hydrogen that has been introduced from surrounding materials.

[0228] Although the conductor 260 is shown as a two-layer structure in Figure 14A, it may also be a single-layer or three-layer structure. The above layered structure is also acceptable.

[0229] Conductor 260a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( Conductive properties that suppress the diffusion of impurities such as N2O, NO, NO2, and copper atoms. It is preferable to use a material. Alternatively, oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the function of suppressing the diffusion of (one of the two).

[0230] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, the insulator 250 contains The presence of oxygen can suppress the oxidation of the conductor 260b, which would otherwise reduce its conductivity. It is possible. Conductive materials that have the function of suppressing oxygen diffusion include, for example, tantalum, nitride. It is preferable to use tantalum, ruthenium, or ruthenium oxide.

[0231] Furthermore, the conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material. Also, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material for the conductor 260b. For example, tungsten, copper, Alternatively, a conductive material mainly composed of aluminum can be used. Also, conductor 26 0b may also be a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. It can also be used as a structure.

[0232] <Metal oxides> It is preferable to use a metal oxide that functions as an oxide semiconductor as oxide 230. The following describes metal oxides applicable to the oxide 230 according to the present invention.

[0233] The metal oxide preferably contains at least indium or zinc. In particular, indium It is preferable to include um and zinc. In addition to these, gallium, yttrium, It is preferable that it contains tin, etc. Also, boron, titanium, iron, nickel, germanium Umium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum Even if it contains one or more types selected from tungsten, magnesium, etc. good.

[0234] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. (Element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium) Boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. Consider the case where one or more elements are selected from the list. In particular, element M is aluminum. Gallium, yttrium, or tin may be used.

[0235] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxi They are sometimes collectively referred to as (de) metal oxides (met It may also be called al oxynitride.

[0236] <Transistor 300> The transistor 300 will be explained using Figure 14B. The transistor 300 is located on a semiconductor substrate 3 A conductor 316 is provided on 11 and functions as a gate, and an insulating element functions as a gate insulator. Edge 315, semiconductor region 313 consisting of a part of the semiconductor substrate 311, and source region It has a low-resistance region 314a and a low-resistance region 314b that function as a drain region. Transistor 300 can be either a p-channel or n-channel type.

[0237] Here, the transistor 300 shown in Figure 14B has a semiconductor region 313 where a channel is formed. (Part of the semiconductor substrate 311) has a convex shape. Also, the side and top of the semiconductor region 313 The surface is provided such that a conductor 316 covers it via an insulator 315 (not shown). Furthermore, the conductor 316 may be made of a material that adjusts the work function. Since the TA300 utilizes the protrusions of the semiconductor substrate 311, it is also called a FIN-type transistor. It will be discovered. Furthermore, an insulator that contacts the upper part of the protrusion and functions as a mask for forming the protrusion. It may also have a protrusion. In this case, a part of the semiconductor substrate 311 is processed to form a protrusion. Although this example illustrates the case, a semiconductor film having a convex shape may also be formed by processing the SOI substrate.

[0238] Note that the transistor 300 shown in Figure 14B is just one example, and its structure is not limited to that example. A suitable transistor should be used depending on the configuration and driving method.

[0239] <Memory device 420> Next, the memory device 420 shown in Figure 13 will be explained using Figure 15A. Regarding transistor 200M in memory device 420, it is heavy with transistor 200. I will omit the repetitive explanation.

[0240] In the memory device 420, the conductor 242a of transistor 200M has a capacitance of 292 Insulator 272 and insulator 273 function as one of the electrodes, and act as dielectrics. The insulators 272 and 273 are placed in between, and the conductor 242a is superimposed on them. A conductive body 290 is provided and functions as the other electrode of capacitance 292. The conductive body 290 is adjacent It may be used as the other electrode of the memory device 420 with a capacity of 292. The conductor 290 is electrically connected to the conductor 290 of the adjacent memory device 420. You may do so.

[0241] The conductor 290 is on the upper surface of the conductor 242a, with the insulators 272 and 273 sandwiched in between. Furthermore, it is also arranged on the side surface of the conductor 242a. At this time, capacitance 292 is located on the conductor 242 A capacitance greater than the capacitance obtained by the area where a and the conductor 290 are superimposed is obtained, therefore, It seems so.

[0242] The conductor 424 is electrically connected to the conductor 242b and is located in the lower layer via the conductor 205. It is electrically connected to the conductive material 424 that is placed there.

[0243] As dielectrics with a capacitance of 292, silicon nitride, silicon oxide nitride, aluminum oxide, and Hafnium oxide and other materials can be used. Furthermore, these materials can be used in a laminated manner. This is possible. When a dielectric with a capacitance of 292 is used in a layered structure, aluminum oxide and silicon nitride are used. Lamination of hafnium oxide and silicon oxide can be used. Here, on top of the lamination The base is not limited. For example, silicon nitride may be laminated on top of aluminum oxide. Aluminum oxide may be laminated on top of silicon nitride.

[0244] Furthermore, as a dielectric material with a capacity of 292, zirconium oxide, which has a higher dielectric constant than the above-mentioned material, is used. You may use this. You may also use a single layer of zirconium oxide as a dielectric with a capacitance of 292. It may also be used as part of a laminate. For example, a laminate of zirconium oxide and aluminum oxide. This can be used. Alternatively, a dielectric with a capacitance of 292 may be stacked in three layers, and the first layer , and zirconium oxide is used for the third layer, and the second layer between the first and third layers is Aluminum oxide may be used.

[0245] By using zirconium oxide, which has a high dielectric constant, as the dielectric with a capacity of 292, the capacity 2 The area occupied by 92 on memory device 420 can be reduced. Therefore, memory device 42 This is preferable because it reduces the area required for 0 and improves bit cost.

[0246] Furthermore, conductor 290 is conductor 205, conductor 242, conductor 260, and conductor 424. Materials that can be used for such purposes can be used.

[0247] In this embodiment, a conductor 424 is sandwiched between the transistor 200M and the capacitor 292 This shows an example of a symmetrical arrangement. Thus, a pair of 200M transistors and 2 capacitances are shown. By arranging 92, the number of conductors 424 that are electrically connected to transistor 200M is reduced. This can reduce the area required for the memory device 420. This is preferable as it can improve cost efficiency.

[0248] If an insulator 241 is provided on the side surface of the conductor 424, the conductor 424 is connected to the conductor 24 It connects to at least a portion of the upper surface of 2b.

[0249] By using conductors 424 and 205, the transistors in the memory unit 470 The 200T and the memory device 420 can be electrically connected.

[0250] <Modified example 1 of memory device 420> Next, using Figure 15B, we will show a modified example of the memory device 420. Let's explain A. Memory device 420A consists of transistor 200M and transistor 20 It has a capacitance of 292A that is electrically connected to 0M. A capacitance of 292A is equivalent to that of a 200M transistor. It is located below it.

[0251] In memory device 420A, the conductor 242a is oxide 243a, oxide 230b, acid The material 230a, the insulator 224, and the insulator 222 are arranged in openings provided in the openings The bottom of the opening is electrically connected to the conductor 205. The conductor 205 is electrically connected to the capacitance 292A. To be continued.

[0252] Capacitance 292A consists of a conductor 294 that functions as one of the electrodes and an insulator that functions as a dielectric. It has a body 295 and a conductor 297 that functions as the other electrode. The conductor 297 is an insulator. 295 is placed in between and superimposed on the conductor 294. Also, the conductor 297 is connected to the conductor 205. Connect electrically.

[0253] The conductor 294 is located at the bottom of the opening formed in the insulator 298, which is provided on the insulator 296. Provided on the sides, the insulator 295 is provided so as to cover the insulator 298 and the conductor 294. Furthermore, the conductor 297 is provided to be embedded in the recess of the insulator 295. It is possible.

[0254] Furthermore, a conductor 299 is provided so as to be embedded in the insulator 296, and the conductor 299 It is electrically connected to the conductor 294. The conductor 299 is connected to the adjacent memory device 420. It may also be electrically connected to the conductor 294 of A.

[0255] The conductor 297 has the insulator 295 in between, and not only the upper surface of the conductor 294, but also the conductor 29 It is also placed on the side of 4. At this time, capacitance 292A is obtained when conductors 294 and 297 are superimposed. This is preferable because it allows for a larger capacity than that obtained by the area being treated.

[0256] As an insulator 295 that functions as a dielectric with a capacitance of 292A, silicon nitride, silicon oxide nitride Cone, aluminum oxide, and hafnium oxide can be used. These materials can be used in a laminated structure. When the insulator 295 is made into a laminated structure, aluminum oxide It is possible to use laminations of aluminum and silicon nitride, or laminations of hafnium oxide and silicon oxide. Here, the top and bottom layers are not limited. For example, silicon nitride on aluminum oxide. The layers may be laminated, or aluminum oxide may be laminated on silicon nitride.

[0257] Furthermore, as the insulator 295, zirconium oxide having a higher dielectric constant than the above material is used. It is also possible to use zirconium oxide as the insulator 295 as a single layer, or as part of a laminate. It may also be used as such. For example, by using a laminate of zirconium oxide and aluminum oxide. This can be done. Alternatively, the insulator 295 may be made into a three-layer laminate, with the first layer and the third layer being Using zirconium oxide, aluminum oxide is used in the second layer between the first and third layers. You may use it.

[0258] By using zirconium oxide, which has a high dielectric constant, as the insulator 295, the capacity becomes 292A. This reduces the area occupied by the memory device 420A. Therefore, the memory device 420 This is preferable because it reduces the area required for A and improves bit costs.

[0259] Furthermore, conductors 297, 294, and 299 are conductor 205, conductor Materials that can be used for 242, conductor 260, conductor 424, etc. can be used. ru.

[0260] Furthermore, as insulator 298, there are insulators 214, 216, 224, and insulator Materials that can be used for 280, etc., can be used.

[0261] <Modified example 2 of memory device 420> Next, using Figure 15C, we will show a modified example of the memory device 420. Let's explain B. Memory device 420B consists of transistor 200M and transistor 20 It has a capacitance of 292B that is electrically connected to 0M. Capacitance 292B is connected to transistor 200M It is installed above it.

[0262] Capacitor 292B consists of a conductor 276 that functions as one of the electrodes and an insulator that functions as a dielectric. It has a body 277 and a conductor 278 that functions as the other electrode. The conductor 278 is an insulator. 277 is placed in between, and the conductor 276 is superimposed on it.

[0263] An insulator 275 is provided on the insulator 282, and the conductor 276 is provided on the insulator 275 and insulator 28 2. Bottom and sides of the openings formed in insulators 280, 273, and 272 It is provided on the surface. The insulator 277 is provided so as to cover the insulator 282 and the conductor 276. Furthermore, the conductor 278 superimposes with the conductor 276 within the recess of the insulator 277. It is provided in such a way, and at least a part of it is provided on the insulator 275 via the insulator 277. The conductor 278 has electrodes with a capacity of 292B, as well as the electrodes of the adjacent memory device 420B. It may also be used as such. Alternatively, the conductor 278 has an adjacent memory device 420B. It may also be electrically connected to the conductor 278.

[0264] The conductor 278 has an insulator 277 in between, and not only the upper surface of the conductor 276, but also the conductor 27 It is also arranged on the side of 6. At this time, the capacitance 292B is obtained when conductors 276 and 278 are superimposed. This is preferable because it allows for a larger capacity than that obtained by the area being treated.

[0265] Alternatively, an insulator 279 may be provided to fill the recesses in the conductor 278.

[0266] As an insulator 277 that functions as a dielectric with capacitance 292B, silicon nitride, silicon oxide nitride Cone, aluminum oxide, and hafnium oxide can be used. These materials can be used in a laminated structure. When the insulator 277 is made into a laminated structure, aluminum oxide It is possible to use laminations of aluminum and silicon nitride, or laminations of hafnium oxide and silicon oxide. Here, the top and bottom layers are not limited. For example, silicon nitride on aluminum oxide. The layers may be laminated, or aluminum oxide may be laminated on silicon nitride.

[0267] Furthermore, as the insulator 277, zirconium oxide having a higher dielectric constant than the above material is used. It is also possible to use zirconium oxide as the insulator 277 as a single layer, or as part of a laminate. It may also be used as such. For example, by using a laminate of zirconium oxide and aluminum oxide. This can be done. Alternatively, the insulator 277 may be made up of three layers, with the first layer and the third layer being Using zirconium oxide, aluminum oxide is used in the second layer between the first and third layers. You may use it.

[0268] By using zirconium oxide, which has a high dielectric constant, as the insulator 277, the capacitance becomes 292B. This reduces the area occupied by memory device 420B. Therefore, memory device 420 This is preferable because it reduces the area required for B and improves bit costs.

[0269] Furthermore, conductors 276 and 278 are conductors 205, conductor 242, and conductor Materials that can be used for 260, conductor 424, etc., can be used.

[0270] Furthermore, as insulators 275 and 279, insulators 214, 216, and Materials that can be used for 224 and the insulator 280 can be used.

[0271] <Connection between memory device 420 and transistor 200T> In Figure 13, in the region 422 enclosed by the dashed line, the memory device 420 is a conductor 42 4 and electrically connected to the gate of transistor 200T via conductor 205. However, this embodiment is not limited to this.

[0272] Figure 16 shows that the memory device 420 consists of conductor 424, conductor 205, conductor 246b, And via conductor 240b, as one of the source and drain of transistor 200T This shows an example of an electrical connection with a functional conductor 242b.

[0273] Thus, the memory device 420 and the transistor layer 413 are configured according to the function of the circuit. The connection method for transistor 200T can be determined.

[0274] Figure 17 shows the transistor layer 413 of the memory unit 470, which has transistor 200T. And, the 4-layer memory device layer 415 (memory device layer 415_1 to memory device layer An example having 415_4) is shown.

[0275] Memory device layers 415_1 to 415_4 each contain multiple memory It has a device 420.

[0276] The memory device 420 is connected to different memory devices via the conductors 424 and 205. The memory device 420 in the transistor layer 415 and the transistor in the transistor layer 413 Connect electrically to the 200T generator.

[0277] The memory unit 470 consists of insulator 211, insulator 212, insulator 214, insulator 287, It is sealed by insulators 282, 283, and 284. Around insulator 284 An insulator 274 is provided in the enclosure. Also, insulator 274, insulator 284, insulator 283, Furthermore, a conductor 430 is provided on the insulator 211, which is electrically connected to the element layer 411.

[0278] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 is acid-resistant when heated. It has the function of releasing elements. Alternatively, the insulator 280 has an excess oxygen region.

[0279] Furthermore, insulators 211, 283, and 284 have blocking properties for hydrogen. It is preferable that the material has high functionality. Also, the insulator 214, insulator 282, and The insulator 287 is preferably a material that has the function of capturing or fixing hydrogen. ru.

[0280] For example, materials that have high blocking properties for hydrogen include silicon nitride, Other examples include silicon nitride oxide. In addition, the above hydrogen capture or hydrogen fixation The functional materials are aluminum oxide, hafnium oxide, and aluminum and ha Examples include oxides containing hafnium (hafnium aluminate).

[0281] In this specification, etc., barrier properties refer to the function of suppressing the diffusion of the corresponding substance (permeability). It is said that the amount is low. Alternatively, it captures and fixes the corresponding substance (gettarin). (Also known as "g") This function is intended to be used.

[0282] Note that insulators 211, 212, 214, 287, 282, and insulation There are no particular limitations on the crystal structure of the materials used for body 283 and insulator 284. The structure may be amorphous or crystalline. For example, it may capture or fix hydrogen. As a material having the function of [this], an amorphous aluminum oxide film is preferable. High-quality aluminum oxide is better at capturing hydrogen and solidifying than highly crystalline aluminum oxide. The amount of product used may be large.

[0283] Here, excess oxygen in the insulator 280 expands the hydrogen in the oxide semiconductor in contact with the insulator 280. The following model can be considered for dispersion.

[0284] Hydrogen present in the oxide semiconductor is absorbed by other elements via the insulator 280 in contact with the oxide semiconductor. It diffuses into the structure. This hydrogen diffusion occurs when excess oxygen in the insulator 280 is released into the water in the oxide semiconductor. It reacts with the element to form an OH bond and diffuses through the insulator 280. The hydrogen atom having an OH bond, This leads to materials that have the function of capturing or fixing hydrogen (typically, insulator 282). Upon reaching this point, it reacts with oxygen atoms bonded to atoms in the insulator 282 (for example, metal atoms). The excess oxygen that had an OH bond is then captured or fixed in the insulator 282. It is presumed that the oxygen atoms remain in the insulator 280 as excess oxygen. In other words, the expansion of the hydrogen... In dispersion, the excess oxygen in insulator 280 is highly likely to play a bridging role.

[0285] To satisfy the above model, the manufacturing process of the memory device is one of the important elements.

[0286] As an example, an insulator 280 containing excess oxygen is formed above the oxide semiconductor, and then, An insulator 282 is formed. After that, it is preferable to perform a heat treatment. This heat treatment is Specifically, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen The heating process is carried out at a temperature of 350°C or higher, preferably 400°C or higher. The heating time is 1 hour or less. Preferably, the incubation period is 4 hours or more, and more preferably 8 hours or more.

[0287] As a result of the above heat treatment, hydrogen in the oxide semiconductor is released into insulator 280, insulator 282, and It can diffuse outward through the insulator 287. In other words, oxide semiconductors, and The absolute amount of hydrogen present near the oxide semiconductor can be reduced.

[0288] After the above heat treatment, insulators 283 and 284 are formed. Insulator 284 is a material that has high blocking properties for hydrogen, therefore, Hydrogen diffused into, or hydrogen present externally, is introduced into the interior, specifically into an oxide semiconductor, Alternatively, it can prevent the substance from entering the insulator 280.

[0289] Regarding the above heat treatment, the configuration performed after the formation of the insulator 282 is as follows: As shown, but not limited to, after the formation of the transistor layer 413, or in memory After the formation of device layer 415_1 to memory device layer 415_4, the above heating treatment is performed on each of them. It is also permissible to perform the above heating treatment. Furthermore, when diffusing hydrogen outward through the above heating treatment, Hydrogen is diffused upward or laterally in the radiator layer 413. Similarly, in the memory device layer 4 When heat treatment is performed after the formation of 15_1 to the memory device layer 415_4, hydrogen It is diffused upwards or sideways.

[0290] Furthermore, by using the above manufacturing process, the insulator 211 and the insulator 283 are bonded together. This results in the formation of the sealing structure described above.

[0291] As described above, by using the above structure and manufacturing process, the hydrogen concentration is reduced. A memory device using an oxide semiconductor can be provided. Therefore, a memory device with good reliability can be provided. An apparatus can be provided. Furthermore, according to one embodiment of the present invention, a device having good electrical characteristics can be provided. We can provide a memory device.

[0292] Figures 18A to 18C show examples of different arrangements of the conductor 424. Figure 18A is, Figure 18B shows the layout of the memory device 420 as viewed from above, and Figure 18B is a comparison of Figure 18A. Figure 18C is a cross-sectional view of the area indicated by the dashed line A1-A2, and Figure 18A shows the area B1-B2 This is a cross-sectional view of the area indicated by the dashed line. Note that in Figure 18A, to facilitate understanding of the figure... The conductor 205 is not shown in the illustration. If the conductor 205 is provided, the conductor 205 is a conductor It has a region that overlaps with 424.

[0293] As shown in Figure 18A, the conductor 424 is superimposed with oxide 230a and oxide 230b. It is provided not only in the region, but also on the outside of oxide 230a and oxide 230b. In Figure 18A, the conductor 424 is located on the B2 side of oxide 230a and oxide 230b. An example of a configuration that allows for discharge is shown, but this embodiment is not limited to this. Conductor 4 24 may be provided so as to protrude on the B1 side of oxide 230a and oxide 230b. The stones may be provided so as to protrude on both the B1 and B2 sides.

[0294] Figures 18B and 18C show the memory device layer on top of the memory device layer 415_p-1. An example of stacking 415_p is shown (where p is a natural number between 2 and n). Memory device layer 4 The memory device 420 of 15_p-1 is connected via the conductor 424 and the conductor 205. Then, it electrically connects to the memory device 420 located in the memory device layer 415_p.

[0295] In Figure 18B, in the memory device layer 415_p-1, the conductor 424 is the memory device Conductor 242 of the siding layer 415_p-1, and conductor 20 of the memory device layer 415_p This shows how it connects to 5. Here, conductor 424 is conductor 242, oxide 243 On the outside of the B2 side of oxide 230b and oxide 230a, memory device layer 415_p It is also connected to the -1 conductor 205.

[0296] In Figure 18C, conductor 424 is conductor 242, oxide 243, oxide 230b, and acid Formed along the B2 side surface of material 230a, insulator 280, insulator 273, insulator 2 Electrical communication occurs between the conductor 205 and the insulator 222 through openings formed in 72, the insulator 224, and the insulator 222. It can be seen that they are directly connected. Here, conductor 424 is connected to conductor 242 and oxide 243. Figure 1 shows how the oxides 230b and 230a are arranged along the B2 side surface. In 8B, it is shown with a dotted line. Also, conductor 242, oxide 243, oxide 230b, oxide Between material 230a, insulator 224, and the B2 side of insulator 222 and conductor 424 In some cases, an insulator 241 may be formed.

[0297] By providing the conductor 424 in areas that do not overlap with the conductor 242, etc., the memory device 4 20 is electrically connected to a memory device 420 located on a different memory device layer 415. It can continue. Also, the memory device 420 is provided on the transistor layer 413. It can also be electrically connected to the 200T transistor.

[0298] Furthermore, when the conductor 424 is used as a bit line, the conductor 424 does not overlap with the conductor 242, etc. By also providing it in the B1-B2 direction, the bit lines of adjacent memory devices 420 The distance can be increased. As shown in Figure 18, the conductor 424 on the conductor 242 The distance between them is d1, but below the oxide 230a, i.e., the insulator 224, The distance between the conductors 424 located within the opening formed in the insulator 222 is d2, The distance between adjacent conductors 424 in the B1-B2 direction is d1. Compared to the case where a certain interval is set to d2, the parasitic capacitance of the conductor 424 is reduced. This is possible. By reducing the parasitic capacitance of conductor 424, the capacitance required for capacitance 292 can be reduced. It is preferable for this reason.

[0299] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0300] (Embodiment 4) In this embodiment, the gold that can be used in the OS transistor described in the above embodiment is CAC-OS (Cloud-Aligned Composite Oxide) is a group oxide. xide semiconductor), and CAAC-OS (c-axis al Structure of igned crystalline oxide semiconductor Let me explain about the formation.

[0301] <Composition of metal oxides> CAC-OS or CAC-metal oxide is a material that has conductive properties in some parts. In addition, a portion of the material has insulating properties, while the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used in the transistor channels. When used in a region where a hole is formed, the conductive function is to allow electrons (or holes) that act as carriers to flow. The function of insulation is the function of preventing the flow of electrons, which act as carriers. The function of conductivity is... By having the insulating function and the other function work complementaryly, a switching function is achieved. The function to switch CAC-OS or CAC-metal oxide on / off is added to the CAC-OS or CAC-metal oxide. It is possible. In CAC-OS or CAC-metal oxide, By separating these functions, it is possible to maximize the performance of both.

[0302] Furthermore, CAC-OS or CAC-metal oxide provides conductive and insulating properties. It has conductive regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. It has the function of being conductive. Furthermore, within the material, the conductive region and the insulating region are separated by nanoparticles. In some cases, they are separated by a bell. Also, conductive regions and insulating regions are located within the material. It may be unevenly distributed. Also, the conductive region appears blurred around the edges and connected in a cloud-like manner when observed. There are cases where this can happen.

[0303] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region The marginal region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed in the material at the following sizes.

[0304] Furthermore, CAC-OS or CAC-metal oxide has different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxi de consists of a component with a wide gap due to the insulating region and a component with a wide gap due to the conductive region. It consists of a component having a low gap. In this configuration, when the carrier is flowing... In components with a narrow gap, the carrier mainly flows. A component having a wide gap acts complementaryly with a component having a narrow gap. In conjunction with the components, carriers also flow to components with a wide gap. Therefore, the above C AC-OS or CAC-metal oxide is applied to the channel formation region of the transistor. When used, a high current driving force is required in the transistor's ON state, i.e., a large ON current. Furthermore, high field-effect mobility can be obtained.

[0305] In other words, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite (metal It can also be called a matrix composite.

[0306] <Structure of metal oxides> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis ali gned crystalline oxide semiconductor), polycrystalline crystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous (us-like oxide semiconductor) and amorphous oxide semiconductor These are some examples.

[0307] Furthermore, oxide semiconductors may be classified differently from those described above when considering their crystal structure. Here, we will explain the classification of crystal structures in oxide semiconductors using Figure 19A. Figure 19A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structures of metal oxides.

[0308] As shown in Figure 19A, IGZO can be broadly divided into Amorphous and Crystal They are classified into line and crystal. Furthermore, within Amorphous, It includes completely amorphous components. Also, Crystalline Among them are CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned C It includes (omposite). Also, within Crystal, there is single cry This includes stal and polycrystal.

[0309] Note that the structure within the thick frame shown in Figure 19A is the New crystalline phase. It is a structure to which it belongs. This structure is the boundary area between Amorphous and Crystal. It is in the region. That is, the energetically unstable Amorphous and Crystal This can be rephrased as having a completely different structure from ine.

[0310] The crystal structure of the film or substrate is determined by X-ray diffraction (XRD). It can be evaluated using an image of quartz glass and Crystal XRD spectrometer for IGZO (also called crystalline IGZO) having a crystal structure classified as ine The cleats are shown in Figures 19B and 19C. Figure 19B shows quartz glass, and Figure 19C shows crystalline glass. This is the XRD spectrum of IGZO. Note that the crystalline IGZO shown in Figure 19C is I The composition is n:Ga:Zn=4:2:3 [atomic ratio]. Also, the crystalline I shown in Figure 19C The GZO (Glass Zoon) has a thickness of 500 nm.

[0311] As shown by the arrow in Figure 19B, the peaks in the XRD spectrum of quartz glass are nearly symmetrical. On the other hand, as shown by the arrow in Figure 19C, crystalline IGZO has a peak in its XRD spectrum. The peak is asymmetric. The asymmetrical peak in the XRD spectrum clearly indicates the presence of a crystal. In other words, if the peaks in the XRD spectrum are not symmetrical, Amorpho It cannot be said that it is us.

[0312] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. Furthermore, it has a distorted crystal structure. Note that distortion refers to the region where multiple nanocrystals are connected. Within the region, between a region with aligned lattice arrangements and another region with aligned lattice arrangements, This refers to the part where the direction has changed.

[0313] Nanocrystals are based on a hexagonal structure, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Yes, it exists. Furthermore, the distortion may have lattice arrangements such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bounds) are present. It is not possible to confirm the grain boundaries (also known as dally). In other words, due to the distortion of the lattice arrangement, the grain boundaries It can be seen that the formation is suppressed. This is because CAAC-OS is in the ab plane direction The arrangement of oxygen atoms is not dense, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by processes such as transformation. A crystal structure in which grain boundaries can be observed is what is known as polycrystalline. It is called a crystal. The grain boundaries become recombination centers, and carriers are trapped. This is likely to cause a decrease in the on-current of the inverter or a decrease in field-effect mobility. Therefore, CAAC-OS, which does not have clearly defined grain boundaries, is suitable for the semiconductor layer of transistors. It is one of the crystalline oxides that has a crystalline structure. Note that to constitute CAAC-OS A configuration having Zn is preferred. For example, In-Zn oxide and In-Ga-Zn oxide. This material is preferable because it can suppress the formation of grain boundaries more effectively than in oxide.

[0314] Furthermore, CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and elements A layered crystalline structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers) are stacked. It tends to have a layered structure (also called a structure). Furthermore, indium and element M are substituted for each other. It is possible, and if element M in the (M,Zn) layer is replaced with indium, then (In,M,Zn) It can also be represented as a layer. Furthermore, if the indium in the In layer is substituted with element M, then (In,M It can also be represented as a layer.

[0315] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has a clear bond. Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries does not occur. It can be said that the crystallinity of oxide semiconductors is reduced due to the inclusion of impurities and the generation of defects. Because it may cause problems, CAAC-OS is an oxide with few impurities and defects (such as oxygen deficiencies). It can also be called a semiconductor. Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. CAAC-OS can withstand high temperatures (so-called thermal budget) in the manufacturing process. It is stable. Therefore, when using CAAC-OS in OS transistors, the manufacturing process is stable. This will broaden the scope of possibilities.

[0316] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). It has periodicity in the atomic arrangement in the region of less than nm. Furthermore, nc-OS has different nanometers. No regularity in crystal orientation is observed between crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. It can sometimes be difficult to distinguish between them.

[0317] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0318] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc -OS and CAAC-OS may have two or more types.

[0319] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0320] By using the above oxide semiconductor in transistors, transistors with high field-effect mobility can be produced. It can be achieved. Furthermore, highly reliable transistors can be realized.

[0321] It is preferable to use an oxide semiconductor with a low carrier density for the transistor. When lowering the carrier density of the conductive film, the impurity concentration in the oxide semiconductor film is reduced. Therefore, the defect level density should be lowered. In this specification, the impurity concentration is low and the defect level Low density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0322] Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Therefore, the trap level density may also be low.

[0323] Furthermore, the time required for charges trapped in the trap levels of oxide semiconductors to disappear is long. Furthermore, it can behave as if it were a fixed charge. Therefore, it can behave as if it were a fixed charge. Transistors in which a channel formation region is formed in an oxide semiconductor exhibit unstable electrical properties. There are cases where this is the case.

[0324] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor must be Reducing it is effective. Also, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the contacting film. Examples of impurities include hydrogen, nitrogen, and aluminum. Examples include potash metals, alkaline earth metals, iron, nickel, and silicon.

[0325] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0326] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, the oxide Defect levels are formed in semiconductors. Therefore, silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (by secondary ion mass spectrometry) SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 at oms / cm 3 The following applies:

[0327] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. This can result in the generation of carriers. Therefore, alkali metals or alkaline earth metals Transistors using oxide semiconductors containing this material tend to exhibit normally-on characteristics. Therefore, reducing the concentration of alkali metals or alkaline earth metals in oxide semiconductors is possible. Preferably. Specifically, alkali metals or a in oxide semiconductor obtained by SIMS The concentration of rutile earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 1 6 atoms / cm 3 Do the following:

[0328] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. The density increases, making it easier to convert to n-type. As a result, nitrogen-containing oxide semiconductors become channeled. The transistor used in the formation region tends to exhibit normally-on characteristics. Therefore, the oxide semiconductor In conductors, it is preferable to reduce nitrogen content as much as possible. For example, in oxide semiconductors. The nitrogen concentration inside is 5 × 10⁻⁶ in SIMS. 19 atoms / cm 3 Less than, preferably 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0329] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. This can sometimes form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the electrons, which are carriers, In some cases, this can be generated. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, resulting in a It can generate electrons, which are rear electrons. Therefore, using an oxide semiconductor containing hydrogen... Transistors tend to exhibit normally-on characteristics. Therefore, hydrogen in oxide semiconductors It is preferable that it be reduced as much as possible. Specifically, in oxide semiconductors, SIM The hydrogen concentration obtained by S is 1 × 10 20 atoms / cm 3 Less than 1 × 1 0 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 less than, More preferably 1 × 10 18 atoms / cm 3 Less than.

[0330] Using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors. This allows for the provision of stable electrical characteristics.

[0331] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0332] (Embodiment 5) This embodiment is an electronic component and electronic device incorporating the storage device shown in the above embodiment. An example of the equipment is shown.

[0333] <Electronic Components> First, using Figures 20A and 20B, we will show an example of an electronic component incorporating a memory device 10A, etc. Then I will give the explanation.

[0334] Figure 20A shows the electronic component 700 and the circuit board (mounted circuit board 704) on which the electronic component 700 is mounted. A perspective view is shown. The electronic component 700 shown in Figure 20A is located on the semiconductor substrate 11 inside the mold 711. It has a memory device 10A in which an element layer 34 is stacked. Figure 20A shows the electronic component 700 To show the internal structure, some parts of the electronic component 700 are omitted. The electronic component 700 is a mo The outside of the 711 is a land 712. The land 712 is electrically connected to the electrode pad 713. The electrode pad 713 is connected to the memory device 10A and is electrically connected by wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. Multiple components are combined and each is electrically connected on the printed circuit board 702. Then the mounting board 704 is completed.

[0335] Figure 20B shows a perspective view of electronic component 730. Electronic component 730 is a SiP (System Integrity Packaging). (in Package) or MCM (Multi Chip Module) is an example. Yes. The electronic component 730 is an interposer 7 on the package substrate 732 (printed circuit board). 31 is provided, and a semiconductor device 735 and a plurality of storage devices 1 are placed on the interposer 731. 0A is provided.

[0336] In electronic component 730, the storage device 10A is a high-bandwidth memory (HBM). An example of its use as dth Memory is shown. Also, semiconductor device 735 is CP Integrated circuits (semiconductor devices) such as U-type processors, GPUs, and FPGAs can be used.

[0337] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. Boards and the like can be used. Interposer 731 is a silicone interposer, resin Interposers and similar devices can be used.

[0338] The interposer 731 has multiple wirings and multiple integrated circuits with different terminal pitches for electrical connection. It has the function of connecting to each other. Multiple wires are provided in single or multi-layer configurations. Also, the interface - The interposer 731 has integrated circuits provided on the package substrate 73 It has the function of electrically connecting to the electrode provided in 2. The interposer is sometimes called a "redistribution board" or "intermediate board." A through electrode is provided, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. In some cases, connections are made. Also, in silicon interposers, TSV(T) is used as a through-electrode. It is also possible to use (through silicon vias).

[0339] It is preferable to use a silicon interposer as the interposer 731. Because interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. This is possible. On the other hand, the wiring of the silicon interposer is formed using a semiconductor process. Because this is possible, it is easy to form fine wiring, which is difficult with resin interposers.

[0340] In HBM, many wires need to be connected to achieve a wide memory bandwidth. Therefore, interposers that implement HBM require the formation of fine and high-density wiring. Therefore, a silicon interposer should be used for the interposer that implements HBM. It is preferable.

[0341] Furthermore, in SiP and MCM using silicon interposers, integrated circuits and interposers are used. The reliability degradation due to differences in thermal expansion coefficients between silicon layers is less likely to occur. Because of its high surface flatness, the integrated circuit and silicon interposer are placed on the silicon interposer. Connection failures between interposers are less likely to occur. In particular, multiple integrated circuits can be placed horizontally on the interposer. In 2.5D packages (2.5-dimensional packaging) where components are arranged in a row, silicon interposers It is preferable to use [this].

[0342] Alternatively, a heat sink (heat dissipation plate) may be placed on top of the electronic component 730. If provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the storage device 10A and the semiconductor device 735 It is preferable to make the heights the same.

[0343] To mount the electronic component 730 onto another substrate, electrodes 733 are attached to the bottom of the package substrate 732. It may be provided. Figure 20B shows an example in which the electrode 733 is formed with a solder ball. By arranging solder balls in a matrix pattern at the bottom of the cage substrate 732, BGA (Ball Grid Array implementation can be achieved. Also, the electrode 733 is formed with conductive pins. This may also be done by providing conductive pins in a matrix at the bottom of the package substrate 732. It is possible to implement PGA (Pin Grid Array).

[0344] Electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. It is possible. For example, SPGA (Staggered Pin Grid Arr ay), LGA (Land Grid Array), QFP (Quad Flat P ackage), QFJ(Quad Flat J-leaded package), Or actual products such as QFN (Quad Flat Non-leaded package) The mounting method can be used.

[0345] <Electronic equipment> Next, an example of an electronic device equipped with the above-mentioned electronic components will be explained using Figure 21.

[0346] The robot 7100 includes an illuminance sensor, microphone, camera, speaker, display, Various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezoelectric sensors, optical sensors, etc.) It includes a gyro sensor, etc., and a moving mechanism, etc. Electronic component 730 is a processor, etc. It has the ability to control these peripheral devices. For example, electronic component 700 is acquired by a sensor. It has the function of storing the data it has collected.

[0347] The microphone has the function of detecting acoustic signals such as the user's voice and ambient sounds. Furthermore, the speaker has the function of emitting audio signals such as voice and warning sounds. The 7100 analyzes the audio signal input via the microphone and performs the necessary actions. Audio signals can be emitted from the speaker. In the robot 7100, the microphone It is possible to communicate with the user using a phone and speaker. ru.

[0348] The camera has the function of imaging the area around the robot 7100. Also, the robot 7100 It has the function of moving using a moving mechanism. Robot 7100 uses a camera to observe its surroundings. By capturing images and analyzing them, it's possible to detect obstacles and other issues while moving.

[0349] Aircraft 7120 is an autonomous aircraft equipped with propellers, cameras, and batteries. It has the function of controlling these peripheral devices. Electronic component 730 has the function of controlling these peripheral devices.

[0350] For example, image data captured by the camera is stored in electronic component 700. Electronic component 730 It can analyze image data and detect the presence or absence of obstacles during movement. The electronic component 730 estimates the remaining battery charge from the change in the battery's storage capacity. It is possible.

[0351] The 7140 cleaning robot has a display on the top and multiple turtles on the sides. It has a brush, control buttons, various sensors, etc. (Not shown in the illustration) The 7140 is equipped with tires, a suction nozzle, etc. The cleaning robot 7140 is self-propelled. It can detect dust and suck it up through a suction port located on the bottom.

[0352] For example, electronic component 730 analyzes the image captured by the camera and identifies walls, furniture, steps, etc. It can determine the presence or absence of obstacles. Furthermore, image analysis can detect if wires or other objects are entangled in the brush. If such an object is detected, the brush rotation can be stopped.

[0353] Automobile 7160 has an engine, tires, brakes, steering system, camera, etc. For example For example, electronic component 730 displays navigation information, speed, engine status, gear selection status, Based on data such as brake usage frequency, the driving conditions of vehicle 7160 are optimized. It controls the camera. For example, image data captured by the camera is stored in electronic component 700.

[0354] Electronic component 700 and / or electronic component 730 are TV device 7200 (television receiver) Devices), smartphones 7210, PCs (personal computers) 7220, 7230 It can be incorporated into game consoles such as the 7240 and 7260.

[0355] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. It is possible. For example, electronic component 730 can perform noise reduction, resolution upconversion, etc. Which image processing should be performed?

[0356] The Smartphone 7210 is an example of a mobile information terminal. It has an microphone, camera, speaker, various sensors, and display unit. Electronic component 730 These peripheral devices are controlled by [this system].

[0357] PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. 7230 includes a keyboard 7232 and a monitor device 7233, which are connected wirelessly or via wired connection. It is connectable. Game console 7240 is an example of a portable game console. Game console 7260 is a stationary game console. This is an example of a stationary game console. The game console 7260 has a controller 7 that can be connected wirelessly or wired. 262 is connected. The controller 7262 has electronic components 700 and / or electronic Component 730 can also be incorporated.

[0358] <Various types of storage devices> Generally, in semiconductor devices such as computers, various types of storage devices (memory) are used depending on the application. It is used. Figure 22 shows various storage devices in a hierarchical structure. The higher the storage device is located, the more... High access speeds are required, and lower-level memory devices have larger storage capacities and higher recording density. The degree can be determined. In Figure 22, starting from the top layer, the arithmetic processing units such as the CPU have registers and The memory that is mixed in, SRAM (Static Random Access Memory) This refers to DRAM and 3D NAND memory.

[0359] Memory embedded as registers in processing units such as CPUs is used for temporary storage of calculation results. Because it is used in various applications, it is frequently accessed by the processing unit. Therefore, rather than memory capacity... Fast operating speed is required. Also, registers are devices that hold configuration information for the arithmetic processing unit. He also possesses talent.

[0360] SRAM is used, for example, as a cache. The cache is held in main memory. It has the function of duplicating and storing some of the information. Frequently used data is cached. By creating copies, you can increase the speed of accessing the data.

[0361] DRAM is used, for example, in main memory. Main memory reads from storage. It has the function of holding the programmed programs and data. The recording density of DRAM is approximately 0 .1~0.3Gbit / mm 2 That is the case.

[0362] 3D NAND memory is used, for example, in storage. Storage requires long-term storage. It has the function of storing essential data and various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density rather than just high operating speed. The recording density of the storage devices used in the storage is approximately 0.6 to 6.0 Gbit / mm². 2 That is the case.

[0363] A storage device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. A storage device according to one embodiment of the present invention has a hierarchy in which the cache is located and the main memory is located It can be suitably used as a storage device located in the boundary region 901 which includes both of the layers. Furthermore, a storage device according to one embodiment of the present invention has a hierarchy in which the main memory is located and storage It is suitable for use as a storage device located in the boundary region 902 which includes both layers in which the device is located. It is possible.

[0364] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible. [Explanation of symbols]

[0365] A0: Bit, A3: Bit, B0: Test bit, BL_1: Bit line, C1: Input terminal C2: Input terminal, C3: Input terminal, C4: Input terminal, C5: Input terminal, C8: Input terminal C61: Capacitor, C71: Capacitor, CK1: Clock signal, CK4: Clock Signal, S_C1: Control signal, S_C2: Control signal, S_C3: Control signal, S_C4: Control Signal, S_C5: Control signal, S_C8: Control signal, T_A0: Input terminal, T_A3: Input Terminals, T_B0: Input terminal, T_CK1: Input terminal, T_CK4: Input terminal, WL_N: Word line, WL_1: Word line, 10A: Memory device, 10B: Memory device, 10C: Memory device Placement, 11: Semiconductor substrate, 20: Peripheral circuitry, 21: Row driver, 22: Column driver, 23: Switch circuit, 23_A: Switch, 23_C: Switch, 24: Precharge cycle Path, 24_1: Transistor, 24_3: Transistor, 25: Sense amplifier, 25_1 :transistor, 25_2:transistor, 25_3:transistor, 25_4:transistor 26: Element layer, 28_a: Transistor, 28_b: Transistor, 29: Circuit ,30:memory cell array, 31_N:memory cell, 31_1:memory cell, 32_N: Transistor, 32_1: Transistor, 33_N: Capacitor, 33_1: Capacitor ,34: element layer, 34_N: element layer, 34_1: element layer, 34_5: element layer, 39: unit 39_M: Unit, 39_1: Unit, 40A: Sealing layer, 40B: Sealing layer, 4 1: Switch circuit, 51: NAND circuit, 51_1: NAND circuit, 51_4: NAND Circuit, 52: Delay circuit, 52_1: Delay circuit, 52_2: Delay circuit, 52_ 4: Delay circuit, 53: XOR circuit, 53_1: XOR circuit, 53_3: XOR circuit, 53_4: XOR circuit, 53_7: XOR circuit, 54: Test bit generation circuit, 55: Error - Detection circuit, 61: transistor, 64: transistor, 71: transistor, 72: transistor Ranjista, 200: Transistor, 200M: Transistor, 200T: Transistor 205: Conductor, 205a: Conductor, 205b: Conductor, 211: Insulator, 212: Insulator Edge material, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: acid 230a: oxide, 230b: oxide, 230c: oxide, 240: conductor, 24 0a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator Body, 242: Conductor, 242a: Conductor, 242b: Conductor, 243: Oxide, 243a : oxide, 243b: oxide, 246: conductor, 246a: conductor, 246b: conductor, 250: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 272: Insulator Body, 273: Insulator, 274: Insulator, 275: Insulator, 276: Conductor, 277: Insulator Body, 278: Conductor, 279: Insulator, 280: Insulator, 282: Insulator, 283: Insulator Body, 284: Insulator, 287: Insulator, 290: Conductor, 292: Capacitance, 292A: Capacitance 292B: Capacitor, 294: Conductor, 295: Insulator, 296: Insulator, 297: Conductor , 298: insulator, 299: conductor, 300: transistor, 311: semiconductor substrate, 31 3: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 31 6: Conductor, 411: Element layer, 413: Transistor layer, 413_m: Transistor layer, 413_1: Transistor layer, 415: Memory device layer, 415_n: Memory device Layer, 415_p: Memory device layer, 415_p-1: Memory device layer, 415_1: Memory device layer, 415_4: Memory device layer, 420: Memory device, 420A :Memory device, 420B:Memory device, 422:Area, 424:Conductor, 426 : Conductor, 428: Conductor, 430: Conductor, 470: Memory unit, 470_m: Me Mori Unit, 470_1: Memory Unit, 700: Electronic Components, 702: Printed Circuit Board 704: Mounting board, 711: Mold, 712: Land, 713: Electrode pad, 714 :Wire, 730:Electronic components, 731:Interposer, 732:Package substrate, 73 3: Electrode, 735: Semiconductor device, 901: Boundary region, 902: Boundary region, 7100: Robo 7120: Flying object, 7140: Cleaning robot, 7160: Car, 7200: TV Device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard Code, 7233: Monitor device, 7240: Game console, 7260: Game console, 7262: Co Controllor

Claims

1. The device comprises a semiconductor substrate, first to Nth first element layers (where N is a natural number of 2 or more) provided above the semiconductor substrate, and a second element layer provided between the semiconductor substrate and the first to Nth first element layers. Each of the first to Nth element layers has a plurality of memory cells, The first element layer of the aforementioned K (where K is an integer between 1 and N) holds a test bit. Data is stored in the first element layers other than the first element layer of K described above. The second element layer has an error detection circuit, The semiconductor substrate has a drive circuit, A memory device in which the channel formation region of a first transistor in each of the plurality of memory cells and the channel formation region of a second transistor in the error detection circuit are made of a metal oxide.

2. The device comprises a semiconductor substrate, first to Nth first element layers (where N is a natural number of 2 or more) provided above the semiconductor substrate, and a second element layer provided between the semiconductor substrate and the first to Nth first element layers. Each of the first to Nth element layers has a plurality of memory cells, The first element layer of the aforementioned K (where K is an integer between 1 and N) holds a test bit. Data is stored in the first element layers other than the first element layer of K described above. The second element layer includes an error detection circuit and a test bit generation circuit. The semiconductor substrate has a drive circuit, A memory device in which the channel formation region of a first transistor in each of the plurality of memory cells, the channel formation region of a second transistor in the error detection circuit, and the channel formation region of a third transistor in the test bit generation circuit are made of a metal oxide.

3. In claim 2, The aforementioned test bit generation circuit is a memory device having the function of generating the test bit when writing the data to the memory cell.

4. In any one of claims 1 to 3, The error detection circuit is a memory device that has the function of detecting errors in the data using the check bit when reading the data from the memory cell.

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