Semiconductor equipment

Abstract

To provide a semiconductor device that can improve reliability. [Solution] The semiconductor device comprises a substrate 10, a source electrode 14, a drain electrode 15, and a gate electrode 16 formed on the upper surface of the substrate 10. At least one of the source electrode 14 and the gate electrode 16 is partially extended toward the drain electrode 15 to form field plates 14a and 16a. The drain electrode 15 is connected to the lower surface of the substrate 10 by a via 18 that penetrates the substrate 10. An insulating film 19 made of a material with a dielectric constant lower than that of the substrate 10 is formed on the wall surface of the via 18.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Horizontal elements such as HEMTs and LDMOSs used as power devices include a substrate, a source electrode, a drain electrode, and a gate electrode formed on the upper surface side of the substrate. HEMT is an abbreviation for High Electron Mobility Transistor. LDMOS is an abbreviation for Lateral Double diffused MOSFET. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0003] In a semiconductor device including such a horizontal element, a half-bridge circuit or the like can be integrated into one chip by forming a via to connect the drain electrode to the lower surface of the substrate (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a horizontal element, by forming a field plate on the source electrode or the gate electrode, the electric field applied to the passivation film covering each electrode can be relaxed. For example, when a voltage is applied to the drain electrode, an electric field is applied to the passivation film near the source electrode due to the potential difference between the source electrode and the drain electrode. At this time, if a field plate is formed on the source electrode, the electric field is dispersed by the field plate, and the breakdown of the passivation film near the source electrode is suppressed.

[0006] However, forming vias below the drain electrode eliminates the escape route for the equipotential lines below the drain electrode, increasing the electric field applied to the passivation film. In particular, the electric field concentrates near the edges of the field plate, making the passivation film more susceptible to damage and reducing the reliability of the semiconductor device as a power device.

[0007] In view of the above points, this disclosure aims to provide a semiconductor device that can improve reliability. [Means for solving the problem]

[0008] To achieve the above objective, according to one aspect of this disclosure, the semiconductor device comprises a substrate (10), a source electrode (14), a drain electrode (15), and a gate electrode (16) formed on the upper surface of the substrate, wherein at least one of the source electrode and the gate electrode is partially extended toward the drain electrode to form a field plate (14a, 16a), the drain electrode is connected to the lower surface of the substrate by a via (18) penetrating the substrate, and an insulating film (19) made of a material with a dielectric constant lower than that of the substrate material is formed on the wall of the via.

[0009] By forming an insulating film on the via wall made of a material with a lower dielectric constant than the substrate material, the insulating film bears the voltage, thereby reducing the voltage borne by the substrate and mitigating the electric field near the field plate. This improves the reliability of the semiconductor device.

[0010] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2A]This is a cross-sectional view showing the manufacturing process of semiconductor devices. [Figure 2B] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 2A. [Figure 2C] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 2B. [Figure 2D] This is a cross-sectional view showing the manufacturing process of semiconductor devices, following Figure 2C. [Figure 3] This figure shows the equipotential lines of Comparative Example 1. [Figure 4] This figure shows the equipotential lines for Comparative Example 2. [Figure 5] This figure shows the equipotential lines of the first embodiment. [Figure 6] This figure shows the equipotential lines near the gate FP of Comparative Example 2. [Figure 7] This figure shows equipotential lines near the gate FP of the first embodiment. [Figure 8] This figure shows equipotential lines near the gate FP of the first embodiment. [Modes for carrying out the invention]

[0012] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First Embodiment) A first embodiment will be described. The semiconductor device 1 of this embodiment, shown in Figure 1, includes a lateral GaN (gallium nitride) HEMT element using a WBG (wide bandgap) material. As shown in Figure 1, the semiconductor device 1 includes a substrate 10. The substrate 10 is made of GaN. A buffer layer 11 made of GaN is laminated on the upper surface of the substrate 10.

[0014] On the upper surface of the buffer layer 11, an electron transport layer 12 and an electron supply layer 13 are laminated in sequence. The electron transport layer 12 is composed of a GaN-based semiconductor material, and the electron supply layer 13 is composed of a GaN-based semiconductor material having a larger bandgap energy than the material of the electron transport layer 12. And, a heterojunction structure is formed by the electron transport layer 12 and the electron supply layer 13, and 2DEG (two-dimensional electron gas) carriers are formed on the side of the electron transport layer 12. In the present embodiment, the electron transport layer 12 is composed of undoped GaN, and the electron supply layer 13 is composed of AlGaN (aluminum gallium nitride). The thickness direction, that is, the lamination direction, of the substrate 10 to the electron supply layer 13 is defined as the X direction, and a direction perpendicular to the X direction is defined as the Y direction.

[0015] On the upper surface of the electron supply layer 13, a source electrode 14, a drain electrode 15, and a gate electrode 16 made of Al (aluminum) are formed. The source electrode 14, the drain electrode 15, and the gate electrode 16 are arranged in a separated state from each other, and the gate electrode 16 is arranged between the source electrode 14 and the drain electrode 15.

[0016] A part of the source electrode 14 is a source FP (field plate) 14a. The source FP 14a is formed by extending the surface layer portion of the source electrode 14 on the side opposite to the electron supply layer 13 in the Y direction toward the drain electrode 15.

[0017] The gate electrode 16 is arranged below the source FP 14a. A part of the gate electrode 16 is a gate FP 16a. The gate FP 16a is formed by extending the surface layer portion of the gate electrode 16 on the side opposite to the electron supply layer 13 in the Y direction toward the source electrode 14 and the drain electrode 15. The source electrode 14, the drain electrode 15, and the gate electrode 16 are covered with a passivation film 17 made of SiO2 (silicon oxide).

[0018] Below the drain electrode 15, a via 18 is formed that penetrates the substrate 10 to the electron supply layer 13, exposing a part of the lower surface of the drain electrode 15 and a part of the lower surface of the passivation film 17. The via 18 is a cylindrical through-hole that opens circularly on the lower surface of the substrate 10. An insulating film 19 is formed on the wall surface of the via 18, and the lower surface of the passivation film 17 exposed by the via 18 is covered with the insulating film 19.

[0019] The insulating film 19 is made of a material with a lower relative permittivity than the material of the substrate 10. As described above, the substrate 10 is made of GaN, and the relative permittivity of GaN is 9.0. And the insulating film 19 is made of a material with a relative permittivity less than 9.0. For example, SiO2 and SiN (silicon nitride), which are often used in semiconductor device processes, have relative permittivities of 3.9 and 7.0, respectively, and the insulating film 19 can be made of SiO2 or SiN. In this embodiment, the insulating film 19 is made of a material with a lower relative permittivity than the materials of the substrate 10 to the electron supply layer 13. From the perspective of improving the electric field relaxation effect in the vicinity of the ends of the source FP14a and the gate FP16a described later, the width of the insulating film 19 in the Y direction is, for example, 0.5 μm or more, or 1 μm or more. Also, the upper limit of the width of the insulating film 19 in the Y direction is, for example, 5 μm, 3 μm, or 2 μm. For example, the width of the insulating film 19 in the Y direction may be 0.5 μm or more and 5 μm or less, or 1 μm or more and 3 μm or less, or 1 μm or more and 2 μm or less.

[0020] The inside of the via 18 is filled with a conductive metal such as Cu (copper) or Al to form a conductive layer 20. The drain electrode 15 is connected to the lower surface of the substrate 10 by the via 18 in which the conductive layer 20 is formed.

[0021] The manufacturing method of the semiconductor device 1 will be described using FIGS. 2A to 2D. In the process shown in FIG. 2A, a substrate 10 made of GaN is prepared, and the buffer layer 11, the electron traveling layer 12, and the electron supply layer 13 are epitaxially grown in order. Then, the source electrode 14 to the passivation film 17 are formed using sputtering or the like.

[0022] In the process shown in Figure 2B, vias 18 are formed that penetrate the substrate 10, buffer layer 11, electron transport layer 12, and electron supply layer 13 using dry etching, laser irradiation, etc. This exposes the lower surface of the drain electrode 15 and the lower surface of the portion of the passivation film 17 that is in contact with the drain electrode 15.

[0023] In the process shown in Figure 2C, insulating film 19 is formed on the lower surface of the substrate 10, the wall surface of the via 18, the lower surface of the drain electrode 15 exposed by the via 18, and the lower surface of the passivation film 17 using CVD, ALD, etc. CVD stands for Chemical Vapor Deposition. ALD stands for Atomic Layer Deposition.

[0024] In the process shown in Figure 2D, the insulating film 19 is patterned using dry etching, wet etching, etc. Specifically, of the insulating film 19, the portions formed on the underside of the drain electrode 15 and the underside of the substrate 10 are removed, while the portions formed on the walls of the vias 18 and the portions formed on the underside of the passivation film 17 are left. After that, the conductive layer 20 is formed by filling the inside of the vias 18 with Cu, Al, etc., thereby forming the semiconductor device 1 shown in Figure 1.

[0025] The operation of semiconductor device 1 will now be described. In semiconductor device 1, switching operation is performed by controlling the gate voltage applied to the gate electrode 16.

[0026] Specifically, 2DEG carriers are induced in the upper surface layer of the electron transport layer 12 due to the piezoelectric effect and polarization effect. When no gate voltage is applied to the gate electrode 16, the drain electrode 15 is made to a higher potential than the source electrode 14, causing current to flow from the drain electrode 15 to the source electrode 14 through these 2DEG carriers. In other words, the semiconductor device 1 is turned ON.

[0027] Then, during turn-off, a reverse voltage is applied to the semiconductor device 1. Specifically, when a gate voltage lower than the threshold voltage is applied to the gate electrode 16, the 2DEG layer becomes depleted, and no current flows between the source electrode 14 and the drain electrode 15.

[0028] The effects of this embodiment will now be described. When the semiconductor device 1 is turned off, a higher voltage is applied to the drain electrode 15 than to the source electrode 14 and the gate electrode 16, and this voltage applies an electric field to the passivation film 17. When the semiconductor device 1 is in use, for example, if a high voltage of 800V is applied to the drain electrode 15, a withstand voltage of about 1500V is required.

[0029] Figures 3 to 8 show the results of the analysis performed by the inventors, illustrating the electric field distribution when a voltage of 1500V is applied to the drain electrode 15. The dashed lines in Figures 3 to 8 represent equipotential lines, and the potential difference between two adjacent equipotential lines is assumed to be the same in each figure. The dimensions of each part are as shown on the vertical and horizontal axes of the figures. The length in the Y direction from the base of the gate electrode 16 to the tip of the source FP14a is 8 μm. The substrate 10 is not shown in Figures 3 to 8.

[0030] Figure 3 shows the analysis results for a configuration in which no via 18 is formed below the drain electrode 15, and the substrate 10 to the electron supply layer 13 are arranged over the entire area below the drain electrode 15. As shown in Figure 3, in this configuration, the substrate 10 to the electron supply layer 13 act as an escape route for equipotential lines in region R1 below the drain electrode 15, and the electric field near the ends of the source FP14a and gate FP16a is relaxed.

[0031] Figure 4 shows the analysis results for a configuration in which no insulating film 19 is formed on the wall surface of via 18, and a conductive layer 20 is formed throughout the entire interior of via 18. As shown in Figure 4, in this configuration, there is no escape route for equipotential lines as in Figure 3, so the electric field concentrates near the ends of source FP14a and gate FP16a, and there is a risk that the passivation film 17 will be destroyed.

[0032] Region R2 in Figure 5 is the area where the insulating film 19 is formed. As shown in Figure 5, by forming the insulating film 19 on the wall surface of the via 18, equipotential lines are densely arranged in the insulating film 19. That is, the insulating film 19 bears the voltage, reducing the voltage borne by the substrate 10 to the electron supply layer 13, and mitigating the electric field near the ends of the source FP 14a and gate FP 16a.

[0033] For example, near gate FP16a, the electric field is relaxed by the formation of the insulating film 19, as shown in Figures 6 to 8. Figure 6 is an enlarged view of the vicinity of gate FP16a in Figure 4. Figures 7 and 8 show equipotential lines near gate FP16a in this embodiment. In Figure 7, the width of the insulating film 19 in the Y direction, that is, the distance between the substrate 10 ~ electron supply layer 13 and the conductive layer 20 facing each other across the insulating film 19, is 1 μm, and in Figure 8, the width of the insulating film 19 in the Y direction is 2 μm.

[0034] As can be seen from Figures 6 to 8, in this embodiment in which the insulating film 19 is formed, the spacing between equipotential lines near the end of the gate FP16a is wider compared to when the insulating film 19 is not formed. In other words, the electric field near the end of the gate FP16a is relaxed.

[0035] Furthermore, as can be seen from Figures 7 and 8, by increasing the width of the insulating film 19 to 2 μm, the spacing between equipotential lines near the end of the gate FP16a is further widened compared to the case where the width of the insulating film 19 is 1 μm, and the electric field is further relaxed.

[0036] Furthermore, the electric field can be further relaxed by increasing the width of the insulating film 19 in the Y direction to more than 2 μm. In addition, in the analysis conducted by the inventors, the electric field was relaxed near the edge of the source FP14a in this embodiment, similar to the relaxation near the gate FP16a.

[0037] As described above, in this embodiment, an insulating film 19 made of a material with a lower dielectric constant than the material of the substrate 10 is formed on the wall surface of the via 18. As a result, the insulating film 19 bears the voltage, reducing the voltage borne by the substrate 10 and mitigating the electric field near the source FP14a and gate FP16a. Therefore, the destruction of the passivation film 17 due to the electric field is suppressed, and the reliability of the semiconductor device 1 is improved.

[0038] (Other embodiments) Furthermore, this disclosure is not limited to the embodiments described above and can be modified as appropriate. Also, it goes without saying that, in the embodiments described above, the elements constituting the embodiments are not necessarily essential unless explicitly stated as particularly essential or considered fundamentally essential. Furthermore, in the embodiments described above, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of the embodiments are mentioned, the embodiments are not limited to those specific numbers unless explicitly stated as particularly essential or considered fundamentally limited to a specific number. Also, when the shapes, positional relationships, etc., of the components are mentioned in the embodiments described above, the embodiments are not limited to those shapes, positional relationships, etc., unless explicitly stated or considered fundamentally limited to specific shapes, positional relationships, etc.

[0039] The semiconductor device 1 may include lateral elements other than GaN HEMTs. For example, the semiconductor device 1 may include ε-Ga2O3 (gallium oxide) HEMT elements and SiC (silicon carbide)-LDMOS elements.

[0040] In the first embodiment, the case in which the substrate 10 is made of GaN, a conductive material, was described, but the substrate 10 may be made of other conductive materials, such as Si (silicon), Ga2O3, etc. Alternatively, the substrate 10 may be made of a semi-insulating material such as SiC or sapphire. For example, if the substrate 10 is made of SiC with a relative permittivity of 9.7, the insulating film 19 can be made of, for example, SiO2 or SiN. Furthermore, the substrate 10 may be an Engineered Substrate with AlN (aluminum nitride) as the base material.

[0041] In the first embodiment, the via 18 is cylindrical, but the via 18 may have other shapes. For example, the opening shape of the via 18 may be polygonal or double-circular.

[0042] Only one of the source FP14a and the gate FP16a may be formed. A gate insulating film may be formed between the gate electrode 16 and the electron supply layer 13. The source electrode 14 may penetrate the electron supply layer 13 and be formed on the upper surface of the electron transport layer 12. [Explanation of Symbols]

[0043] 10 circuit boards 14 Source electrodes 14a Source FP 15 Drain electrode 16 Guard Station 16a Gate FP 18 Beer 19 Insulating film

Claims

1. A semiconductor device, The substrate (10) and The substrate comprises a source electrode (14), a drain electrode (15), and a gate electrode (16) formed on the upper surface side, At least one of the source electrode and the gate electrode is partially extended toward the drain electrode to form a field plate (14a, 16a), The drain electrode is connected to the lower surface of the substrate by a via (18) that penetrates the substrate. A semiconductor device having an insulating film (19) formed on the wall surface of the via, which is made of a material with a lower dielectric constant than the material of the substrate.

2. The electron transport layer (12) formed on the upper surface side of the substrate, The electron supply layer (13) is laminated on the upper surface of the electron transport layer, The source electrode and the drain electrode are formed on the upper surface side of the electron transport layer. The semiconductor device according to claim 1, wherein the gate electrode is formed on the upper surface side of the electron supply layer.

3. The substrate is made of GaN, Si, Ga ２ O ３ The semiconductor device according to claim 1, which is composed of SiC, sapphire, or AlN.

4. The insulating film is SiO ２ Alternatively, the semiconductor device according to claim 1, which is composed of SiN.

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