Semiconductor equipment

Abstract

To provide a semiconductor device with improved characteristics. [Solution] According to the embodiment, the semiconductor device includes first to third electrodes, a semiconductor member, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is provided between the first electrode and the second electrode in a first direction from the first electrode to the second electrode. The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region is Al x1 Ga 1-x1 It includes N(0≦x1<1). The second semiconductor region is Al x2 Ga 1-x2 N(x1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] For example, improvements in the characteristics of semiconductor devices such as transistors are desired. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-201716 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of improving its characteristics. [Means for solving the problem]

[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is provided between the first electrode and the second electrode in a first direction from the first electrode to the second electrode. At least a portion of the first insulating member is provided between the third electrode and the semiconductor member. The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region is Al x1 Ga 1-x1It includes N(0≦x1<1). The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second direction from the first partial region to the first electrode intersects the first direction. The direction from the second partial region to the second electrode is along the second direction. The direction from the third partial region to the first electrode portion is along the second direction. The fourth position of the fourth partial region in the first direction is between the first position of the first partial region in the first direction and the third position of the third partial region in the first direction. The fifth position of the fifth partial region in the first direction is between the third position and the second position of the second partial region in the first direction. The second semiconductor region includes Al x2 Ga 1-x2 It includes N(x1<x2≦1). The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. At least a part of the first electrode portion is between the first semiconductor portion and the second semiconductor portion in the first direction. The second semiconductor region includes a first semiconductor surface and a second semiconductor surface. The second semiconductor surface faces the first semiconductor region. The second semiconductor surface is between the first semiconductor region and the first semiconductor surface in the second direction. The third partial region includes a first part and a second part. The first partial position of the first part in the first direction is between the fourth position and the second partial position of the second part in the first direction. The first part includes a first surface facing the first electrode portion in the second direction. The second part includes a second surface facing the first electrode portion in the second direction. The first distance along the second direction between the first surface and the second semiconductor surface is shorter than the second distance along the second direction between the second surface and the second semiconductor surface. The fourth partial region includes an opposing portion facing the first electrode portion in the first direction. The first part and the opposing portion do not contain p-type impurities. Or, the first concentration of the p-type impurities in the first part is 0.2 times or more and 5 times or less the opposing portion concentration of the p-type impurities in the opposing portion.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the characteristics of the semiconductor device. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.

Modes for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the specification of the present application and each figure, the same reference numerals are given to the same elements as those described above with respect to the previously presented figures, and the detailed description is appropriately omitted.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a semiconductor member 10M, and a first insulating member 41.

[0009] Let the first direction D1 from the first electrode 51 to the second electrode 52 be the X-axis direction. Let one direction perpendicular to the X-axis direction be the Z-axis direction. Let the direction perpendicular to the X-axis direction and the Z-axis direction be the Y-axis direction.

[0010] The third electrode 53 includes a first electrode portion 53a. The first electrode portion 53a is provided between the first electrode 51 and the second electrode 52 in the first direction D1.

[0011] At least a portion of the first insulating member 41 is provided between the third electrode 53 and the semiconductor member 10M.

[0012] The semiconductor component 10M includes a first semiconductor region 10 and a second semiconductor region 20. The first semiconductor region 10 is Al x1 Ga 1-x1 N(0≦x1<1) is included. The composition ratio x1 can be, for example, 0 or greater and 0.13 or less. The first semiconductor region 10 includes, for example, GaN.

[0013] The first semiconductor region 10 includes a first subregion 11, a second subregion 12, a third subregion 13, a fourth subregion 14, and a fifth subregion 15. The second direction D2 from the first subregion 11 to the first electrode 51 intersects with the first direction D1. The second direction D2 may be, for example, the Z-axis direction. The direction from the second subregion 12 to the second electrode 52 follows the second direction D2. The direction from the third subregion 13 to the first electrode portion 53a follows the second direction D2.

[0014] In the second direction D2, the region overlapping with the first electrode 51 corresponds to the first subregion 11. In the second direction D2, the region overlapping with the second electrode 52 corresponds to the second subregion 12. In the second direction D2, the region overlapping with the first electrode portion 53a corresponds to the third subregion 13.

[0015] The fourth position of the fourth subregion 14 in the first direction D1 lies between the first position of the first subregion 11 in the first direction D1 and the third position of the third subregion 13 in the first direction D1. The fifth position of the fifth subregion 15 in the first direction D1 lies between the third position and the second position of the second subregion 12 in the first direction D1.

[0016] The second semiconductor region 20 is Al x2 Ga 1-x2It includes N(x1 < x2 ≤ 1). The composition ratio x2 may be, for example, 0.15 or more and 0.35 or less. The second semiconductor region 20 includes, for example, AlGaN.

[0017] The second semiconductor region 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. The direction from the fifth partial region 15 to the second semiconductor portion 22 is along the second direction D2.

[0018] At least a part of the first electrode portion 53a is between the first semiconductor portion 21 and the second semiconductor portion 22 in the first direction D1. A part of the first electrode portion 53a may be provided between the fourth partial region 14 and the fifth partial region 15 in the first direction D1.

[0019] The second semiconductor region 20 includes a first semiconductor surface Fs1 and a second semiconductor surface Fs2. The second semiconductor surface Fs2 faces the first semiconductor region 10. The second semiconductor surface Fs2 is between the first semiconductor region 10 and the first semiconductor surface Fs1 in the second direction D2. The first semiconductor surface Fs1 is, for example, the upper surface.

[0020] The third partial region 13 includes a first part p1 and a second part p2. The position of the first part p1 in the first direction D1 (the first part position) is between the fourth position of the fourth partial region 14 in the first direction D1 and the position of the second part p2 in the first direction D1 (the second part position).

[0021] The first part p1 includes a first surface F1. The first surface F1 faces the first electrode portion 53a in the second direction D2. The second part p2 includes a second surface F2. The second surface F2 faces the first electrode portion 53a in the second direction D2.

[0022] Let the distance along the second direction D2 between the first surface F1 and the second semiconductor surface Fs2 be the first distance d1. Let the distance along the second direction D2 between the second surface F2 and the second semiconductor surface Fs2 be the second distance d2. The first distance d1 is shorter than the second distance d2. Based on the second semiconductor surface Fs2, the first surface F1 is shallower than the second surface F2.

[0023] The fourth subregion 14 includes the opposing portion 14p. The opposing portion 14p faces the first electrode portion 53a in the first direction D1.

[0024] In this embodiment, the first portion p1 and the opposing portion 14p do not contain p-type impurities, or the concentration of p-type impurities in the first portion p1 is substantially the same as the concentration of p-type impurities in the opposing portion 14p. For example, the first concentration of p-type impurities in the first portion p1 is 0.2 times or more and 5 times or less the opposing portion concentration of p-type impurities in the opposing portion 14p. For example, the first portion p1 and the opposing portion 14p are i-GaN.

[0025] The second portion p2 does not contain p-type impurities. Alternatively, the first concentration is between 0.2 and 5 times the second concentration of p-type impurities in the second portion p2. For example, the second portion p2 is i-GaN.

[0026] In the semiconductor device 110, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 is, for example, a potential referenced to the potential of the first electrode 51. The first electrode 51 functions, for example, as one of the source electrode and the drain electrode. The second electrode 52 functions, for example, as the other of the source electrode and the drain electrode. The third electrode 53 functions, for example, as the gate electrode. The semiconductor device 110 is, for example, a transistor.

[0027] The first semiconductor region 10 includes a portion facing the second semiconductor region 20. A carrier region 10C is formed in this portion. The carrier region 10C is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0028] As already explained, at least a portion of the first electrode portion 53a lies between the first semiconductor portion 21 and the second semiconductor portion 22 in the first direction D1. The third electrode 53 is a recessed gate electrode. For example, a high threshold voltage can be obtained. For example, normally-off operation can be obtained.

[0029] As described above, in the embodiment, the first distance d1 is shorter than the second distance d2. This allows for, for example, a low on-resistance while maintaining a high threshold voltage.

[0030] For example, in the reference example, the first distance d1 is the same as the second distance d2. In such a reference example, increasing the first distance d1 (i.e., the second distance d2) results in a higher threshold voltage but a higher on-resistance. On the other hand, decreasing the first distance d1 (i.e., the second distance d2) results in a lower on-resistance but a lower threshold voltage.

[0031] In contrast, in this embodiment, the second distance d2 is long in the second portion p2 close to the second electrode 52. This allows for a high threshold voltage. On the other hand, the first distance d1 is short in the first portion p1 close to the first electrode 51. This allows for a low on-resistance. In this embodiment, a high threshold voltage and low on-resistance can be obtained. According to this embodiment, a semiconductor device with improved characteristics can be provided.

[0032] In this embodiment, the distance along the first direction D1 between the first electrode 51 and the third electrode 53 is shorter than the distance along the first direction D1 between the third electrode 53 and the second electrode 52. The first electrode 51 is, for example, a source electrode. The second electrode 52 is a drain electrode.

[0033] The first electrode 51, the second electrode 52, and the third electrode 53 may extend along a third direction D3. The third direction D3 intersects a plane containing the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0034] In this embodiment, the first concentration of p-type impurities in the first portion p1 is, for example, 1 × 10⁻⁶17 cm -3 It may be less than. The first concentration may be, for example, 1×10 16 cm -3 It may also be less than. The second concentration of the p-type impurities in the second portion p2 may be, for example, 1×10 17 cm -3 It may be less than. The second concentration may be, for example, 1×10 16 cm -3 It may also be less than. By the low concentration of impurities in these portions (the first semiconductor region 10), for example, a high carrier concentration can be obtained. Thereby, for example, a lower on-resistance can be obtained.

[0035] As shown in FIG. 1, the semiconductor device 110 may include a first compound member 31. The first compound member 31 contains Al z1 Ga 1-z1 N (x2 < z1 ≤ 1). The composition ratio z1 may be, for example, 0.8 or more and 1 or less. The first compound member 31 contains, for example, AlN.

[0036] At least a part of the first compound member 31 is provided between the opposing portion 14p and the first insulating member 41, between the first portion p1 and the first insulating member 41, and between the second portion p2 and the first insulating member 41.

[0037] For example, the first portion p1 includes a portion facing the first compound member 31. A carrier region 10C may be formed in this portion. For example, the second portion p2 includes a portion facing the first compound member 31. A carrier region 10C may be formed in this portion. With these regions, a low on-resistance can be easily obtained.

[0038] For example, if at least either the first portion p1 or the second portion p2 contains p-type impurities, it is difficult to form the above carrier region 10C. By the first portion p1 and the second portion p2 substantially not containing p-type impurities, a low on-resistance can be effectively obtained.

[0039] For example, a low concentration of p-type impurities in the opposing portion 14p results in a high carrier concentration in the current path including the opposing portion 14p. This leads to a low on-resistance.

[0040] Figure 2 is a graph illustrating the characteristics of a semiconductor device. Figure 2 illustrates experimental results for a reference example where the first distance d1 is the same as the second distance d2. The horizontal axis represents the second distance d2 (i.e., the first distance d1). The vertical axis represents the threshold voltage. As shown in Figure 2, a high threshold voltage Vth is obtained when the second distance d2 is 100 nm or greater. When the second distance d2 is less than 75 nm, the threshold voltage Vth is low. It is thought that a current path is generated when the second distance d2 is less than 75 nm.

[0041] From the results in Figure 2, it is considered that when the first distance d1 is less than 75 nm, a low resistance can be obtained in the current path of the first portion p1.

[0042] In the embodiment, the first distance d1 is preferably less than 75 nm, for example. Low on-resistance is easily and stably obtained. The second distance d2 is preferably 100 nm or more, for example. High threshold voltage Vth is easily and stably obtained. The second distance d2 may also be 130 nm or more, for example.

[0043] For example, the first distance d1 can be less than or equal to half of the second distance d2.

[0044] The first portion p1 may, for example, face the end of the first electrode portion 53a on the side of the first electrode 51 (the first end). The second portion p2 may face the end of the first electrode portion 53a on the side of the second electrode 52 (the second end).

[0045] For example, the first surface F1 may be aligned with the first direction D1. The second surface F2 may be aligned with the first direction D1. The first surface F1 and the second surface F2 may be aligned with, for example, a plane perpendicular to the second direction D2 (the XY plane). Low resistance is easily obtained in the current path including the first part p1 and the second part p2.

[0046] As shown in Figure 1, the third sub-region 13 may include a first step difference s1 between the first sub-region p1 and the second sub-region p2. By discontinuously changing the depth, for example, a high threshold and a low on-resistance can be easily obtained stably.

[0047] As shown in Figure 1, the first insulating member 41 may include a first insulating region 41a, a second insulating region 41b, and a third insulating region 41c. At least a portion of the first insulating region 41a is located between the first semiconductor portion 21 and the first electrode portion 53a. At least a portion of the second insulating region 41b is located between the first electrode portion 53a and the second semiconductor portion 22. The third insulating region 41c is located between the third partial region 13 and the first electrode portion 53a in the second direction D2.

[0048] The first compound member 31 may include a first compound region 31a, a second compound region 31b, and a third compound region 31c. At least a portion of the first compound region 31a lies between the first semiconductor portion 21 and the first insulating region 41a. At least a portion of the second compound region 31b lies between the second insulating region 41b and the second semiconductor portion 22. The third compound region 31c lies between the third partial region 13 and the third insulating region 41c in the second direction D2.

[0049] The semiconductor device 110 may further include a second insulating member 42. The second insulating member 42 includes a first insulating portion 42a and a second insulating portion 42b. The first insulating portion 42a is located between the first semiconductor portion 21 and a portion of the first insulating member 41 in a second direction D2. The second insulating portion 42b is located between the second semiconductor portion 22 and another portion of the first insulating member 41 in a second direction D2. The second insulating member 42 functions, for example, as a protective film. The second insulating member 42 may include, for example, at least one selected from the group consisting of oxygen and nitrogen, and Si.

[0050] The first insulating member 41 may include, for example, at least one selected from the group consisting of oxygen and nitrogen, and Si. The first insulating member 41 may also include, for example, silicon oxide. Good insulating properties can be obtained.

[0051] In embodiments, the p-type impurity includes, for example, at least one selected from the group consisting of Mg, Zn, and Be. The p-type impurity includes, for example, Mg.

[0052] As shown in Figure 1, the opposing portion 14p includes a first side surface SF1 that faces the first electrode portion 53a. The angle between the first side surface SF1 and the first surface F1 (first angle) may be between 80 degrees and 100 degrees. For example, the first side surface SF1 may be substantially perpendicular to the first surface F1.

[0053] The fifth subregion 15 includes a second side surface SF2 facing the first electrode portion 53a in the first direction D1. The angle between the second side surface SF2 and the second surface F2 (second angle) may be between 80 and 100 degrees. For example, the second side surface SF2 may be substantially perpendicular to the second surface F2. A second angle close to 90 degrees makes it easier to obtain, for example, a high threshold voltage Vth.

[0054] As shown in Figure 1, the semiconductor device 110 may include a substrate 18s, which may be, for example, a silicon substrate. The semiconductor device 110 may include a nitride layer 18a. The nitride layer 18a is provided between the substrate 18s and the first semiconductor region 10. The nitride layer 18a may include, for example, Al, Ga, and N. The nitride layer 18a is, for example, a buffer layer. The nitride layer 18a is provided on the substrate 18s. The first semiconductor region 10 is provided on the nitride layer 18a. The second semiconductor region 20 is provided on the first semiconductor region 10. For example, a first electrode 51, a second electrode 52, and a third electrode 53 are provided on the first semiconductor region 10.

[0055] The semiconductor component 10M may include an intermediate layer 18b containing carbon (C). The intermediate layer 18b is provided between the nitride layer 18a and the first semiconductor region 10. The intermediate layer 18b may have the same composition as, for example, the first semiconductor region 10. The intermediate layer 18b may be, for example, a GaN layer containing carbon. For example, high insulation properties can be easily obtained. The concentration of carbon in the intermediate layer 18b may be, for example, 1 × 10⁻⁶. 18 cm-3 The above is 1 x 10 21 cm -3 The following is fine.

[0056] The first semiconductor region 10 may contain carbon. The concentration of carbon in the first semiconductor region 10 is lower than the concentration of carbon in the intermediate layer 18b. The concentration of carbon in the first semiconductor region 10 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 The following is acceptable: The concentration of Mg in the first semiconductor region 10 is lower than the concentration of carbon in the first semiconductor region 10. The concentration of Mg in the first semiconductor region 10 may be 1 / 5 or less of the concentration of carbon in the first semiconductor region 10.

[0057] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 3, in the semiconductor device 111 according to this embodiment, the first semiconductor region 10 includes a third portion p3. Except for this, the configuration of the semiconductor device 111 may be the same as that of the semiconductor device 110.

[0058] In the semiconductor device 111, the third subregion 13 further includes a third subregion p3. The position of the third subregion p3 in the first direction D1 (third subregion position) lies between the position of the first subregion p1 in the first direction D1 (first subregion position) and the position of the second subregion p2 in the first direction D1 (second subregion position).

[0059] The third portion p3 includes a third surface F3 facing the first electrode portion 53a in the second direction D2. The distance between the third surface F3 and the second semiconductor surface Fs2 along the second direction D2 is defined as the third distance d3. The third distance d3 is between the first distance d1 and the second distance d2.

[0060] For example, the third portion p3 does not contain p-type impurities. Alternatively, the first concentration is 0.2 times or more and 5 times or less the third concentration of p-type impurities in the third portion p3. Thus, the third portion region 13 may include three or more surfaces.

[0061] The third subregion 13 may include a second step difference s2 between the third subregion p3 and the second subregion p2. The third subregion 13 may include two or more steps. By discontinuously changing the depth, for example, a high threshold and a low on-resistance can be easily obtained stably.

[0062] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 4, in the semiconductor device 112 according to this embodiment, the first semiconductor region 10 includes a third step s3, etc. Aside from this, the configuration of the semiconductor device 111 may be the same as that of the semiconductor device 110.

[0063] In the semiconductor device 112, the third partial region 13 may include a third step s3 and a fourth step s4, etc.

[0064] The first part p1 and the second part p2 described above may be formed by processing the semiconductor member 10M using multiple masks. Multiple steps may be formed, for example, by repeatedly performing a process that includes processing the semiconductor member 10M using a mask and retracting the mask.

[0065] (Second Embodiment) Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in Figure 5, in the semiconductor device 120 according to this embodiment, the first surface F1 and the second surface F2 are inclined with respect to the second direction D2. Aside from this, the configuration of the semiconductor device 120 may be the same as that of the semiconductor device 110 according to the first embodiment.

[0066] In the semiconductor device 120, at least one of the first surface F1 and the second surface F2 may be inclined with respect to the first direction D1. In the semiconductor device 120 as well, the first distance d1 is shorter than the second distance d2. A high threshold voltage and low on-resistance can be obtained. According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0067] In the embodiment, information regarding the shape of the nitride region can be obtained, for example, by electron microscope images. Information regarding composition and elemental concentration can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information regarding composition may also be obtained, for example, by reciprocal lattice space mapping.

[0068] The embodiments may include the following technical proposals. (Technical proposal 1) First electrode and, The second electrode and, A third electrode including a first electrode portion, wherein the first electrode portion is provided between the first electrode and the second electrode in a first direction from the first electrode to the second electrode, and the third electrode is provided between the first electrode and the second electrode. Semiconductor components and First insulating member and Equipped with, At least a portion of the first insulating member is provided between the third electrode and the semiconductor member, The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region is Al x1 Ga 1-x1 N(0≦x1<1), The first semiconductor region includes a first subregion, a second subregion, a third subregion, a fourth subregion, and a fifth subregion. The second direction from the first subregion to the first electrode intersects the first direction, The direction from the second subregion to the second electrode is along the second direction, The direction from the third subregion to the first electrode portion is along the second direction, The fourth position of the fourth subregion in the first direction is located between the first position of the first subregion in the first direction and the third position of the third subregion in the first direction. The fifth position of the fifth partial region in the first direction is between the third position and the second position of the second partial region in the first direction. The second semiconductor region contains Al x2 Ga 1-x2 and N (x1 < x2 ≤ 1). The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. At least a part of the first electrode portion is between the first semiconductor portion and the second semiconductor portion in the first direction. The second semiconductor region includes a first semiconductor surface and a second semiconductor surface. The second semiconductor surface faces the first semiconductor region, and the second semiconductor surface is between the first semiconductor region and the first semiconductor surface in the second direction. The third partial region includes a first part and a second part. The first partial position of the first part in the first direction is between the fourth position and the second partial position of the second part in the first direction. The first part includes a first surface facing the first electrode portion in the second direction. The second part includes a second surface facing the first electrode portion in the second direction. The first distance along the second direction between the first surface and the second semiconductor surface is shorter than the second distance along the second direction between the second surface and the second semiconductor surface. The fourth partial region includes a facing portion facing the first electrode portion in the first direction. The first part and the facing portion do not contain p-type impurities, or The first concentration of the p-type impurities in the first part is 0.2 times or more and 5 times or less than the facing portion concentration of the p-type impurities in the facing portion. Semiconductor device.

[0069] (Technical solution 2) The second part does not contain the p-type impurities, or The semiconductor device according to Claim 1, wherein the first concentration is 0.2 times or more and 5 times or less the second concentration of the p-type impurities in the second part.

[0070] (Claim 3) The second concentration is less than 1×10 17 cm -3 The semiconductor device according to Claim 2.

[0071] (Claim 4) The first concentration is less than 1×10 17 cm -3 The semiconductor device according to any one of Claims 1 to 3.

[0072] (Claim 5) Al z1 Ga 1-z1 Further comprising a first compound member containing N(x2 < z1 ≦ 1), The semiconductor device according to any one of Claims 1 to 4, wherein at least a part of the first compound member is provided between the opposing part and the first insulating member, between the first part and the first insulating member, and between the second part and the first insulating member.

[0073] (Claim 6) The first distance is less than 75 nm, The semiconductor device according to any one of Claims 1 to 5, wherein the second distance is 100 nm or more.

[0074] (Claim 7) The semiconductor device according to any one of Claims 1 to 5, wherein the first distance is 1 / 2 or less of the second distance.

[0075] (Claim 8) The first part faces the first end on the side of the first electrode of the first electrode part, The semiconductor device according to any one of Claims 1 to 7, wherein the second part faces the second end on the side of the second electrode of the first electrode part.

[0076] (Technical proposal 9) The first surface is aligned along the first direction, The second surface is a semiconductor device according to any one of the technical proposals 1 to 8, along the first direction.

[0077] (Technical proposal 10) A semiconductor device according to any one of the technical proposals 1 to 8, wherein at least one of the first surface and the second surface is inclined with respect to the first direction.

[0078] (Technical proposal 11) The semiconductor device according to any one of the technical proposals 1 to 10, wherein the distance between the first electrode and the third electrode along the first direction is shorter than the distance between the third electrode and the second electrode along the first direction.

[0079] (Technical proposal 12) The semiconductor device according to any one of the technical proposals 1 to 11, wherein the third sub-region includes a first step difference between the first and second parts.

[0080] (Technical proposal 13) The aforementioned third subregion further includes the third part, The position of the third portion in the first direction is between the position of the first portion and the position of the second portion. The third portion includes a third surface facing the first electrode portion in the second direction, The semiconductor device according to any one of Technical Proposals 1 to 12, wherein the third distance along the second direction between the third surface and the first semiconductor surface is between the first distance and the second distance.

[0081] (Technical proposal 14) The third portion is free from the p-type impurity, or The semiconductor device according to Technical Proposal 13, wherein the first concentration is 0.2 times or more and 5 times or less the third concentration of the p-type impurity in the third portion.

[0082] (Technical proposal 15) The semiconductor device according to Technical Proposal 13 or 14, wherein the third portion region includes a second step between the third portion and the second portion.

[0083] (Technical proposal 16) The semiconductor device according to Technical Proposal 15, wherein the third portion region includes one or more steps provided between the second step and the second portion.

[0084] (Technical proposal 17) The semiconductor device according to any one of the technical proposals 1 to 16, wherein the p-type impurity comprises at least one selected from the group consisting of Mg, Zn, and Be.

[0085] (Technical proposal 18) The opposing portion includes a first side surface facing the first electrode portion, A semiconductor device according to any one of Technical Proposals 1 to 17, wherein the first angle between the first side surface and the first surface is 80 degrees or more and 100 degrees or less.

[0086] (Technical proposal 19) The fifth subregion includes a second surface facing the first electrode portion in the first direction, The semiconductor device according to any one of Technical Proposals 1 to 18, wherein the second angle between the second side surface and the second surface is 80 degrees or more and 100 degrees or less.

[0087] (Technical proposal 20) Further comprising a second insulating member, The second insulating member includes the first insulating portion and the second insulating portion, The first insulating portion is located between the first semiconductor portion and a part of the first insulating member in the second direction. The semiconductor device according to any one of Technical Proposals 1 to 19, wherein the second insulating portion is located between the second semiconductor portion and another part of the first insulating member in the second direction.

[0088] According to the embodiment, a semiconductor device capable of improving characteristics is provided.

[0089] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element included in a semiconductor device, such as electrodes, semiconductor members, semiconductor regions, and insulating members, is included within the scope of the present invention as long as it can be implemented in the same manner and similar effects can be obtained by appropriately selecting from the range known to those skilled in the art.

[0090] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0091] Furthermore, all semiconductor devices that can be implemented by those skilled in the art by appropriately modifying the design based on the semiconductor devices described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0092] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and these modifications and alterations are also understood to fall within the scope of the present invention.

[0093] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0094] 10, 20: First and second semiconductor regions, 10C: Carrier region, 10M: Semiconductor component 11-15: 1st-5th subregions, 14p: Opposing region, 18a: Nitride layer, 18b: Intermediate layer, 18s: Substrate, 21, 22: 1st and 2nd semiconductor regions, 31: 1st compound member, 31a-31c: 1st-3rd compound regions, 41: 1st insulating member, 41a-41c: 1st-3rd insulating regions, 42: 2nd insulating member, 42a, 42b: 1st and 2nd insulating regions, 51-53: 1st-3rd electrodes, 53a: 1st electrode region, 110-112, 120: Semiconductor device, D1-D3: 1st-3rd directions, F1-F3: 1st-3rd surfaces, Fs1, Fs2: 1st and 2nd semiconductor surfaces, SF1, SF2: 1st and 2nd sides, Vth: Threshold voltage d1~d3: 1st to 3rd distance, p1~p3: 1st to 3rd section, s1~s4: 1st to 4th step difference

Claims

1. First electrode and, The second electrode and A third electrode including a first electrode portion, wherein the first electrode portion is provided between the first electrode and the second electrode in a first direction from the first electrode to the second electrode, and the third electrode is provided between the first electrode and the second electrode. Semiconductor components and First insulating member and Equipped with, At least a portion of the first insulating member is provided between the third electrode and the semiconductor member, The semiconductor member includes a first semiconductor region and a second semiconductor region, The first semiconductor region is Al ｘ１ Ga １－ｘ１ N includes (0 ≤ x1 < 1), The first semiconductor region includes a first subregion, a second subregion, a third subregion, a fourth subregion, and a fifth subregion. The second direction from the first subregion to the first electrode intersects the first direction. The direction from the second subregion to the second electrode is along the second direction, The direction from the third subregion to the first electrode portion is along the second direction, The fourth position of the fourth subregion in the first direction is located between the first position of the first subregion in the first direction and the third position of the third subregion in the first direction. The fifth position in the first direction of the fifth subregion is located between the third position and the second position in the first direction of the second subregion. The above second semiconductor region is Al ｘ２ Ga １－ｘ２ N (including x1 < x2 ≤ 1), The second semiconductor region includes the first semiconductor portion and the second semiconductor portion. The direction from the fourth subregion to the first semiconductor subregion is along the second direction, The direction from the fifth subregion to the second semiconductor subregion is along the second direction, At least a portion of the first electrode portion is located between the first semiconductor portion and the second semiconductor portion in the first direction. The second semiconductor region includes a first semiconductor surface and a second semiconductor surface, the second semiconductor surface facing the first semiconductor region, and the second semiconductor surface is located between the first semiconductor region and the first semiconductor surface in the second direction. The third sub-region includes the first and second sub-regions, The first part position of the first part in the first direction is between the fourth position and the second part position of the second part in the first direction. The first portion includes a first surface facing the first electrode portion in the second direction, The second portion includes a second surface facing the first electrode portion in the second direction, The first distance along the second direction between the first surface and the second semiconductor surface is shorter than the second distance along the second direction between the second surface and the second semiconductor surface. The fourth subregion includes a facing portion that faces the first electrode portion in the first direction, The first portion and the opposing portion are free from p-type impurities, or The first concentration of the p-type impurity in the first portion is 0.2 times or more and 5 times or less the opposing portion concentration of the p-type impurity in the opposing portion of the semiconductor device.

2. The second portion described above does not contain the p-type impurity, or The semiconductor device according to claim 1, wherein the first concentration is 0.2 times or more and 5 times or less the second concentration of the p-type impurity in the second portion.

3. The second concentration is 1 × 10 １７ cm －３ The semiconductor device according to claim 2, wherein the semiconductor device is less than [amount missing].

4. The first concentration is 1 × 10 １７ cm －３ A semiconductor device according to any one of claims 1 to 3, wherein the value is less than [value missing].

5. Al ｚ１ Ga １－ｚ１ further comprising a first compound member containing N (x2 < z1 ≤ 1) A semiconductor device according to any one of claims 1 to 3, wherein at least a portion of the first compound member is provided between the opposing portion and the first insulating member, between the first portion and the first insulating member, and between the second portion and the first insulating member.

6. The first distance is less than 75 nm. The semiconductor device according to any one of claims 1 to 3, wherein the second distance is 100 nm or more.

7. The semiconductor device according to any one of claims 1 to 3, wherein the first distance is 1 / 2 or less of the second distance.

8. The first portion faces the first end of the first electrode portion on the side of the first electrode, The semiconductor device according to any one of claims 1 to 3, wherein the second portion faces the second end of the first electrode portion on the side of the second electrode.

9. The first surface is aligned along the first direction, The second surface is aligned with the first direction, as described in any one of claims 1 to 3.

10. The semiconductor device according to any one of claims 1 to 3, wherein at least one of the first surface and the second surface is inclined with respect to the first direction.

11. The semiconductor device according to any one of claims 1 to 3, wherein the distance between the first electrode and the third electrode along the first direction is shorter than the distance between the third electrode and the second electrode along the first direction.

12. The semiconductor device according to any one of claims 1 to 3, wherein the third partial region includes a first step difference between the first and second portions.

13. The aforementioned third subregion further includes the third portion, The position of the third portion in the first direction is between the position of the first portion and the position of the second portion. The third portion includes a third surface facing the first electrode portion in the second direction, The semiconductor device according to any one of claims 1 to 3, wherein the third distance along the second direction between the third surface and the first semiconductor surface is between the first distance and the second distance.

14. The third portion is free from the p-type impurity, or The semiconductor device according to claim 13, wherein the first concentration is 0.2 times or more and 5 times or less the third concentration of the p-type impurity in the third portion.

15. The semiconductor device according to claim 13, wherein the third portion region includes a second step between the third portion and the second portion.

16. The semiconductor device according to claim 15, wherein the third partial region includes one or more steps provided between the second step and the second portion.

17. The semiconductor device according to any one of claims 1 to 3, wherein the p-type impurity comprises at least one selected from the group consisting of Mg, Zn, and Be.

18. The opposing portion includes a first side surface facing the first electrode portion, The semiconductor device according to any one of claims 1 to 3, wherein the first angle between the first side surface and the first surface is 80 degrees or more and 100 degrees or less.

19. The fifth portion region includes a second surface facing the first electrode portion in the first direction, The semiconductor device according to any one of claims 1 to 3, wherein the second angle between the second side surface and the second surface is 80 degrees or more and 100 degrees or less.

20. Further comprising a second insulating member, The second insulating member includes the first insulating portion and the second insulating portion, The first insulating portion is located between the first semiconductor portion and a part of the first insulating member in the second direction. The semiconductor device according to any one of claims 1 to 3, wherein the second insulating portion is located between the second semiconductor portion and another part of the first insulating member in the second direction.

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