Nitride semiconductor equipment

Abstract

The present invention provides a nitride semiconductor device that can reduce on-resistance. [Solution] The nitride semiconductor device 200 includes a first nitride semiconductor layer 2, second nitride semiconductor layers 3, 3A located thereon and having a larger bandgap energy than the first nitride semiconductor layer, a third nitride semiconductor layer 4 located thereon and having a smaller bandgap energy than the second nitride semiconductor layer, a P-type semiconductor layer 6 electrically connected to the third nitride semiconductor layer, a control electrode 7 located thereon, a first electrode 8 located on the first nitride semiconductor layer and spaced apart from the third nitride semiconductor layer, and a second electrode 10 located spaced apart from the third nitride semiconductor layer which extends in the opposite direction from the first electrode across the control electrode when viewed in plan, and which reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, or a second electrode 10 provided on the upper part of a diffusion layer 14 with a high impurity concentration that reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer.

Description

Technical Field

[0005]

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] In a FET, which is a typical nitride semiconductor device using a nitride semiconductor, a phenomenon called current collapse easily occurs. Current collapse is a phenomenon in which once the device is turned off and then turned on again, the resistance value (on-resistance) increases (the current becomes difficult to flow). If the characteristics of current collapse are poor, high-speed switching becomes difficult, and extremely serious problems occur in the operation of the device.

[0003] A structure is known that includes a channel layer composed of a first nitride semiconductor layer such as GaN, a barrier layer composed of a second nitride semiconductor layer such as AlGaN having a larger bandgap energy than the first nitride semiconductor layer, and a polarization superjunction layer (PSJ structure) composed of a third nitride semiconductor layer having a smaller bandgap energy than the second nitride semiconductor layer such as GaN. A two-dimensional electron gas layer is generated in the channel layer near the interface between the channel layer and the barrier layer, a two-dimensional hole gas layer is generated in the PSJ structure near the interface between the barrier layer and the PSJ structure, and drain electrodes, gate electrodes, and source electrodes are arranged on the barrier layer (for example, Patent Document 1). It is disclosed that according to this structure, electric field concentration is unlikely to occur and the current collapse phenomenon can be reduced.

[0004] Also, it is disclosed that by sandwiching a layer such as AlN having a higher Al composition ratio than the barrier layer between the channel layer and the barrier layer, the concentration of the two-dimensional electron gas layer can be increased.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] By creating a polarized superjunction (PSJ) layer, a two-dimensional hole gas layer is generated, which can reduce the current collapse phenomenon. However, the generation of the two-dimensional hole gas layer reduces the carrier concentration in the two-dimensional electron gas layer. By inserting a layer such as AlN with a higher Al composition ratio than the barrier layer between the channel layer and the barrier layer, the concentration in the two-dimensional electron gas layer can be increased, but there is a problem in that the on-resistance cannot be sufficiently reduced.

[0007] This disclosure was made to solve the above problems and aims to provide a nitride semiconductor device that can reduce on-resistance. [Means for solving the problem]

[0008] This disclosure has been made to achieve the above objective, and comprises a first nitride semiconductor layer in which a two-dimensional electron gas layer is generated, a second nitride semiconductor layer on the first nitride semiconductor layer having a larger bandgap energy than the first nitride semiconductor layer, a third nitride semiconductor layer in a part of the second nitride semiconductor layer having a smaller bandgap energy than the second nitride semiconductor layer and in which a two-dimensional hole gas layer is generated, a P-type semiconductor layer electrically connected to the third nitride semiconductor layer, a control electrode on the P-type semiconductor layer, and the first nitride The present invention provides a nitride semiconductor device comprising: a first electrode located on a semiconductor layer and spaced apart from the third nitride semiconductor layer; and a second electrode, viewed in plan, spaced apart from the end of the third nitride semiconductor layer that extends on the opposite side of the control electrode from the first electrode, wherein the second electrode reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, or the second electrode reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer and is provided on top of a diffusion layer with a higher impurity concentration than the second nitride semiconductor layer.

[0009] Such nitride semiconductor devices can reduce on-resistance.

[0010] Furthermore, if the second electrode extends from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, the nitride semiconductor device can include a groove extending from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, and the second electrode provided on the side of the groove on the control electrode side that extends to the first nitride semiconductor layer.

[0011] Such nitride semiconductor devices can also reduce on-resistance.

[0012] In this case, a nitride semiconductor device can be provided in which a fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer is further included between the first nitride semiconductor layer and the second nitride semiconductor layer, the groove is formed penetrating the fourth nitride semiconductor layer, and the second electrode is provided in the groove to a position deeper than the fourth nitride semiconductor layer.

[0013] Such nitride semiconductor devices can also reduce on-resistance.

[0014] In this case, the thickness of the second nitride semiconductor layer in the region between the groove and the third nitride semiconductor layer where the third nitride semiconductor layer is not disposed is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer, and a portion of the second electrode provided in the groove extends at least from within the groove to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side, thus creating a nitride semiconductor device.

[0015] This allows for a stable reduction in contact between the third nitride semiconductor layer and the drain electrode, while also reducing variations in on-resistance, thereby achieving a more stable reduction in on-resistance.

[0016] In this case, the second electrode can be a nitride semiconductor device having a gradient such that the distance between the third nitride semiconductor layer and the second electrode increases in the direction in which the upper surface of the second nitride semiconductor layer faces the portion of the second electrode that extends on the upper surface of the second nitride semiconductor layer and faces the third nitride semiconductor layer.

[0017] As a result, at the height where the third nitride semiconductor layer is provided, the second electrode can be further separated from the third nitride semiconductor layer, thereby reducing on-resistance variation and lowering the on-resistance, while also securing a greater distance between the third nitride semiconductor layer and the second electrode, and enabling a reduction in chip size.

[0018] Furthermore, if the second electrode is provided on top of the diffusion layer, the nitride semiconductor device can further include a fourth nitride semiconductor layer between the first nitride semiconductor layer and the second nitride semiconductor layer, the fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer, and the diffusion layer is formed at a depth greater than that of the fourth nitride semiconductor layer.

[0019] Such nitride semiconductor devices can also reduce on-resistance.

[0020] Furthermore, when the second electrode is provided on the upper part of the diffusion layer, the thickness of the second nitride semiconductor layer in the region between the second electrode and the third nitride semiconductor layer where the third nitride semiconductor layer is not provided is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer, and a portion of the second electrode provided on the diffusion layer extends at least to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side, thus creating a nitride semiconductor device.

[0021] This allows for a stable reduction in contact between the third nitride semiconductor layer and the drain electrode, while also reducing variations in on-resistance, thereby achieving a more stable reduction in on-resistance.

[0022] At this time, the second electrode can be a nitride semiconductor device in which a portion of the second electrode extending on the upper surface of the second nitride semiconductor layer and facing the third nitride semiconductor layer has an inclination such that the distance between the third nitride semiconductor layer and the second electrode increases in the direction in which the upper surface of the second nitride semiconductor layer faces.

[0023] Thereby, at the height where the third nitride semiconductor layer is provided, the second electrode can be further separated from the third nitride semiconductor layer. Therefore, while reducing the variation in on-resistance and reducing the on-resistance, the distance between the third nitride semiconductor layer and the second electrode can be secured, and the chip size can be reduced.

[0024] At this time, a fifth nitride semiconductor layer having a higher Al composition ratio than the second nitride semiconductor layer is further included between the second nitride semiconductor layer and the third nitride semiconductor layer, and the fifth nitride semiconductor layer is not provided in a region where the third nitride semiconductor layer is not disposed between the second electrode and the third nitride semiconductor layer. A nitride semiconductor device can be formed.

[0025] By further providing the fifth nitride semiconductor layer, the height of the third nitride semiconductor layer becomes higher, so it becomes easier to secure the distance between the third nitride semiconductor layer and the second electrode. Thereby, the distance between the third nitride semiconductor layer and the second electrode can be secured, and the chip size can be reduced.

Advantages of the Invention

[0026] As described above, according to the nitride semiconductor device of the present disclosure, the on-resistance can be reduced.

Brief Description of the Drawings

[0027] [Figure 1] The nitride semiconductor device according to the first embodiment of the present disclosure is shown. [Figure 2] The nitride semiconductor device according to the second embodiment of the present disclosure is shown. [Figure 3] The nitride semiconductor device according to the third embodiment of the present disclosure is shown. [Modes for carrying out the invention]

[0028] The disclosure is described in detail below, but is not limited to this.

[0029] As mentioned above, there was a need for nitride semiconductor devices that could reduce on-resistance.

[0030] As a result of diligent study on the above problems, the present inventors have provided a first nitride semiconductor layer in which a two-dimensional electron gas layer is formed, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap energy than the first nitride semiconductor layer, a third nitride semiconductor layer in a part of the second nitride semiconductor layer and having a smaller bandgap energy than the second nitride semiconductor layer and in which a two-dimensional hole gas layer is formed, a P-type semiconductor layer electrically connected to the third nitride semiconductor layer, a control electrode on the P-type semiconductor layer, and the third nitride semiconductor layer located on the first nitride semiconductor layer. We have discovered that on-resistance can be reduced by a nitride semiconductor device comprising a first electrode disposed away from a conductor layer, and a second electrode disposed away from the end of a third nitride semiconductor layer that extends in a plan view, sandwiching the control electrode and on the opposite side from the first electrode, wherein the second electrode reaches the first nitride semiconductor layer from the upper surface of the second nitride semiconductor layer, or the second electrode reaches the first nitride semiconductor layer from the upper surface of the second nitride semiconductor layer and is provided on top of a diffusion layer with a higher impurity concentration than the second nitride semiconductor layer, and have completed this disclosure.

[0031] The following explanation will be given with reference to the drawings.

[0032] [First Embodiment] Figure 1 shows a nitride semiconductor device according to the first embodiment of the present disclosure. As shown in Figure 1, the nitride semiconductor device 100 according to the first embodiment of the present disclosure includes a first nitride semiconductor layer 2 made of, for example, undoped GaN. The first nitride semiconductor layer 2 may be formed directly or optionally via a buffer layer (not shown) on a substrate 1 made of a nitride-based semiconductor such as silicon, silicon carbide, sapphire, or GaN. A second nitride semiconductor layer 3 is provided on the first nitride semiconductor layer 2, which has a larger bandgap energy than the first nitride semiconductor, and is made of, for example, undoped AlGaN. A third nitride semiconductor layer 4 is provided on the second nitride semiconductor layer 3, which has a smaller bandgap energy than the second nitride semiconductor in a part of its region, and is made of, for example, undoped GaN, and at least a part of it has a PSJ structure 5. A two-dimensional electron gas (2DEG) layer 20 is generated in the first nitride semiconductor layer 2 near the interface between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2. Furthermore, a two-dimensional hole gas (2DHG) layer 21 is formed within the third nitride semiconductor layer 4 near the interface between the second nitride semiconductor layer 3 and the third nitride semiconductor layer 4. In such a structure, as shown in Figure 1, the two-dimensional electron gas (2DEG) layer 20 within the first nitride semiconductor layer 2 forms a portion 20H with a high concentration of the two-dimensional electron gas layer and a portion 20L with a low concentration of the two-dimensional electron gas layer.

[0033] Furthermore, a P-type semiconductor layer 6, such as a P-type metal oxide layer like P-type GaN or NiO, and a control electrode 7, such as Ni / Au, are stacked on the second nitride semiconductor layer 3 or the third nitride semiconductor layer 4, electrically connected to the third nitride semiconductor layer 4. In a planar view, the second electrode 10 is positioned away from the end of the third nitride semiconductor layer 4, which extends on the opposite side of the first electrode 8, with the control electrode 7 in between. The first electrode 8 is located on the first nitride semiconductor layer 2 and is positioned away from the third nitride semiconductor layer 4. The second electrode 10 extends from the upper surface of the second nitride semiconductor layer 3 to the first nitride semiconductor layer 2. The PSJ structure 5 is the portion of the third nitride semiconductor layer 4 that extends further toward the second electrode 10 than the P-type semiconductor layer 6.

[0034] In the nitride semiconductor device 100 according to the first embodiment of this disclosure, the contact resistance can be reduced and the on-resistance can be reduced by the direct contact between the second electrode 10 and the relatively high-density portion 20H of the two-dimensional electron gas layer where the third nitride semiconductor layer 4 is not provided.

[0035] Furthermore, since the second electrode 10 is in direct contact with the two-dimensional electron gas layer 20, the width of the cross-section of the second electrode 10 in the lateral direction (from the gate electrode 7 to the second electrode 10) is not required to be very large. Therefore, the chip size can be reduced.

[0036] Furthermore, the first nitride semiconductor layer 2 may be a channel layer, the second nitride semiconductor layer 3 may be a barrier layer, the control electrode 7 may be a gate electrode, the first electrode 8 may be a source electrode, and the second electrode 10 may be a drain electrode.

[0037] As shown in Figure 1, the second electrode 10 is not in contact with the third nitride semiconductor layer 4, and is preferably formed on the side surface of the control electrode 7 in the groove 11 that reaches the first nitride semiconductor layer 2. Furthermore, it may be formed to fill the groove 11, such as by being formed across the side surface and bottom surface of the groove 11.

[0038] The thickness of portion 3A of the second nitride semiconductor layer between the second electrode 10 and the third nitride semiconductor layer 4 may be the same as the thickness of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4, or it may be thinner (for example, 5 nm) than the thickness of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4. If portion 3A is thin, a step or slope may be provided on the upper surface of portion 3A of the second nitride semiconductor layer. Furthermore, as shown in the figure, it is preferable that at least a part of the second electrode 10 extends (climbs up) on the upper surface of portion 3A of the second nitride semiconductor layer.

[0039] In other words, the thickness of the portion 3A of the second nitride semiconductor layer 3 in the region between the groove 11 and the third nitride semiconductor layer 4 where the third nitride semiconductor layer 4 is not located may be the same as the thickness of the portion of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4, or it may be smaller. Furthermore, it is preferable that a portion of the second electrode 10 provided in the groove 11 extends at least from within the groove 11 to the upper surface of the second nitride semiconductor layer 3A. This reduces contact variations between the third nitride semiconductor layer 4 and the second electrode 10, and because the second electrode 10 is in direct contact with the relatively high-density portion 20H of the two-dimensional electron gas layer where the third nitride semiconductor layer 4 is not provided, it is possible to effectively reduce on-resistance while further reducing on-resistance variations.

[0040] As shown in Figure 1, a fourth nitride semiconductor layer (first spacer layer) 12, such as AlN, with a higher Al composition ratio than the second nitride semiconductor layer 3, may be provided between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2. The groove 11 is formed to penetrate the fourth nitride semiconductor layer (first spacer layer) 12, and the second electrode 10 can be provided to a position deeper than the fourth nitride semiconductor layer (first spacer layer) 12 within the groove 11.

[0041] In a conventional structure, that is, a structure in which the second electrode is formed only on the second nitride semiconductor layer 3, if a fourth nitride semiconductor layer (first spacer layer) 12 is provided, the on-resistance between them increases when current flows from the second electrode 10 to the two-dimensional electron gas layer 20 through the fourth nitride semiconductor layer (first spacer layer) 12. On the other hand, as in the nitride semiconductor device according to the first embodiment of this disclosure, if the second electrode 10 is provided penetrating the fourth nitride semiconductor layer (first spacer layer) 12 and reaching the first nitride semiconductor layer 2 at a position deeper than the fourth nitride semiconductor layer (first spacer layer) 12, the high-concentration two-dimensional electron gas layer 20 and the second electrode 10 come into direct contact, which is preferable because it can stably reduce the on-resistance.

[0042] Furthermore, a fifth nitride semiconductor layer (second spacer layer) 13, such as AlN with a higher Al composition ratio than the second nitride semiconductor, may be provided between the third nitride semiconductor layer 4 and the second nitride semiconductor layer 3. The portion 3A of the second nitride semiconductor layer between the second electrode 10 and the third nitride semiconductor layer 4, where the third nitride semiconductor layer 4 is not present, may be omitted from the fifth nitride semiconductor layer (second spacer layer) 13. This allows for an increase in the concentration of the two-dimensional hole gas layer within the third nitride semiconductor layer 4.

[0043] Furthermore, since an electric field peak occurs near the end of the third nitride semiconductor layer 4 on the second electrode 10 side, it is necessary to ensure a certain distance between the third nitride semiconductor layer 4 and the second electrode 10. Here, a slope (taper 10T) is provided from the upper surface of the portion where the third nitride semiconductor layer 4 is not placed (in the example of Figure 1, portion 3A of the second nitride semiconductor layer) so as to move further away from the third nitride semiconductor layer 4 upwards.

[0044] Thus, it is desirable that the second electrode 10 has a taper 10T in the portion of the second electrode 10 facing the third nitride semiconductor layer 4, so that the distance between the third nitride semiconductor layer 4 and the second electrode 10 increases upward. In other words, in Figure 1, it is desirable that the taper 10T be provided on the upper part of the second electrode 10 so as to move upward (in the direction in which the upper surface of the second nitride semiconductor layer 3 faces) away from the third nitride semiconductor layer 4. As a result, at the height in which the third nitride semiconductor layer 4 is provided, the second electrode 10 can be moved further away from the third nitride semiconductor layer 4, so that the chip size can be reduced while maintaining the distance between the third nitride semiconductor layer 4 and the second electrode 10. The angle of the taper 10T can be, for example, 10 to 70 degrees, preferably 10 to 50 degrees, with respect to the upper surface of the flat portion of the second nitride semiconductor layer 3.

[0045] Furthermore, it is desirable that the angle of the taper 10T on the upper part of the second electrode 10 with respect to the upper surface of the flat portion of the second nitride semiconductor layer 3 is smaller than the angle of the (side surface) of the second electrode 10 provided on the side surface of the groove 11. Also, in order to increase the concentration near the two-dimensional electron gas layer 20 with which the second electrode 10 directly contacts, it is desirable that the angle of the (side surface) of the groove 11 with respect to the upper surface of the flat portion of the second nitride semiconductor layer 3 be steep (for example, 70 to 90 degrees). Moreover, in order to suppress manufacturing variations in the on-resistance between the second electrode 10 provided on the side surface of the steep groove 11 and the two-dimensional electron gas layer 20, it is desirable that the second electrode 10 is in contact with the entire side surface of the groove 11 on the control electrode 7 side.

[0046] Furthermore, as shown in Figure 1, portion 3A of the second nitride semiconductor layer 3 may be thinner than the second nitride semiconductor layer 3. This results in a lower relative height of the taper 10T of the second electrode 10, making it easier to secure a greater distance between the third nitride semiconductor layer 4 and the taper 10T of the second electrode 10, which is more preferable from the viewpoint of reducing the chip size.

[0047] Furthermore, as shown in Figure 1, a fifth nitride semiconductor layer (second spacer layer) 13, having a higher Al content than the second nitride semiconductor layer, may be further included between the second nitride semiconductor layer 3 and the third nitride semiconductor layer 4, and the portion 3A of the second nitride semiconductor layer 3 where the third nitride semiconductor layer 4 is not located may not have the fifth nitride semiconductor layer (second spacer layer) 13. This increases the height of the third nitride semiconductor layer 4, making it easier to secure a greater distance between the third nitride semiconductor layer 4 and the taper 10T of the second electrode 10, which is more preferable from the viewpoint of reducing chip size. Of course, the conventional effects of providing the fifth nitride semiconductor layer (second spacer layer) 13 can also be obtained.

[0048] The nitride semiconductor device described herein is not particularly limited and can be a semiconductor device such as an FET. Furthermore, the first electrode 8 can have the same structure as the second electrode 10. Specifically, the first electrode 8 may be provided within the groove 11, as shown in Figure 1 for the second electrode 10.

[0049] [Second Embodiment] Figure 2 shows a nitride semiconductor device 200 according to the second embodiment of this disclosure. Note that some matters described in the first embodiment of this disclosure may be omitted. However, the matters described in the first embodiment are also applicable to the nitride semiconductor device according to the second embodiment.

[0050] As shown in Figure 2, the nitride semiconductor device 200 according to the second embodiment of this disclosure has a different configuration of the second electrode portion compared to the first embodiment. Specifically, the second embodiment differs from the first embodiment in that the second electrode is provided on the upper part of the diffusion layer 14, which extends from the upper surface of the second nitride semiconductor layer 3 to the first nitride semiconductor layer 2 and has a higher concentration of N-type impurities than the second nitride semiconductor layer 3.

[0051] In the nitride semiconductor device 200 according to the second embodiment of this disclosure, the contact resistance can be reduced and the on-resistance can be reduced by the direct contact between the relatively high-density portion 20H of the two-dimensional electron gas layer where the third nitride semiconductor layer 4 is not provided and the diffusion layer 14 below the second electrode 10. Note that the upper part of the diffusion layer 14 and the third nitride semiconductor layer 4 are not in direct contact, and the diffusion layer 14 is spaced apart from the third nitride semiconductor layer 4.

[0052] In the nitride semiconductor device 200 according to the second embodiment, similar to the nitride semiconductor device 100 according to the first embodiment, a fourth nitride semiconductor layer (first spacer layer) 12 having a higher Al content than the second nitride semiconductor layer 3 may be further included between the first nitride semiconductor layer 2 and the second nitride semiconductor layer 3, and the diffusion layer 14 may be formed to extend to a position deeper than the fourth nitride semiconductor layer (first spacer layer) 12. If the diffusion layer 14 is provided penetrating the fourth nitride semiconductor layer (first spacer layer) 12 and reaching the first nitride semiconductor layer 2 at a position deeper than the fourth nitride semiconductor layer (first spacer layer) 12, the high-concentration two-dimensional electron gas layer 20 and the diffusion layer 14 will come into direct contact, and the on-resistance can be stably reduced.

[0053] Furthermore, the thickness of the portion 3A of the second nitride semiconductor layer 3 in the region between the diffusion layer 14 and the third nitride semiconductor layer 4 where the third nitride semiconductor layer 4 is not located may be the same, but it can be made smaller than the thickness of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4. The diffusion layer 14 extends from the upper surface of the portion 3A of the second nitride semiconductor layer 3 to the first nitride semiconductor layer 2. Preferably, a portion of the second electrode 10 provided on the diffusion layer 14 extends to the upper surface of the second nitride semiconductor layer 3A on the third nitride semiconductor layer 4 side. This makes it possible to further reduce on-resistance variation and reduce on-resistance.

[0054] Similar to the first embodiment, a fifth nitride semiconductor layer (second spacer layer) 13 is provided between the second nitride semiconductor layer 3 and the third nitride semiconductor layer 4, and the fifth nitride semiconductor layer (second spacer layer) 13 may not be provided on portion 3A of the second nitride semiconductor layer 3.

[0055] Furthermore, the first electrode 8 can have the same structure as the second electrode 10. Specifically, as shown in Figure 2, the first electrode 8 may be placed on top of the diffusion layer 15.

[0056] Furthermore, the second electrode 10 is provided with a taper (10T) in the portion of the second electrode 10 that extends over the upper surface of the second nitride semiconductor layer 3A and faces the third nitride semiconductor layer 4, so that the distance between the third nitride semiconductor layer 4 and the second electrode 10 increases in the direction of the upper surface of the second nitride semiconductor layer 3 (the direction in which the upper surface of the second nitride semiconductor layer 3 faces). As a result, at the height where the third nitride semiconductor layer 4 is provided, the second electrode 10 can be further separated from the third nitride semiconductor layer 4, thereby ensuring a sufficient distance between the third nitride semiconductor layer 4 and the second electrode 10 (reducing the chip size).

[0057] Furthermore, as shown in Figure 2, portion 3A of the second nitride semiconductor layer 3 may be thinner than the second nitride semiconductor layer 3. This makes the relative height of the taper 10T of the second electrode 10 lower, making it easier to secure a greater distance between the third nitride semiconductor layer 4 and the taper 10T of the second electrode 10, which is more preferable from the viewpoint of reducing the chip size. Also, as shown in Figure 2, a fifth nitride semiconductor layer (second spacer layer) 13 having a higher Al content than the second nitride semiconductor layer may be further included between the second nitride semiconductor layer 3 and the third nitride semiconductor layer 4, and the portion 3A of the second nitride semiconductor layer 3 where the third nitride semiconductor layer 4 is not placed may not have the fifth nitride semiconductor layer (second spacer layer) 13.

[0058] [Third Embodiment] Regardless of the lower form of the second electrode 10, the on-resistance can also be reduced by the upper form of the second electrode 10, that is, as shown in Figure 3, by having the second electrode 10 formed on the upper surface of a portion 3A of the second nitride semiconductor layer 3 that is thinner than the thickness of the portion of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4, and having a slope (taper 10T) in the portion of the second electrode 10 facing the third nitride semiconductor layer 4 such that the distance between the third nitride semiconductor layer 4 and the second electrode 10 increases upward (in the direction the upper surface faces) of the second nitride semiconductor layer 3. This is because the distance between the second electrode 10 and the first electrode 8 can be shortened while ensuring sufficient distance between the slope (taper 10T) of the second electrode 10 and the third nitride semiconductor layer 4.

[0059] Furthermore, even if the portion 3A of the second nitride semiconductor layer 3 is made thinner than the portion of the second nitride semiconductor layer 3 directly beneath the third nitride semiconductor layer 4, or if it is made the same thickness, a fifth nitride semiconductor layer (second spacer layer) 13 with a higher Al content than the second nitride semiconductor layer may also be included. In this case as well, the on-resistance can be reduced. This is because the distance between the second electrode 10 and the first electrode 8 can be shortened while ensuring sufficient distance between the slope (taper 10T) of the second electrode 10 and the third nitride semiconductor layer 4.

[0060] <Variation> In the first, second, and third embodiments, the second electrode 10 was described, but the first electrode 8 may have the same structure as the second electrode 10. In a typical process, the first electrode 8 and the second electrode 10 are sometimes formed simultaneously. Therefore, if the second electrode 10 and the first electrode 8 have the same structure (such as providing a taper), further reduction in on-resistance, simplification of the manufacturing process, and cost reduction can be achieved.

[0061] Furthermore, the first electrode and / or second electrode may be provided only on the side facing the control electrode or the third semiconductor region. Alternatively, the elements may be formed symmetrically with respect to the first electrode or the second electrode.

[0062] As described above, nitride semiconductor devices according to the first, second, and third embodiments of this disclosure can reduce on-resistance.

[0063] This specification includes the following embodiments: [1]: A nitride semiconductor device comprising: a first nitride semiconductor layer on which a two-dimensional electron gas layer is generated; a second nitride semiconductor layer on the first nitride semiconductor layer having a larger bandgap energy than the first nitride semiconductor layer; a third nitride semiconductor layer in a part of the second nitride semiconductor layer having a smaller bandgap energy than the second nitride semiconductor layer and on which a two-dimensional hole gas layer is generated; a P-type semiconductor layer electrically connected to the third nitride semiconductor layer; a control electrode on the P-type semiconductor layer; a first electrode on the first nitride semiconductor layer, spaced apart from the third nitride semiconductor layer; and a second electrode, viewed in plan, spaced apart from the end of the third nitride semiconductor layer that extends on the opposite side of the first electrode with the control electrode in between, the second electrode reaching from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, or the second electrode reaching from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer and provided on top of a diffusion layer with a higher impurity concentration than the second nitride semiconductor layer. [2]: The nitride semiconductor device according to [1], wherein the second electrode extends from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, and the second electrode is provided on the side of the groove on the control electrode side that extends to the first nitride semiconductor layer. [3]: The nitride semiconductor device according to [2], further comprising a fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer between the first nitride semiconductor layer and the second nitride semiconductor layer, wherein the groove is formed through the fourth nitride semiconductor layer, and the second electrode is provided in the groove to a position deeper than the fourth nitride semiconductor layer. [4]: The nitride semiconductor device according to [2] or [3] above, wherein the thickness of the second nitride semiconductor layer in the region between the groove and the third nitride semiconductor layer where the third nitride semiconductor layer is not disposed is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer, and a portion of the second electrode provided in the groove extends at least from within the groove to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side. [5]: The nitride semiconductor device according to [4], wherein the second electrode has a slope from the portion of the second electrode that extends on the upper surface of the second nitride semiconductor layer and faces the third nitride semiconductor layer, in the direction in which the distance between the third nitride semiconductor layer and the second electrode increases. [6]: The nitride semiconductor device according to [1], wherein the second electrode is provided on top of the diffusion layer, and further includes a fourth nitride semiconductor layer between the first nitride semiconductor layer and the second nitride semiconductor layer, the fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer, and the diffusion layer is formed to a depth greater than the fourth nitride semiconductor layer. [7]: The nitride semiconductor device according to [1] or [6] above, wherein the second electrode is provided on top of the diffusion layer, and the thickness of the second nitride semiconductor layer in the region between the second electrode and the third nitride semiconductor layer where the third nitride semiconductor layer is not provided is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer, and a portion of the second electrode provided on the diffusion layer extends at least to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side. [8]: The nitride semiconductor device according to [7], wherein the second electrode has a slope from the portion of the second electrode that extends on the upper surface of the second nitride semiconductor layer and faces the third nitride semiconductor layer, in the direction in which the distance between the third nitride semiconductor layer and the second electrode increases. [9]: A nitride semiconductor device according to [1], [2], [3], [4], [5], [6], [7], or [8], further comprising a fifth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer between the second nitride semiconductor layer and the third nitride semiconductor layer, wherein the fifth nitride semiconductor layer is not provided in the region between the second electrode and the third nitride semiconductor layer where the third nitride semiconductor layer is not disposed.

[0064] This disclosure is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of this disclosure and produces similar effects is included within the technical scope of this disclosure. [Explanation of Symbols]

[0065] 1...Substrate, 2...First nitride semiconductor layer, 3, 3A...Second nitride semiconductor layer, 4…Third nitride semiconductor layer, 5…PSJ structure, 6…P-type semiconductor layer 6, 7...Control electrode, 8...First electrode, 10...Second electrode, 10T...Taper 11…groove, 12…fourth nitride semiconductor layer (first spacer layer), 13…5th nitride semiconductor layer (2nd spacer layer), 14, 15…diffusion layer, 20...Two-dimensional electron gas (2DEG) layer, 20H... Regions with high concentration in the two-dimensional electron gas layer, 20L…A portion of the 2D electron gas layer with low concentration, 21...2-dimensional hole gas (2DHG) layer, 100, 200... Nitride semiconductor equipment.

Claims

1. A first nitride semiconductor layer in which a two-dimensional electron gas layer is formed, A second nitride semiconductor layer is located on the first nitride semiconductor layer and has a larger bandgap energy than the first nitride semiconductor layer, A third nitride semiconductor layer exists in a portion of the second nitride semiconductor layer, having a smaller bandgap energy than the second nitride semiconductor layer, and in which a two-dimensional hole gas layer is formed. A P-type semiconductor layer electrically connected to the third nitride semiconductor layer, The control electrode on the P-type semiconductor layer, A first electrode located on the first nitride semiconductor layer and spaced apart from the third nitride semiconductor layer, A nitride semiconductor device characterized in that, when viewed in plan, a second electrode is disposed at a distance from the end of the third nitride semiconductor layer that extends on the opposite side of the first electrode with respect to the control electrode, and the second electrode includes either the second electrode that reaches the first nitride semiconductor layer from the upper surface of the second nitride semiconductor layer, or the second electrode that reaches the first nitride semiconductor layer from the upper surface of the second nitride semiconductor layer and is provided on the upper part of a diffusion layer with a higher impurity concentration than the second nitride semiconductor layer.

2. When the second electrode extends from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, The nitride semiconductor device according to claim 1, characterized in that it includes a groove extending from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, and the second electrode provided on the side of the groove on the control electrode side extending to the first nitride semiconductor layer.

3. The first nitride semiconductor layer and the second nitride semiconductor layer further include a fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer, The nitride semiconductor device according to claim 2, characterized in that the groove is formed through the fourth nitride semiconductor layer, and the second electrode is provided in the groove to a position deeper than the fourth nitride semiconductor layer.

4. The thickness of the second nitride semiconductor layer in the region between the groove and the third nitride semiconductor layer where the third nitride semiconductor layer is not disposed is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer. The nitride semiconductor device according to claim 2, characterized in that a portion of the second electrode provided in the groove extends at least from within the groove to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side.

5. The nitride semiconductor device according to claim 4, characterized in that the second electrode has a slope such that the distance between the third nitride semiconductor layer and the second electrode increases in the direction in which the upper surface of the second nitride semiconductor layer faces the portion of the second electrode that extends on the upper surface of the second nitride semiconductor layer and faces the third nitride semiconductor layer.

6. When the second electrode is provided on the upper part of the diffusion layer, The first nitride semiconductor layer and the second nitride semiconductor layer further include a fourth nitride semiconductor layer having a higher Al content than the second nitride semiconductor layer, The nitride semiconductor device according to claim 1, characterized in that the diffusion layer is formed at a deeper position than the fourth nitride semiconductor layer.

7. When the second electrode is provided on the upper part of the diffusion layer, The thickness of the second nitride semiconductor layer in the region between the second electrode and the third nitride semiconductor layer where the third nitride semiconductor layer is not disposed is smaller than the thickness of the second nitride semiconductor layer directly beneath the third nitride semiconductor layer. The nitride semiconductor device according to claim 1, characterized in that a portion of the second electrode provided on the diffusion layer extends at least to the upper surface of the second nitride semiconductor layer on the third nitride semiconductor layer side.

8. The nitride semiconductor device according to claim 7, characterized in that the second electrode has a slope such that the distance between the third nitride semiconductor layer and the second electrode increases in the direction in which the upper surface of the second nitride semiconductor layer faces the portion of the second electrode that extends on the upper surface of the second nitride semiconductor layer and faces the third nitride semiconductor layer.

9. A fifth nitride semiconductor layer, having a higher Al content than the second nitride semiconductor layer, is further included between the second nitride semiconductor layer and the third nitride semiconductor layer. The nitride semiconductor device according to any one of claims 1 to 8, characterized in that the region between the second electrode and the third nitride semiconductor layer, where the third nitride semiconductor layer is not disposed, is not provided with the fifth nitride semiconductor layer.

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