Electronic circuit, drive circuit, and calculation method

Abstract

The present invention provides an electronic circuit, a drive circuit, and a calculation method that can more accurately calculate the slew rate of the current flowing through a switching element. [Solution] The electronic circuit according to this embodiment includes: a timing detection unit that detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value; and a calculation unit that calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing.

Description

Technical Field

[0001] This embodiment relates to an electronic circuit, a drive circuit, and a calculation method.

Background Art

[0002] For switching elements used in power supply circuits, inverters, etc., the shorter the transition time during turn-on or turn-off, the less the power loss. However, electromagnetic noise (EMI: Electro-Magnetic Interference) is generated when the switching element turns on or off, and the magnitude of the EMI increases as the transition time becomes shorter. That is, there is a trade-off relationship between power loss and EMI.

[0003] To adjust such a trade-off, it is conceivable to calculate the current slew rate during turn-on or turn-off of the switching element and control the magnitude of the drive current supplied to the switching element according to the calculated current slew rate. As a method for calculating the current slew rate of a switching element, a method of calculating the current slew rate based on the voltage generated in the parasitic inductance included in the switching element and an estimated value of the parasitic inductance is known. However, generally, it is difficult to accurately estimate the value of the parasitic inductance, and as a result, there is a problem that the current slew rate cannot be accurately calculated.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] This embodiment provides an electronic circuit, a drive circuit, and a calculation method that can more accurately calculate the slew rate of the current flowing through a switching element. [Means for solving the problem]

[0006] To solve the above problems, the electronic circuit according to this embodiment includes a timing detection unit that detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value, and a calculation unit that calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing.

[0007] The drive circuit according to this embodiment includes: a timing detection unit that detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value; a calculation unit that calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing; and a supply unit that supplies a drive current to the switching element according to the current slew rate.

[0008] The calculation method according to this embodiment detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value, and calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing. [Brief explanation of the drawing]

[0009] [Figure 1] This diagram shows the configuration of a half-inbridge inverter according to Embodiment 1. [Figure 2] This diagram shows the voltage and current waveforms of a switching element. [Figure 3] This is a diagram showing the detailed configuration of the drive circuit. [Figure 4] This figure shows the relationship between the drain current waveform of the switching element and the voltage waveforms of the drive circuit. [Figure 5] This diagram illustrates the operation of the current detection unit. [Figure 6] This diagram shows the detailed configuration of the drive current supply unit. [Figure 7] This figure shows the configuration of a half-inbridge inverter according to Embodiment 2. [Figure 8] This figure shows the configuration of a three-phase inverter according to Embodiment 3. [Modes for carrying out the invention]

[0010] This embodiment will be described below with reference to the drawings. In the drawings, the same or corresponding elements are denoted by the same reference numeral, and detailed descriptions are omitted as appropriate.

[0011] (Embodiment 1) Figure 1 shows the configuration of a half-bridge inverter 100 according to Embodiment 1. The half-bridge inverter 100 comprises a half-bridge circuit 10, a high-side drive circuit 20, a low-side drive circuit 30, and a control circuit 40. A load 50 is connected to the output of the half-bridge inverter 100.

[0012] The half-bridge circuit 10 includes a high-side switching element 11A and a low-side switching element 11B whose drive is controlled according to a control signal supplied from the control circuit 40. For example, the switching elements 11A and 11B are N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In this case, the switching elements 11A and 11B have a Kelvin source terminal (KS) in addition to the gate, drain, and power source (PS) terminals. Alternatively, the switching elements 11A and 11B may be N-channel IGBTs (Insulated Gate Bipolar Transistors). In this case, the switching elements 11A and 11B have a Kelvin emitter terminal (KE) in addition to the gate, collector, and power emitter (PE) terminals.

[0013] The drain of the high-side switching element 11A is connected to the power supply voltage VDD of the half-bridge inverter 100. The Kelvin source KS of the switching element 11A is connected to the ground of the high-side drive circuit 20. A parasitic inductance Ls (high-side parasitic inductance Ls) is present between the Kelvin source KS and the power source PS of the switching element 11A. The power source PS of the switching element 11A is connected to the drain of the low-side switching element 11B via the high-side shunt resistor Rs_HS. The voltage of the power source PS is input to the high-side drive circuit 20 via the voltage divider circuit 29 and capacitor C1 (high-side capacitor C1).

[0014] The Kelvin source KS of the low-side switching element 11B is connected to the ground of the low-side drive circuit 30. A parasitic inductance Ls (low-side parasitic inductance Ls) is included between the Kelvin source KS and the power source PS of the switching element 11B. The power source PS of the switching element 11B is connected to the ground GND of the half-bridge inverter 100 via the low-side shunt resistor Rs_LS. The voltage of the power source PS is input to the low-side drive circuit 30 via the voltage divider circuit 39 and capacitor C1 (low-side capacitor C1).

[0015] In this embodiment 1, the grounds of the high-side drive circuit 20 and the low-side drive circuit 30 are isolated from the ground GND of the half-bridge inverter 100. The switching elements 11A and 11B and the drive circuits 20 and 30 may be contained in separate IC packages or in the same IC package. Furthermore, the switching elements 11A and 11B and the drive circuits 20 and 30 may be mounted on different semiconductor substrates or on the same semiconductor substrate.

[0016] The direction of the current (load current) Iload supplied from the half-bridge inverter 100 to the load 50 is defined as positive when it flows from the half-bridge circuit 10 to the load 50, and negative when it flows from the load 50 to the half-bridge circuit 10. However, this definition may be reversed.

[0017] The high-side drive circuit 20 supplies a drive current Ig_HS to the high-side switching element 11A according to the high-side control signal IS_HS supplied from the control circuit 40. Specifically, when the high-side control signal IS_HS is Hi (e.g., +5V), the drive current Ig_HS flows from the drive circuit 20 towards the gate of the switching element 11A. On the other hand, when the high-side control signal IS_HS is Lo (e.g., 0V), the drive current Ig_HS flows from the gate of the switching element 11A towards the drive circuit 20.

[0018] The high-side drive circuit 20 calculates the currents (current slew rates) flowing through the switching element 11A at the time of turn-on and turn-off of the switching element 11A based on the voltage generated in the high-side parasitic inductance Ls at the time of turn-on and turn-off of the switching element 11A and the drain current (on-current) during conduction of the switching element 11A, and controls the magnitude of the drive current Ig_HS according to each calculated current slew rate.

[0019] Similarly, the low-side drive circuit 30 supplies the drive current Ig_LS to the low-side switching element 11B according to the low-side control signal IS_LS supplied from the control circuit 40. Specifically, when the low-side control signal IS_LS is Hi (for example, +5V), the drive current Ig_HS flows from the drive circuit 30 toward the gate of the switching element 11B. On the other hand, when the high-side control signal IS_HS is Lo (for example, 0V), the drive current Ig_HS flows from the gate of the switching element 11B toward the drive circuit 30.

[0020] The low-side drive circuit 30 calculates the respective current slew rates at the time of turn-on and turn-off of the switching element 11B based on the voltage generated in the low-side parasitic inductance Ls at the time of turn-on and turn-off of the switching element 11B and the drain current (on-current) during conduction of the switching element 11B, and controls the magnitude of the drive current Ig_LS according to each calculated current slew rate.

[0021] The control circuit 40 supplies a high-side control signal IS_HS to the high-side drive circuit 20 and a low-side control signal IS_LS to the low-side drive circuit 30. The load 50 is any electronic or electrical device driven by AC power. For example, if the load 50 is an AC motor, the control circuit 40 supplies a PWM-modulated high-side control signal IS_HS to the high-side drive circuit 20 and a PWM-modulated low-side control signal IS_LS to the low-side drive circuit 30. Alternatively, the half-bridge inverter 100 may be installed in power supply equipment such as a PV inverter for solar power generation. In this case, the output of the half-bridge circuit 10 is connected to the power grid instead of the load 50.

[0022] Figure 2 shows the voltage and current waveforms of switching element 11A. The top waveform is the time waveform of the gate-power source voltage Vgs of switching element 11A. The second waveform is the time waveform of the drain current Id of switching element 11A. The third waveform is the time waveform of the drain-power source voltage Vds of switching element 11A. The bottom waveform is the time waveform of the voltage Vls generated across the parasitic inductance Ls of switching element 11A. The voltage and current waveforms of switching element 11B are similar.

[0023] At time t0, the gate-power source voltage Vgs of the switching element 11A begins to rise. At time t1_ON, when the gate-power source voltage Vgs reaches the threshold voltage, the drain current Id begins to flow. At time t2_ON, when the drain current Id becomes equal to the load current Iload, the rise in the drain current Id stops, and the drain-power source voltage Vds begins to fall.

[0024] The period from time t1_ON to t2_ON corresponds to the turn-on time of the switching element 11A. During the period from time t2_ON to t1_OFF, the switching element 11A is in a conductive state, and the drain current Id during this period is the on-current Id_ON of the switching element 11A. In this embodiment 1, the current slew rate SR_ON at the time of turn-on of the switching element 11A is calculated according to the following equation (1).

[0025]

number

[0026] When the switching element 11A turns off, the drain current Id decreases from Id_ON to zero during the period from time t1_OFF to t2_OFF. The period from time t1_OFF to t2_OFF corresponds to the turn-off time of the switching element 11A. In this embodiment 1, the current slew rate SR_OFF at the time of turn-off of the switching element 11A is calculated according to the following equation (2).

[0027]

number

[0028] Figure 3 shows the detailed configuration of the high-side drive circuit 20. The configuration of the low-side drive circuit 30 is similar. Hereafter, switching elements 11A and shunt resistors Rs_HS will be abbreviated as switching element 11 and shunt resistor Rs, etc., as needed, and the following explanation applies to both the high-side drive circuit 20 and the low-side drive circuit 30. The high-side drive circuit 20 and the low-side drive circuit 30 will be referred to as drive circuits 20 / 30.

[0029] The drive circuit 20 / 30 includes a bias circuit 21, a turn-on timing detection unit 22a (first timing detection unit) and a turn-off timing detection unit 22b (second timing detection unit), a low-pass filter 23, a sampling clock generator 24, a sample-and-hold circuit 25, a turn-on slew rate calculation unit 26a (first slew rate calculation unit) and a turn-off slew rate calculation unit 26b (second slew rate calculation unit), and a turn-on drive current supply unit 27a and a turn-off drive current supply unit 27b.

[0030] In this embodiment 1, the voltage between the Kelvin source KS and the power source PS of the switching element 11 is equal to the voltage Vls generated across the parasitic inductance Ls of the switching element 11. This voltage Vls is divided by resistors R1 and R2 included in the voltage divider circuit 29, the DC component is removed by capacitor C1, and then it is input to the In1 terminal of the drive circuit 20. The voltage V1 input to the In1 terminal of the drive circuit 20 / 30 is expressed by the following equation (3).

[0031]

number

[0032] The bias circuit 21 includes a DC power supply Vdd and resistors R3 and R4, and generates a voltage Vps by adding a predetermined bias voltage Vbias to the voltage V1. The voltage Vps generated by the bias circuit 21 is expressed by the following equation (4).

[0033]

number

[0034] Generally, it is preferable that the voltage input to an integrated circuit falls between the power supply voltage Vdd of the integrated circuit and ground. In this embodiment 1, by appropriately adjusting resistors R1 to R4 and the DC power supply Vdd, the voltage Vls generated across the parasitic inductance Ls of the switching element 11 is converted into a voltage Vps between the power supply voltage Vdd of the drive circuit 20 / 30 and ground. However, if the voltage Vls generated across the parasitic inductance Ls is already between the power supply voltage Vdd and ground, the voltage divider circuit 29 and the bias circuit 21 may be omitted.

[0035] The turn-on timing detection unit 22a is composed of a comparator and compares the voltage Vps generated by the bias circuit 21 with a predetermined reference voltage Vref_ON. The turn-on timing detection unit 22a detects the voltage generated across the parasitic inductance Ls of the switching element 11 as voltage Vps and compares the detected voltage with a predetermined reference voltage Vref_ON. Specifically, if the voltage Vps is greater than Vref_ON, the output signal S_ON of the turn-on timing detection unit 22a becomes Low. On the other hand, if the voltage Vps is less than Vref_ON, the output signal S_ON of the turn-on timing detection unit 22a becomes High.

[0036] Figure 4 shows the relationship between the drain current waveform of the switching element 11 and the voltage waveforms of the drive circuit 20. The top waveform is the time waveform of the drain current Id of the switching element 11. The second waveform is the time waveform of the voltage Vdiv divided by the voltage divider circuit 29. The third waveform is the time waveform of the voltage Vps generated by the bias circuit 21. The fourth waveform is the time waveform of the output signal S_ON of the turn-on timing detection unit 22a. The bottom waveform is the time waveform of the output signal S_OFF of the turn-off timing detection unit 22b.

[0037] As shown in the time waveform of the voltage Vps in Figure 4, the reference voltage Vref_ON is set to a predetermined voltage value smaller than the bias voltage Vbias. The timing at which the output signal S_ON of the turn-on timing detection unit 22a changes from Lo to Hi (t1_ON) corresponds to the first timing when the voltage Vls generated in the parasitic inductance Ls matches a predetermined value corresponding to the reference voltage Vref_ON. In other words, the first timing corresponds to the timing when the voltage Vls changes from a value greater than the predetermined value to a value less than the predetermined value. Furthermore, the timing at which the output signal S_ON of the turn-on timing detection unit 22a changes from Hi to Lo (t2_ON) corresponds to the second timing when the voltage Vls generated in the parasitic inductance Ls matches a predetermined value corresponding to the reference voltage Vref_ON again. In other words, the second timing corresponds to the timing when the voltage Vls changes from a value less than the predetermined value to a value greater than the predetermined value.

[0038] The turn-on slew rate calculation unit 26a, described later, can calculate the turn-on time T_ON of the switching element 11 as t2_ON - t1_ON from these first timing (t1_ON) and second timing (t2_ON).

[0039] Similarly, the turn-off timing detection unit 22b is composed of a comparator and compares the voltage Vps generated by the bias circuit 21 with a predetermined reference voltage Vref_OFF. The turn-off timing detection unit 22b detects the voltage generated across the parasitic inductance Ls of the switching element 11 as voltage Vps and compares the detected voltage with a predetermined reference voltage Vref_OFF. Specifically, if the voltage Vps is less than Vref_OFF, the output signal S_OFF of the turn-off timing detection unit 22b becomes Hi. On the other hand, if the voltage Vps is greater than Vref_OFF, the output signal S_OFF of the turn-off timing detection unit 22b becomes Lo.

[0040] As shown in the time waveform of the voltage Vps in Figure 4, the reference voltage Vref_OFF is set to a predetermined voltage value greater than the bias voltage Vbias. The timing at which the output signal S_OFF of the turn-off timing detection unit 22b changes from Hi to Lo (t1_OFF) corresponds to the first timing when the voltage Vls generated in the parasitic inductance Ls matches a predetermined value corresponding to the reference voltage Vref_OFF. In other words, the first timing corresponds to the timing when the voltage Vls changes from a value less than the predetermined value to a value greater than the predetermined value. Furthermore, the timing at which the output signal S_OFF of the turn-off timing detection unit 22b changes from Lo to Hi (t2_OFF) corresponds to the second timing when the voltage Vls generated in the parasitic inductance Ls again matches a predetermined value corresponding to the reference voltage Vref_OFF. In other words, the second timing corresponds to the timing when the voltage Vls changes from a value greater than the predetermined value to a value less than the predetermined value.

[0041] The turn-off slew rate calculation unit 26b, described later, can calculate the turn-off time T_OFF of the switching element 11 as t2_OFF - t1_OFF from these first timing (t1_OFF) and second timing (t2_OFF).

[0042] Note that the absolute values ​​of the predetermined reference voltage Vref_ON and the predetermined reference voltage Vref_OFF may be the same or different.

[0043] Next, the voltage V2 input to the In2 terminal of the drive circuit 20 / 30 is the sum of the voltage Vls generated across the parasitic inductance Ls and the voltage Vrs generated across the shunt resistor Rs, and is expressed by the following equation (5).

[0044]

number

[0045] During the conduction of the switching element 11, that is, during the period from time t2_ON to t1_OFF in Figure 2, the drain current Id is a constant on-current Id_ON that does not change over time. Therefore, the voltage V2 when the switching element 11 is conduction is expressed by the following equation (6) using the on-current Id_ON.

[0046]

number

[0047] However, even when the switching element 11 is conducting, high-frequency noise generated when the switching element 11 is turned on remains in the voltage V2. The low-pass filter 23 removes the high-frequency noise component remaining in the voltage V2 and outputs it. In detail, the low-pass filter 23 includes resistors R5 and R6, capacitor C2, and operational amplifier 231. The output voltage Vlpf of the low-pass filter 23 is expressed by the following equation (7), where s is the Laplace transform operator.

[0048]

number

[0049] As described above, it is preferable that the voltage input to the integrated circuit falls between the power supply voltage Vdd of the integrated circuit and ground. In this embodiment 1, by appropriately adjusting resistors R5 and R6 and capacitor C2, the output voltage Vlpf of the low-pass filter is made to fall between the power supply voltage Vdd of the drive circuit 20 and ground. Also, due to the properties of the negatively feedback-connected operational amplifier (virtual ground), the voltage V2 is fixed to ground.

[0050] The sampling clock generator 24 and the sample-and-hold circuit 25 constitute a current detection unit that detects the on-current Id_ON of the switching element 11. The sampling clock generator 24 generates a sampling clock for the sample-and-hold circuit 25, described below, based on the control signal IS.

[0051] Figure 5 illustrates the operation of the current detection unit. The top waveform is the time waveform of the drain current Id of the switching element 11. The second waveform is the time waveform of the voltage Vrs generated across the shunt resistor Rs. The third waveform is the time waveform of the output voltage Vlpf of the low-pass filter 23. The fourth waveform is the time waveform of the output of the sampling clock generator 24. The bottom waveform is the time waveform of the control signal IS.

[0052] As shown in Figure 5, the sampling clock generator 24 outputs a clock pulse at a timing suitable for measuring the output voltage Vlpf corresponding to the on-current Id_ON of the switching element 11. More specifically, the sampling clock generator 24 outputs a clock pulse at a timing after a predetermined time Δt has elapsed, with reference to the time t0 when the control signal IS rises.

[0053] The sample-and-hold circuit 25 samples the output voltage Vlpf of the low-pass filter 23 corresponding to the on-current Id_ON of the switching element 11. In detail, the sample-and-hold circuit 25 includes a capacitor C3 and a switch 251. The switch 251 is normally open, but closes when a sampling clock is input, and the output voltage Vlpf of the low-pass filter 23 at this time is held in the capacitor C3.

[0054] Specifically, the voltage Vsmp held by the sample-and-hold circuit 25 is expressed by the following equation (8).

[0055]

number

[0056] Therefore, the ON current Id_ON of the switching element 11 is expressed by the following equation (9).

[0057]

number

[0058] Furthermore, if the residual noise in voltage V2 has little effect and sampling it as is is not problematic, the low-pass filter 23 may be omitted. Also, since the speed of change of the drain current Id of the switching element 11 is sufficiently slow compared to the switching frequency, high speed is not required for the response speed of the shunt resistor Rs.

[0059] The turn-on slew rate calculation unit 26a is composed of a multiplication circuit or a CPU (Central Processing Unit), etc., and calculates the turn-on slew rate SR_ON of the switching element 11. Specifically, the turn-on slew rate calculation unit 26a calculates the current slew rate SR_ON of the switching element 11 at the time of turn-on according to the following formula (10) from the first timing (t1_ON) and second timing (t2_ON) detected by the turn-on timing detection unit 22a and the on current Id_ON of the switching element 11 detected by the current detection unit.

[0060]

number

[0061] Similarly, the turn-off slew rate calculation unit 26b is composed of a multiplication circuit or a CPU, etc., and calculates the turn-off slew rate SR_OFF of the switching element 11. In detail, the turn-off slew rate calculation unit 26b calculates the current slew rate SR_OFF of the switching element 11 at the time of turn-off according to the following formula (11) from the first timing (t1_OFF) and second timing (t2_OFF) detected by the turn-off timing detection unit 22b and the ON current Id_ON of the switching element 11 detected by the current detection unit.

[0062]

number

[0063] Figure 6 shows the detailed configuration of the turn-on drive current supply unit 27a and the turn-off drive current supply unit 27b. The turn-on drive current supply unit 27a includes an adder 271a and a variable current source 272a. The adder 271a calculates the deviation between the current slew rate SR_ON at the time of turn-on, calculated by the turn-on slew rate calculation unit 26a, and a predetermined target value SRref_ON. The variable current source 272a outputs a turn-on drive current Ig_ON corresponding to the deviation. Specifically, if the current slew rate SR_ON at the nth turn-on is greater than the target value SRref_ON, the variable current source 272a reduces the drive current Ig_ON at the (n+1)th turn-on. For example, when controlling the drive current Ig with a digital value, the drive current Ig_ON at the (n+1)th turn-on is reduced by 1 LSB, or by a value corresponding to the deviation. On the other hand, if the current slew rate SR_ON at the nth turn-on is smaller than the target value SRref_ON, the variable current source 272a increases the drive current Ig_ON at the (n+1)th turn-on. For example, if the drive current Ig is controlled by a digital value, the drive current Ig_ON at the (n+1)th turn-on is increased by 1 LSB, or by a value corresponding to the deviation.

[0064] Similarly, the turn-off drive current supply unit 27b includes an adder 271b and a variable current source 272b. The adder 271b calculates the deviation between the turn-off current slew rate SR_OFF calculated by the turn-off slew rate calculation unit 26b and a predetermined target value SRref_OFF. The variable current source 272b outputs a turn-off drive current Ig_OFF corresponding to the deviation.

[0065] Specifically, if the current slew rate SR_OFF at the nth turn-off is greater than the target value SRRef_OFF, the variable current source 272b reduces the drive current Ig_OFF at the nth turn-off. For example, if the drive current Ig is controlled by a digital value, the drive current Ig_OFF at the (n+1)th turn-off is reduced by 1 LSB, or by a value corresponding to the deviation. On the other hand, if the current slew rate SR_OFF is less than the target value SRref_OFF, the variable current source 272b increases the drive current Ig_OFF at the (n+1)th turn-off. For example, if the drive current Ig is controlled by a digital value, the drive current Ig_OFF at the (n+1)th turn-off is increased by 1 LSB, or by a value corresponding to the deviation.

[0066] Furthermore, the timing at which the drive current supply units 27a and 27b change the magnitude of the drive current Ig is as follows: as soon as the slew rate calculation unit 26 calculates the nth slew rate, the magnitude of the drive current Ig may be changed immediately. At time t2_ON, the current slew rate at turn-on can be calculated, and even if the drive current Ig is changed after time t2_ON, the on current Id_ON has already finished changing, so there is no effect on the current slew rate. The same applies to the current slew rate at turn-off; even if the drive current Ig is changed after time t2_OFF, there is no effect on the on current Id_ON. Alternatively, the drive current supply units 27a and 27b may control the variable current source 272 to change the magnitude of the drive current Ig in accordance with the timing of the next turn-on / turn-off by referring to the control signal IS.

[0067] When the switching element 11 is turned on, i.e., when the control signal IS = Hi, switch 28a is closed and switch 28b is open. At this time, the turn-on drive current Ig_ON, adjusted according to the current slew rate SR_ON at the time of the previous turn-on, is supplied or output as the drive current Ig from the Out terminal of the drive circuit 20 / 30. On the other hand, when the switching element 11 is turned off, i.e., when the control signal IS = Lo, the output of the NOT gate 28c becomes Hi, so switch 28a is open and switch 28b is closed. At this time, the turn-off drive current Ig_OFF, adjusted according to the current slew rate SR_OFF at the time of the previous turn-off, is supplied or output as the drive current Ig from the Out terminal of the drive circuit 20. The drive current Ig at this time is the current that flows from the gate of the switching element 11 towards the Out terminal (current is drawn from the gate of the switching element 11).

[0068] As described above, in this embodiment 1, the slew rate calculation unit 26 (turn-on SR calculation unit 26a and turn-off SR calculation unit 26b) calculates the current slew rate SR of the switching element 11 based on the on-current Id_ON of the switching element 11 and the first timing (t1) and second timing (t2) when the voltage Vls generated in the parasitic inductance Ls of the switching element 11 matches a predetermined value. Therefore, the specific value of the parasitic inductance Ls of the switching element 11 is not required when calculating the current slew rate SR. Due to these features, this embodiment 1 can calculate the current slew rate of the switching element more accurately compared to conventional technology that calculates the current slew rate based on an estimated value of the parasitic inductance Ls.

[0069] Furthermore, in this embodiment 1, the drive current supply unit 27 supplies a drive current Ig to the switching element 11 according to the current slew rate SR calculated by the slew rate calculation unit 26. This allows for free adjustment of the current slew rate during the turn-on and turn-off of the switching element. As a result, a trade-off between the power loss and EMI of the switching element can be achieved.

[0070] (Embodiment 2) Figure 7 shows the configuration of the half-bridge inverter 200 according to Embodiment 2. In this Embodiment 2, instead of the shunt resistor Rs, low-pass filter 23, sampling clock generator 24, and sample-and-hold circuit 25 of Embodiment 1, a current sensor 260 for measuring the output current Iout of the half-bridge circuit 10 is provided. For example, the current sensor 260 may be a Hall effect element.

[0071] The turn-on SR calculation unit 26a of the high-side drive circuit 220 detects the on-current Id_ON=Iout of the switching element 11A from the output current Iout of the half-bridge circuit 10 detected by the current sensor 260 when the high-side control signal IS_HS=Hi. Similarly, the turn-on SR calculation unit 26a of the low-side drive circuit 230 detects the on-current Id_ON=Iout of the switching element 11B from the output current Iout of the half-bridge circuit 10 detected by the current sensor 260 when the low-side control signal IS_LS=Hi.

[0072] In this second embodiment, a shunt resistor Rs is not required to detect the on-current Id_ON of the switching element 11, thus avoiding power loss and noise generation in the shunt resistor Rs. Furthermore, since the speed of change of the load current Iload is sufficiently slow compared to the switching frequency, high speed is not required for the response speed of the current sensor 260. Therefore, a relatively inexpensive current sensor can be used.

[0073] (Embodiment 3) Figure 8 shows the configuration of a three-phase inverter 300 according to Embodiment 3. The three-phase inverter 300 includes three half-bridge circuits 310A to 310C, three high-side drive circuits 320A to 320C, three low-side drive circuits 330A to 330C, and a control circuit 340. A load 350 is connected to the output of the three-phase inverter 300. The half-bridge circuits 310A to 310C have the same configuration as the half-bridge circuit 210 of Embodiment 2. The high-side drive circuits 320A to 320C have the same configuration as the drive circuit 220 of Embodiment 2. The low-side drive circuits 330A to 330C have the same configuration as the drive circuit 230 of Embodiment 2.

[0074] The control circuit 340 supplies high-side control signals to the high-side drive circuits 320A to 320C, and low-side control signals to the low-side drive circuits 330A to 330C. The load 350 is any electronic or electrical device driven by three-phase AC power. For example, if the load 350 is a three-phase AC motor, the control circuit 340 supplies PWM-modulated high-side control signals to the high-side drive circuits 320A to 320C, and PWM-modulated low-side control signals to the low-side drive circuits 330A to 330C. In general three-phase inverter control, current sensors are often required to detect the current of each phase. In this case, it is not necessary to add new current sensors for the high-side and low-side drive circuits, and existing current sensors can be used.

[0075] As another application example, an inverter equipped with a high-side drive circuit, a low-side drive circuit, a half-bridge circuit, and a control circuit may be used as a PV inverter for solar power generation. In this case, the output of the PV inverter is connected to the power grid.

[0076] While several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the embodiments. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, and combinations can be made without departing from the spirit of the embodiments. These embodiments and their variations are included in the scope and spirit of the embodiments, as well as in the claims and their equivalents.

[0077] Furthermore, this embodiment can also be configured as follows. [Item 1] (Electronic circuit) A timing detection unit (22) detects a voltage (Vls) generated in the parasitic inductance (Ls) of a switching element (11) whose drive is controlled according to a control signal (IS), and detects a first timing (t1) at which the voltage becomes less than or greater than a predetermined value, and a second timing (t2) after the first timing at which the voltage becomes more than or less than the predetermined value. A calculation unit (26) calculates the slew rate (SR) of the current flowing through the switching element based on the current (Id_ON) flowing through the switching element at the first timing and the second timing, An electronic circuit equipped with the following features. [Item 2] The calculation unit (26) calculates the slew rate of the current flowing through the switching element using the following formula: SR = Id_ON / (t2 - t1) Calculated according to the following: However, SR is the slew rate of the current flowing through the switching element, Id_ON is the current flowing through the switching element, t1 is the first timing, and t2 is the second timing. The electronic circuit described in item 1. [Item 3] The timing detection unit (22) is A first timing detection unit that detects the first timing (t1_ON) and the second timing (t2_ON) when the switching element is turned on, A second timing detection unit (22b) detects the first timing (t1_OFF) and the second timing (t2_OFF) when the switching element is turned off, Includes, The calculation unit (26) is, A first slew rate calculation unit (26a) calculates the slew rate (SR_ON) of the switching element at the turn-on time based on the current flowing through the switching element at the first timing (t1_ON) and the second timing (t2_ON) at the turn-on time, A second slew rate calculation unit (26b) calculates the slew rate (SR_OFF) of the switching element at the time of turn-off based on the current flowing through the switching element at the first timing (t1_OFF) and the second timing (t2_OFF) at the time of turn-off, including, The electronic circuit described in item 1 or 2. [Item 4] The system further includes a current detection unit that detects the current flowing through the switching element based on the voltage (Vrs) generated across a shunt resistor (Rs) connected in series with the switching element. The calculation unit uses the current detected by the current detection unit. An electronic circuit as described in any one of items 1 to 3. [Item 5] The aforementioned switching element is included in the half-bridge circuit. The calculation unit uses the output current (Iout) detected by the current sensor (260) that detects the output current (Iout) of the half-bridge circuit as the current flowing through the switching element. An electronic circuit as described in any one of items 1 to 3. [Item 6] The current detection units (24, 25) are A generator (24) that generates a sampling clock based on the aforementioned control signal (IS), A sample-and-hold circuit (25) samples the current flowing through the switching element according to the sampling clock, including, The electronic circuit described in item 4. [Item 7] The aforementioned switching element is a MOSFET, The voltage (Vls) generated in the parasitic inductance is the voltage between the Kelvin source terminal (KS) and the power source terminal (PS) of the MOSFET. An electronic circuit as described in any one of items 1 through 6. [Item 8] The aforementioned switching element is an IGBT, The voltage (Vls) generated in the parasitic inductance is the voltage between the Kelvin emitter terminal (KE) and the power emitter terminal (PE) of the IGBT. An electronic circuit as described in any one of items 1 through 6. [Item 9] (Drive Circuit) A timing detection unit (22) detects a voltage (Vls) generated in the parasitic inductance (Ls) of a switching element (11) whose drive is controlled according to a control signal (IS), and detects a first timing (t1) at which the voltage becomes less than or greater than a predetermined value, and a second timing (t2) after the first timing at which the voltage becomes more than or less than the predetermined value. A calculation unit (26) calculates the slew rate (SR) of the current flowing through the switching element based on the current (Id_ON) flowing through the switching element at the first timing and the second timing, A supply unit (27) supplies a drive current to the switching element that corresponds to the slew rate of the current flowing through the switching element, A drive circuit equipped with the following features. [Item 10] (Three-phase inverter) The first to third half-bridge circuits each contain two switching elements, The first to third drive circuits described in item 9, which drive the first to third half-bridge circuits respectively, A three-phase inverter equipped with this feature. [Item 11] (Calculation method) The voltage (Vls) generated in the parasitic inductance (Ls) of a switching element (11) whose drive is controlled according to a control signal (IS) is detected, and a first timing (t1) at which the voltage becomes less than or greater than a predetermined value is detected, and a second timing (t2) after the first timing at which the voltage becomes greater than or less than the predetermined value is detected. Based on the current (Id_ON) flowing through the switching element at the first and second timings, the slew rate (SR) of the current flowing through the switching element is calculated. Calculation method. [Explanation of symbols]

[0078] 10 Half-bridge circuit 11A high-side switching element 11B Low-side switching element 20 High-side drive circuit 21 Bias Circuit 22a Turn-on timing detection unit (first timing detection unit) 22b Turn-off timing detection unit (second timing detection unit) 23 Low-pass filter 231 Op-amps 24. Sampling Clock Generator (Current Detection Unit) 25. Sample and Hold Circuit (Current Detection Section) 251 switches 26a Turn-on slew rate calculation unit (first slew rate calculation unit) 26b Turn-off / Through Rate Calculation Unit (Second Thru-Rate Calculation Unit) 27a Turn-on drive current supply unit (supply unit) 271a Adder 271b Adder 272a Variable current source 272b Variable current source 27b Turn-off drive current supply unit (supply unit) 28a switch 28b switch 28c NOT gate 29. Voltage divider circuit 30 Low-side drive circuit 39. Voltage divider circuit 40 Control circuits 50 load 100 Half-bridge inverter 200 Half-bridge inverter 210 Half-bridge circuit 220 High-side drive circuit 230 Low-side drive circuit 260 Current Sensors 300 Three-Phase Inverter 310A Half-Bridge Circuit 310B Half-Bridge Circuit 310C Half-Bridge Circuit 320A High-Side Drive Circuit 320B High-Side Drive Circuit 320C High-Side Drive Circuit 330A Low-Side Drive Circuit 330B Low-Side Drive Circuit 330C Low-Side Drive Circuit 340 Control circuits 350 load C1 Capacitor C2 Capacitor C3 Capacitor D Drain G Gate Gnd terminal GND (Ground) KS Kelvin Sauce Id drain current Id_ON On-current Ig_HS High-side drive current Ig_LS Low-side drive current Iload Load current In1 terminal In2 terminal Iout half-bridge circuit output current IS_HS Highside Control Signal IS_LS Lowside Control Signal Ls Parasitic Inductance Out terminal PS Power Source Rs_HS High-side shunt resistor Rs_LS Low-side shunt resistor S_OFF Turn-off timing detection unit output signal S_ON Turn-on Timing Detection Unit Output Signal SR_OFF Current slew rate during turn-off SR_ON Current slew rate at turn-on SRref_OFF Target value of current slew rate during turn-off SRref_ON Target value of current slew rate at turn-on t0 time t1_ON Turn-on start time (first timing for turn-on) t2_ON Turn-on end time (second timing of turn-on) t1_OFF Turn-off start time (first timing for turn-off) t2_OFF Turn-off end time (second timing during turn-off) t3 time TP_OFF ​​Turn-off time TP_ON Turn-on time V1 Input voltage of In1 terminal V2 In2 terminal input voltage Vbias Bias Voltage Vdd DC power supply Vds (Drain-Power Source Voltage) VDD power supply voltage Vgs (Gate-to-Power Source Voltage) Vlpf low-pass filter output voltage Vls is the voltage generated across the parasitic inductance. Vps is the generated voltage of the bias circuit. Vref_OFF Reference voltage Vref_ON Reference voltage Vrs is the voltage generated across the shunt resistor. Vsmp: Voltage held in sample-and-hold circuit

Claims

1. A timing detection unit detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value. A calculation unit that calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing, An electronic circuit equipped with the following features.

2. The calculation unit calculates the slew rate of the current flowing through the switching element using the following formula: SR=Id_ON / (t2-t1) Calculated according to the following: However, SR is the slew rate of the current flowing through the switching element, Id_ON is the current flowing through the switching element, t1 is the first timing, and t2 is the second timing. The electronic circuit according to claim 1.

3. The timing detection unit, A first timing detection unit for detecting the first timing and the second timing when the switching element is turned on, A second timing detection unit for detecting the first timing and the second timing when the switching element is turned off, Includes, The calculation unit described above, A first slew rate calculation unit calculates the slew rate of the switching element at the turn-on time based on the current flowing through the switching element at the first timing and the second timing at the turn-on time, A second slew rate calculation unit calculates the slew rate of the switching element at the time of turn-off based on the current flowing through the switching element at the first timing and the second timing during the turn-off, including, The electronic circuit according to claim 1.

4. The system further includes a current detection unit that detects the current flowing through the switching element based on the voltage generated across a shunt resistor connected in series with the switching element. The calculation unit uses the current detected by the current detection unit. The electronic circuit according to claim 1.

5. The aforementioned switching element is included in the half-bridge circuit. The calculation unit uses the output current detected by the current sensor that detects the output current of the half-bridge circuit as the current flowing through the switching element. The electronic circuit according to claim 1.

6. The current detection unit is A generator that generates a sampling clock based on the aforementioned control signal, A sample-and-hold circuit that samples the current flowing through the switching element according to the sampling clock, including, The electronic circuit according to claim 4.

7. The switching element is a MOSFET, The voltage generated in the parasitic inductance is the voltage between the Kelvin source terminal and the power source terminal of the MOSFET. The electronic circuit according to claim 1.

8. The switching element is an IGBT. The voltage generated in the parasitic inductance is the voltage between the Kelvin emitter terminal and the power emitter terminal of the IGBT. The electronic circuit according to claim 1.

9. A timing detection unit detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value. A calculation unit that calculates the slew rate of the current flowing through the switching element based on the current flowing through the switching element at the first timing and the second timing, A supply unit that supplies a drive current to the switching element corresponding to the slew rate of the current flowing through the switching element, A drive circuit equipped with the following features.

10. The first to third half-bridge circuits each contain two switching elements, The first to third drive circuits according to claim 9, which drive the first to third half-bridge circuits respectively, A three-phase inverter equipped with this feature.

11. The system detects a voltage generated in the parasitic inductance of a switching element whose drive is controlled according to a control signal, and detects a first timing when the voltage is less than or greater than a predetermined value, and a second timing after the first timing when the voltage is greater than or less than the predetermined value. Based on the current flowing through the switching element at the first timing and the second timing, the slew rate of the current flowing through the switching element is calculated. Calculation method.

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